QuarkSocPkg/QuarkSocPkg.dec - edk2 - Git at Google

 ## @file
 # INTEL Quark SoC Module Package Reference Implementations
 #
 # This Module provides FRAMEWORK reference implementation for INTEL Quark SoC.
 # Copyright (c) 2013-2015 Intel Corporation.
 #
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
 # which accompanies this distribution.  The full text of the license may be found at
 # http://opensource.org/licenses/bsd-license.php
 #
 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 ##


 ################################################################################
 #
 # Defines Section - statements that will be processed to create a Makefile.
 #
 ################################################################################

 [Defines]
   DEC_SPECIFICATION              = 0x00010005
   PACKAGE_NAME                   = QuarkSocPkg
   PACKAGE_GUID                   = 28DECF17-6C75-448f-87DC-BDE4BD579919
   PACKAGE_VERSION                = 0.1


 ################################################################################
 #
 # Include Section - list of Include Paths that are provided by this package.
 #                   Comments are used for Keywords and Module Types.
 #
 # Supported Module Types:
 #  SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER BASE
 #
 ################################################################################
 [Includes]
   #
   # North Cluster
   #
   QuarkNorthCluster/Include
   QuarkNorthCluster/MemoryInit/Pei

   #
   # South Cluster
   #
   QuarkSouthCluster/Include

 ################################################################################
 #
 # Library Class Header section - list of Library Class header files that are
 #                                provided by this package.
 #
 ################################################################################
 [LibraryClasses]
   #
   # North Cluster
   #
   QNCAccessLib|QuarkNorthCluster/Include/Library/QNCAccessLib.h
   IntelQNCLib|QuarkNorthCluster/Include/Library/IntelQNCLib.h
   IohLib|QuarkSouthCluster/Include/Library/IohLib.h
   I2cLib|QuarkSouthCluster/Include/Library/I2cLib.h

 ################################################################################
 #
 # Global Guid Definition section - list of Global Guid C Name Data Structures
 #                                  that are provided by this package.
 #
 ################################################################################
 [Guids]
   #
   # North Cluster
   #
   gEfiQuarkNcSocIdTokenSpaceGuid  = { 0xca452c6a, 0xdf0c, 0x4dc9, { 0x82, 0xfb, 0xea, 0xe2, 0xab, 0x31, 0x29, 0x46 }}
   gQncS3CodeInLockBoxGuid   =  { 0x1f18c5b3, 0x29ed, 0x4d9e, {0xa5, 0x4, 0x6d, 0x97, 0x8e, 0x7e, 0xd5, 0x69}}
   gQncS3ContextInLockBoxGuid = { 0xe5769ea9, 0xe706, 0x454b, {0x95, 0x7f, 0xaf, 0xc6, 0xdb, 0x4b, 0x8a, 0xd}}

   #
   # South Cluster
   #
   gEfiQuarkSCSocIdTokenSpaceGuid  = { 0xef251b71, 0xceed, 0x484e, { 0x82, 0xe3, 0x3a, 0x1f, 0x34, 0xf5, 0x12, 0xe2 }}

 ################################################################################
 #
 # Global Ppi Definition section - list of Global Ppi C Name Data Structures
 #                                  that are provided by this package.
 #
 ################################################################################
 [Ppis]
   #
   # North Cluster
   #
   gQNCMemoryInitPpiGuid = { 0x21ff1fee, 0xd33a, 0x4fce, { 0xa6, 0x5e, 0x95, 0x5e, 0xa3, 0xc4, 0x1f, 0x40}}

 ################################################################################
 #
 # Global Protocols Definition section - list of Global Protocols C Name Data
 #                                  Structures that are provided by this package.
 #
 ################################################################################
 [Protocols]
   #
   # North Cluster
   #
   gEfiPlatformPolicyProtocolGuid = { 0x2977064F, 0xAB96, 0x4FA9, { 0x85, 0x45, 0xF9, 0xC4, 0x02, 0x51, 0xE0, 0x7F }}
   gEfiSmmIchnDispatch2ProtocolGuid = { 0xadf3a128, 0x416d, 0x4060, { 0x8d, 0xdf, 0x30, 0xa1, 0xd7, 0xaa, 0xb6, 0x99 }}
   gEfiSpiProtocolGuid = { 0x1156efc6, 0xea32, 0x4396, { 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 }}
   gEfiSmmSpiProtocolGuid  = { 0xD9072C35, 0xEB8F, 0x43ad, { 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 }}
   gEfiQncS3SupportProtocolGuid  = { 0xe287d20b, 0xd897, 0x4e1e, { 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 }}

   #
   # South Cluster
   #
   gEfiSDHostIoProtocolGuid = {0xb63f8ec7, 0xa9c9, 0x4472, {0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51}}

 ################################################################################
 #
 # PCD Declarations section - list of all PCDs Declared by this Package
 #                            Only this package should be providing the
 #                            declaration, other packages should not.
 #
 ################################################################################

 [PcdsFeatureFlag]
   #
   # North Cluster
   #
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddressFixed|TRUE|BOOLEAN|0x10000001

   #
   # South Cluster
   #
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdEhciRecoveryEnabled|FALSE|BOOLEAN|0x10000003
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdI2CFastModeEnabled|FALSE|BOOLEAN|0x10000005

   #
   # Feature Flag equivalent to linux SDHCI_QUIRK_NO_HISPD_BIT to stop
   # setting of SD HCI hi_spd_en bit in HOST_CTL register.
   #
   # Alway TRUE ie high speed enable bit must never
   # be set so we stay within SD interface Setup/Hold time.
   #
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdSdHciQuirkNoHiSpd|TRUE|BOOLEAN|0x10000004

 [PcdsFixedAtBuild]
   #
   # North Cluster
   #

   # Values of Io Port Base Address, MMIO base address and space size.
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress|0x1000|UINT16|0x10000200
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress|0x1010|UINT16|0x10000201
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoLVL2|0x1014|UINT16|0x10000202

   gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress|0x1080|UINT16|0x10000205
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress|0x1100|UINT16|0x10000206
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddress|0x1040|UINT16|0x10000207
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress|0x1140|UINT16|0x10000209

   gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress|0xFED1C000|UINT64|0x1000020B
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress|0xFEC00000|UINT64|0x1000020C

   gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicSize|0x1000|UINT64|0x1000020D
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioSize|0x4000|UINT64|0x1000020E

   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize|0x02000000|UINT64|0x1000020F
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000|UINT64|0x10000210
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetSize|0x400|UINT64|0x10000211
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdTSegSize|0x200000|UINT32|0x10000212

   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoBase|0x2000|UINT16|0x10000214
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoSize|0xE000|UINT16|0x10000215
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base|0x90000000|UINT32|0x1000021B
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Size|0x20000000|UINT32|0x1000021C
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Base|0xB0000000|UINT64|0x1000021D
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Size|0x30000000|UINT64|0x1000021E

   # Values for programming Interrupt Route Configuration Registers:
   # Indicates which interrupt routing is connected to the INTA/B/C/D pins reported in the
   # "DxIP" register fields. This will be the internal routing, the device interrupt is connected
   # to the interrupt controller.
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent0IR|0x0000|UINT16|0x10000223
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent1IR|0x7654|UINT16|0x10000224
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent2IR|0x0000|UINT16|0x10000225
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent3IR|0x3210|UINT16|0x10000226

   gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationPort|0xb2|UINT16|0x10000232
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmDataPort|0xb3|UINT16|0x10000233
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationData|0x55|UINT8|0x10000234
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPlatformSmbusAddrNum|0x0|UINT32|0x10000235
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPlatformSmbusAddrTable|0x0|UINT64|0x10000236

   gEfiQuarkNcSocIdTokenSpaceGuid.PcdESramMemorySize|0x00080000|UINT32|0x10000240
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdDeviceEnables|0x03|UINT32|0x10000237
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdPcieRootPortConfiguration|{0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00}|VOID*|0x10000239
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile |{ 0x8B, 0xEA, 0x5E, 0xD7, 0xD2, 0x23, 0xD4, 0x4E, 0xBC, 0x4F, 0x57, 0x51, 0xD4, 0xA1, 0x8D, 0xCF }|VOID*|0x1000023A

   #
   # South Cluster
   #
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohI2cMmioBase|0xA001F000|UINT64|0x20000005
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiP2PMemoryBaseAddress|0xA0000000|UINT32|0x20000006
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiQNCUsbControllerMemoryBaseAddress|0xA0010000|UINT32|0x20000007
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase|0xA0020000|UINT64|0x20000008
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac0MmioBase|0xA0024000|UINT64|0x20000009
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac1MmioBase|0xA0028000|UINT64|0x2000000A

   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartBusNumber|0x00|UINT8|0x20000013
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartDevNumber|0x14|UINT8|0x20000014
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartFunctionNumber|0x5|UINT8|0x20000001
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber|0x00|UINT8|0x20000029
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber|0x15|UINT8|0x2000002A
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber|0x2|UINT8|0x2000002B
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister|0x14|UINT8|0x2000002D

 [PcdsDynamic, PcdsDynamicEx]
   #
   # North Cluster
   #
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdQncS3CodeInLockBoxAddress|0|UINT64|0x30000026
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdQncS3CodeInLockBoxSize|0|UINT64|0x30000027

   ## Intel(R) Quark(TM) Soc X1000 processor MRC Parameters.  Default is for Galileo Gen 2 platform.<BR><BR>
   # @Prompt Intel(R) Quark(TM) Soc X1000 processor MRC Parameters.
   gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|{0x08, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}|VOID*|0x40000001

   #
   # South Cluster
   #
   ## MAC0 address for the Ethernet Controller in Intel(R) Quark(TM) Soc X1000 processor.  Default is 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff.<BR><BR>
   # @Prompt Ethernet MAC 0 Address.
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}|VOID*|0x50000001

   ## MAC1 address for the Ethernet Controller in Intel(R) Quark(TM) Soc X1000 processor.  Default is 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff.<BR><BR>
   # @Prompt Ethernet MAC 1 Address.
   gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}|VOID*|0x50000002
	## @file
	# INTEL Quark SoC Module Package Reference Implementations
	#
	# This Module provides FRAMEWORK reference implementation for INTEL Quark SoC.
	# Copyright (c) 2013-2015 Intel Corporation.
	#
	# This program and the accompanying materials
	# are licensed and made available under the terms and conditions of the BSD License
	# which accompanies this distribution. The full text of the license may be found at
	# http://opensource.org/licenses/bsd-license.php
	#
	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	#
	##


	################################################################################
	#
	# Defines Section - statements that will be processed to create a Makefile.
	#
	################################################################################

	[Defines]
	DEC_SPECIFICATION = 0x00010005
	PACKAGE_NAME = QuarkSocPkg
	PACKAGE_GUID = 28DECF17-6C75-448f-87DC-BDE4BD579919
	PACKAGE_VERSION = 0.1



	################################################################################
	#
	# Include Section - list of Include Paths that are provided by this package.
	# Comments are used for Keywords and Module Types.
	#
	# Supported Module Types:
	# SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER BASE
	#
	################################################################################
	[Includes]
	#
	# North Cluster
	#
	QuarkNorthCluster/Include
	QuarkNorthCluster/MemoryInit/Pei

	#
	# South Cluster
	#
	QuarkSouthCluster/Include

	################################################################################
	#
	# Library Class Header section - list of Library Class header files that are
	# provided by this package.
	#
	################################################################################
	[LibraryClasses]
	#
	# North Cluster
	#
	QNCAccessLib\|QuarkNorthCluster/Include/Library/QNCAccessLib.h
	IntelQNCLib\|QuarkNorthCluster/Include/Library/IntelQNCLib.h
	IohLib\|QuarkSouthCluster/Include/Library/IohLib.h
	I2cLib\|QuarkSouthCluster/Include/Library/I2cLib.h

	################################################################################
	#
	# Global Guid Definition section - list of Global Guid C Name Data Structures
	# that are provided by this package.
	#
	################################################################################
	[Guids]
	#
	# North Cluster
	#
	gEfiQuarkNcSocIdTokenSpaceGuid = { 0xca452c6a, 0xdf0c, 0x4dc9, { 0x82, 0xfb, 0xea, 0xe2, 0xab, 0x31, 0x29, 0x46 }}
	gQncS3CodeInLockBoxGuid = { 0x1f18c5b3, 0x29ed, 0x4d9e, {0xa5, 0x4, 0x6d, 0x97, 0x8e, 0x7e, 0xd5, 0x69}}
	gQncS3ContextInLockBoxGuid = { 0xe5769ea9, 0xe706, 0x454b, {0x95, 0x7f, 0xaf, 0xc6, 0xdb, 0x4b, 0x8a, 0xd}}

	#
	# South Cluster
	#
	gEfiQuarkSCSocIdTokenSpaceGuid = { 0xef251b71, 0xceed, 0x484e, { 0x82, 0xe3, 0x3a, 0x1f, 0x34, 0xf5, 0x12, 0xe2 }}

	################################################################################
	#
	# Global Ppi Definition section - list of Global Ppi C Name Data Structures
	# that are provided by this package.
	#
	################################################################################
	[Ppis]
	#
	# North Cluster
	#
	gQNCMemoryInitPpiGuid = { 0x21ff1fee, 0xd33a, 0x4fce, { 0xa6, 0x5e, 0x95, 0x5e, 0xa3, 0xc4, 0x1f, 0x40}}

	################################################################################
	#
	# Global Protocols Definition section - list of Global Protocols C Name Data
	# Structures that are provided by this package.
	#
	################################################################################
	[Protocols]
	#
	# North Cluster
	#
	gEfiPlatformPolicyProtocolGuid = { 0x2977064F, 0xAB96, 0x4FA9, { 0x85, 0x45, 0xF9, 0xC4, 0x02, 0x51, 0xE0, 0x7F }}
	gEfiSmmIchnDispatch2ProtocolGuid = { 0xadf3a128, 0x416d, 0x4060, { 0x8d, 0xdf, 0x30, 0xa1, 0xd7, 0xaa, 0xb6, 0x99 }}
	gEfiSpiProtocolGuid = { 0x1156efc6, 0xea32, 0x4396, { 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 }}
	gEfiSmmSpiProtocolGuid = { 0xD9072C35, 0xEB8F, 0x43ad, { 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 }}
	gEfiQncS3SupportProtocolGuid = { 0xe287d20b, 0xd897, 0x4e1e, { 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 }}

	#
	# South Cluster
	#
	gEfiSDHostIoProtocolGuid = {0xb63f8ec7, 0xa9c9, 0x4472, {0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51}}

	################################################################################
	#
	# PCD Declarations section - list of all PCDs Declared by this Package
	# Only this package should be providing the
	# declaration, other packages should not.
	#
	################################################################################

	[PcdsFeatureFlag]
	#
	# North Cluster
	#
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddressFixed\|TRUE\|BOOLEAN\|0x10000001

	#
	# South Cluster
	#
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdEhciRecoveryEnabled\|FALSE\|BOOLEAN\|0x10000003
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdI2CFastModeEnabled\|FALSE\|BOOLEAN\|0x10000005

	#
	# Feature Flag equivalent to linux SDHCI_QUIRK_NO_HISPD_BIT to stop
	# setting of SD HCI hi_spd_en bit in HOST_CTL register.
	#
	# Alway TRUE ie high speed enable bit must never
	# be set so we stay within SD interface Setup/Hold time.
	#
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdSdHciQuirkNoHiSpd\|TRUE\|BOOLEAN\|0x10000004

	[PcdsFixedAtBuild]
	#
	# North Cluster
	#

	# Values of Io Port Base Address, MMIO base address and space size.
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress\|0x1000\|UINT16\|0x10000200
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress\|0x1010\|UINT16\|0x10000201
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoLVL2\|0x1014\|UINT16\|0x10000202

	gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress\|0x1080\|UINT16\|0x10000205
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress\|0x1100\|UINT16\|0x10000206
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddress\|0x1040\|UINT16\|0x10000207
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress\|0x1140\|UINT16\|0x10000209

	gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress\|0xFED1C000\|UINT64\|0x1000020B
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress\|0xFEC00000\|UINT64\|0x1000020C

	gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicSize\|0x1000\|UINT64\|0x1000020D
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioSize\|0x4000\|UINT64\|0x1000020E

	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize\|0x02000000\|UINT64\|0x1000020F
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetBaseAddress\|0xFED00000\|UINT64\|0x10000210
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetSize\|0x400\|UINT64\|0x10000211
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdTSegSize\|0x200000\|UINT32\|0x10000212

	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoBase\|0x2000\|UINT16\|0x10000214
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoSize\|0xE000\|UINT16\|0x10000215
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base\|0x90000000\|UINT32\|0x1000021B
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Size\|0x20000000\|UINT32\|0x1000021C
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Base\|0xB0000000\|UINT64\|0x1000021D
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Size\|0x30000000\|UINT64\|0x1000021E

	# Values for programming Interrupt Route Configuration Registers:
	# Indicates which interrupt routing is connected to the INTA/B/C/D pins reported in the
	# "DxIP" register fields. This will be the internal routing, the device interrupt is connected
	# to the interrupt controller.
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent0IR\|0x0000\|UINT16\|0x10000223
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent1IR\|0x7654\|UINT16\|0x10000224
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent2IR\|0x0000\|UINT16\|0x10000225
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent3IR\|0x3210\|UINT16\|0x10000226

	gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationPort\|0xb2\|UINT16\|0x10000232
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmDataPort\|0xb3\|UINT16\|0x10000233
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationData\|0x55\|UINT8\|0x10000234
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPlatformSmbusAddrNum\|0x0\|UINT32\|0x10000235
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPlatformSmbusAddrTable\|0x0\|UINT64\|0x10000236

	gEfiQuarkNcSocIdTokenSpaceGuid.PcdESramMemorySize\|0x00080000\|UINT32\|0x10000240
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdDeviceEnables\|0x03\|UINT32\|0x10000237
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPcieRootPortConfiguration\|{0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00}\|VOID*\|0x10000239
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile \|{ 0x8B, 0xEA, 0x5E, 0xD7, 0xD2, 0x23, 0xD4, 0x4E, 0xBC, 0x4F, 0x57, 0x51, 0xD4, 0xA1, 0x8D, 0xCF }\|VOID*\|0x1000023A

	#
	# South Cluster
	#
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohI2cMmioBase\|0xA001F000\|UINT64\|0x20000005
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiP2PMemoryBaseAddress\|0xA0000000\|UINT32\|0x20000006
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiQNCUsbControllerMemoryBaseAddress\|0xA0010000\|UINT32\|0x20000007
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase\|0xA0020000\|UINT64\|0x20000008
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac0MmioBase\|0xA0024000\|UINT64\|0x20000009
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac1MmioBase\|0xA0028000\|UINT64\|0x2000000A

	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartBusNumber\|0x00\|UINT8\|0x20000013
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartDevNumber\|0x14\|UINT8\|0x20000014
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartFunctionNumber\|0x5\|UINT8\|0x20000001
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber\|0x00\|UINT8\|0x20000029
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber\|0x15\|UINT8\|0x2000002A
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber\|0x2\|UINT8\|0x2000002B
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister\|0x14\|UINT8\|0x2000002D

	[PcdsDynamic, PcdsDynamicEx]
	#
	# North Cluster
	#
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQncS3CodeInLockBoxAddress\|0\|UINT64\|0x30000026
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQncS3CodeInLockBoxSize\|0\|UINT64\|0x30000027

	## Intel(R) Quark(TM) Soc X1000 processor MRC Parameters. Default is for Galileo Gen 2 platform.<BR><BR>
	# @Prompt Intel(R) Quark(TM) Soc X1000 processor MRC Parameters.
	gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters\|{0x08, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\|VOID*\|0x40000001

	#
	# South Cluster
	#
	## MAC0 address for the Ethernet Controller in Intel(R) Quark(TM) Soc X1000 processor. Default is 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff.<BR><BR>
	# @Prompt Ethernet MAC 0 Address.
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0\|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\|VOID*\|0x50000001

	## MAC1 address for the Ethernet Controller in Intel(R) Quark(TM) Soc X1000 processor. Default is 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff.<BR><BR>
	# @Prompt Ethernet MAC 1 Address.
	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1\|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\|VOID*\|0x50000002