#/** @file | |
# ARM processor package. | |
# | |
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> | |
# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved. | |
# | |
# This program and the accompanying materials | |
# are licensed and made available under the terms and conditions of the BSD License | |
# which accompanies this distribution. The full text of the license may be found at | |
# http://opensource.org/licenses/bsd-license.php | |
# | |
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
# | |
#**/ | |
[Defines] | |
DEC_SPECIFICATION = 0x00010005 | |
PACKAGE_NAME = ArmPkg | |
PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F | |
PACKAGE_VERSION = 0.1 | |
################################################################################ | |
# | |
# Include Section - list of Include Paths that are provided by this package. | |
# Comments are used for Keywords and Module Types. | |
# | |
# Supported Module Types: | |
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION | |
# | |
################################################################################ | |
[Includes.common] | |
Include # Root include for the package | |
[LibraryClasses.common] | |
ArmLib|Include/Library/ArmLib.h | |
ArmMmuLib|Include/Library/ArmMmuLib.h | |
SemihostLib|Include/Library/Semihosting.h | |
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h | |
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h | |
ArmGicArchLib|Include/Library/ArmGicArchLib.h | |
ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h | |
ArmSvcLib|Include/Library/ArmSvcLib.h | |
OpteeLib|Include/Library/OpteeLib.h | |
[Guids.common] | |
gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } } | |
## ARM MPCore table | |
# Include/Guid/ArmMpCoreInfo.h | |
gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} } | |
[Protocols.common] | |
## Arm System Control and Management Interface(SCMI) Base protocol | |
## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h | |
gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } } | |
## Arm System Control and Management Interface(SCMI) Clock management protocol | |
## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h | |
gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } } | |
## Arm System Control and Management Interface(SCMI) Clock management protocol | |
## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h | |
gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } } | |
[Ppis] | |
## Include/Ppi/ArmMpCoreInfo.h | |
gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} } | |
[PcdsFeatureFlag.common] | |
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001 | |
# On ARM Architecture with the Security Extension, the address for the | |
# Vector Table can be mapped anywhere in the memory map. It means we can | |
# point the Exception Vector Table to its location in CpuDxe. | |
# By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress) | |
gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022 | |
# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before | |
# it has been configured by the CPU DXE | |
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032 | |
# Define if the spin-table mechanism is used by the secondary cores when booting | |
# Linux (instead of PSCI) | |
gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033 | |
# Define if the GICv3 controller should use the GICv2 legacy | |
gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042 | |
# Whether to implement warm reboot for capsule update using a jump back to the | |
# PEI entry point with caches and interrupts disabled. | |
gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F | |
[PcdsFeatureFlag.ARM] | |
# Whether to map normal memory as non-shareable. FALSE is the safe choice, but | |
# TRUE may be appropriate to fix performance problems if you don't care about | |
# hardware coherency (i.e., no virtualization or cache coherent DMA) | |
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043 | |
[PcdsFixedAtBuild.common] | |
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006 | |
# This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file. | |
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor. | |
gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024 | |
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004 | |
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005 | |
# | |
# ARM Secure Firmware PCDs | |
# | |
gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015 | |
gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016 | |
gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F | |
gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030 | |
# | |
# ARM Hypervisor Firmware PCDs | |
# | |
gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A | |
gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B | |
gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C | |
gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D | |
# Use ClusterId + CoreId to identify the PrimaryCore | |
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031 | |
# The Primary Core is ClusterId[0] & CoreId[0] | |
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037 | |
# | |
# ARM L2x0 PCDs | |
# | |
gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B | |
# | |
# ARM Normal (or Non Secure) Firmware PCDs | |
# | |
gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C | |
gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E | |
# | |
# Value to add to a host address to obtain a device address, using | |
# unsigned 64-bit integer arithmetic on both ARM and AArch64. This | |
# means we can rely on truncation on overflow to specify negative | |
# offsets. | |
# | |
gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044 | |
[PcdsFixedAtBuild.common, PcdsPatchableInModule.common] | |
gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B | |
gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D | |
[PcdsFixedAtBuild.ARM] | |
# | |
# ARM Security Extension | |
# | |
# Secure Configuration Register | |
# - BIT0 : NS - Non Secure bit | |
# - BIT1 : IRQ Handler | |
# - BIT2 : FIQ Handler | |
# - BIT3 : EA - External Abort | |
# - BIT4 : FW - F bit writable | |
# - BIT5 : AW - A bit writable | |
# - BIT6 : nET - Not Early Termination | |
# - BIT7 : SCD - Secure Monitor Call Disable | |
# - BIT8 : HCE - Hyp Call enable | |
# - BIT9 : SIF - Secure Instruction Fetch | |
# 0x31 = NS | EA | FW | |
gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038 | |
# By default we do not do a transition to non-secure mode | |
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E | |
# The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory | |
gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020 | |
# If the fixed FDT address is not available, then it should be loaded below the kernel. | |
# The recommendation from the Linux kernel is to have the FDT below 16KB. | |
# (see the kernel doc: Documentation/arm/Booting) | |
gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023 | |
# The FDT blob must be loaded at a 64bit aligned address. | |
gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026 | |
# Non Secure Access Control Register | |
# - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality | |
# - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 | |
# - BIT11 : cp11 - Non-secure access to coprocessor 11 enable | |
# - BIT10 : cp10 - Non-secure access to coprocessor 10 enable | |
# 0xC00 = cp10 | cp11 | |
gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039 | |
[PcdsFixedAtBuild.AARCH64] | |
# | |
# AArch64 Security Extension | |
# | |
# Secure Configuration Register | |
# - BIT0 : NS - Non Secure bit | |
# - BIT1 : IRQ Handler | |
# - BIT2 : FIQ Handler | |
# - BIT3 : EA - External Abort | |
# - BIT4 : FW - F bit writable | |
# - BIT5 : AW - A bit writable | |
# - BIT6 : nET - Not Early Termination | |
# - BIT7 : SCD - Secure Monitor Call Disable | |
# - BIT8 : HCE - Hyp Call enable | |
# - BIT9 : SIF - Secure Instruction Fetch | |
# - BIT10: RW - Register width control for lower exception levels | |
# - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer | |
# - BIT12: TWI - Trap WFI | |
# - BIT13: TWE - Trap WFE | |
# 0x501 = NS | HCE | RW | |
gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038 | |
# By default we do transition to EL2 non-secure mode with Stack for EL2. | |
# Mode Description Bits | |
# NS EL2 SP2 all interrupts disabled = 0x3c9 | |
# NS EL1 SP1 all interrupts disabled = 0x3c5 | |
# Other modes include using SP0 or switching to Aarch32, but these are | |
# not currently supported. | |
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E | |
# If the fixed FDT address is not available, then it should be loaded above the kernel. | |
# The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB. | |
# (see the kernel doc: Documentation/arm64/booting.txt) | |
gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023 | |
# The FDT blob must be loaded at a 2MB aligned address. | |
gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026 | |
# | |
# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be | |
# redefined when using UEFI in a context of virtual machine. | |
# | |
[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common] | |
# System Memory (DRAM): These PCDs define the region of in-built system memory | |
# Some platforms can get DRAM extensions, these additional regions may be | |
# declared to UEFI using separate resource descriptor HOBs | |
gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029 | |
gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A | |
[PcdsFixedAtBuild.common, PcdsDynamic.common] | |
# | |
# ARM Architectural Timer | |
# | |
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034 | |
# ARM Architectural Timer Interrupt(GIC PPI) numbers | |
gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035 | |
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036 | |
gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040 | |
gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041 | |
# | |
# ARM Generic Watchdog | |
# | |
gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007 | |
gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008 | |
gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009 | |
# | |
# ARM Generic Interrupt Controller | |
# | |
gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C | |
# Base address for the GIC Redistributor region that contains the boot CPU | |
gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E | |
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D | |
gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025 | |
# | |
# Bases, sizes and translation offsets of IO and MMIO spaces, respectively. | |
# Note that "IO" is just another MMIO range that simulates IO space; there | |
# are no special instructions to access it. | |
# | |
# The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are | |
# specific to their containing address spaces. In order to get the physical | |
# address for the CPU, for a given access, the respective translation value | |
# has to be added. | |
# | |
# The translations always have to be initialized like this, using UINT64: | |
# | |
# UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space | |
# UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space | |
# UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space | |
# | |
# PcdPciIoTranslation = IoCpuBase - PcdPciIoBase; | |
# PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base; | |
# PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base; | |
# | |
# because (a) the target address space (ie. the cpu-physical space) is | |
# 64-bit, and (b) the translation values are meant as offsets for *modular* | |
# arithmetic. | |
# | |
# Accordingly, the translation itself needs to be implemented as: | |
# | |
# UINT64 UntranslatedIoAddress; // input parameter | |
# UINT32 UntranslatedMmio32Address; // input parameter | |
# UINT64 UntranslatedMmio64Address; // input parameter | |
# | |
# UINT64 TranslatedIoAddress; // output parameter | |
# UINT64 TranslatedMmio32Address; // output parameter | |
# UINT64 TranslatedMmio64Address; // output parameter | |
# | |
# TranslatedIoAddress = UntranslatedIoAddress + | |
# PcdPciIoTranslation; | |
# TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address + | |
# PcdPciMmio32Translation; | |
# TranslatedMmio64Address = UntranslatedMmio64Address + | |
# PcdPciMmio64Translation; | |
# | |
# The modular arithmetic performed in UINT64 ensures that the translation | |
# works correctly regardless of the relation between IoCpuBase and | |
# PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and | |
# PcdPciMmio64Base. | |
# | |
gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050 | |
gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051 | |
gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052 | |
gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053 | |
gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054 | |
gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055 | |
gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056 | |
gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057 | |
gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058 | |
# | |
# Inclusive range of allowed PCI buses. | |
# | |
gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059 | |
gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A |