| commit | da57acb4c396cfc978c0652fec9dfb17a4f67ad8 | [log] [tgz] |
|---|---|---|
| author | Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> | Wed Sep 24 00:49:11 2025 -0700 |
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | Tue Sep 30 14:45:37 2025 +0800 |
| tree | b7ab218286786f6f97078e0f3dfa533e1b151d45 | |
| parent | 060ed1bbbe0fd1a8583d09d7766cf3f194b23edc [diff] |
arch: arm: socfpga: Configure USB3 System Manager registers For successful reset staggering pulse operation, reset pulse override bit is set. Port overcurrent bit 1, which in reality reflects PIPE power present signal is set to avoid giving false information of Vbus status to HPS controller. Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>