/*
 * Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Refer docs/README.imxmage for more details about how-to configure
 * and create imximage boot image
 *
 * The syntax is taken as close as possible with the kwbimage
 */

#include <config.h>

/* image version */

IMAGE_VERSION 2

/*
 * Boot Device : sd
 */

BOOT_FROM	sd

/*
 * Secure boot support
 */
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
#endif

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
 */

/* Enable OCRAM EPDC */
DATA 4 0x30340004 0x4F400005

/* =============================================================================
 * DDR Controller Registers
 * =============================================================================
 * Memory type:           DDR3
 * Manufacturer:          ISSI
 * Device Part Number:    IS43TR16256AL-125KBL
 * Clock Freq.:           533MHz
 * Density per CS in Gb:  4
 * Chip Selects used:     1
 * Number of Banks:       8
 * Row address:          15
 * Column address:       10
 * Data bus width:       16
 * ROW-BANK interleave:  ENABLED
 * =============================================================================
 */

DATA 4 0x30391000 0x00000002    // deassert presetn
DATA 4 0x307A0000 0x01041001    // DDRC_MSTR
DATA 4 0x307A0064 0x00400046    // DDRC_RFSHTMG
DATA 4 0x307a0490 0x00000001    // DDRC_PCTRL_0
DATA 4 0x307A00D4 0x00690000    // DDRC_INIT1
DATA 4 0x307A00D0 0x00020083    // DDRC_INIT0
DATA 4 0x307A00DC 0x09300004    // DDRC_INIT3
DATA 4 0x307A00E0 0x04080000    // DDRC_INIT4
DATA 4 0x307A00E4 0x00100004    // DDRC_INIT5
DATA 4 0x307A00F4 0x0000033F    // DDRC_RANKCTL
DATA 4 0x307A0100 0x090B1109    // DDRC_DRAMTMG0
DATA 4 0x307A0104 0x0007020D    // DDRC_DRAMTMG1
DATA 4 0x307A0108 0x03040407    // DDRC_DRAMTMG2
DATA 4 0x307A010C 0x00002006    // DDRC_DRAMTMG3
DATA 4 0x307A0110 0x04020205    // DDRC_DRAMTMG4
DATA 4 0x307A0114 0x03030202    // DDRC_DRAMTMG5
DATA 4 0x307A0120 0x00000803    // DDRC_DRAMTMG8
DATA 4 0x307A0180 0x00800020    // DDRC_ZQCTL0
DATA 4 0x307A0190 0x02098204    // DDRC_DFITMG0
DATA 4 0x307A0194 0x00030303    // DDRC_DFITMG1
DATA 4 0x307A01A0 0x80400003    // DDRC_DFIUPD0
DATA 4 0x307A01A4 0x00100020    // DDRC_DFIUPD1
DATA 4 0x307A01A8 0x80100004    // DDRC_DFIUPD2
DATA 4 0x307A0200 0x00000015    // DDRC_ADDRMAP0
DATA 4 0x307A0204 0x00070707    // DDRC_ADDRMAP1
DATA 4 0x307A0210 0x00000F0F    // DDRC_ADDRMAP4
DATA 4 0x307A0214 0x06060606    // DDRC_ADDRMAP5
DATA 4 0x307A0218 0x0F060606    // DDRC_ADDRMAP6
DATA 4 0x307A0240 0x06000604    // DDRC_ODTCFG
DATA 4 0x307A0244 0x00000001    // DDRC_ODTMAP


/* =============================================================================
 * PHY Control Register
 * =============================================================================
 */

DATA 4 0x30391000 0x00000000    // deassert presetn
DATA 4 0x30790000 0x17420F40    // DDR_PHY_PHY_CON0
DATA 4 0x30790004 0x10210100    // DDR_PHY_PHY_CON1
DATA 4 0x30790010 0x00060807    // DDR_PHY_PHY_CON4
DATA 4 0x307900B0 0x1010007E    // DDR_PHY_MDLL_CON0
DATA 4 0x3079009C 0x00000D6E    // DDR_PHY_DRVDS_CON0
DATA 4 0x30790030 0x08080808    // DDR_PHY_OFFSET_WR_CON0
DATA 4 0x30790020 0x08080808    // DDR_PHY_OFFSET_RD_CON0
DATA 4 0x30790050 0x01000010    // DDR_PHY_OFFSETD_CON0
DATA 4 0x30790050 0x00000010    // DDR_PHY_OFFSETD_CON0
DATA 4 0x30790018 0x0000000F    // DDR_PHY_LP_CON0
DATA 4 0x307900C0 0x0E407304    // DDR_PHY_ZQ_CON0 - Start Manual ZQ
DATA 4 0x307900C0 0x0E447304
DATA 4 0x307900C0 0x0E447306
DATA 4 0x307900C0 0x0E447304    // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
DATA 4 0x307900C0 0x0E407304    // DDR_PHY_ZQ_CON0 - End Manual ZQ


/* =============================================================================
 * Final Initialization start sequence
 * =============================================================================
 */

DATA 4 0x30384130 0x00000000    // Disable Clock
DATA 4 0x30340020 0x00000178    // IOMUX_GRP_GRP8 - Start input to PHY
DATA 4 0x30384130 0x00000002    // Enable Clock
/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */