)]}'
{
  "commit": "da57acb4c396cfc978c0652fec9dfb17a4f67ad8",
  "tree": "b7ab218286786f6f97078e0f3dfa533e1b151d45",
  "parents": [
    "060ed1bbbe0fd1a8583d09d7766cf3f194b23edc"
  ],
  "author": {
    "name": "Naresh Kumar Ravulapalli",
    "email": "nareshkumar.ravulapalli@altera.com",
    "time": "Wed Sep 24 00:49:11 2025 -0700"
  },
  "committer": {
    "name": "Tien Fong Chee",
    "email": "tien.fong.chee@intel.com",
    "time": "Tue Sep 30 14:45:37 2025 +0800"
  },
  "message": "arch: arm: socfpga: Configure USB3 System Manager registers\n\nFor successful reset staggering pulse operation, reset pulse\noverride bit is set. Port overcurrent bit 1, which in reality\nreflects PIPE power present signal is set to avoid giving\nfalse information of Vbus status to HPS controller.\n\nSigned-off-by: Naresh Kumar Ravulapalli \u003cnareshkumar.ravulapalli@altera.com\u003e\nReviewed-by: Tien Fong Chee \u003ctien.fong.chee@altera.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "054a28d845da82ec60c5d7f2bf0ccde78f654b5b",
      "old_mode": 33188,
      "old_path": "arch/arm/mach-socfpga/include/mach/system_manager_soc64.h",
      "new_id": "f768a3a55cb2d50240f65d10f6052680175ed5e8",
      "new_mode": 33188,
      "new_path": "arch/arm/mach-socfpga/include/mach/system_manager_soc64.h"
    },
    {
      "type": "modify",
      "old_id": "4b42158be9d9731eaa02939f33a4fc3961ec8b68",
      "old_mode": 33188,
      "old_path": "arch/arm/mach-socfpga/system_manager_soc64.c",
      "new_id": "913f93c8f94d8eed319f52161a9e63bedab05eea",
      "new_mode": 33188,
      "new_path": "arch/arm/mach-socfpga/system_manager_soc64.c"
    }
  ]
}