diff --git a/Kconfig b/Kconfig
index 7bdb536..301ebf8 100644
--- a/Kconfig
+++ b/Kconfig
@@ -147,7 +147,7 @@
 
 config SYS_MALLOC_LEN
 	hex "Define memory for Dynamic allocation"
-	depends on ARCH_ZYNQ || ARCH_VERSAL
+	depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP
 	help
 	  This defines memory to be allocated for Dynamic allocation
 	  TODO: Use for other architectures
diff --git a/MAINTAINERS b/MAINTAINERS
index c41bc89..3662579 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -519,6 +519,7 @@
 M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-fsl-qoriq.git
+F:	drivers/watchdog/sp805_wdt.c
 
 I2C
 M:	Heiko Schocher <hs@denx.de>
diff --git a/README b/README
index fd1e17c..e2efef0 100644
--- a/README
+++ b/README
@@ -3294,12 +3294,12 @@
 
 - CONFIG_SYS_FMAN_FW_ADDR
 	The address in the storage device where the FMAN microcode is located.  The
-	meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+	meaning of this address depends on which CONFIG_SYS_QE_FMAN_FW_IN_xxx macro
 	is also specified.
 
 - CONFIG_SYS_QE_FW_ADDR
 	The address in the storage device where the QE microcode is located.  The
-	meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+	meaning of this address depends on which CONFIG_SYS_QE_FMAN_FW_IN_xxx macro
 	is also specified.
 
 - CONFIG_SYS_QE_FMAN_FW_LENGTH
diff --git a/arch/Kconfig b/arch/Kconfig
index 239289b..e574b0d 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -28,6 +28,7 @@
 	select HAVE_PRIVATE_LIBGCC
 	select SYS_BOOT_GET_CMDLINE
 	select SYS_BOOT_GET_KBD
+	select SUPPORT_OF_CONTROL
 
 config MICROBLAZE
 	bool "MicroBlaze architecture"
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 00be3d1..01ff57c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1262,6 +1262,28 @@
 	  development platform that supports the QorIQ LS1012A
 	  Layerscape Architecture processor.
 
+config TARGET_LS1028AQDS
+	bool "Support ls1028aqds"
+	select ARCH_LS1028A
+	select ARM64
+	select ARMV8_MULTIENTRY
+	help
+	  Support for Freescale LS1028AQDS platform
+	  The LS1028A Development System (QDS) is a high-performance
+	  development platform that supports the QorIQ LS1028A
+	  Layerscape Architecture processor.
+
+config TARGET_LS1028ARDB
+	bool "Support ls1028ardb"
+	select ARCH_LS1028A
+	select ARM64
+	select ARMV8_MULTIENTRY
+	help
+	  Support for Freescale LS1028ARDB platform
+	  The LS1028A Development System (RDB) is a high-performance
+	  development platform that supports the QorIQ LS1028A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1088ARDB
 	bool "Support ls1088ardb"
 	select ARCH_LS1088A
@@ -1466,6 +1488,7 @@
 	imply CMD_DM
 	imply CMD_POWEROFF
 	imply ENV_VARS_UBOOT_RUNTIME_CONFIG
+	imply USE_PREBOOT
 	help
 	  Support for STM32MP SoC family developed by STMicroelectronics,
 	  MPUs based on ARM cortex A core
@@ -1666,6 +1689,7 @@
 source "board/freescale/ls2080aqds/Kconfig"
 source "board/freescale/ls2080ardb/Kconfig"
 source "board/freescale/ls1088a/Kconfig"
+source "board/freescale/ls1028a/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index 3db31c0..5de6305 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -49,6 +49,9 @@
 
 ulong timer_get_boot_us(void)
 {
+	if (!gd->arch.timer_rate_hz)
+		timer_init();
+
 	return lldiv(get_ticks(), gd->arch.timer_rate_hz / 1000000);
 }
 
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 7405c3a..8a97d5b 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -104,6 +104,7 @@
 		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
 		   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
 		   !TARGET_LS1012AFRWY && \
+		   !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
 		   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f48481f..a843c1e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -20,6 +20,40 @@
 	select SYS_I2C_MXC_I2C2
 	imply PANIC_HANG
 
+config ARCH_LS1028A
+	bool
+	select ARMV8_SET_SMPEN
+	select FSL_LSCH3
+	select NXP_LSCH3_2
+	select SYS_FSL_HAS_CCI400
+	select SYS_FSL_SRDS_1
+	select SYS_HAS_SERDES
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_LE
+	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_HAS_DDR3
+	select SYS_FSL_HAS_DDR4
+	select SYS_FSL_HAS_SEC
+	select SYS_FSL_SEC_COMPAT_5
+	select SYS_FSL_SEC_LE
+	select FSL_TZASC_1
+	select ARCH_EARLY_INIT_R
+	select BOARD_EARLY_INIT_F
+	select SYS_I2C_MXC
+	select SYS_I2C_MXC_I2C1
+	select SYS_I2C_MXC_I2C2
+	select SYS_I2C_MXC_I2C3
+	select SYS_I2C_MXC_I2C4
+	select SYS_I2C_MXC_I2C5
+	select SYS_I2C_MXC_I2C6
+	select SYS_I2C_MXC_I2C7
+	select SYS_I2C_MXC_I2C8
+	select SYS_FSL_ERRATUM_A009007
+	select SYS_FSL_ERRATUM_A008514 if !TFABOOT
+	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
+	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+	imply PANIC_HANG
+
 config ARCH_LS1043A
 	bool
 	select ARMV8_SET_SMPEN
@@ -242,8 +276,9 @@
 
 config FSL_PCIE_COMPAT
 	string "PCIe compatible of Kernel DT"
-	depends on PCIE_LAYERSCAPE
+	depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
 	default "fsl,ls1012a-pcie" if ARCH_LS1012A
+	default "fsl,ls1028a-pcie" if ARCH_LS1028A
 	default "fsl,ls1043a-pcie" if ARCH_LS1043A
 	default "fsl,ls1046a-pcie" if ARCH_LS1046A
 	default "fsl,ls2080a-pcie" if ARCH_LS2080A
@@ -343,6 +378,7 @@
 
 config MAX_CPUS
 	int "Maximum number of CPUs permitted for Layerscape"
+	default 2 if ARCH_LS1028A
 	default 4 if ARCH_LS1043A
 	default 4 if ARCH_LS1046A
 	default 16 if ARCH_LS2080A
@@ -377,7 +413,7 @@
 config SYS_CCI400_OFFSET
 	hex "Offset for CCI400 base"
 	depends on SYS_FSL_HAS_CCI400
-	default 0x3090000 if ARCH_LS1088A
+	default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
 	default 0x180000 if FSL_LSCH2
 	help
 	  Offset for CCI400 base
@@ -446,6 +482,7 @@
 
 config SYS_FSL_PCLK_DIV
 	int "Platform clock divider"
+	default 1 if ARCH_LS1028A
 	default 1 if ARCH_LS1043A
 	default 1 if ARCH_LS1046A
 	default 1 if ARCH_LS1088A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index e9bc987..a8d3cf9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -48,3 +48,7 @@
 ifneq ($(CONFIG_ARCH_LS1088A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
 endif
+
+ifneq ($(CONFIG_ARCH_LS1028A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 12d709e..edb9c96 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -58,6 +58,7 @@
 	CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
 	CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
 	CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+	CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
 	CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
 	CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
 	CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
@@ -246,18 +247,34 @@
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 	  CONFIG_SYS_PCIE3_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+#endif
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 	  CONFIG_SYS_PCIE4_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 #endif
+#ifdef SYS_PCIE5_PHYS_ADDR
+	{ SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
+	  SYS_PCIE5_PHYS_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#endif
+#ifdef SYS_PCIE6_PHYS_ADDR
+	{ SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
+	  SYS_PCIE6_PHYS_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#endif
 	{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 	  CONFIG_SYS_FSL_WRIOP1_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@ -341,11 +358,13 @@
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 	  CONFIG_SYS_PCIE3_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
+#endif
 	{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 	  CONFIG_SYS_FSL_DRAM_SIZE3,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
@@ -448,16 +467,20 @@
 				final_map[i].virt = 0x2800000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 			case CONFIG_SYS_PCIE3_PHYS_ADDR:
 				final_map[i].phys = 0x3000000000ULL;
 				final_map[i].virt = 0x3000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
+#endif
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 			case CONFIG_SYS_PCIE4_PHYS_ADDR:
 				final_map[i].phys = 0x3800000000ULL;
 				final_map[i].virt = 0x3800000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
+#endif
 			default:
 				break;
 			}
@@ -785,12 +808,8 @@
 	if (prio)
 		return ENVL_UNKNOWN;
 
-#ifdef CONFIG_CHAIN_OF_TRUST
-	/* Check Boot Mode
-	 * If Boot Mode is Secure, return ENVL_NOWHERE
-	 */
-	if (fsl_check_boot_mode_secure() == 1)
-		goto done;
+#ifdef	CONFIG_ENV_IS_NOWHERE
+	return env_loc;
 #endif
 
 	switch (src) {
@@ -820,9 +839,6 @@
 		break;
 	}
 
-#ifdef CONFIG_CHAIN_OF_TRUST
-done:
-#endif
 	return env_loc;
 }
 #endif	/* CONFIG_TFABOOT */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index a0e2621..ad55573 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -8,6 +8,7 @@
 	6. LS2088A
 	7. LS2081A
 	8. LX2160A
+	9. LS1028A
 
 LS1043A
 ---------
@@ -328,3 +329,53 @@
 
 2)LX2080A, few difference w.r.t. LX2160A:
        a) Eight 64-bit ARM v8 Cortex-A72 CPUs
+
+
+LS1028A
+--------
+The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with
+a GPU and LCD controller, as well as two TSN-enabled Ethernet controllers and
+a TSNenabled 4-port switch.
+
+The high performance Cortex-A72 cores, performing above 16,000 CoreMarks,
+combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and
+Octal/Quad SPI interfaces provide capabilities for a number of industrial and
+embedded applications. The device provides excellent integration with the
+new Time-Sensitive Networking standard, and enables a number of
+TSN applications.
+
+The LS1028A SoC includes the following function and features:
+ - Two 64-bit ARM v8 A72 CPUs
+ - Cache Coherent interconnect (CCI-400)
+ - One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC
+ - eDP/Displayport interface
+ - Graphics processing unit
+ - One Configurable x4 SerDes
+ - Ethernet interfaces
+   - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one
+   ethernet MAC supporting 1G, 100M, 10M.
+   - Switched: TSN IP to support four 2.5/1G interfaces.
+   - None of the MACs support MACSEC
+   - Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII
+   - Support for 10G-SXGMII and 10G-QXGMII.
+   - Energy efficient Ethernet support (802.3az)
+   - IEEE 1588 support
+  - High-speed peripheral interfaces
+    - Two PCIe 3.0 controllers, one supporting x4 operation
+    - One serial ATA (SATA 3.0) controller
+  - Additional peripheral interfaces
+    - Two high-speed USB 2.0/3.0 controllers with integrated PHY each
+      supporting host or device modes
+    - Two Enhanced secure digital host controllers (SD/SDIO/eMMC)
+    - Two Serial peripheral interface (SPI) controllers
+    - Eight I2C controllers
+    - Two UART controllers
+    - Additional six Industrual UARTs (LPUART).
+    - One FlexSPI controller
+    - General Purpose IO (GPIO)
+    - Two CAN-FD interfaces
+    - Eight Flextimers with PWM I/O
+  - Support for hardware virtualization and partitioning enforcement
+  - Layerscape Trust Architecture
+  - Service Processor (SP) provides pre-boot initialization and secure-boot
+    capabilities
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
new file mode 100644
index 0000000..ef598c4
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+	u8 rcw_lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} },
+	{0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} },
+	{0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} },
+	{0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} },
+	{0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
+	{0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },
+	{0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },
+	{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
+	{}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0ec7bc9..31ef2b6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -329,6 +329,8 @@
 	fsl-ls2088a-rdb-qspi.dtb \
 	fsl-ls1088a-rdb.dtb \
 	fsl-ls1088a-qds.dtb \
+	fsl-ls1028a-rdb.dtb \
+	fsl-ls1028a-qds.dtb \
 	fsl-lx2160a-rdb.dtb \
 	fsl-lx2160a-qds.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index f22cbf4..1125e57 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -136,7 +136,9 @@
 
 		sata: sata@3200000 {
 			compatible = "fsl,ls1012a-ahci";
-			reg = <0x0 0x3200000 0x0 0x10000>;
+			reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+			       0x0 0x20140520 0x0 0x4>;	 /* ecc sata addr */
+			reg-names = "sata-base", "ecc-addr";
 			interrupts = <0 69 4>;
 			clocks = <&clockgen 4 0>;
 			status = "disabled";
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts
new file mode 100644
index 0000000..46a0419
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028AQDS device tree source
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1028a.dtsi"
+
+/ {
+	model = "NXP Layerscape 1028a QDS Board";
+	compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
+};
+
+&dspi0 {
+	status = "okay";
+};
+
+&dspi1 {
+	status = "okay";
+};
+
+&dspi2 {
+	status = "okay";
+};
+
+&esdhc0 {
+	status = "okay";
+};
+
+&esdhc1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
new file mode 100644
index 0000000..932cfa2
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028ARDB device tree source
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1028a.dtsi"
+
+/ {
+	model = "NXP Layerscape 1028a RDB Board";
+	compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
+};
+
+&dspi0 {
+	status = "okay";
+};
+
+&dspi1 {
+	status = "okay";
+};
+
+&dspi2 {
+	status = "okay";
+};
+
+&esdhc0 {
+	status = "okay";
+};
+
+&esdhc1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
new file mode 100644
index 0000000..e6a443a
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028a SOC common device tree source
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/ {
+	compatible = "fsl,ls1028a";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	sysclk: sysclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "sysclk";
+	};
+
+	clockgen: clocking@1300000 {
+		compatible = "fsl,ls1028a-clockgen";
+		reg = <0x0 0x1300000 0x0 0xa0000>;
+		#clock-cells = <2>;
+		clocks = <&sysclk>;
+	};
+
+	memory@01080000 {
+		device_type = "memory";
+		reg = <0x00000000 0x01080000 0 0x80000000>;
+		      /* DRAM space - 1, size : 2 GB DRAM */
+	};
+
+	gic: interrupt-controller@6000000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+			  <0x0 0x06040000 0 0x40000>;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <1 9 0x4>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
+			     <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
+			     <1 11 0x8>, /* Virtual PPI, active-low */
+			     <1 10 0x8>; /* Hypervisor PPI, active-low */
+	};
+
+	fspi: flexspi@20C0000 {
+		compatible = "nxp,dn-fspi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x20C0000 0x0 0x10000>,
+			<0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/
+		reg-names = "FSPI", "FSPI-memory";
+		num-cs = <1>;
+		status = "disabled";
+	};
+
+	serial0: serial@21c0500 {
+		device_type = "serial";
+		compatible = "fsl,ns16550", "ns16550a";
+		reg = <0x0 0x21c0500 0x0 0x100>;
+		interrupts = <0 32 0x1>; /* edge triggered */
+		status = "disabled";
+	};
+
+	serial1: serial@21c0600 {
+		device_type = "serial";
+		compatible = "fsl,ns16550", "ns16550a";
+		reg = <0x0 0x21c0600 0x0 0x100>;
+		interrupts = <0 32 0x1>; /* edge triggered */
+		status = "disabled";
+	};
+
+	pcie@3400000 {
+	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
+	       reg = <0x00 0x03400000 0x0 0x80000
+		       0x00 0x03480000 0x0 0x40000   /* lut registers */
+		       0x00 0x034c0000 0x0 0x40000  /* pf controls registers */
+		       0x80 0x00000000 0x0 0x20000>; /* configuration space */
+	       reg-names = "dbi", "lut", "ctrl", "config";
+	       #address-cells = <3>;
+	       #size-cells = <2>;
+	       device_type = "pci";
+	       num-lanes = <4>;
+	       bus-range = <0x0 0xff>;
+	       ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000   /* downstream I/O */
+		       0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie@3500000 {
+	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
+	       reg = <0x00 0x03500000 0x0 0x80000
+		       0x00 0x03580000 0x0 0x40000   /* lut registers */
+		       0x00 0x035c0000 0x0 0x40000  /* pf controls registers */
+		       0x88 0x00000000 0x0 0x20000>; /* configuration space */
+	       reg-names = "dbi", "lut", "ctrl", "config";
+	       #address-cells = <3>;
+	       #size-cells = <2>;
+	       device_type = "pci";
+	       num-lanes = <4>;
+	       bus-range = <0x0 0xff>;
+	       ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000   /* downstream I/O */
+		       0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	i2c0: i2c@2000000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2000000 0x0 0x10000>;
+		interrupts = <0 34 0x4>;
+		clock-names = "i2c";
+		clocks = <&clockgen 4 0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@2010000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2010000 0x0 0x10000>;
+		interrupts = <0 34 0x4>;
+		clock-names = "i2c";
+		clocks = <&clockgen 4 0>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@2020000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2020000 0x0 0x10000>;
+		interrupts = <0 35 0x4>;
+		clock-names = "i2c";
+		clocks = <&clockgen 4 0>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@2030000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2030000 0x0 0x10000>;
+		interrupts = <0 35 0x4>;
+		clock-names = "i2c";
+		clocks = <&clockgen 4 0>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@2040000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2040000 0x0 0x10000>;
+		interrupts = <0 74 0x4>;
+		clock-names = "i2c";
+		clocks = <&clockgen 4 0>;
+		status = "disabled";
+	};
+
+	i2c5: i2c@2050000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2050000 0x0 0x10000>;
+		interrupts = <0 74 0x4>;
+		clock-names = "i2c";
+		clocks = <&clockgen 4 0>;
+		status = "disabled";
+	};
+
+	i2c6: i2c@2060000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2060000 0x0 0x10000>;
+		interrupts = <0 75 0x4>;
+		clock-names = "i2c";
+		clocks = <&clockgen 4 0>;
+		status = "disabled";
+	};
+
+	i2c7: i2c@2070000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2070000 0x0 0x10000>;
+		interrupts = <0 75 0x4>;
+		clock-names = "i2c";
+		clocks = <&clockgen 4 0>;
+		status = "disabled";
+	};
+
+	usb1: usb3@3100000 {
+		compatible = "fsl,layerscape-dwc3";
+		reg = <0x0 0x3100000 0x0 0x10000>;
+		interrupts = <0 80 0x4>;
+		dr_mode = "host";
+		status = "disabled";
+	};
+
+	usb2: usb3@3110000 {
+		compatible = "fsl,layerscape-dwc3";
+		reg = <0x0 0x3110000 0x0 0x10000>;
+		interrupts = <0 81 0x4>;
+		dr_mode = "host";
+		status = "disabled";
+	};
+
+	dspi0: dspi@2100000 {
+		compatible = "fsl,vf610-dspi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2100000 0x0 0x10000>;
+		interrupts = <0 26 0x4>;
+		clock-names = "dspi";
+		clocks = <&clockgen 4 0>;
+		num-cs = <5>;
+		litte-endian;
+		status = "disabled";
+	};
+
+	dspi1: dspi@2110000 {
+		compatible = "fsl,vf610-dspi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2110000 0x0 0x10000>;
+		interrupts = <0 26 0x4>;
+		clock-names = "dspi";
+		clocks = <&clockgen 4 0>;
+		num-cs = <5>;
+		little-endian;
+		status = "disabled";
+	};
+
+	dspi2: dspi@2120000 {
+		compatible = "fsl,vf610-dspi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2120000 0x0 0x10000>;
+		interrupts = <0 26 0x4>;
+		clock-names = "dspi";
+		clocks = <&clockgen 4 0>;
+		num-cs = <5>;
+		little-endian;
+		status = "disabled";
+	};
+
+	esdhc0: esdhc@2140000 {
+		compatible = "fsl,esdhc";
+		reg = <0x0 0x2140000 0x0 0x10000>;
+		interrupts = <0 28 0x4>;
+		big-endian;
+		bus-width = <4>;
+		status = "disabled";
+	};
+
+	esdhc1: esdhc@2150000 {
+		compatible = "fsl,esdhc";
+		reg = <0x0 0x2150000 0x0 0x10000>;
+		interrupts = <0 63 0x4>;
+		big-endian;
+		non-removable;
+		bus-width = <4>;
+		status = "disabled";
+	};
+
+	sata: sata@3200000 {
+		compatible = "fsl,ls1028a-ahci";
+		reg = <0x0 0x3200000 0x0 0x10000>;
+		interrupts = <0 133 4>;
+		clocks = <&clockgen 4 1>;
+		status = "disabled";
+	};
+
+	cluster1_core0_watchdog: wdt@c000000 {
+		compatible = "arm,sp805-wdt";
+		reg = <0x0 0xc000000 0x0 0x1000>;
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index bb70992..b159c3c 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -290,7 +290,9 @@
 
 		sata: sata@3200000 {
 			compatible = "fsl,ls1043a-ahci";
-			reg = <0x0 0x3200000 0x0 0x10000>;
+			reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+			       0x0 0x20140520 0x0 0x4>;  /* ecc sata addr*/
+			reg-names = "sata-base", "ecc-addr";
 			interrupts = <0 69 4>;
 			clocks = <&clockgen 4 0>;
 			status = "disabled";
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 5ac10e0..fdf93fd 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -294,7 +294,9 @@
 
 		sata: sata@3200000 {
 			compatible = "fsl,ls1046a-ahci";
-			reg = <0x0 0x3200000 0x0 0x10000>;
+			reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+			       0x0 0x20140520 0x0 0x4>;	 /* ecc sata addr*/
+			reg-names = "sata-base", "ecc-addr";
 			interrupts = <0 69 4>;
 			clocks = <&clockgen 4 1>;
 			status = "disabled";
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 9455e03..7c70585 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -153,7 +153,9 @@
 
 	sata: sata@3200000 {
 		compatible = "fsl,ls1088a-ahci";
-		reg = <0x0 0x3200000 0x0 0x10000>;
+		reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+		       0x7 0x100520  0x0 0x4>;	 /* ecc sata addr*/
+		reg-names = "sata-base", "ecc-addr";
 		interrupts = <0 133 4>;
 		status = "disabled";
 	};
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 510b070..2822078 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -176,4 +176,89 @@
 			status = "disabled";
 
 	};
+
+	pcie@3400000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03480000 0x0 0x40000   /* LUT registers */
+		       0x00 0x034c0000 0x0 0x40000   /* PF control registers */
+		       0x80 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+	};
+
+	pcie@3500000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03580000 0x0 0x40000   /* LUT registers */
+		       0x00 0x035c0000 0x0 0x40000   /* PF control registers */
+		       0x88 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <2>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
+	};
+
+	pcie@3600000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03680000 0x0 0x40000   /* LUT registers */
+		       0x00 0x036c0000 0x0 0x40000   /* PF control registers */
+		       0x90 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
+	};
+
+	pcie@3700000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03780000 0x0 0x40000   /* LUT registers */
+		       0x00 0x037c0000 0x0 0x40000   /* PF control registers */
+		       0x98 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
+	};
+
+	pcie@3800000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03880000 0x0 0x40000   /* LUT registers */
+		       0x00 0x038c0000 0x0 0x40000   /* PF control registers */
+		       0xa0 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
+	};
+
+	pcie@3900000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03980000 0x0 0x40000   /* LUT registers */
+		       0x00 0x039c0000 0x0 0x40000   /* PF control registers */
+		       0xa8 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
+	};
 };
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 7670a39..8a0f473 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -406,7 +406,9 @@
 
 		sata: sata@3200000 {
 			compatible = "fsl,ls1021a-ahci";
-			reg = <0x3200000 0x10000>;
+			reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+			       0x0 0x20220520 0x0 0x4>;	 /* ecc sata addr*/
+			reg-names = "sata-base", "ecc-addr";
 			interrupts = <0 101 4>;
 			status = "disabled";
 		};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
index 0446fd4..60c4192 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
@@ -16,10 +16,6 @@
 	#size-cells = <1>;
 	model = "SOCFPGA Arria10 Dev Kit";	/* Bootloader setting: uboot.model */
 
-	chosen {
-		cff-file = "socfpga.rbf";	/* Bootloader setting: uboot.rbf_filename */
-	};
-
 	/* Clock sources */
 	clocks {
 		#address-cells = <1>;
diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
index 7d9b95c..dc30360 100644
--- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
@@ -16,8 +16,8 @@
  * address mapping : RBC
  * Tc > + 85C : N
  */
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.43"
-#define DDR_MEM_SPEED 533
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.44"
+#define DDR_MEM_SPEED 533000
 #define DDR_MEM_SIZE 0x20000000
 
 #define DDR_MSTR 0x00041401
@@ -108,11 +108,11 @@
 #define DDR_DX1DLLCR 0x40000000
 #define DDR_DX1DQTR 0xFFFFFFFF
 #define DDR_DX1DQSTR 0x3DB02000
-#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2GCR 0x0000CE80
 #define DDR_DX2DLLCR 0x40000000
 #define DDR_DX2DQTR 0xFFFFFFFF
 #define DDR_DX2DQSTR 0x3DB02000
-#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3GCR 0x0000CE80
 #define DDR_DX3DLLCR 0x40000000
 #define DDR_DX3DQTR 0xFFFFFFFF
 #define DDR_DX3DQSTR 0x3DB02000
diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
index 8a5a821..8158a56 100644
--- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -1,9 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 /*
  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-/* STM32MP157C ED1 and ED2 BOARD configuration
+ *
+ * STM32MP157C ED1 BOARD configuration
  * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
  * Reference used NT5CC256M16DP-DI from NANYA
  *
@@ -15,10 +14,11 @@
  * timing mode	optimized
  * Scheduling/QoS options : type = 2
  * address mapping : RBC
+ * Tc > + 85C : N
  */
 
-#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
-#define DDR_MEM_SPEED 533
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.44"
+#define DDR_MEM_SPEED 533000
 #define DDR_MEM_SIZE 0x40000000
 
 #define DDR_MSTR 0x00040401
@@ -62,7 +62,7 @@
 #define DDR_ADDRMAP11 0x00000000
 #define DDR_ODTCFG 0x06000600
 #define DDR_ODTMAP 0x00000001
-#define DDR_SCHED 0x00001201
+#define DDR_SCHED 0x00000C01
 #define DDR_SCHED1 0x00000000
 #define DDR_PERFHPR1 0x01000001
 #define DDR_PERFLPR1 0x08000200
@@ -74,15 +74,15 @@
 #define DDR_PCCFG 0x00000010
 #define DDR_PCFGR_0 0x00010000
 #define DDR_PCFGW_0 0x00000000
-#define DDR_PCFGQOS0_0 0x02100B03
+#define DDR_PCFGQOS0_0 0x02100C03
 #define DDR_PCFGQOS1_0 0x00800100
-#define DDR_PCFGWQOS0_0 0x01100B03
+#define DDR_PCFGWQOS0_0 0x01100C03
 #define DDR_PCFGWQOS1_0 0x01000200
 #define DDR_PCFGR_1 0x00010000
 #define DDR_PCFGW_1 0x00000000
-#define DDR_PCFGQOS0_1 0x02100B03
-#define DDR_PCFGQOS1_1 0x00800100
-#define DDR_PCFGWQOS0_1 0x01100B03
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
 #define DDR_PCFGWQOS1_1 0x01000200
 #define DDR_PGCR 0x01442E02
 #define DDR_PTR0 0x0022AA5B
@@ -100,7 +100,7 @@
 #define DDR_MR2 0x00000208
 #define DDR_MR3 0x00000000
 #define DDR_ODTCR 0x00010000
-#define DDR_ZQ0CR1 0x0000005B
+#define DDR_ZQ0CR1 0x00000038
 #define DDR_DX0GCR 0x0000CE81
 #define DDR_DX0DLLCR 0x40000000
 #define DDR_DX0DQTR 0xFFFFFFFF
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 903d509..eb21c09 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -229,6 +229,67 @@
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 
+#elif defined(CONFIG_ARCH_LS1028A)
+#define CONFIG_SYS_FSL_NUM_CC_PLLS		3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_TZASC_400
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE				0x02200000
+#define TZPCR0SIZE_BASE				(TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
+
+#define	SRDS_MAX_LANES	4
+
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE				0x06000000
+#define GICR_BASE				0x06040000
+
+/* SMMU Definitions */
+#define SMMU_BASE				0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* SEC */
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index d62754e..bdeb625 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -34,10 +34,19 @@
 #define CONFIG_SYS_FSL_QBMAN_BASE	0x818000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
+#ifdef CONFIG_ARCH_LS2080A
 #define CONFIG_SYS_PCIE1_PHYS_SIZE	0x200000000
 #define CONFIG_SYS_PCIE2_PHYS_SIZE	0x200000000
 #define CONFIG_SYS_PCIE3_PHYS_SIZE	0x200000000
 #define CONFIG_SYS_PCIE4_PHYS_SIZE	0x200000000
+#else
+#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x800000000
+#define SYS_PCIE5_PHYS_SIZE		0x800000000
+#define SYS_PCIE6_PHYS_SIZE		0x800000000
+#endif
 #define CONFIG_SYS_FSL_WRIOP1_BASE	0x4300000000
 #define CONFIG_SYS_FSL_WRIOP1_SIZE	0x100000000
 #define CONFIG_SYS_FSL_AIOP1_BASE	0x4b00000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 9fab88a..24c1b0e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -167,10 +167,25 @@
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
 #define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
-#ifdef CONFIG_ARCH_LS1088A
+#ifdef CONFIG_ARCH_LX2160A
+#define SYS_PCIE5_ADDR				(CONFIG_SYS_IMMR + 0x2800000)
+#define SYS_PCIE6_ADDR				(CONFIG_SYS_IMMR + 0x2900000)
+#endif
+
+#ifdef CONFIG_ARCH_LX2160A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x9000000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x9800000000ULL
+#define SYS_PCIE5_PHYS_ADDR			0xa000000000ULL
+#define SYS_PCIE6_PHYS_ADDR			0xa800000000ULL
+#elif CONFIG_ARCH_LS1088A
 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x2000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x2800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x3000000000ULL
+#elif CONFIG_ARCH_LS1028A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
 #else
 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
@@ -375,6 +390,12 @@
 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
 #define FSL_CHASSIS3_SRDS1_REGSR	29
 #define FSL_CHASSIS3_SRDS2_REGSR	30
+#elif defined(CONFIG_ARCH_LS1028A)
+#define	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK	0xFFFF0000
+#define	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT	16
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR	29
 #endif
 #define RCW_SB_EN_REG_INDEX	9
 #define RCW_SB_EN_MASK		0x00000400
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 7d95c4e..234440b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -83,6 +83,7 @@
 /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
 #define SVR_LS1043A_P23		0x879202
 #define SVR_LS1023A_P23		0x87920A
+#define SVR_LS1028A		0x870B00
 #define SVR_LS1046A		0x870700
 #define SVR_LS1026A		0x870708
 #define SVR_LS1048A		0x870320
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index e017d8b..c53cc57 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -87,7 +87,7 @@
 #define FSL_PEX_STREAM_ID_NUM		(0x100)
 #endif
 
-#if defined(CONFIG_ARCH_LS2080A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A)
 #define FSL_PEX_STREAM_ID_END		22
 #elif defined(CONFIG_ARCH_LS1088A)
 #define FSL_PEX_STREAM_ID_END		18
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index c3ca8cd..27d0b6a 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -40,5 +40,6 @@
 #endif
 
 void do_bridge_reset(int enable, unsigned int mask);
+void socfpga_pl310_clear(void);
 
 #endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index db1983d..49dadd4 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -70,6 +70,60 @@
 	/* Disable the L2 cache */
 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
+
+void socfpga_pl310_clear(void)
+{
+	u32 mask = 0xff, ena = 0;
+
+	icache_enable();
+
+	/* Disable the L2 cache */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+	writel(0x0, &pl310->pl310_tag_latency_ctrl);
+	writel(0x10, &pl310->pl310_data_latency_ctrl);
+
+	/* enable BRESP, instruction and data prefetch, full line of zeroes */
+	setbits_le32(&pl310->pl310_aux_ctrl,
+		     L310_AUX_CTRL_DATA_PREFETCH_MASK |
+		     L310_AUX_CTRL_INST_PREFETCH_MASK |
+		     L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+	/* Enable the L2 cache */
+	ena = readl(&pl310->pl310_ctrl);
+	ena |= L2X0_CTRL_EN;
+
+	/*
+	 * Invalidate the PL310 L2 cache. Keep the invalidation code
+	 * entirely in L1 I-cache to avoid any bus traffic through
+	 * the L2.
+	 */
+	asm volatile(
+		".align	5			\n"
+		"	b	3f		\n"
+		"1:	str	%1,	[%4]	\n"
+		"	dsb			\n"
+		"	isb			\n"
+		"	str	%0,	[%2]	\n"
+		"	dsb			\n"
+		"	isb			\n"
+		"2:	ldr	%0,	[%2]	\n"
+		"	cmp	%0,	#0	\n"
+		"	bne	2b		\n"
+		"	str	%0,	[%3]	\n"
+		"	dsb			\n"
+		"	isb			\n"
+		"	b	4f		\n"
+		"3:	b	1b		\n"
+		"4:	nop			\n"
+	: "+r"(mask), "+r"(ena)
+	: "r"(&pl310->pl310_inv_way),
+	  "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
+	: "memory", "cc");
+
+	/* Disable the L2 cache */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
 #endif
 
 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index b466307..b820cb0 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -110,6 +110,7 @@
 
 	socfpga_init_security_policies();
 	socfpga_sdram_remap_zero();
+	socfpga_pl310_clear();
 
 	/* Assert reset to all except L4WD0 and L4TIMER0 */
 	socfpga_per_reset_all();
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 1a60cdc..87b76b4 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -5,7 +5,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/pl310.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <image.h>
@@ -25,8 +24,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
-	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
@@ -63,60 +60,6 @@
 }
 #endif
 
-static void socfpga_pl310_clear(void)
-{
-	u32 mask = 0xff, ena = 0;
-
-	icache_enable();
-
-	/* Disable the L2 cache */
-	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
-	writel(0x111, &pl310->pl310_tag_latency_ctrl);
-	writel(0x121, &pl310->pl310_data_latency_ctrl);
-
-	/* enable BRESP, instruction and data prefetch, full line of zeroes */
-	setbits_le32(&pl310->pl310_aux_ctrl,
-		     L310_AUX_CTRL_DATA_PREFETCH_MASK |
-		     L310_AUX_CTRL_INST_PREFETCH_MASK |
-		     L310_SHARED_ATT_OVERRIDE_ENABLE);
-
-	/* Enable the L2 cache */
-	ena = readl(&pl310->pl310_ctrl);
-	ena |= L2X0_CTRL_EN;
-
-	/*
-	 * Invalidate the PL310 L2 cache. Keep the invalidation code
-	 * entirely in L1 I-cache to avoid any bus traffic through
-	 * the L2.
-	 */
-	asm volatile(
-		".align	5			\n"
-		"	b	3f		\n"
-		"1:	str	%1,	[%4]	\n"
-		"	dsb			\n"
-		"	isb			\n"
-		"	str	%0,	[%2]	\n"
-		"	dsb			\n"
-		"	isb			\n"
-		"2:	ldr	%0,	[%2]	\n"
-		"	cmp	%0,	#0	\n"
-		"	bne	2b		\n"
-		"	str	%0,	[%3]	\n"
-		"	dsb			\n"
-		"	isb			\n"
-		"	b	4f		\n"
-		"3:	b	1b		\n"
-		"4:	nop			\n"
-	: "+r"(mask), "+r"(ena)
-	: "r"(&pl310->pl310_inv_way),
-	  "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
-	: "memory", "cc");
-
-	/* Disable the L2 cache */
-	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-
 void board_init_f(ulong dummy)
 {
 	const struct cm_config *cm_default_cfg = cm_get_default_config();
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 73aa382..77f66c6 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -17,12 +17,20 @@
 	select SPL_DM_RESET
 	select SPL_SERIAL_SUPPORT
 	select SPL_SYSCON
+	imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
+	imply SPL_BOOTSTAGE if BOOTSTAGE
 	imply SPL_DISPLAY_PRINT
 	imply SPL_LIBDISK_SUPPORT
 
 config SYS_SOC
 	default "stm32mp"
 
+config SYS_MALLOC_LEN
+	default 0x2000000
+
+config ENV_SIZE
+	default 0x1000
+
 config TARGET_STM32MP1
 	bool "Support stm32mp1xx"
 	select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
@@ -33,6 +41,10 @@
 	select STM32_RCC
 	select STM32_RESET
 	select SYS_ARCH_TIMER
+	imply BOOTCOUNT_LIMIT
+	imply BOOTSTAGE
+	imply CMD_BOOTCOUNT
+	imply CMD_BOOTSTAGE
 	imply SYSRESET_PSCI if STM32MP1_TRUSTED
 	imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
 	help
@@ -70,6 +82,18 @@
 	  Partition on the second MMC to load U-Boot from when the MMC is being
 	  used in raw mode
 
+config BOOTSTAGE_STASH_ADDR
+	default 0xC3000000
+
+if BOOTCOUNT_LIMIT
+config SYS_BOOTCOUNT_SINGLEWORD
+	default y
+
+# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
+config SYS_BOOTCOUNT_ADDR
+	default 0x5C00A154
+endif
+
 if DEBUG_UART
 
 config DEBUG_UART_BOARD_INIT
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
index 9ed8d8c..0166649 100644
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -7,9 +7,9 @@
 #include <dm.h>
 #include <misc.h>
 #include <asm/io.h>
-#include <linux/iopoll.h>
 #include <asm/arch/stm32mp1_smc.h>
 #include <linux/arm-smccc.h>
+#include <linux/iopoll.h>
 
 #define BSEC_OTP_MAX_VALUE		95
 
diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h
index 1857584..b8a17cf 100644
--- a/arch/arm/mach-stm32mp/include/mach/ddr.h
+++ b/arch/arm/mach-stm32mp/include/mach/ddr.h
@@ -6,6 +6,13 @@
 #ifndef __MACH_STM32MP_DDR_H_
 #define __MACH_STM32MP_DDR_H_
 
-int board_ddr_power_init(void);
+/* DDR power initializations */
+enum ddr_type {
+	STM32MP_DDR3,
+	STM32MP_LPDDR2,
+	STM32MP_LPDDR3,
+};
+
+int board_ddr_power_init(enum ddr_type ddr_type);
 
 #endif
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index c526c88..6795352 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -88,6 +88,7 @@
 #define TAMP_BACKUP_MAGIC_NUMBER	TAMP_BACKUP_REGISTER(4)
 #define TAMP_BACKUP_BRANCH_ADDRESS	TAMP_BACKUP_REGISTER(5)
 #define TAMP_BOOT_CONTEXT		TAMP_BACKUP_REGISTER(20)
+#define TAMP_BOOTCOUNT			TAMP_BACKUP_REGISTER(21)
 
 #define TAMP_BOOT_MODE_MASK		GENMASK(15, 8)
 #define TAMP_BOOT_MODE_SHIFT		8
diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
index c2dff38..139bb09 100644
--- a/arch/arm/mach-stm32mp/psci.c
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -47,14 +47,14 @@
 	return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
 }
 
-static void __secure stm32mp_smp_kick_all_cpus(void)
+static void __secure stm32mp_raise_sgi0(int cpu)
 {
 	u32 gic_dist_addr;
 
 	gic_dist_addr = stm32mp_get_gicd_base_address();
 
-	/* kick all CPUs (except this one) by writing to GICD_SGIR */
-	writel(1U << 24, gic_dist_addr + GICD_SGIR);
+	/* ask cpu with SGI0 */
+	writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR);
 }
 
 void __secure psci_arch_cpu_entry(void)
@@ -62,6 +62,9 @@
 	u32 cpu = psci_get_cpu_id();
 
 	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
+
+	/* reset magic in TAMP register */
+	writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
 }
 
 int __secure psci_features(u32 function_id, u32 psci_fid)
@@ -127,6 +130,16 @@
 	if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
 		return ARM_PSCI_RET_ALREADY_ON;
 
+	/* reset magic in TAMP register */
+	if (readl(TAMP_BACKUP_MAGIC_NUMBER))
+		writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
+	/*
+	 * ROM code need a first SGI0 after core reset
+	 * core is ready when magic is set to 0 in ROM code
+	 */
+	while (readl(TAMP_BACKUP_MAGIC_NUMBER))
+		stm32mp_raise_sgi0(cpu);
+
 	/* store target PC and context id*/
 	psci_save(cpu, pc, context_id);
 
@@ -142,7 +155,8 @@
 		writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
 		       TAMP_BACKUP_MAGIC_NUMBER);
 
-	stm32mp_smp_kick_all_cpus();
+	/* Generate an IT to start the core */
+	stm32mp_raise_sgi0(cpu);
 
 	return ARM_PSCI_RET_SUCCESS;
 }
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 1f6df5c..fef1081 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -6,36 +6,69 @@
 
 # processor family
 config MCF520x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
 	bool
 
 config MCF52x2
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
 	bool
 
 config MCF523x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
 	bool
 
 config MCF530x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
 	bool
 
 config MCF5301x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
 	bool
 
 config MCF532x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
 	bool
 
 config MCF537x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
 	bool
 
 config MCF5441x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
 	bool
 
 config MCF5445x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
 	bool
 
 config MCF5227x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
 	bool
 
 config MCF547x_8x
+	select OF_CONTROL
+        select DM
+        select DM_SERIAL
 	bool
 
 # processor type
diff --git a/arch/m68k/cpu/mcf5227x/Makefile b/arch/m68k/cpu/mcf5227x/Makefile
index ef43893..6a38c48 100644
--- a/arch/m68k/cpu/mcf5227x/Makefile
+++ b/arch/m68k/cpu/mcf5227x/Makefile
@@ -6,4 +6,4 @@
 # ccflags-y += -DET_DEBUG
 
 extra-y	= start.o
-obj-y	= cpu.o speed.o cpu_init.o interrupts.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o dspi.o
diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c
index 0d6a484..3bbc42f 100644
--- a/arch/m68k/cpu/mcf5227x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5227x/cpu_init.c
@@ -16,6 +16,15 @@
 #include <asm/rtc.h>
 #include <linux/compiler.h>
 
+void cfspi_port_conf(void)
+{
+	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+	out_8(&gpio->par_dspi,
+	      GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+	      GPIO_PAR_DSPI_SCK_SCK);
+}
+
 /*
  * Breath some life into the CPU...
  *
@@ -93,6 +102,8 @@
 #endif
 
 	icache_enable();
+
+	cfspi_port_conf();
 }
 
 /*
@@ -137,57 +148,3 @@
 		break;
 	}
 }
-
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	out_8(&gpio->par_dspi,
-		GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-		GPIO_PAR_DSPI_SCK_SCK);
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
-	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
-		return -1;
-
-	/* Clear FIFO and resume transfer */
-	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		break;
-	case 2:
-		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
-		setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
-		break;
-	}
-
-	return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
-	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	/* Clear FIFO */
-	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		break;
-	case 2:
-		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
-		break;
-	}
-}
-#endif
diff --git a/arch/m68k/cpu/mcf5227x/dspi.c b/arch/m68k/cpu/mcf5227x/dspi.c
new file mode 100644
index 0000000..8fc4da2
--- /dev/null
+++ b/arch/m68k/cpu/mcf5227x/dspi.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Angelo Dureghello <angleo@sysam.it>
+ *
+ * CPU specific dspi routines
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CF_DSPI
+void dspi_chip_select(int cs)
+{
+	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		break;
+	case 2:
+		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+		setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
+		break;
+	}
+}
+
+void dspi_chip_unselect(int cs)
+{
+	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		break;
+	case 2:
+		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+		break;
+	}
+}
+#endif /* CONFIG_CF_DSPI */
diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S
index e1b6c35..61f9c68 100644
--- a/arch/m68k/cpu/mcf5227x/start.S
+++ b/arch/m68k/cpu/mcf5227x/start.S
@@ -378,7 +378,8 @@
 	clr.l	%sp@-
 
 	/* run low-level board init code (from flash) */
-	bsr	board_init_f
+	move.l	#board_init_f, %a1
+	jsr	(%a1)
 
 	/* board_init_f() does not return */
 
diff --git a/arch/m68k/cpu/mcf5445x/Makefile b/arch/m68k/cpu/mcf5445x/Makefile
index be2cb2a..ba90fc3 100644
--- a/arch/m68k/cpu/mcf5445x/Makefile
+++ b/arch/m68k/cpu/mcf5445x/Makefile
@@ -6,4 +6,4 @@
 # ccflags-y += -DET_DEBUG
 
 extra-y	= start.o
-obj-y	= cpu.o speed.o cpu_init.o interrupts.o pci.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 7632d92..8f4991c 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -66,6 +66,32 @@
 #endif
 }
 
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+	out_8(&gpio->par_dspi,
+	      GPIO_PAR_DSPI_SIN_SIN |
+	      GPIO_PAR_DSPI_SOUT_SOUT |
+	      GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+	pm_t *pm = (pm_t *)MMAP_PM;
+
+	out_8(&gpio->par_dspi0,
+	      GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+	      GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+	out_8(&gpio->srcr_dspiow, 3);
+
+	/* DSPI0 */
+	out_8(&pm->pmcr0, 23);
+#endif
+}
+#endif
+
 /*
  * Breath some life into the CPU...
  *
@@ -204,6 +230,10 @@
 		GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
 		GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
 
+#ifdef CONFIG_CF_SPI
+	cfspi_port_conf();
+#endif
+
 #ifdef CONFIG_SYS_FSL_I2C
 	out_be16(&gpio->par_feci2c,
 		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
@@ -433,115 +463,3 @@
 }
 #endif
 
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-#ifdef CONFIG_MCF5445x
-	out_8(&gpio->par_dspi,
-		GPIO_PAR_DSPI_SIN_SIN |
-		GPIO_PAR_DSPI_SOUT_SOUT |
-		GPIO_PAR_DSPI_SCK_SCK);
-#endif
-
-#ifdef CONFIG_MCF5441x
-	pm_t *pm = (pm_t *) MMAP_PM;
-
-	out_8(&gpio->par_dspi0,
-		GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
-		GPIO_PAR_DSPI0_SCK_DSPI0SCK);
-	out_8(&gpio->srcr_dspiow, 3);
-
-	/* DSPI0 */
-	out_8(&pm->pmcr0, 23);
-#endif
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
-	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
-		return -1;
-
-	/* Clear FIFO and resume transfer */
-	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-#ifdef CONFIG_MCF5445x
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		break;
-	case 1:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
-		break;
-	case 2:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
-		break;
-	case 3:
-		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
-		setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
-		break;
-	case 5:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
-		break;
-	}
-#endif
-
-#ifdef CONFIG_MCF5441x
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
-		setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
-		break;
-	case 1:
-		clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
-		setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
-		break;
-	}
-#endif
-
-	return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
-	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	/* Clear FIFO */
-	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-#ifdef CONFIG_MCF5445x
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		break;
-	case 1:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
-		break;
-	case 2:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
-		break;
-	case 3:
-		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
-		break;
-	case 5:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
-		break;
-	}
-#endif
-
-#ifdef CONFIG_MCF5441x
-	if (cs == 1)
-		clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
-#endif
-}
-
-#endif
diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c
new file mode 100644
index 0000000..b0e2f2c
--- /dev/null
+++ b/arch/m68k/cpu/mcf5445x/dspi.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Angelo Dureghello <angleo@sysam.it>
+ *
+ * CPU specific dspi routines
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CF_DSPI
+void dspi_chip_select(int cs)
+{
+	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		break;
+	case 1:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+		break;
+	case 2:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+		break;
+	case 3:
+		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+		setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
+		break;
+	case 5:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+		break;
+	}
+#endif
+#ifdef CONFIG_MCF5441x
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi0,
+			  ~GPIO_PAR_DSPI0_PCS0_MASK);
+		setbits_8(&gpio->par_dspi0,
+			  GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
+		break;
+	case 1:
+		clrbits_8(&gpio->par_dspiow,
+			  GPIO_PAR_DSPIOW_DSPI0PSC1);
+		setbits_8(&gpio->par_dspiow,
+			  GPIO_PAR_DSPIOW_DSPI0PSC1);
+		break;
+	}
+#endif
+}
+
+void dspi_chip_unselect(int cs)
+{
+	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		break;
+	case 1:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+		break;
+	case 2:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+		break;
+	case 3:
+		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+		break;
+	case 5:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+		break;
+	}
+#endif
+#ifdef CONFIG_MCF5441x
+	if (cs == 1)
+		clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+#endif
+}
+#endif /* CONFIG_CF_DSPI */
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S
index 7cb5db7..4dd57bf 100644
--- a/arch/m68k/cpu/mcf547x_8x/start.S
+++ b/arch/m68k/cpu/mcf547x_8x/start.S
@@ -131,7 +131,8 @@
 	 * then (and always) gd struct space will be reserved
 	 */
 	move.l	%sp, -(%sp)
-	bsr	board_init_f_alloc_reserve
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
 
 	/* update stack and frame-pointers */
 	move.l  %d0, %sp
@@ -139,7 +140,8 @@
 
 	/* initialize reserved area */
 	move.l	%d0, -(%sp)
-	bsr	board_init_f_init_reserve
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
 	jbsr	cpu_init_f
diff --git a/arch/m68k/cpu/u-boot.lds b/arch/m68k/cpu/u-boot.lds
index 9645120..64cf2ff 100644
--- a/arch/m68k/cpu/u-boot.lds
+++ b/arch/m68k/cpu/u-boot.lds
@@ -68,13 +68,15 @@
 	__ex_table : { *(__ex_table) }
 	__stop___ex_table = .;
 
-	. = ALIGN(256);
+	. = ALIGN(4);
 	__init_begin = .;
 	.text.init : { *(.text.init) }
 	.data.init : { *(.data.init) }
-	. = ALIGN(256);
+	. = ALIGN(4);
 	__init_end = .;
 
+	_end = .;
+
 	__bss_start = .;
 	.bss (NOLOAD)       :
 	{
diff --git a/arch/m68k/dts/M5208EVBE.dts b/arch/m68k/dts/M5208EVBE.dts
new file mode 100644
index 0000000..e78513f
--- /dev/null
+++ b/arch/m68k/dts/M5208EVBE.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5208.dtsi"
+
+/ {
+	model = "Freescale M5208EVBE";
+	compatible = "fsl,M5208EVBE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M52277EVB.dts b/arch/m68k/dts/M52277EVB.dts
new file mode 100644
index 0000000..a2210c8
--- /dev/null
+++ b/arch/m68k/dts/M52277EVB.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5227x.dtsi"
+
+/ {
+	model = "Freescale M52277EVB";
+	compatible = "fsl,M52277EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M52277EVB_stmicro.dts b/arch/m68k/dts/M52277EVB_stmicro.dts
new file mode 100644
index 0000000..5fd3ca5
--- /dev/null
+++ b/arch/m68k/dts/M52277EVB_stmicro.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5227x.dtsi"
+
+/ {
+	model = "Freescale M52277_stmicro";
+	compatible = "fsl,M52277_stmicro";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5235EVB.dts b/arch/m68k/dts/M5235EVB.dts
new file mode 100644
index 0000000..1a32539
--- /dev/null
+++ b/arch/m68k/dts/M5235EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf523x.dtsi"
+
+/ {
+	model = "Freescale M5235EVB";
+	compatible = "fsl,M5235EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5235EVB_Flash32.dts b/arch/m68k/dts/M5235EVB_Flash32.dts
new file mode 100644
index 0000000..fcbffb2
--- /dev/null
+++ b/arch/m68k/dts/M5235EVB_Flash32.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf523x.dtsi"
+
+/ {
+	model = "Freescale M5235EVB_Flash32";
+	compatible = "fsl,M5235EVB_Flash32";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5249EVB.dts b/arch/m68k/dts/M5249EVB.dts
new file mode 100644
index 0000000..b2a1be9
--- /dev/null
+++ b/arch/m68k/dts/M5249EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5249.dtsi"
+
+/ {
+	model = "Freescale M5249EVB";
+	compatible = "fsl,M5249EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5253DEMO.dts b/arch/m68k/dts/M5253DEMO.dts
new file mode 100644
index 0000000..7ebaa9a
--- /dev/null
+++ b/arch/m68k/dts/M5253DEMO.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5253.dtsi"
+
+/ {
+	model = "Freescale M5253DEMO";
+	compatible = "fsl,M5253DEMO";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5272C3.dts b/arch/m68k/dts/M5272C3.dts
new file mode 100644
index 0000000..6efb8a4
--- /dev/null
+++ b/arch/m68k/dts/M5272C3.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5272.dtsi"
+
+/ {
+	model = "Freescale M5272C3";
+	compatible = "fsl,M5272C3";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5275EVB.dts b/arch/m68k/dts/M5275EVB.dts
new file mode 100644
index 0000000..cd9eb7d
--- /dev/null
+++ b/arch/m68k/dts/M5275EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5275.dtsi"
+
+/ {
+	model = "Freescale M5275EVB";
+	compatible = "fsl,M5275EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5282EVB.dts b/arch/m68k/dts/M5282EVB.dts
new file mode 100644
index 0000000..9527caa
--- /dev/null
+++ b/arch/m68k/dts/M5282EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+	model = "Freescale M5282EVB";
+	compatible = "fsl,M5282EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M53017EVB.dts b/arch/m68k/dts/M53017EVB.dts
new file mode 100644
index 0000000..b267488
--- /dev/null
+++ b/arch/m68k/dts/M53017EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5301x.dtsi"
+
+/ {
+	model = "Freescale M53017EVB";
+	compatible = "fsl,M53017EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5329AFEE.dts b/arch/m68k/dts/M5329AFEE.dts
new file mode 100644
index 0000000..7d121d6
--- /dev/null
+++ b/arch/m68k/dts/M5329AFEE.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5329.dtsi"
+
+/ {
+	model = "Freescale M5329AFEE";
+	compatible = "fsl,M5329AFEE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5329BFEE.dts b/arch/m68k/dts/M5329BFEE.dts
new file mode 100644
index 0000000..cd087b6
--- /dev/null
+++ b/arch/m68k/dts/M5329BFEE.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5329.dtsi"
+
+/ {
+	model = "Freescale M5329BFEE";
+	compatible = "fsl,M5329BFEE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5373EVB.dts b/arch/m68k/dts/M5373EVB.dts
new file mode 100644
index 0000000..930f911
--- /dev/null
+++ b/arch/m68k/dts/M5373EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf537x.dtsi"
+
+/ {
+	model = "Freescale M5373EVB";
+	compatible = "fsl,M5373EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M54418TWR.dts b/arch/m68k/dts/M54418TWR.dts
new file mode 100644
index 0000000..7765c7a
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR";
+	compatible = "fsl,M54418TWR";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54418TWR_nand_mii.dts b/arch/m68k/dts/M54418TWR_nand_mii.dts
new file mode 100644
index 0000000..9b1cb85
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR_nand_mii.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR_nand_mii";
+	compatible = "fsl,M54418TWR_nand_mii";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54418TWR_nand_rmii.dts b/arch/m68k/dts/M54418TWR_nand_rmii.dts
new file mode 100644
index 0000000..824a66a
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR_nand_rmii.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR_nand_rmii";
+	compatible = "fsl,M54418TWR_nand_rmii";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts
new file mode 100644
index 0000000..74fa197
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR_nand_rmii_lowfreq";
+	compatible = "fsl,M54418TWR_nand_rmii_lowfreq";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54418TWR_serial_mii.dts b/arch/m68k/dts/M54418TWR_serial_mii.dts
new file mode 100644
index 0000000..22f27b5
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR_serial_mii.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR_serial_mii";
+	compatible = "fsl,M54418TWR_serial_mii";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54418TWR_serial_rmii.dts b/arch/m68k/dts/M54418TWR_serial_rmii.dts
new file mode 100644
index 0000000..0ddefd9
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR_serial_rmii.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR_serial_rmii";
+	compatible = "fsl,M54418TWR_serial_rmii";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54451EVB.dts b/arch/m68k/dts/M54451EVB.dts
new file mode 100644
index 0000000..b57bfea
--- /dev/null
+++ b/arch/m68k/dts/M54451EVB.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54451EVB";
+	compatible = "fsl,M54451EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54451EVB_stmicro.dts b/arch/m68k/dts/M54451EVB_stmicro.dts
new file mode 100644
index 0000000..9a088e1
--- /dev/null
+++ b/arch/m68k/dts/M54451EVB_stmicro.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54451EVB_stmicro";
+	compatible = "fsl,M54451EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54455EVB.dts b/arch/m68k/dts/M54455EVB.dts
new file mode 100644
index 0000000..dd11181
--- /dev/null
+++ b/arch/m68k/dts/M54455EVB.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54455EVB";
+	compatible = "fsl,M54455EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54455EVB_a66.dts b/arch/m68k/dts/M54455EVB_a66.dts
new file mode 100644
index 0000000..70d544b
--- /dev/null
+++ b/arch/m68k/dts/M54455EVB_a66.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54455EVB_a66";
+	compatible = "fsl,M54455EVB_a66";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54455EVB_i66.dts b/arch/m68k/dts/M54455EVB_i66.dts
new file mode 100644
index 0000000..b37a872
--- /dev/null
+++ b/arch/m68k/dts/M54455EVB_i66.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54455EVB_i66";
+	compatible = "fsl,M54455EVB_i66";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M54455EVB_intel.dts b/arch/m68k/dts/M54455EVB_intel.dts
new file mode 100644
index 0000000..c92228f
--- /dev/null
+++ b/arch/m68k/dts/M54455EVB_intel.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54455EVB_intel";
+	compatible = "fsl,M5275EVB_intel";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/M54455EVB_stm33.dts b/arch/m68k/dts/M54455EVB_stm33.dts
new file mode 100644
index 0000000..9e467f9
--- /dev/null
+++ b/arch/m68k/dts/M54455EVB_stm33.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54455EVB_stm33";
+	compatible = "fsl,M5275EVB_stm33";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
diff --git a/arch/m68k/dts/M5475AFE.dts b/arch/m68k/dts/M5475AFE.dts
new file mode 100644
index 0000000..0c0a79b
--- /dev/null
+++ b/arch/m68k/dts/M5475AFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475AFE";
+	compatible = "fsl,M5475AFE";
+};
+
diff --git a/arch/m68k/dts/M5475BFE.dts b/arch/m68k/dts/M5475BFE.dts
new file mode 100644
index 0000000..c4d1409
--- /dev/null
+++ b/arch/m68k/dts/M5475BFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475BFE";
+	compatible = "fsl,M5475BFE";
+};
+
diff --git a/arch/m68k/dts/M5475CFE.dts b/arch/m68k/dts/M5475CFE.dts
new file mode 100644
index 0000000..4c92c33
--- /dev/null
+++ b/arch/m68k/dts/M5475CFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475CFE";
+	compatible = "fsl,M5475CFE";
+};
+
diff --git a/arch/m68k/dts/M5475DFE.dts b/arch/m68k/dts/M5475DFE.dts
new file mode 100644
index 0000000..c41c1b3
--- /dev/null
+++ b/arch/m68k/dts/M5475DFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475DFE";
+	compatible = "fsl,M5475DFE";
+};
+
diff --git a/arch/m68k/dts/M5475EFE.dts b/arch/m68k/dts/M5475EFE.dts
new file mode 100644
index 0000000..5a920b2
--- /dev/null
+++ b/arch/m68k/dts/M5475EFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475EFE";
+	compatible = "fsl,M5475EFE";
+};
+
diff --git a/arch/m68k/dts/M5475FFE.dts b/arch/m68k/dts/M5475FFE.dts
new file mode 100644
index 0000000..d312a6a
--- /dev/null
+++ b/arch/m68k/dts/M5475FFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475FFE";
+	compatible = "fsl,M5475FFE";
+};
+
diff --git a/arch/m68k/dts/M5475GFE.dts b/arch/m68k/dts/M5475GFE.dts
new file mode 100644
index 0000000..9e794da
--- /dev/null
+++ b/arch/m68k/dts/M5475GFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475GFE";
+	compatible = "fsl,M5475GFE";
+};
+
diff --git a/arch/m68k/dts/M5485AFE.dts b/arch/m68k/dts/M5485AFE.dts
new file mode 100644
index 0000000..3466751
--- /dev/null
+++ b/arch/m68k/dts/M5485AFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485AFE";
+	compatible = "fsl,M5485AFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
diff --git a/arch/m68k/dts/M5485BFE.dts b/arch/m68k/dts/M5485BFE.dts
new file mode 100644
index 0000000..6d48795
--- /dev/null
+++ b/arch/m68k/dts/M5485BFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485BFE";
+	compatible = "fsl,M5485BFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
diff --git a/arch/m68k/dts/M5485CFE.dts b/arch/m68k/dts/M5485CFE.dts
new file mode 100644
index 0000000..d1a7d9d
--- /dev/null
+++ b/arch/m68k/dts/M5485CFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485CFE";
+	compatible = "fsl,M5485CFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
diff --git a/arch/m68k/dts/M5485DFE.dts b/arch/m68k/dts/M5485DFE.dts
new file mode 100644
index 0000000..7c362e2
--- /dev/null
+++ b/arch/m68k/dts/M5485DFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485DFE";
+	compatible = "fsl,M5485DFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
diff --git a/arch/m68k/dts/M5485EFE.dts b/arch/m68k/dts/M5485EFE.dts
new file mode 100644
index 0000000..4c688dc
--- /dev/null
+++ b/arch/m68k/dts/M5485EFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485EFE";
+	compatible = "fsl,M5485EFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
diff --git a/arch/m68k/dts/M5485FFE.dts b/arch/m68k/dts/M5485FFE.dts
new file mode 100644
index 0000000..87ec2c5
--- /dev/null
+++ b/arch/m68k/dts/M5485FFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485FFE";
+	compatible = "fsl,M5485FFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
diff --git a/arch/m68k/dts/M5485GFE.dts b/arch/m68k/dts/M5485GFE.dts
new file mode 100644
index 0000000..9f67e55
--- /dev/null
+++ b/arch/m68k/dts/M5485GFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485GFE";
+	compatible = "fsl,M5485GFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
diff --git a/arch/m68k/dts/M5485HFE.dts b/arch/m68k/dts/M5485HFE.dts
new file mode 100644
index 0000000..2eb2213
--- /dev/null
+++ b/arch/m68k/dts/M5485HFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485HFE";
+	compatible = "fsl,M5485HFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile
new file mode 100644
index 0000000..e059f23
--- /dev/null
+++ b/arch/m68k/dts/Makefile
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \
+	M52277EVB_stmicro.dtb
+dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \
+	M5235EVB_Flash32.dtb
+dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb
+dtb-$(CONFIG_TARGET_EB_CPU5282) += eb_cpu5282.dtb \
+	eb_cpu5282_internal.dtb
+dtb-$(CONFIG_TARGET_M5208EVBE) += M5208EVBE.dtb
+dtb-$(CONFIG_TARGET_M5249EVB) += M5249EVB.dtb
+dtb-$(CONFIG_TARGET_M5253DEMO) += M5253DEMO.dtb
+dtb-$(CONFIG_TARGET_M5272C3) += M5272C3.dtb
+dtb-$(CONFIG_TARGET_M5275EVB) += M5275EVB.dtb
+dtb-$(CONFIG_TARGET_M5282EVB) += M5282EVB.dtb
+dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb
+dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb
+dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb
+dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb
+dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \
+	M54418TWR_nand_mii.dtb \
+	M54418TWR_nand_rmii.dtb \
+	M54418TWR_serial_mii.dtb \
+	M54418TWR_serial_rmii.dtb \
+	M54418TWR_nand_rmii_lowfreq.dtb
+dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \
+	M54451EVB_stmicro.dtb
+dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \
+	M54455EVB_intel.dtb \
+	M54455EVB_stm33.dtb \
+	M54455EVB_a66.dtb \
+	M54455EVB_i66.dtb
+dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
+dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
+dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \
+	M5475BFE.dtb \
+	M5475CFE.dtb \
+	M5475DFE.dtb \
+	M5475EFE.dtb \
+	M5475FFE.dtb \
+	M5475GFE.dtb
+dtb-$(CONFIG_TARGET_M5485EVB) += M5485AFE.dtb \
+	M5485BFE.dtb \
+	M5485CFE.dtb \
+	M5485DFE.dtb \
+	M5485EFE.dtb \
+	M5485FFE.dtb \
+	M5485GFE.dtb \
+	M5485HFE.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
diff --git a/arch/m68k/dts/amcore.dts b/arch/m68k/dts/amcore.dts
new file mode 100644
index 0000000..c21fb8f
--- /dev/null
+++ b/arch/m68k/dts/amcore.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5307.dtsi"
+
+/ {
+	model = "Sysam AMCORE";
+	compatible = "sysam,AMCORE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/astro_mcf5373l.dts b/arch/m68k/dts/astro_mcf5373l.dts
new file mode 100644
index 0000000..1b1a46a
--- /dev/null
+++ b/arch/m68k/dts/astro_mcf5373l.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf537x.dtsi"
+
+/ {
+	model = "Astro mcf5373l";
+	compatible = "astro,mcf5373l";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/cobra5272.dts b/arch/m68k/dts/cobra5272.dts
new file mode 100644
index 0000000..f3b7497
--- /dev/null
+++ b/arch/m68k/dts/cobra5272.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5272.dtsi"
+
+/ {
+	model = "Cobra 5272";
+	compatible = "cobra,M5272";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/eb_cpu5282.dts b/arch/m68k/dts/eb_cpu5282.dts
new file mode 100644
index 0000000..4641e9c
--- /dev/null
+++ b/arch/m68k/dts/eb_cpu5282.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+	model = "BuS eb_cpuM5282";
+	compatible = "bus,eb_cpuM5282";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/eb_cpu5282_internal.dts b/arch/m68k/dts/eb_cpu5282_internal.dts
new file mode 100644
index 0000000..0acb793
--- /dev/null
+++ b/arch/m68k/dts/eb_cpu5282_internal.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+	model = "BuS eb_cpu5282_internals";
+	compatible = "bus,eb_cpu5282_internals";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi
new file mode 100644
index 0000000..558d8bf
--- /dev/null
+++ b/arch/m68k/dts/mcf5208.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5208";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi
new file mode 100644
index 0000000..8c95edd
--- /dev/null
+++ b/arch/m68k/dts/mcf5227x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5227x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi@fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi
new file mode 100644
index 0000000..9e79d47
--- /dev/null
+++ b/arch/m68k/dts/mcf523x.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf523x";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart@280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5249.dtsi b/arch/m68k/dts/mcf5249.dtsi
new file mode 100644
index 0000000..248b3dc
--- /dev/null
+++ b/arch/m68k/dts/mcf5249.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5249";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar@10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart@1c0 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x1c0 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5253.dtsi b/arch/m68k/dts/mcf5253.dtsi
new file mode 100644
index 0000000..3bde2d6
--- /dev/null
+++ b/arch/m68k/dts/mcf5253.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5253";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar@10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart@1c0 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x1c0 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart3: uart@c00 {
+				compatible = "fsl,mcf-uart";
+				reg = <0xc00 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi
new file mode 100644
index 0000000..2935552
--- /dev/null
+++ b/arch/m68k/dts/mcf5271.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5271";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart@280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5272.dtsi b/arch/m68k/dts/mcf5272.dtsi
new file mode 100644
index 0000000..a561177
--- /dev/null
+++ b/arch/m68k/dts/mcf5272.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5272";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar@10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart@100 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x100 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@140 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x140 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi
new file mode 100644
index 0000000..b375609
--- /dev/null
+++ b/arch/m68k/dts/mcf5275.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5275";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart@280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi
new file mode 100644
index 0000000..3ad1be7
--- /dev/null
+++ b/arch/m68k/dts/mcf5282.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5282";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart@280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi
new file mode 100644
index 0000000..0891e4d
--- /dev/null
+++ b/arch/m68k/dts/mcf5301x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5301x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi@fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5307.dtsi b/arch/m68k/dts/mcf5307.dtsi
new file mode 100644
index 0000000..e199cf9
--- /dev/null
+++ b/arch/m68k/dts/mcf5307.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5307";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* MBAR */
+		mbar: mbar@10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart@1c0 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x1c0 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi
new file mode 100644
index 0000000..aeaa643
--- /dev/null
+++ b/arch/m68k/dts/mcf5329.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5329";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi
new file mode 100644
index 0000000..aeaa643
--- /dev/null
+++ b/arch/m68k/dts/mcf537x.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5329";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi
new file mode 100644
index 0000000..71b392a
--- /dev/null
+++ b/arch/m68k/dts/mcf5441x.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5441x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		uart3: uart@fc06c000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc06c000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi@fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+
+		dspi1: dspi@fc03c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc03c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+
+		dspi2: dspi@ec038000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xec038000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+
+		dspi3: dspi@ec03c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xec03c00 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi
new file mode 100644
index 0000000..ccbee29
--- /dev/null
+++ b/arch/m68k/dts/mcf5445x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5445x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi@fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf54xx.dtsi b/arch/m68k/dts/mcf54xx.dtsi
new file mode 100644
index 0000000..537bb42
--- /dev/null
+++ b/arch/m68k/dts/mcf54xx.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf54x5";
+
+	aliases {
+		/* TO DO, clarify on serial, this SoC seems to have SPC and
+		 * no UARTS.
+		 */
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar@80000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x80000000 0x10000>;
+			reg = <0x80000000 0x10000>;
+
+			dspi0: dspi@8a00 {
+				compatible = "fsl,mcf-dspi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x8a00 0x100>;
+				spi-max-frequency = <50000000>;
+				num-cs = <4>;
+				spi-mode = <0>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts
new file mode 100644
index 0000000..fd8ce4f
--- /dev/null
+++ b/arch/m68k/dts/stmark2.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Sysam stmark2";
+	compatible = "sysam,stmark2";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	spi-mode = <3>;
+	status = "okay";
+
+	flash: is25lp128@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <60000000>;
+		reg = <1>;
+	};
+};
diff --git a/arch/m68k/include/asm/coldfire/dspi.h b/arch/m68k/include/asm/coldfire/dspi.h
index afd5c79..ddd8f33 100644
--- a/arch/m68k/include/asm/coldfire/dspi.h
+++ b/arch/m68k/include/asm/coldfire/dspi.h
@@ -138,4 +138,8 @@
 /* Bit definitions and macros for DRFDR group */
 #define DSPI_RFDR_RXDATA(x)		(((x)&0x0000FFFF))
 
+/* Architecture-related operations */
+void dspi_chip_select(int cs);
+void dspi_chip_unselect(int cs);
+
 #endif				/* __DSPI_H__ */
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9cf8e98..5cb9bdf 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -84,13 +84,13 @@
 	select DM_SERIAL
 	imply DM_SPI
 	imply DM_SPI_FLASH
-	select ARCH_MISC_INIT
 	select MIPS_TUNE_24KC
 	select OF_CONTROL
 	select ROM_EXCEPTION_VECTORS
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
 	select SUPPORTS_LITTLE_ENDIAN
+	select SYS_MALLOC_CLEAR_ON_INIT
 	select SYSRESET
 
 config ARCH_JZ47XX
diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c
index fcd0484..b0a6397 100644
--- a/arch/mips/mach-mtmips/cpu.c
+++ b/arch/mips/mach-mtmips/cpu.c
@@ -68,18 +68,3 @@
 
 	return 0;
 }
-
-int arch_misc_init(void)
-{
-	/*
-	 * It has been noticed, that sometimes the d-cache is not in a
-	 * "clean-state" when U-Boot is running on MT7688. This was
-	 * detected when using the ethernet driver (which uses d-cache)
-	 * and a TFTP command does not complete. Flushing the complete
-	 * d-cache (again?) here seems to fix this issue.
-	 */
-	flush_dcache_range(gd->bd->bi_memstart,
-			   gd->bd->bi_memstart + gd->ram_size - 1);
-
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 0057f19..aebf168 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -352,7 +352,6 @@
 	select PHYS_64BIT
 	select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 	select FSL_DDR_INTERACTIVE
-	imply CMD_SATA
 
 config TARGET_T2080RDB
 	bool "Support T2080RDB"
@@ -361,6 +360,7 @@
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply FSL_SATA
 	imply PANIC_HANG
 
 config TARGET_T2081QDS
@@ -1081,10 +1081,8 @@
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_IFC
-	imply CMD_SATA
 	imply CMD_NAND
 	imply CMD_REGINFO
-	imply FSL_SATA
 
 config ARCH_T2081
 	bool
diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi
index db65ea5..d2bebb0 100644
--- a/arch/powerpc/dts/t2080.dtsi
+++ b/arch/powerpc/dts/t2080.dtsi
@@ -58,5 +58,50 @@
 			device_type = "open-pic";
 			clock-frequency = <0x0>;
 		};
+
+		esdhc: esdhc@114000 {
+			compatible = "fsl,esdhc";
+			reg = <0x114000 0x1000>;
+			interrupts = <48 2 0 0>;
+			clock-frequency = <0>;
+			sdhci,auto-cmd12;
+			bus-width = <4>;
+			voltage-ranges = <1800 1800 3300 3300>;
+		};
+
+		usb0: usb@210000 {
+			compatible = "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <44 0x2 0 0>;
+			phy_type = "utmi";
+		};
+
+		usb1: usb@211000 {
+			compatible = "fsl-usb2-dr";
+			reg = <0x211000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <45 0x2 0 0>;
+			dr_mode = "host";
+			phy_type = "utmi";
+		};
+
+		sata0: sata@220000 {
+			compatible = "fsl,pq-sata-v2";
+			reg = <0x220000 0x1000>;
+			interrupts = <68 0x2 0 0>;
+			sata-number = <0x0>;
+			sata-fpdma = <0x0>;
+		};
+
+		sata1: sata@221000 {
+			compatible = "fsl,pq-sata-v2";
+			reg = <0x221000 0x1000>;
+			interrupts = <69 0x2 0 0>;
+			sata-number = <0x0>;
+			sata-fpdma = <0x0>;
+		};
 	};
 };
diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig
new file mode 100644
index 0000000..ca22c92
--- /dev/null
+++ b/board/freescale/ls1028a/Kconfig
@@ -0,0 +1,65 @@
+if TARGET_LS1028AQDS
+
+config SYS_BOARD
+	default "ls1028a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1028aqds"
+
+config EMMC_BOOT
+	bool "Support for booting from EMMC"
+	default n
+
+config SYS_TEXT_BASE
+	default 0x96000000 if SD_BOOT || EMMC_BOOT
+	default 0x82000000 if TFABOOT
+	default 0x20100000
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA header Addr"
+	default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
+
+if TARGET_LS1028ARDB
+
+config SYS_BOARD
+	default "ls1028a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1028ardb"
+
+config EMMC_BOOT
+	bool "Support for booting from EMMC"
+	default n
+
+config SYS_TEXT_BASE
+	default 0x96000000 if SD_BOOT || EMMC_BOOT
+	default 0x82000000 if TFABOOT
+	default 0x20100000
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS
new file mode 100644
index 0000000..6f1a95e
--- /dev/null
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -0,0 +1,21 @@
+LS1028AQDS BOARD
+M:	Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
+M:	Rai Harninder <harninder.rai@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M:	Tang Yuantian <andy.tang@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1028a/
+F:	include/configs/ls1028a_common.h
+F:	include/configs/ls1028aqds.h
+F:	configs/ls1028aqds_tfa_defconfig
+
+LS1028ARDB BOARD
+M:	Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
+M:	Rai Harninder <harninder.rai@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M:	Tang Yuantian <andy.tang@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1028a/
+F:	include/configs/ls1028a_common.h
+F:	include/configs/ls1028ardb.h
+F:	configs/ls1028ardb_tfa_defconfig
diff --git a/board/freescale/ls1028a/Makefile b/board/freescale/ls1028a/Makefile
new file mode 100644
index 0000000..9bc144c
--- /dev/null
+++ b/board/freescale/ls1028a/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2019 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls1028a.o
+obj-y += ddr.o
diff --git a/board/freescale/ls1028a/README b/board/freescale/ls1028a/README
new file mode 100644
index 0000000..323881f
--- /dev/null
+++ b/board/freescale/ls1028a/README
@@ -0,0 +1,164 @@
+Overview
+--------
+The LS1028A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports ARM SoC LS1028A and its
+derivatives.
+
+LS1028A SoC Overview
+--------------------------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+RDB Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+For XSPI NOR boot (default)
+SW2: 1111_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+For SD Boot
+SW2: 1000_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+For eMMC Boot
+SW2: 1001_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+LS1028ARDB board Overview
+-------------------------
+Processor
+ Two Arm Cortex- A72 processor cores:
+  - Based on 64-bit ARMv8 architecture
+  - Up to 1.3 GHz operation
+  - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
+    data cache
+  - Arranged as a single cluster of two cores sharing a single 1 MB L2
+    cache
+DDR memory
+  - Five onboard 1G x8 discrete memory modules (Four data byte lanes
+    ECC)
+  - 32-bit data and 4-bit ECC
+  - One chip select
+  - Data transfer rates of up to 1.6 GT/s
+  - Single-bit error correction and double-bit error detection ECC (4-bit
+    check word across 32-bit data)
+High-speed serial ports(SerDes)
+ - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
+   Qualcomm AR8033 PHY
+ - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
+   through the NXP F104S8A PHY
+ - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
+   (8 Gbit/s) cards
+ - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
+   slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
+   SATA Gen 3 cards (6 Gbit/s) at a time
+eSDHC
+ - eSDHC1, eSDHC2
+SPI
+ - Connects to two mikroBUS sockets to support mikro-click modules,
+   such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
+   field communications (NFC) controller
+Octal SPI (XSPI)
+ - One 256 MB onboard XSPI serial NOR flash memory
+ - One 512 MB onboard XSPI serial NAND flash memory
+ - Supports a QSPI emulator for offboard QSPI emulation
+I2C
+ - All system devices are accessed via I2C1, which is multiplexed on
+   I2C multiplexer PCA9848 to isolate address conflicts and reduce
+   capacitive load
+ - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
+   thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
+   1 and 2
+CAN
+ - The two CAN DB9 ports can support CAN FD fast phase at data rates of
+   up to 5 Mbit/s
+Serial audio interface(SAI)
+ - Audio codec SGTL5000 provides headphone and audio LINEOUT for
+   stereo speakers
+ - IEEE1588 interface to support audio on SAI4
+
+QDS Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+For SD Boot
+SW1 : 1000_0000
+SW2 : 1110_0110
+SW3 : 0000_0010
+SW4 : 0000_0000
+SW5 : 0000_0000
+SW6 : 0000_0000
+SW7 : 1111_0011
+SW8 : 1110_0000
+SW9 : 1000_0001
+SW10: 1110_0000
+
+For XSPI Boot
+SW1 : 1111_0000
+SW2 : 0000_0110
+SW3 : 0000_0010
+SW4 : 0000_0000
+SW5 : 0110_0000
+SW6 : 0101_0000
+SW7 : 1111_0011
+SW8 : 1110_0000
+SW9 : 1000_0000
+SW10: 1110_0000
+
+LS1028AQDS board Overview
+-------------------------
+Processor
+ Two Arm Cortex- A72 processor cores:
+  - Based on 64-bit ARMv8 architecture
+  - Up to 1.3 GHz operation
+  - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
+    data cache
+  - Arranged as a single cluster of two cores sharing a single 1 MB L2
+    cache
+DDR memory
+ - Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L
+ - Supports a single- or dual-ranked SODIMM or UDIMM connector
+ - 32-bit data and 4-bit ECC
+ - Supports x8/x16 devices
+ - Supports ECC error detection and correction
+ - 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to
+   all devices in case of DDR3L or DDR4, respectively. Power can
+   switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or
+   DDR4 devices, respectively
+SerDes (Serializer/Deserializer)
+ - Four-lane (0-3) SerDes:
+ - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
+   Gbit SXGMII, 1 Gbit SGMII
+ - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+   SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII
+ - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+   SGMII
+ - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+   SGMII, SATA 2.0/3.0
+ - Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII
+   add-in cards
+ - Lane 1 connects to a 2x10 connector with SFP+ through a retimer;
+   lane 2 (TX lines) connects to an SMA connector
+   Lane 3 connects to 1x7 header to support SATA devices
+eSDHC
+ - eSDHC1, eSDHC2
+SPI
+ - SPI1 and SPI2 support three onboard SPI flash memory devices:
+    512 Mbit high-speed flash (with speed of up to 108/54 MHz)
+    memory for storage
+    4 Mbit low-speed flash memory (with speed of up to 40 MHz)
+    64 Mbit high-speed flash memory (with speed of up to 104/80
+    MHz)
+ - SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of
+   up to 104/80 MHz)
+ - All memories operate at 1.8 V
+ - A header is provided on SPI1 to test SPI slave mode
+I2C
+ - LS1028A supports eight I2C controllers
+Serial audio interface(SAI)
+ Two SAI ports with audio codec SGTL5000:
+  - Include stereo LINEIN with support for external analog input
+  - Provide headphone and line output
+Display
+ - DisplayPort connector to connect the DP data to a 4K display device
+   (computer monitor)
+ - eDP connector to connect the DP data to a 4K display panel
diff --git a/board/freescale/ls1028a/ddr.c b/board/freescale/ls1028a/ddr.c
new file mode 100644
index 0000000..74d3af5
--- /dev/null
+++ b/board/freescale/ls1028a/ddr.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
new file mode 100644
index 0000000..e5de4eb
--- /dev/null
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <hwconfig.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <environment.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <fsl_immap.h>
+#include <netdev.h>
+
+#include <fdtdec.h>
+#include <miiphy.h>
+#include "../common/qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int config_board_mux(void)
+{
+#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
+	u8 reg;
+
+	reg = QIXIS_READ(brdcfg[13]);
+	/* Field| Function
+	 * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
+	 * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
+	 * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
+	 * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
+	 */
+	reg &= ~(0xf0);
+	reg |= 0xb0;
+	QIXIS_WRITE(brdcfg[13], reg);
+
+	reg = QIXIS_READ(brdcfg[15]);
+	/* Field| Function
+	 * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
+	 * CAN1 | 0= CAN #1 transceiver enabled
+	 * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
+	 * CAN2 | 0= CAN #2 transceiver enabled
+	 */
+	reg &= ~(0xc0);
+	QIXIS_WRITE(brdcfg[15], reg);
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+#ifndef CONFIG_SYS_EARLY_PCI_INIT
+	pci_init();
+#endif
+
+#if defined(CONFIG_TARGET_LS1028ARDB)
+	u8 val = I2C_MUX_CH_DEFAULT;
+
+	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
+#endif
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+	config_board_mux();
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
+
+	fsl_lsch3_early_init_f();
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	ft_cpu_setup(blob, bd);
+
+	/* fixup DT for the two GPP DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+#ifdef CONFIG_RESV_RAM
+	/* reduce size if reserved memory is within this bank */
+	if (gd->arch.resv_ram >= base[0] &&
+	    gd->arch.resv_ram < base[0] + size[0])
+		size[0] = gd->arch.resv_ram - base[0];
+	else if (gd->arch.resv_ram >= base[1] &&
+		 gd->arch.resv_ram < base[1] + size[1])
+		size[1] = gd->arch.resv_ram - base[1];
+#endif
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_QIXIS
+int checkboard(void)
+{
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+#endif
+	u8 sw;
+
+	int clock;
+	char *board;
+	char buf[64] = {0};
+	static const char *freq[6] = {"100.00", "125.00", "156.25",
+					"161.13", "322.26", "100.00 SS"};
+
+	cpu_name(buf);
+	/* find the board details */
+	sw = QIXIS_READ(id);
+
+	switch (sw) {
+	case 0x46:
+		board = "QDS";
+		break;
+	case 0x47:
+		board = "RDB";
+		break;
+	case 0x49:
+		board = "HSSI";
+		break;
+	default:
+		board = "unknown";
+		break;
+	}
+
+	sw = QIXIS_READ(arch);
+	printf("Board: %s-%s, Version: %c, boot from ",
+	       buf, board, (sw & 0xf) + 'A' - 1);
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+#ifdef CONFIG_TFABOOT
+	if (src == BOOT_SOURCE_SD_MMC) {
+		puts("SD\n");
+	} else if (src == BOOT_SOURCE_SD_MMC2) {
+		puts("eMMC\n");
+	} else {
+#endif
+#ifdef CONFIG_SD_BOOT
+		puts("SD\n");
+#elif defined(CONFIG_EMMC_BOOT)
+		puts("eMMC\n");
+#else
+		switch (sw) {
+		case 0:
+		case 4:
+			printf("NOR\n");
+			break;
+		case 1:
+			printf("NAND\n");
+			break;
+		default:
+			printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+			break;
+		}
+#endif
+#ifdef CONFIG_TFABOOT
+	}
+#endif
+
+	printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
+	puts("SERDES1 Reference : ");
+
+	sw = QIXIS_READ(brdcfg[2]);
+#ifdef CONFIG_TARGET_LS1028ARDB
+	clock = (sw >> 6) & 3;
+#else
+	clock = (sw >> 4) & 0xf;
+#endif
+
+	printf("Clock1 = %sMHz ", freq[clock]);
+#ifdef CONFIG_TARGET_LS1028ARDB
+	clock = (sw >> 4) & 3;
+#else
+	clock = sw & 0xf;
+#endif
+	printf("Clock2 = %sMHz\n", freq[clock]);
+
+	return 0;
+}
+#endif
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 3875d04..6109b28 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -449,12 +449,20 @@
 
 int board_init(void)
 {
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
 #ifdef CONFIG_ENV_IS_NOWHERE
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
 
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+	/* invert AQR107 IRQ pins polarity */
+	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
+#endif
+
 #ifdef CONFIG_FSL_CAAM
 	sec_init();
 #endif
diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c
index 5c1acca..c3d832f 100644
--- a/board/st/stm32mp1/board.c
+++ b/board/st/stm32mp1/board.c
@@ -38,9 +38,10 @@
 #endif
 
 #ifdef CONFIG_PMIC_STPMIC1
-int board_ddr_power_init(void)
+int board_ddr_power_init(enum ddr_type ddr_type)
 {
 	struct udevice *dev;
+	bool buck3_at_1800000v = false;
 	int ret;
 
 	ret = uclass_get_device_by_driver(UCLASS_PMIC,
@@ -49,53 +50,127 @@
 		/* No PMIC on board */
 		return 0;
 
-	/* VTT = Set LDO3 to sync mode */
-	ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
-	if (ret < 0)
-		return ret;
+	switch (ddr_type) {
+	case STM32MP_DDR3:
+		/* VTT = Set LDO3 to sync mode */
+		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+		if (ret < 0)
+			return ret;
 
-	ret &= ~STPMIC1_LDO3_MODE;
-	ret &= ~STPMIC1_LDO12356_VOUT_MASK;
-	ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
+		ret &= ~STPMIC1_LDO3_MODE;
+		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+		ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
 
-	ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
-			     ret);
-	if (ret < 0)
-		return ret;
+		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				     ret);
+		if (ret < 0)
+			return ret;
 
-	/* VDD_DDR = Set BUCK2 to 1.35V */
-	ret = pmic_clrsetbits(dev,
-			      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
-			      STPMIC1_BUCK_VOUT_MASK,
-			      STPMIC1_BUCK2_1350000V);
-	if (ret < 0)
-		return ret;
+		/* VDD_DDR = Set BUCK2 to 1.35V */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_VOUT_MASK,
+				      STPMIC1_BUCK2_1350000V);
+		if (ret < 0)
+			return ret;
 
-	/* Enable VDD_DDR = BUCK2 */
-	ret = pmic_clrsetbits(dev,
-			      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
-			      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
-	if (ret < 0)
-		return ret;
+		/* Enable VDD_DDR = BUCK2 */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+		if (ret < 0)
+			return ret;
 
-	mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 
-	/* Enable VREF */
-	ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
-			      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
-	if (ret < 0)
-		return ret;
+		/* Enable VREF */
+		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+		if (ret < 0)
+			return ret;
 
-	mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 
-	/* Enable LDO3 */
-	ret = pmic_clrsetbits(dev,
-			      STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
-			      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
-	if (ret < 0)
-		return ret;
+		/* Enable VTT = LDO3 */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+		if (ret < 0)
+			return ret;
 
-	mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		break;
+
+	case STM32MP_LPDDR2:
+	case STM32MP_LPDDR3:
+		/*
+		 * configure VDD_DDR1 = LDO3
+		 * Set LDO3 to 1.8V
+		 * + bypass mode if BUCK3 = 1.8V
+		 * + normal mode if BUCK3 != 1.8V
+		 */
+		ret = pmic_reg_read(dev,
+				    STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
+		if (ret < 0)
+			return ret;
+
+		if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
+			buck3_at_1800000v = true;
+
+		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+		if (ret < 0)
+			return ret;
+
+		ret &= ~STPMIC1_LDO3_MODE;
+		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+		ret |= STPMIC1_LDO3_1800000;
+		if (buck3_at_1800000v)
+			ret |= STPMIC1_LDO3_MODE;
+
+		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				     ret);
+		if (ret < 0)
+			return ret;
+
+		/* VDD_DDR2 : Set BUCK2 to 1.2V */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_VOUT_MASK,
+				      STPMIC1_BUCK2_1200000V);
+		if (ret < 0)
+			return ret;
+
+		/* Enable VDD_DDR1 = LDO3 */
+		ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		/* Enable VDD_DDR2 =BUCK2 */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		/* Enable VREF */
+		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		break;
+
+	default:
+		break;
+	};
 
 	return 0;
 }
diff --git a/common/Kconfig b/common/Kconfig
index 1a1951f..c759952 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -247,6 +247,7 @@
 config PREBOOT
 	string "preboot default value"
 	depends on USE_PREBOOT
+	default ""
 	help
 	  This is the default of "preboot" environment variable.
 
diff --git a/common/Makefile b/common/Makefile
index 8c92feb..c7e41ef 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -124,6 +124,7 @@
 
 obj-y += cli.o
 obj-$(CONFIG_FSL_DDR_INTERACTIVE) += cli_simple.o cli_readline.o
+obj-$(CONFIG_STM32MP1_DDR_INTERACTIVE) += cli_simple.o cli_readline.o
 obj-$(CONFIG_DFU_OVER_USB) += dfu.o
 obj-y += command.o
 obj-$(CONFIG_$(SPL_TPL_)LOG) += log.o
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 4e7cf6e..f31e9b0 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -722,11 +722,6 @@
 #include <jffs2/load_kernel.h>
 #include <mtd_node.h>
 
-struct reg_cell {
-	unsigned int r0;
-	unsigned int r1;
-};
-
 static int fdt_del_subnodes(const void *blob, int parent_offset)
 {
 	int off, ndepth;
@@ -785,9 +780,9 @@
 {
 	struct list_head *pentry;
 	struct part_info *part;
-	struct reg_cell cell;
 	int off, ndepth = 0;
 	int part_num, ret;
+	int sizecell;
 	char buf[64];
 
 	ret = fdt_del_partitions(blob, parent_offset);
@@ -795,6 +790,13 @@
 		return ret;
 
 	/*
+	 * Check if size/address is 1 or 2 cells.
+	 * We assume #address-cells and #size-cells have same value.
+	 */
+	sizecell = fdt_getprop_u32_default_node(blob, parent_offset,
+						0, "#size-cells", 1);
+
+	/*
 	 * Check if it is nand {}; subnode, adjust
 	 * the offset in this case
 	 */
@@ -842,10 +844,21 @@
 				goto err_prop;
 		}
 
-		cell.r0 = cpu_to_fdt32(part->offset);
-		cell.r1 = cpu_to_fdt32(part->size);
 add_reg:
-		ret = fdt_setprop(blob, newoff, "reg", &cell, sizeof(cell));
+		if (sizecell == 2) {
+			ret = fdt_setprop_u64(blob, newoff,
+					      "reg", part->offset);
+			if (!ret)
+				ret = fdt_appendprop_u64(blob, newoff,
+							 "reg", part->size);
+		} else {
+			ret = fdt_setprop_u32(blob, newoff,
+					      "reg", part->offset);
+			if (!ret)
+				ret = fdt_appendprop_u32(blob, newoff,
+							 "reg", part->size);
+		}
+
 		if (ret == -FDT_ERR_NOSPACE) {
 			ret = fdt_increase_size(blob, 512);
 			if (!ret)
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index b3de724..c92c62e 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -48,7 +48,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index e576a87..8959910 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -36,7 +36,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index 896df53..c94444f 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -35,7 +35,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index bd427f3..b5f2ab9 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -48,7 +48,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index e376a19..3eb3107 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -36,7 +36,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index 90e19bd..b11b071 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -36,7 +36,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index c35c752..412a7d4 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -32,7 +32,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index 03b925f..2df7196 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -35,7 +35,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index cf61c62..200257a 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -31,7 +31,9 @@
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index 832b694..9336e73 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -31,7 +31,9 @@
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 934cda4..9b5d35c 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -11,6 +11,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
index efa5e71..55f6fb9 100644
--- a/configs/M52277EVB_defconfig
+++ b/configs/M52277EVB_defconfig
@@ -15,6 +15,7 @@
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
 CONFIG_CMD_JFFS2=y
+CONFIG_DEFAULT_DEVICE_TREE="M52277EVB"
 CONFIG_ENV_IS_IN_FLASH=y
 # CONFIG_NET is not set
 CONFIG_MTD_NOR_FLASH=y
@@ -25,4 +26,5 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
index cafc861..ee0dced 100644
--- a/configs/M52277EVB_stmicro_defconfig
+++ b/configs/M52277EVB_stmicro_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
 CONFIG_CMD_JFFS2=y
+CONFIG_DEFAULT_DEVICE_TREE="M52277EVB_stmicro"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_CS=y
 CONFIG_ENV_SPI_CS=2
@@ -26,4 +27,5 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index fff5743..2e40b21 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -16,6 +16,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5235EVB_Flash32"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index 07e0f4f..fd5dd98 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -16,6 +16,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5235EVB"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig
index 908f6a1..c39818b 100644
--- a/configs/M5249EVB_defconfig
+++ b/configs/M5249EVB_defconfig
@@ -9,6 +9,7 @@
 CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
 # CONFIG_NET is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig
index 4685c4e..0775ad5 100644
--- a/configs/M5253DEMO_defconfig
+++ b/configs/M5253DEMO_defconfig
@@ -13,4 +13,5 @@
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MAC_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO"
 CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index 85283d4..c39876d 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -13,6 +13,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5272C3"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index 5ff2624..ecb3e32 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -15,6 +15,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5275EVB"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index 289922b..731fb1e 100644
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -13,6 +13,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5282EVB"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index 0b1073a..92dfd02 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M53017EVB"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index c6dff0e..20acb64 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -15,6 +15,7 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index 56dba26..96c57ec 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -15,6 +15,7 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 3982320..ef66d7c 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -15,6 +15,7 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5373EVB"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
index a239f4a..08af6f2 100644
--- a/configs/M54418TWR_defconfig
+++ b/configs/M54418TWR_defconfig
@@ -19,6 +19,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_CS=y
 CONFIG_ENV_SPI_CS=1
@@ -26,4 +27,5 @@
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig
index 04ca3a8..6fa822d 100644
--- a/configs/M54418TWR_nand_mii_defconfig
+++ b/configs/M54418TWR_nand_mii_defconfig
@@ -19,8 +19,10 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_mii"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig
index f6acf60..1fa7b38 100644
--- a/configs/M54418TWR_nand_rmii_defconfig
+++ b/configs/M54418TWR_nand_rmii_defconfig
@@ -19,8 +19,10 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
index 6b631d6..5208e59 100644
--- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig
+++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
@@ -19,8 +19,10 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii_lowfreq"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
index 8b72bd3..131fd3a 100644
--- a/configs/M54418TWR_serial_mii_defconfig
+++ b/configs/M54418TWR_serial_mii_defconfig
@@ -19,6 +19,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_mii"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_CS=y
 CONFIG_ENV_SPI_CS=1
@@ -26,4 +27,5 @@
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
index a239f4a..fd561f3 100644
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ b/configs/M54418TWR_serial_rmii_defconfig
@@ -19,6 +19,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_rmii"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_CS=y
 CONFIG_ENV_SPI_CS=1
@@ -26,4 +27,5 @@
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig
index 8448b6c..f0bd93f 100644
--- a/configs/M54451EVB_defconfig
+++ b/configs/M54451EVB_defconfig
@@ -20,6 +20,7 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54451EVB"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -30,4 +31,5 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig
index b614ca7..144d29b 100644
--- a/configs/M54451EVB_stmicro_defconfig
+++ b/configs/M54451EVB_stmicro_defconfig
@@ -19,6 +19,7 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54451EVB_stmicro"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_CS=y
 CONFIG_ENV_SPI_CS=1
@@ -31,4 +32,5 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig
index f9be1c3..ca40308 100644
--- a/configs/M54455EVB_a66_defconfig
+++ b/configs/M54455EVB_a66_defconfig
@@ -24,6 +24,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_JFFS2=y
 CONFIG_ISO_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_a66"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -34,4 +35,5 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig
index abb69a9..3ca2d73 100644
--- a/configs/M54455EVB_defconfig
+++ b/configs/M54455EVB_defconfig
@@ -25,6 +25,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_JFFS2=y
 CONFIG_ISO_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -35,4 +36,5 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig
index 6050df5..20abcd8 100644
--- a/configs/M54455EVB_i66_defconfig
+++ b/configs/M54455EVB_i66_defconfig
@@ -24,6 +24,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_JFFS2=y
 CONFIG_ISO_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_i66"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -34,4 +35,5 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig
index 686c00e..a17e4fa 100644
--- a/configs/M54455EVB_intel_defconfig
+++ b/configs/M54455EVB_intel_defconfig
@@ -24,6 +24,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_JFFS2=y
 CONFIG_ISO_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_intel"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -34,4 +35,5 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig
index 467bfae..c3f0464 100644
--- a/configs/M54455EVB_stm33_defconfig
+++ b/configs/M54455EVB_stm33_defconfig
@@ -24,6 +24,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_JFFS2=y
 CONFIG_ISO_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_stm33"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_CS=y
 CONFIG_ENV_SPI_CS=1
@@ -36,4 +37,5 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig
index b0296ac..368f73e 100644
--- a/configs/M5475AFE_defconfig
+++ b/configs/M5475AFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475AFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig
index 7fc61bd..d44b0b2 100644
--- a/configs/M5475BFE_defconfig
+++ b/configs/M5475BFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475BFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig
index 22d1074..108ef97 100644
--- a/configs/M5475CFE_defconfig
+++ b/configs/M5475CFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475CFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig
index ee8c2ab..9325db5 100644
--- a/configs/M5475DFE_defconfig
+++ b/configs/M5475DFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475DFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig
index 939e56b..6873f15 100644
--- a/configs/M5475EFE_defconfig
+++ b/configs/M5475EFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475EFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig
index 1fef8ff..a98e804c 100644
--- a/configs/M5475FFE_defconfig
+++ b/configs/M5475FFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475FFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig
index d78caff..ed75743 100644
--- a/configs/M5475GFE_defconfig
+++ b/configs/M5475GFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475GFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig
index 5cda25a..8f94ac9 100644
--- a/configs/M5485AFE_defconfig
+++ b/configs/M5485AFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485AFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig
index 7cd4a53..96bd520 100644
--- a/configs/M5485BFE_defconfig
+++ b/configs/M5485BFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485BFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig
index ff5e8ef..148be33 100644
--- a/configs/M5485CFE_defconfig
+++ b/configs/M5485CFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485CFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig
index c4dd6c3..5facb07 100644
--- a/configs/M5485DFE_defconfig
+++ b/configs/M5485DFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485DFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig
index 4e84828..ece3e11 100644
--- a/configs/M5485EFE_defconfig
+++ b/configs/M5485EFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485EFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig
index f6264e8..c2a2d92 100644
--- a/configs/M5485FFE_defconfig
+++ b/configs/M5485FFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485FFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig
index 9a589e0..9cf6202 100644
--- a/configs/M5485GFE_defconfig
+++ b/configs/M5485GFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485GFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig
index edc50c8..e6c9225 100644
--- a/configs/M5485HFE_defconfig
+++ b/configs/M5485HFE_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485HFE"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
index 753d697..8678616 100644
--- a/configs/MCR3000_defconfig
+++ b/configs/MCR3000_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_MPC8xx=y
+CONFIG_SYS_IMMR=0xFF000000
 CONFIG_TARGET_MCR3000=y
 CONFIG_8xx_GCLK_FREQ=132000000
 CONFIG_CMD_IMMAP=y
@@ -36,7 +37,6 @@
 CONFIG_SYS_BR7_PRELIM_BOOL=y
 CONFIG_SYS_BR7_PRELIM=0x1C000001
 CONFIG_SYS_OR7_PRELIM=0xFFFF810A
-CONFIG_SYS_IMMR=0xFF000000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTDELAY=5
 CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index 1a38ebd..5faf20f 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -58,6 +58,39 @@
 CONFIG_LBLAW2_BASE=0xF0000000
 CONFIG_LBLAW2_NAME="VSC7385"
 CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385_BASE"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
@@ -103,41 +136,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385_BASE"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index 04eb29a..9b58860 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -73,12 +73,56 @@
 CONFIG_LBLAW3_BASE=0xFA000000
 CONFIG_LBLAW3_NAME="BCSR"
 CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE2800000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
@@ -109,55 +153,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE2800000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="BCSR"
-CONFIG_BR3_OR3_BASE=0xFA000000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index 8bbeb97..98fcda1 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -72,12 +72,56 @@
 CONFIG_LBLAW3_BASE=0xFA000000
 CONFIG_LBLAW3_NAME="BCSR"
 CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE2800000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
@@ -108,55 +152,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE2800000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="BCSR"
-CONFIG_BR3_OR3_BASE=0xFA000000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 29b12d0..48c1977 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -75,12 +75,56 @@
 CONFIG_LBLAW3_BASE=0xFA000000
 CONFIG_LBLAW3_NAME="BCSR"
 CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="NAND"
+CONFIG_BR0_OR0_BASE=0xE2800000
+CONFIG_BR0_ERRORCHECKING_BOTH=y
+CONFIG_BR0_MACHINE_FCM=y
+CONFIG_OR0_SCY_1=y
+CONFIG_OR0_CSCT_8_CYCLE=y
+CONFIG_OR0_CST_ONE_CLOCK=y
+CONFIG_OR0_CHT_TWO_CLOCK=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FLASH"
+CONFIG_BR1_OR1_BASE=0xFE000000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_8_MBYTES=y
+CONFIG_OR1_SCY_9=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_EHTR_1_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
@@ -117,55 +161,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="NAND"
-CONFIG_BR0_OR0_BASE=0xE2800000
-CONFIG_BR0_ERRORCHECKING_BOTH=y
-CONFIG_BR0_MACHINE_FCM=y
-CONFIG_BR0_PORTSIZE_8BIT=y
-CONFIG_OR0_AM_32_KBYTES=y
-CONFIG_OR0_SCY_1=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_CHT_TWO_CLOCK=y
-CONFIG_OR0_CSCT_8_CYCLE=y
-CONFIG_OR0_CST_ONE_CLOCK=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FLASH"
-CONFIG_BR1_OR1_BASE=0xFE000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_8_MBYTES=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_9=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_EHTR_1_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="BCSR"
-CONFIG_BR3_OR3_BASE=0xFA000000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index 2dc31ed..eee9227 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -74,12 +74,56 @@
 CONFIG_LBLAW3_BASE=0xFA000000
 CONFIG_LBLAW3_NAME="BCSR"
 CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="NAND"
+CONFIG_BR0_OR0_BASE=0xE2800000
+CONFIG_BR0_ERRORCHECKING_BOTH=y
+CONFIG_BR0_MACHINE_FCM=y
+CONFIG_OR0_SCY_1=y
+CONFIG_OR0_CSCT_8_CYCLE=y
+CONFIG_OR0_CST_ONE_CLOCK=y
+CONFIG_OR0_CHT_TWO_CLOCK=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FLASH"
+CONFIG_BR1_OR1_BASE=0xFE000000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_8_MBYTES=y
+CONFIG_OR1_SCY_9=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_EHTR_1_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
@@ -116,55 +160,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="NAND"
-CONFIG_BR0_OR0_BASE=0xE2800000
-CONFIG_BR0_ERRORCHECKING_BOTH=y
-CONFIG_BR0_MACHINE_FCM=y
-CONFIG_BR0_PORTSIZE_8BIT=y
-CONFIG_OR0_AM_32_KBYTES=y
-CONFIG_OR0_SCY_1=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_CHT_TWO_CLOCK=y
-CONFIG_OR0_CSCT_8_CYCLE=y
-CONFIG_OR0_CST_ONE_CLOCK=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FLASH"
-CONFIG_BR1_OR1_BASE=0xFE000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_8_MBYTES=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_9=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_EHTR_1_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="BCSR"
-CONFIG_BR3_OR3_BASE=0xFA000000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index 08b5cc5..2a550bc 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -76,6 +76,30 @@
 CONFIG_LBLAW1_BASE=0xE0600000
 CONFIG_LBLAW1_NAME="NAND"
 CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
@@ -83,6 +107,7 @@
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -116,32 +141,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index 8ea942d..349d611 100644
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -70,12 +70,26 @@
 CONFIG_LBLAW0_BASE=0xFE000000
 CONFIG_LBLAW0_NAME="FLASH"
 CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_OPT_SPEC_READ=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -92,21 +106,6 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index c39f449..3eda9a4 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -68,9 +68,53 @@
 CONFIG_LBLAW3_BASE=0xF8008000
 CONFIG_LBLAW3_NAME="PIB"
 CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
@@ -88,60 +132,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_32_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index 0e65d21..ede3b8a 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -88,9 +88,53 @@
 CONFIG_LBLAW3_BASE=0xF8008000
 CONFIG_LBLAW3_NAME="PIB"
 CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1"
@@ -108,60 +152,6 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_32_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index 472384f..370a914 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -88,9 +88,53 @@
 CONFIG_LBLAW3_BASE=0xF8008000
 CONFIG_LBLAW3_NAME="PIB"
 CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1"
@@ -108,60 +152,6 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_32_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index ec8a94c..5b1c8f8 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -85,9 +85,53 @@
 CONFIG_LBLAW3_BASE=0xF8008000
 CONFIG_LBLAW3_NAME="PIB"
 CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
@@ -105,60 +149,6 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_32_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index 8a26001..34fbe53 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -68,9 +68,53 @@
 CONFIG_LBLAW3_BASE=0xF8008000
 CONFIG_LBLAW3_NAME="PIB"
 CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -87,60 +131,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_32_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig
index 35b394b..f99aaec 100644
--- a/configs/MPC8349EMDS_PCI64_defconfig
+++ b/configs/MPC8349EMDS_PCI64_defconfig
@@ -53,6 +53,25 @@
 CONFIG_LBLAW1_BASE=0xE2400000
 CONFIG_LBLAW1_NAME="BCSR"
 CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -60,6 +79,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSEC1EP_3=y
 CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -72,7 +93,6 @@
 CONFIG_CMD_DATE=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
-CONFIG_NETDEVICES=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
@@ -80,29 +100,3 @@
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xE2400000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_EHTR_NORMAL=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig
index 936458a..9c2182e 100644
--- a/configs/MPC8349EMDS_SDRAM_defconfig
+++ b/configs/MPC8349EMDS_SDRAM_defconfig
@@ -57,11 +57,6 @@
 CONFIG_LBLAW2_BASE=0xF0000000
 CONFIG_LBLAW2_NAME="SDRAM"
 CONFIG_LBLAW2_LENGTH_64_MBYTES=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
 CONFIG_ELBC_BR0_OR0=y
 CONFIG_BR0_OR0_NAME="FLASH"
 CONFIG_BR0_OR0_BASE=0xFE000000
@@ -89,6 +84,13 @@
 CONFIG_OR2_COLS_9=y
 CONFIG_OR2_ROWS_13=y
 CONFIG_OR2_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -106,12 +108,9 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_MARVELL=y
-CONFIG_NETDEVICES=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_MPC8XXX_SPI=y
 CONFIG_OF_LIBFDT=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig
index 9649967..3a1268a 100644
--- a/configs/MPC8349EMDS_SLAVE_defconfig
+++ b/configs/MPC8349EMDS_SLAVE_defconfig
@@ -51,6 +51,25 @@
 CONFIG_LBLAW1_BASE=0xE2400000
 CONFIG_LBLAW1_NAME="BCSR"
 CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -58,6 +77,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSEC1EP_3=y
 CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -75,34 +96,7 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
-CONFIG_NETDEVICES=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xE2400000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_EHTR_NORMAL=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index bb0d166..9cd3daa 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -53,6 +53,25 @@
 CONFIG_LBLAW1_BASE=0xE2400000
 CONFIG_LBLAW1_NAME="BCSR"
 CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -60,6 +79,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSEC1EP_3=y
 CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -83,29 +104,3 @@
 CONFIG_SPI=y
 CONFIG_MPC8XXX_SPI=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xE2400000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_EHTR_NORMAL=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index eddb72b..b4cf8c3 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -97,12 +97,55 @@
 CONFIG_LBLAW3_BASE=0xF0000000
 CONFIG_LBLAW3_NAME="CF"
 CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="VSC7385"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_AM_128_KBYTES=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="LED"
+CONFIG_BR2_OR2_BASE=0xF9000000
+CONFIG_OR2_AM_2_MBYTES=y
+CONFIG_OR2_SCY_9=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CF"
+CONFIG_BR3_OR3_BASE=0xF0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_BR3_MACHINE_UPMA=y
+CONFIG_OR3_BI_BURSTINHIBIT=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSEC1EP_3=y
 CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"
@@ -131,52 +174,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="VSC7385"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="LED"
-CONFIG_BR2_OR2_BASE=0xF9000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_2_MBYTES=y
-CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_9=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="CF"
-CONFIG_BR3_OR3_BASE=0xF0000000
-CONFIG_BR3_MACHINE_UPMA=y
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_BI_BURSTINHIBIT=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index b394da3..fbfeda5 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -97,12 +97,55 @@
 CONFIG_LBLAW3_BASE=0xF0000000
 CONFIG_LBLAW3_NAME="CF"
 CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="VSC7385"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_AM_128_KBYTES=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="LED"
+CONFIG_BR2_OR2_BASE=0xF9000000
+CONFIG_OR2_AM_2_MBYTES=y
+CONFIG_OR2_SCY_9=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CF"
+CONFIG_BR3_OR3_BASE=0xF0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_BR3_MACHINE_UPMA=y
+CONFIG_OR3_BI_BURSTINHIBIT=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSEC1EP_3=y
 CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -139,52 +182,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="VSC7385"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="LED"
-CONFIG_BR2_OR2_BASE=0xF9000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_2_MBYTES=y
-CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_9=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="CF"
-CONFIG_BR3_OR3_BASE=0xF0000000
-CONFIG_BR3_MACHINE_UPMA=y
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_BI_BURSTINHIBIT=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index 274fbdd..e9a8bb1 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -96,12 +96,55 @@
 CONFIG_LBLAW3_BASE=0xF0000000
 CONFIG_LBLAW3_NAME="CF"
 CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="VSC7385"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_AM_128_KBYTES=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="LED"
+CONFIG_BR2_OR2_BASE=0xF9000000
+CONFIG_OR2_AM_2_MBYTES=y
+CONFIG_OR2_SCY_9=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CF"
+CONFIG_BR3_OR3_BASE=0xF0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_BR3_MACHINE_UPMA=y
+CONFIG_OR3_BI_BURSTINHIBIT=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSEC1EP_3=y
 CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -138,52 +181,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="VSC7385"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="LED"
-CONFIG_BR2_OR2_BASE=0xF9000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_2_MBYTES=y
-CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_9=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="CF"
-CONFIG_BR3_OR3_BASE=0xF0000000
-CONFIG_BR3_MACHINE_UPMA=y
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_BI_BURSTINHIBIT=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index 6e6fc54..7b69f5b 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -101,12 +101,49 @@
 CONFIG_LBLAW3_BASE=0xE0600000
 CONFIG_LBLAW3_NAME="NAND"
 CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="NAND"
+CONFIG_BR3_OR3_BASE=0xE0600000
+CONFIG_BR3_ERRORCHECKING_BOTH=y
+CONFIG_BR3_MACHINE_FCM=y
+CONFIG_OR3_BCTLD_NOT_ASSERTED=y
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_CST_ONE_CLOCK=y
+CONFIG_OR3_CHT_TWO_CLOCK=y
+CONFIG_OR3_RST_ONE_CLOCK=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -137,46 +174,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="NAND"
-CONFIG_BR3_OR3_BASE=0xE0600000
-CONFIG_BR3_ERRORCHECKING_BOTH=y
-CONFIG_BR3_MACHINE_FCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_BCTLD_NOT_ASSERTED=y
-CONFIG_OR3_RST_ONE_CLOCK=y
-CONFIG_OR3_SCY_1=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_CHT_TWO_CLOCK=y
-CONFIG_OR3_CST_ONE_CLOCK=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig
index 421e176..17ccb40 100644
--- a/configs/MPC837XEMDS_SLAVE_defconfig
+++ b/configs/MPC837XEMDS_SLAVE_defconfig
@@ -61,12 +61,49 @@
 CONFIG_LBLAW3_BASE=0xE0600000
 CONFIG_LBLAW3_NAME="NAND"
 CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="NAND"
+CONFIG_BR3_OR3_BASE=0xE0600000
+CONFIG_BR3_ERRORCHECKING_BOTH=y
+CONFIG_BR3_MACHINE_FCM=y
+CONFIG_OR3_BCTLD_NOT_ASSERTED=y
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_CST_ONE_CLOCK=y
+CONFIG_OR3_CHT_TWO_CLOCK=y
+CONFIG_OR3_RST_ONE_CLOCK=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
@@ -90,46 +127,3 @@
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="NAND"
-CONFIG_BR3_OR3_BASE=0xE0600000
-CONFIG_BR3_ERRORCHECKING_BOTH=y
-CONFIG_BR3_MACHINE_FCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_BCTLD_NOT_ASSERTED=y
-CONFIG_OR3_RST_ONE_CLOCK=y
-CONFIG_OR3_SCY_1=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_CHT_TWO_CLOCK=y
-CONFIG_OR3_CST_ONE_CLOCK=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index cd03f3f..47125e2 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -81,12 +81,49 @@
 CONFIG_LBLAW3_BASE=0xE0600000
 CONFIG_LBLAW3_NAME="NAND"
 CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="NAND"
+CONFIG_BR3_OR3_BASE=0xE0600000
+CONFIG_BR3_ERRORCHECKING_BOTH=y
+CONFIG_BR3_MACHINE_FCM=y
+CONFIG_OR3_BCTLD_NOT_ASSERTED=y
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_CST_ONE_CLOCK=y
+CONFIG_OR3_CHT_TWO_CLOCK=y
+CONFIG_OR3_RST_ONE_CLOCK=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -113,46 +150,3 @@
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="NAND"
-CONFIG_BR3_OR3_BASE=0xE0600000
-CONFIG_BR3_ERRORCHECKING_BOTH=y
-CONFIG_BR3_MACHINE_FCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_BCTLD_NOT_ASSERTED=y
-CONFIG_OR3_RST_ONE_CLOCK=y
-CONFIG_OR3_SCY_1=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_CHT_TWO_CLOCK=y
-CONFIG_OR3_CST_ONE_CLOCK=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig
index c90ebc8..4dcaed2 100644
--- a/configs/MPC837XERDB_SLAVE_defconfig
+++ b/configs/MPC837XERDB_SLAVE_defconfig
@@ -61,12 +61,45 @@
 CONFIG_LBLAW2_BASE=0xF0000000
 CONFIG_LBLAW2_NAME="VSC7385"
 CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"
@@ -86,7 +119,6 @@
 CONFIG_CMD_FAT=y
 CONFIG_FSL_SATA=y
 CONFIG_MTD_NOR_FLASH=y
-CONFIG_NETDEVICES=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
@@ -96,41 +128,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 95f4796..738e75a 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -101,12 +101,45 @@
 CONFIG_LBLAW2_BASE=0xF0000000
 CONFIG_LBLAW2_NAME="VSC7385"
 CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCIE"
@@ -139,41 +172,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
index f3544a2..190b0b8 100644
--- a/configs/MPC8568MDS_defconfig
+++ b/configs/MPC8568MDS_defconfig
@@ -25,5 +25,6 @@
 CONFIG_PHY_MARVELL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig
index 5140ae9..08e17bf 100644
--- a/configs/MPC8569MDS_ATM_defconfig
+++ b/configs/MPC8569MDS_ATM_defconfig
@@ -28,5 +28,7 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_E1000=y
+CONFIG_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig
index a778eae..f1b4a7b 100644
--- a/configs/MPC8569MDS_defconfig
+++ b/configs/MPC8569MDS_defconfig
@@ -27,5 +27,7 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_E1000=y
+CONFIG_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index ebbd4e5..5f751ed 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -60,6 +60,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index 87eae41..2e5ac93 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -57,6 +57,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index 07e2265..b65c245 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -58,6 +58,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index ae7752b..273435a 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -46,6 +46,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index 5b322e2..6cfd222 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -59,6 +59,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 6f1aa14..fd1c638 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -56,6 +56,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index 7f8951f..bd91531 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -57,6 +57,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
index 093c0ae..9671af1 100644
--- a/configs/P1021RDB-PC_defconfig
+++ b/configs/P1021RDB-PC_defconfig
@@ -45,6 +45,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig
index b4e27c4..ee2aee4 100644
--- a/configs/P1023RDB_defconfig
+++ b/configs/P1023RDB_defconfig
@@ -34,7 +34,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index 703b8d7..e2407e3 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -43,6 +43,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index 676f439..e5e80152 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -56,6 +56,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index fb77418..7b1c766 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -53,6 +53,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index bfda4f1..795e011 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -54,6 +54,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
index 19ac763..a22f1a1 100644
--- a/configs/P1025RDB_defconfig
+++ b/configs/P1025RDB_defconfig
@@ -42,6 +42,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 44966d8..e42fac3 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -38,7 +38,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 3d558c5..c339f1b 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index f42c141..91514e1 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 4fb3794..f164b1f 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
index ac74a25..4161d10 100644
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
@@ -33,7 +33,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 2a70296..f322c93 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -36,7 +36,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index b1bc659..d832063 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -39,7 +39,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 81ce703..6a31ce9 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -38,7 +38,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 7392948..c6b2291 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index f7ed963..483e393 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index c89ee84..0aebf86 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
index 2bc3f81..efb759d 100644
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
@@ -33,7 +33,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 6bae5a5..a44c1b4 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -36,7 +36,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index b67e12a..36884a8 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index 0e47d70..e6b1207 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index b108367..5155657 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
index a011c8c..095b21f 100644
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
@@ -33,7 +33,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index ee4f51d..995248d 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -36,7 +36,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index 078d70b..85f04ac 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -40,7 +40,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
index 7cbd790..0c9328b 100644
--- a/configs/P5020DS_NAND_defconfig
+++ b/configs/P5020DS_NAND_defconfig
@@ -39,7 +39,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
index c5438e2..c319a84 100644
--- a/configs/P5020DS_SDCARD_defconfig
+++ b/configs/P5020DS_SDCARD_defconfig
@@ -38,7 +38,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index 16607ae..85fa7bd 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -38,7 +38,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
index 0ac8813..5ae3097 100644
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ b/configs/P5020DS_SPIFLASH_defconfig
@@ -38,7 +38,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
index 487ad27..79de46e 100644
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
@@ -34,7 +34,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
index 6ef6de9..df43d13 100644
--- a/configs/P5020DS_defconfig
+++ b/configs/P5020DS_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index fd277ce..c085e68 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -40,7 +40,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index b2c61d7..5368f40 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -39,7 +39,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index dbff8f7..f1aa187 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -38,7 +38,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index 2469443..22b4d4e 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -38,7 +38,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 1552f84..7f31813 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -38,7 +38,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index e8ff36e..40d04e9 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -37,7 +37,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 80213d1..a495e3f 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -56,7 +56,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index 41176c2..c175ff6 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -55,7 +55,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index ebb5ce3..886aba7 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -44,7 +44,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index f3db410..3de2f30 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -56,7 +56,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index b334490..cadc16a 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -43,7 +43,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index dd5c006..423d642 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -47,7 +47,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index 9d887f1..6a61ddf 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -44,7 +44,9 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index 3d4099f..a3a27e8 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -60,7 +60,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 02226df..6fba569 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -59,7 +59,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index 5d8a919..9d6bc98 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -48,7 +48,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index 4077a2f..366fa96 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -60,7 +60,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index fbba22c..af0eb46 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -47,7 +47,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index ea00def..8377729 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -58,7 +58,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 6b966b6..3d72157 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -57,7 +57,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index 76e959f..cb751df 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -46,7 +46,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 59e1e77..9b5943f 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -58,7 +58,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 683a619..9059329 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -45,7 +45,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index 50757d9..4e12ba0 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -55,7 +55,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index 5d70e01..81c47e6 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -54,7 +54,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index d1b3c1a..7391eff 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -43,7 +43,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index 7b81373..259ff24 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -55,7 +55,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index 17c47de..8d7427d 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -42,7 +42,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index fad61d4..9aa5523 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -47,7 +47,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index a86936a..9cd30e5 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -49,7 +49,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index e3ae3d7..5901ca5 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -48,7 +48,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 991590e..2f32b67 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -56,7 +56,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index bd0590b..e1a8428 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -55,7 +55,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index ea400b2..5f482c3 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -44,7 +44,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index 4ac5e8a..ce3d812 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -56,7 +56,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index 3e7b3e8..9ef146b 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -43,7 +43,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 9d9e560..2cd3440 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -56,7 +56,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index fc3e188..d0789c7 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -55,7 +55,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index 9d40088..d52521c 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -44,7 +44,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index fdb8943..9f0b004 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -56,7 +56,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 466aea2..749baf6 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -43,7 +43,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
index f5614eb..1e55947 100644
--- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
@@ -61,7 +61,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index 8e32bb7..95c29ed 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -58,7 +58,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index 5134f55..e4b00f1 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -57,7 +57,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index 2060085..90a21d8 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -58,7 +58,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index d968324..7aeac60 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -45,7 +45,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index 5072f2a..a255e08 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -43,7 +43,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index 2bf2647..6378c95 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -42,7 +42,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 4c39f66..20f45c0 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -39,7 +40,10 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -56,9 +60,14 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 5fe12da..983acc8 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -8,6 +8,7 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -39,7 +40,10 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -55,9 +59,14 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index dd71811..6996f85 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SECURE_BOOT=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -26,7 +28,11 @@
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_DM=y
+CONFIG_FSL_AHCI=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -42,13 +48,17 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 899f61c..b1327a7 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -40,7 +41,10 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -56,9 +60,14 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 133dc7d..1346d5e 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -2,6 +2,8 @@
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -22,8 +24,13 @@
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_REMOTE=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
@@ -34,10 +41,14 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 7f5a26f..bcbd276 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -3,6 +3,7 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -28,7 +29,10 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
 CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -44,9 +48,14 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 1bb90f3..679c06f 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -54,7 +54,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 1a7070c..d8fc219 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -53,7 +53,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index 0166821..120bfcc 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -42,7 +42,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index ceb0230..667a746 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -54,7 +54,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index a5d83bc..ab071ab 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -34,7 +34,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index e782ba0..f1f0f13 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -41,7 +41,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 91a719f..d4073a9 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -54,7 +54,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index c1bc097..bea3044 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -53,7 +53,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index f6a3f61..31ad09c 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -54,7 +54,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index 83d5e50..5dfb4f2 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -34,7 +34,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index e785b58..306d8b7 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -41,7 +41,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index 3021884..1a637c1 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -48,7 +48,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index b584638..94c35f2 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -47,7 +47,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index bf7b701..fafcdd5 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -36,7 +36,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index 7834ebf..50970fc 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -35,7 +35,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index c5a8bb0..077961d 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -35,7 +35,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index e66e5fd..0771add 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -48,7 +48,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index 715ec90..5fb4c3a 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -47,7 +47,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index 2535ea3..55a7f19 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -36,7 +36,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index d360f3b..3eb0701 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -32,7 +32,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index 89cd173..c9f541c 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -35,7 +35,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index eeab2ec..91c00c8 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -47,7 +47,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index ef26e7c..446c141 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -35,7 +35,9 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index 9d9f105..65ab07e 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -103,8 +103,19 @@
 # CONFIG_LBLAW2_ENABLE is not set
 CONFIG_LBLAW3=y
 # CONFIG_LBLAW3_ENABLE is not set
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0x80000000
+CONFIG_BR0_PORTSIZE_32BIT=y
+CONFIG_OR0_AM_1_GBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -137,15 +148,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0x80000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_32BIT=y
-CONFIG_OR0_AM_1_GBYTES=y
-CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig
index 5ed6b5a..53f66c7 100644
--- a/configs/TWR-P1025_defconfig
+++ b/configs/TWR-P1025_defconfig
@@ -43,6 +43,7 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index 07f1ecc..8ec72f4 100644
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -1,9 +1,9 @@
 CONFIG_RISCV=y
 CONFIG_SYS_TEXT_BASE=0x80000000
-CONFIG_XIP=y
-CONFIG_TARGET_AX25_AE350=y
-CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_XIP=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
@@ -15,7 +15,6 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_SEPARATE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
index 28afd81..8e423a7 100644
--- a/configs/ae350_rv64_xip_defconfig
+++ b/configs/ae350_rv64_xip_defconfig
@@ -1,10 +1,10 @@
 CONFIG_RISCV=y
 CONFIG_SYS_TEXT_BASE=0x80000000
-CONFIG_XIP=y
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_AX25_AE350=y
 CONFIG_ARCH_RV64I=y
+CONFIG_XIP=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
@@ -16,7 +16,6 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_SEPARATE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index 5753b10..3a57946 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -9,9 +9,9 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index 43e71cd..6a00ea2 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -16,11 +16,10 @@
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_DIAG=y
+CONFIG_DEFAULT_DEVICE_TREE="amcore"
 CONFIG_ENV_IS_IN_FLASH=y
 # CONFIG_NET is not set
-CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_SERIAL=y
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 37ad6ac..c1b727e 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -42,4 +42,3 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index 230c4cb..126b50c 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -16,6 +16,7 @@
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
 CONFIG_CMD_JFFS2=y
+CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l"
 # CONFIG_NET is not set
 CONFIG_FPGA_ALTERA=y
 CONFIG_FPGA_CYCLON2=y
diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig
index 437e2d9..f16d0fe 100644
--- a/configs/beelink_gs1_defconfig
+++ b/configs/beelink_gs1_defconfig
@@ -1,11 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I_H6=y
 CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_PSCI_RESET is not set
-CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_TEXT_BASE=0x20060
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index 3787a95..25ea77e 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -2,12 +2,13 @@
 CONFIG_SYS_VENDOR="bitmain"
 CONFIG_SYS_BOARD="antminer_s9"
 CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
-CONFIG_ARCH_ZYNQ=y
 CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_ENV_OFFSET=0x300000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xEFFFFF0
 CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
 CONFIG_DEBUG_UART=y
@@ -48,7 +49,6 @@
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xEFFFFF0
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index 98423f2..7c455d2 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -4,6 +4,8 @@
 CONFIG_SYS_TEXT_BASE=0x3f401000
 CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c
 CONFIG_TARGET_BK4R1=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg"
@@ -34,18 +36,12 @@
 CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c
 CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
 CONFIG_SYS_I2C_MXC=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_MISC=y
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index 192c344..33253b1 100644
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -71,6 +71,25 @@
 CONFIG_LBLAW1_BASE=0xF0000000
 CONFIG_LBLAW1_NAME="WINDOW1"
 CONFIG_LBLAW1_LENGTH_256_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFFC00000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_4_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="WINDOW1"
+CONFIG_BR1_OR1_BASE=0xF0000000
+CONFIG_BR1_PORTSIZE_32BIT=y
+CONFIG_OR1_AM_256_KBYTES=y
+CONFIG_OR1_SETA_EXTERNAL=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -95,24 +114,3 @@
 CONFIG_BAUDRATE=9600
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFFC00000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_4_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="WINDOW1"
-CONFIG_BR1_OR1_BASE=0xF0000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_32BIT=y
-CONFIG_OR1_AM_256_KBYTES=y
-CONFIG_OR1_SETA_EXTERNAL=y
diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig
index f2b0814..2da4fc6 100644
--- a/configs/calimain_defconfig
+++ b/configs/calimain_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TARGET_CALIMAIN=y
 CONFIG_DA850_LOWLEVEL=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_BOOTCOUNT_ADDR=0x01C23000
 CONFIG_BOOTDELAY=0
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -24,7 +25,6 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x01C23000
 CONFIG_DA8XX_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 0278353..4ce6a09 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -1,16 +1,9 @@
 CONFIG_X86=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_X86_RUN_64BIT=y
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_TARGET_CHROMEBOOK_LINK64=y
@@ -57,13 +50,9 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
-CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_INTEL=y
@@ -72,7 +61,6 @@
 CONFIG_SPL_DM_RTC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-CONFIG_SPL_TIMER=y
 CONFIG_TPM_TIS_LPC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 1806d95..b7b886b 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -46,8 +46,8 @@
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
-CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_MV=y
diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig
index fc295af..8865618 100644
--- a/configs/cobra5272_defconfig
+++ b/configs/cobra5272_defconfig
@@ -11,6 +11,7 @@
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
+CONFIG_DEFAULT_DEVICE_TREE="cobra5272"
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MII=y
 CONFIG_BAUDRATE=19200
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index af74f35..72e9128 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -41,12 +41,12 @@
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_UUID=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig
index 66ba04e..26e1c91 100644
--- a/configs/crs305-1g-4s_defconfig
+++ b/configs/crs305-1g-4s_defconfig
@@ -5,14 +5,12 @@
 CONFIG_TARGET_CRS305_1G_4S=y
 CONFIG_BUILD_TARGET="u-boot.kwb"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
-# CONFIG_CMD_USB is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
@@ -33,7 +31,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
-# CONFIG_NAND is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_MACRONIX=y
@@ -45,8 +42,3 @@
 CONFIG_PCI_MVEBU=y
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
-# CONFIG_USB is not set
-# CONFIG_DM_USB is not set
-# CONFIG_USB_EHCI_HCD is not set
-# CONFIG_USB_STORAGE is not set
-# CONFIG_USB_HOST_ETHER is not set
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index deec9f6..d9ec5c7 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -39,7 +40,6 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DWC_AHSATA=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index e2f69eb..3b793f4 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -10,6 +10,8 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_FIT=y
@@ -61,8 +63,6 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_DEVICE=y
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 3632706..daaf83a 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -15,6 +15,7 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282"
 CONFIG_LED_STATUS=y
 CONFIG_LED_STATUS0=y
 CONFIG_LED_STATUS_BIT=8
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 73c6744..7bd0d30 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -14,6 +14,7 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal"
 CONFIG_LED_STATUS=y
 CONFIG_LED_STATUS0=y
 CONFIG_LED_STATUS_BIT=8
diff --git a/configs/edison_defconfig b/configs/edison_defconfig
index b99906a..840c87a 100644
--- a/configs/edison_defconfig
+++ b/configs/edison_defconfig
@@ -32,7 +32,6 @@
 CONFIG_DFU_RAM=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_DM_PCI_COMPAT=y
-CONFIG_RTC_MC146818=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Intel"
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index fc4b094..9601b12 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3368=y
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
@@ -22,7 +23,6 @@
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
 CONFIG_BOOTSTAGE=y
 CONFIG_SPL_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
@@ -38,7 +38,6 @@
 CONFIG_SPL_ATF=y
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
-CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
 CONFIG_TPL_BOOTROM_SUPPORT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 9ee9daa..31c1b17 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -5,7 +5,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_ROCKCHIP_RK322X=y
-CONFIG_TPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
 CONFIG_TARGET_EVB_RK3229=y
 CONFIG_NR_DRAM_BANKS=2
@@ -26,7 +26,6 @@
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SPL_OPTEE=y
-CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig
index e099506..4edade4 100644
--- a/configs/gardena-smart-gateway-mt7688-ram_defconfig
+++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig
@@ -1,17 +1,19 @@
 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
 CONFIG_ARCH_MTMIPS=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_IMAGE_FORMAT_LEGACY=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
+CONFIG_USE_PREBOOT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
@@ -26,6 +28,7 @@
 CONFIG_CMD_MTD=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_WDT=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -42,8 +45,6 @@
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_HAVE_BLOCK_DEVICE=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
 CONFIG_CLK=y
 CONFIG_LED=y
 CONFIG_LED_BLINK=y
diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig
index ad0db2e..707d270 100644
--- a/configs/gardena-smart-gateway-mt7688_defconfig
+++ b/configs/gardena-smart-gateway-mt7688_defconfig
@@ -1,6 +1,8 @@
 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x9c000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
 CONFIG_ARCH_MTMIPS=y
 CONFIG_BOOT_ROM=y
 CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y
@@ -8,13 +10,13 @@
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_IMAGE_FORMAT_LEGACY=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
+CONFIG_USE_PREBOOT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
@@ -29,6 +31,7 @@
 CONFIG_CMD_MTD=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_WDT=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -45,8 +48,6 @@
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_HAVE_BLOCK_DEVICE=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
 CONFIG_CLK=y
 CONFIG_LED=y
 CONFIG_LED_BLINK=y
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index 346b1b2..3a29bb1 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig
@@ -131,7 +131,6 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
-CONFIG_CMD_MII_DRIVER=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_HASH=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 3111451..8be881b 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SYS_VPD_EEPROM_SIZE=1024
 CONFIG_TARGET_GE_BX50V3=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
@@ -39,7 +40,6 @@
 CONFIG_BOOTCOUNT_EXT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=10
 CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
-CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index 50e6bce..6873810 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -4,6 +4,8 @@
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_SYS_TEXT_BASE=0x00008000
 CONFIG_NR_DRAM_BANKS=0
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
@@ -19,8 +21,6 @@
 CONFIG_ENV_IS_IN_NVRAM=y
 CONFIG_SCSI_AHCI=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
 # CONFIG_MMC is not set
 CONFIG_SCSI=y
 CONFIG_CONS_INDEX=0
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index bc4c2a9..abb409d 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -54,13 +54,35 @@
 CONFIG_LBLAW1_BASE=0xE0600000
 CONFIG_LBLAW1_NAME="FPGA0"
 CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
-CONFIG_SICR_GPIO_A_GPIO=y
-CONFIG_SICR_GPIO_B_GPIO=y
 CONFIG_SICR_IEEE1588_A_GPIO=y
 CONFIG_SICR_GTM_GPIO=y
 CONFIG_SICR_ETSEC2_GPIO=y
@@ -70,6 +92,8 @@
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -105,31 +129,3 @@
 CONFIG_CONS_INDEX=2
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index af93aef..6f221a3 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -54,13 +54,35 @@
 CONFIG_LBLAW1_BASE=0xE0600000
 CONFIG_LBLAW1_NAME="FPGA0"
 CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
-CONFIG_SICR_GPIO_A_GPIO=y
-CONFIG_SICR_GPIO_B_GPIO=y
 CONFIG_SICR_IEEE1588_A_GPIO=y
 CONFIG_SICR_GTM_GPIO=y
 CONFIG_SICR_ETSEC2_GPIO=y
@@ -70,6 +92,8 @@
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -103,31 +127,3 @@
 CONFIG_CONS_INDEX=2
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index d9b1642..43454a1 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_BOOTCOUNT_ADDR=0x9
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -71,11 +72,49 @@
 CONFIG_LBLAW3_BASE=0xE3000000
 CONFIG_LBLAW3_NAME="CPLD"
 CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_10=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE1000000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_4=y
+CONFIG_OR1_PGS_LARGE=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_RST_ONE_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="MRAM"
+CONFIG_BR2_OR2_BASE=0xE2000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_7=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CPLD"
+CONFIG_BR3_OR3_BASE=0xE3000000
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_IMAGE_FORMAT_LEGACY=y
@@ -109,7 +148,6 @@
 CONFIG_CMD_UBI=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_I2C=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x9
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -125,50 +163,3 @@
 CONFIG_SPI=y
 CONFIG_MPC8XXX_SPI=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFF800000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_8BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_10=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE1000000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_PGS_LARGE=y
-CONFIG_OR1_RST_ONE_CLOCK=y
-CONFIG_OR1_SCY_4=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="MRAM"
-CONFIG_BR2_OR2_BASE=0xE2000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_SCY_7=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="CPLD"
-CONFIG_BR3_OR3_BASE=0xE3000000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_32_KBYTES=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_SCY_1=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index e92f1be..b659799 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -9,6 +9,8 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024
 CONFIG_DEBUG_UART_BASE=0x021f0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_LIBDISK_SUPPORT=y
@@ -51,8 +53,6 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024
 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
 CONFIG_SYS_I2C_MXC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 7383124..bc84a66 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
-CONFIG_ARCH_IMX8M=y
 CONFIG_SPL_SYS_ICACHE_OFF=y
 CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_IMX8MQ_EVK=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 1a6ce3a..1c67b98 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
-CONFIG_ARCH_IMX8=y
 CONFIG_SPL_SYS_ICACHE_OFF=y
 CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -11,11 +11,11 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
 CONFIG_NR_DRAM_BANKS=3
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg"
 CONFIG_BOOTDELAY=3
 CONFIG_LOG=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index c4a8cf3..d735d34 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
-CONFIG_ARCH_IMX8=y
 CONFIG_SPL_SYS_ICACHE_OFF=y
 CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig
index 4243933..7ee4ce4 100644
--- a/configs/kmcoge4_defconfig
+++ b/configs/kmcoge4_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xfff40000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
 CONFIG_MPC85xx=y
 CONFIG_TARGET_KMP204X=y
 CONFIG_FIT=y
@@ -37,7 +38,6 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
@@ -48,6 +48,8 @@
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 941efcd..faeb0c7 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -104,6 +105,43 @@
 CONFIG_LBLAW3_BASE=0xA0000000
 CONFIG_LBLAW3_NAME="PAXE"
 CONFIG_LBLAW3_LENGTH_512_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_64_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PAXE"
+CONFIG_BR3_OR3_BASE=0xA0000000
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_2=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_ELBC_BR4_OR4=y
+CONFIG_BR4_OR4_NAME="BFTIC3"
+CONFIG_BR4_OR4_BASE=0xB0000000
+CONFIG_OR4_AM_256_MBYTES=y
+CONFIG_OR4_SCY_2=y
+CONFIG_OR4_CSNT_EARLIER=y
+CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR4_TRLX_RELAXED=y
+CONFIG_OR4_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -111,6 +149,9 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_ACR_APARK_MASTER=y
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_2=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -138,7 +179,6 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -147,51 +187,7 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_BCH=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_64_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PAXE"
-CONFIG_BR3_OR3_BASE=0xA0000000
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_2=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_ELBC_BR4_OR4=y
-CONFIG_BR4_OR4_NAME="BFTIC3"
-CONFIG_BR4_OR4_BASE=0xB0000000
-CONFIG_BR4_PORTSIZE_8BIT=y
-CONFIG_OR4_AM_256_MBYTES=y
-CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR4_CSNT_EARLIER=y
-CONFIG_OR4_EAD_EXTRA=y
-CONFIG_OR4_SCY_2=y
-CONFIG_OR4_TRLX_RELAXED=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_LCRR_EADC_2=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 4929a60..518e9f4 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -77,6 +78,34 @@
 CONFIG_LBLAW3_BASE=0xA0000000
 CONFIG_LBLAW3_NAME="PAXE"
 CONFIG_LBLAW3_LENGTH_512_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_64_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PAXE"
+CONFIG_BR3_OR3_BASE=0xA0000000
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_2=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -84,6 +113,9 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_ACR_APARK_MASTER=y
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_2=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -110,7 +142,6 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
@@ -120,40 +151,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_64_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PAXE"
-CONFIG_BR3_OR3_BASE=0xA0000000
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_2=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_LCRR_EADC_2=y
diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig
index 8f02b85..6675c31 100644
--- a/configs/kmlion1_defconfig
+++ b/configs/kmlion1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xfff40000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
 CONFIG_MPC85xx=y
 CONFIG_TARGET_KMP204X=y
 CONFIG_FIT=y
@@ -37,7 +38,6 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
@@ -48,6 +48,8 @@
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index afe424b..8231ce4 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -92,6 +93,40 @@
 CONFIG_LBLAW3_BASE=0xB0000000
 CONFIG_LBLAW3_NAME="APP2"
 CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_4=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -99,6 +134,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_ACR_APARK_MASTER=y
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -125,7 +162,6 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
@@ -135,50 +171,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_4_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_4=y
-CONFIG_OR3_EHTR_NORMAL=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 1a78680..72931a7 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -78,6 +79,34 @@
 CONFIG_LBLAW2_BASE=0xA0000000
 CONFIG_LBLAW2_NAME="APP1"
 CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -85,6 +114,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_ACR_APARK_MASTER=y
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -111,7 +142,6 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
@@ -121,42 +151,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_4_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index d874149..14f7c2f 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -79,6 +80,31 @@
 CONFIG_LBLAW3_BASE=0xB0000000
 CONFIG_LBLAW3_NAME="APP2"
 CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_5=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -86,6 +112,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_ACR_APARK_MASTER=y
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
@@ -115,7 +143,6 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -124,39 +151,8 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_BCH=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_5=y
-CONFIG_OR3_EHTR_NORMAL=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index 32d0980..42fbbbb 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -92,6 +93,40 @@
 CONFIG_LBLAW3_BASE=0xB0000000
 CONFIG_LBLAW3_NAME="APP2"
 CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_4=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -99,6 +134,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_ACR_APARK_MASTER=y
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -125,7 +162,6 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
@@ -135,50 +171,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_4_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_4=y
-CONFIG_OR3_EHTR_NORMAL=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
index 26d9a7c..6f2f732 100644
--- a/configs/kmvect1_defconfig
+++ b/configs/kmvect1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -93,6 +94,40 @@
 CONFIG_LBLAW3_BASE=0xB0000000
 CONFIG_LBLAW3_NAME="APP2"
 CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_PORTSIZE_16BIT=y
+CONFIG_BR2_MACHINE_UPMA=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_3=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -100,6 +135,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_ACR_APARK_MASTER=y
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
@@ -128,7 +165,6 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
@@ -138,45 +174,7 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_BR2_MACHINE_UPMA=y
-CONFIG_BR2_PORTSIZE_16BIT=y
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_SCY_3=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index f6a1874..921af0d 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -7,11 +7,11 @@
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEBUG_UART=y
-CONFIG_NR_DRAM_BANKS=1
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig
index c2502b2..7d7cdf0 100644
--- a/configs/linkit-smart-7688-ram_defconfig
+++ b/configs/linkit-smart-7688-ram_defconfig
@@ -5,7 +5,6 @@
 CONFIG_BOARD_LINKIT_SMART_7688=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_IMAGE_FORMAT_LEGACY=y
diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig
index fba1bfd..b3acbbc 100644
--- a/configs/linkit-smart-7688_defconfig
+++ b/configs/linkit-smart-7688_defconfig
@@ -8,7 +8,6 @@
 CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_IMAGE_FORMAT_LEGACY=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
new file mode 100644
index 0000000..717b810
--- /dev/null
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1028AQDS=y
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_TFABOOT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
new file mode 100644
index 0000000..a8e4ddb
--- /dev/null
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1028ARDB=y
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_TFABOOT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index f700b51..65b2dd1 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -42,10 +42,12 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 99b05a3..51fc761 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -43,10 +43,12 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_SCSI=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 6ba95bc..fcd117d 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -58,10 +58,12 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 631ba8f..65734f5 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -43,10 +43,12 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 1d68863..ff37969 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -37,10 +37,12 @@
 CONFIG_SPI_FLASH=y
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index dd71128..0459cc8 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -58,10 +58,12 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index cc86b1f..a52aa54 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -51,10 +51,12 @@
 CONFIG_SPI_FLASH=y
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index 0bc111e..16ba82d 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -43,6 +43,7 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 2c079e7..19529f5 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -49,6 +49,7 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 4700a27..57791a7 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -35,10 +35,12 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 12aca07..49d498a 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -36,10 +36,12 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 9d96d22..0a8a365 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -54,10 +54,12 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index a94c7b7..6daa82f 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -54,10 +54,12 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 90f3d25..4d9138f 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -52,10 +52,12 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 418215e..9e71d03 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -52,10 +52,12 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 2216699..2f80e71 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -37,6 +37,7 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 9e97431..80cc2b9 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -40,6 +40,7 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig
index 2581e6d..e863c97 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -42,10 +42,12 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 3d6e5c0..30f9d82 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -43,10 +43,12 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
index a7c5392..a2381b7 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -44,10 +44,12 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_SCSI=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index 18dcc9f..ddb83fc 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -51,10 +51,12 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index 1d92bec..7c0b0d3 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -10,7 +10,7 @@
 CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:2m(uboot),14m(free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_BOOTZ=y
@@ -25,7 +25,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:2m(uboot),14m(free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)"
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -35,13 +35,16 @@
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index 28ceabc..10fd8b3 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -60,10 +60,12 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index 2b11a38..0f256d7 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -17,7 +17,7 @@
 CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:2m(uboot),14m(free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_TEXT_BASE=0x10000000
@@ -40,7 +40,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:2m(uboot),14m(free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
@@ -51,13 +51,16 @@
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 39589fd..0dbc770 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -44,6 +44,7 @@
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 763ddee..17f3ba1 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -48,8 +48,10 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 9b6e56d..2c7cc09 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -17,7 +17,7 @@
 CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_TEXT_BASE=0x10000000
@@ -37,7 +37,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
@@ -48,13 +48,16 @@
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index 3522756..dd78445 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -12,7 +12,7 @@
 CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
@@ -23,7 +23,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_DM=y
@@ -31,14 +31,17 @@
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index a4ba4ca..ef5e73d 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -11,7 +11,7 @@
 CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
@@ -22,7 +22,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -32,14 +32,17 @@
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index f78786a..a4038b8 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -18,7 +18,7 @@
 CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_BOARD_INIT=y
@@ -39,7 +39,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
@@ -51,13 +51,16 @@
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 5afe644..2d7ace6 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -17,7 +17,7 @@
 CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
@@ -37,7 +37,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
@@ -45,13 +45,16 @@
 CONFIG_SPL_DM=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index bf5e1a0..b70a82b 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -17,7 +17,7 @@
 CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_BOARD_INIT=y
@@ -36,7 +36,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
@@ -47,13 +47,16 @@
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 29fddef..1365725 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -13,7 +13,7 @@
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
@@ -24,7 +24,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_DM=y
@@ -32,10 +32,12 @@
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 8d57172..816c628 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -12,7 +12,7 @@
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
@@ -23,7 +23,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_ENV_IS_IN_MMC=y
@@ -34,10 +34,12 @@
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index bd22aa0..bb90ed7 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
@@ -35,6 +35,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index 8fb8bab..8aeca65 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -35,6 +35,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index 186e309..5b5cbfa 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -46,6 +46,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index fbbb212..ff820a5 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -44,6 +44,7 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index 60e8a0b..265303c 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
@@ -36,6 +36,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index 7844c84..6dd9df2 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -36,6 +36,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 3a0c555..3d53129 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -47,6 +47,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 15d6902..51b74e7 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -47,6 +47,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index bf309b8..3c4437d 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -38,6 +38,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index 9911dc1..8cea8c7 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -39,6 +39,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 48dbf62..3a36941 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -49,6 +49,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 0a84512..53abf71 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -39,6 +39,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index 651e45b..9d1715f 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -47,6 +47,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 2941766..c92121e 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -41,6 +41,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index 240da82..d4b5d87 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -32,6 +32,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index d729668..a38ec3d 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -36,6 +36,7 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index 1cffc2e..d3312c6 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -44,6 +44,7 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index 655a23a..1aa8dd9 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -47,6 +47,7 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index bc9985f..a6a253f 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -19,6 +19,7 @@
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
@@ -43,6 +44,10 @@
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_SCSI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index 15c66a4..d68b40d 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -19,6 +19,7 @@
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
@@ -42,6 +43,11 @@
 CONFIG_PHY_CORTINA=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_SCSI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index 8240845..5cb29fd 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -20,6 +20,7 @@
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
@@ -41,6 +42,10 @@
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
 CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_SCSI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 1dc4ada..94f58a8 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -20,6 +20,7 @@
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
@@ -42,6 +43,11 @@
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_SCSI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index e5f8c9e..0e5fa01 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -8,6 +8,8 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
 # CONFIG_CMD_BMODE is not set
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
@@ -49,8 +51,6 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
 CONFIG_FSL_ESDHC=y
 CONFIG_NAND=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 6afa6704..e875626 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -41,7 +41,6 @@
 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
 CONFIG_NETCONSOLE=y
 CONFIG_SPL_DM=y
-CONFIG_DM_GPIO=y
 CONFIG_XILINX_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index 0789ecd..cb0da47 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -56,6 +56,28 @@
 CONFIG_LBLAW2_BASE=0xFBFF8000
 CONFIG_LBLAW2_NAME="CPLD"
 CONFIG_LBLAW2_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFC000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_64_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_4=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="SJA1000"
+CONFIG_BR1_OR1_BASE=0xFBFF0000
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_EHTR_1_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="CPLD"
+CONFIG_BR2_OR2_BASE=0xFBFF8000
+CONFIG_OR2_SCY_4=y
+CONFIG_OR2_EHTR_1_CYCLE=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
@@ -71,6 +93,8 @@
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=5
@@ -93,34 +117,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFC000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_64_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_SCY_4=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="SJA1000"
-CONFIG_BR1_OR1_BASE=0xFBFF0000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_SCY_5=y
-CONFIG_OR1_EHTR_1_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="CPLD"
-CONFIG_BR2_OR2_BASE=0xFBFF8000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_32_KBYTES=y
-CONFIG_OR2_SCY_4=y
-CONFIG_OR2_EHTR_1_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig
index 753a11a..687d6e8 100644
--- a/configs/mscc_serval_defconfig
+++ b/configs/mscc_serval_defconfig
@@ -25,6 +25,10 @@
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)"
@@ -50,6 +54,7 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
+CONFIG_MSCC_SERVAL_SWITCH=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_DM_SERIAL=y
@@ -57,8 +62,3 @@
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_LZMA=y
-CONFIG_CMD_DHCP=y
-# CONFIG_NET_TFTP_VARS is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_MSCC_SERVAL_SWITCH=y
diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
index b809066..bf48966 100644
--- a/configs/mx53cx9020_defconfig
+++ b/configs/mx53cx9020_defconfig
@@ -24,9 +24,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FPGA_ALTERA=y
 CONFIG_FPGA_CYCLON2=y
-CONFIG_DM=y
-CONFIG_DM_MMC=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index 6c3818d..19ebab7 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SYS_VPD_EEPROM_I2C_BUS=2
 CONFIG_SYS_VPD_EEPROM_SIZE=1024
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg"
@@ -37,7 +38,6 @@
 CONFIG_BOOTCOUNT_EXT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=10
 CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
-CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MII=y
@@ -46,8 +46,7 @@
 CONFIG_RTC_S35392A=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_MX5=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index d9f2137..37df3f3 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -6,11 +6,11 @@
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEBUG_UART=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index c283278..68fd9ff 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -6,11 +6,11 @@
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEBUG_UART=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 54cba0e..46bdb03 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEGRA=y
 CONFIG_SYS_TEXT_BASE=0x81000100
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000
 CONFIG_DEBUG_UART_BASE=0x70006000
 CONFIG_DEBUG_UART_CLOCK=408000000
 CONFIG_TEGRA124=y
@@ -13,7 +14,6 @@
 CONFIG_BOOTSTAGE=y
 CONFIG_SPL_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000
 CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_TEXT_BASE=0x80108000
diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
index 3f02c89..0f5edef 100644
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig
@@ -6,11 +6,11 @@
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEBUG_UART=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 4002dba..171341b 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -31,10 +31,6 @@
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
 CONFIG_SYS_I2C_MXC=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index 17043d5..9545d6b 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -16,8 +16,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-hobbit"
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_TEXT_BASE=0x00911000
 CONFIG_SPL_I2C_SUPPORT=y
@@ -28,14 +26,10 @@
 CONFIG_CMD_BOOTMENU=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX7=y
-CONFIG_DM_GPIO=y
 CONFIG_CMD_SPL=y
 CONFIG_CMD_SPL_WRITE_SIZE=0x20000
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
-CONFIG_DM_MMC=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -46,6 +40,8 @@
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-hobbit"
 CONFIG_DFU_MMC=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
@@ -53,10 +49,14 @@
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index 81eda9d..92ab9c5 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -16,8 +16,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="ask"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_TEXT_BASE=0x00911000
 CONFIG_SPL_I2C_SUPPORT=y
@@ -28,10 +26,6 @@
 CONFIG_CMD_BOOTMENU=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX7=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
 CONFIG_CMD_SPL=y
 CONFIG_CMD_SPL_WRITE_SIZE=0x20000
 CONFIG_CMD_DFU=y
@@ -46,6 +40,8 @@
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
 CONFIG_DFU_MMC=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
@@ -53,10 +49,14 @@
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index 0aa1487..042affe 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -16,8 +16,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_TEXT_BASE=0x00911000
 CONFIG_SPL_I2C_SUPPORT=y
@@ -28,14 +26,10 @@
 CONFIG_CMD_BOOTMENU=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX7=y
-CONFIG_DM_GPIO=y
 CONFIG_CMD_SPL=y
 CONFIG_CMD_SPL_WRITE_SIZE=0x20000
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
-CONFIG_DM_MMC=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -46,6 +40,8 @@
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
 CONFIG_DFU_MMC=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
@@ -53,10 +49,14 @@
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index d8792d6..b1cd5b4 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -1,15 +1,10 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0x1110000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_MAX_CPUS=2
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_X86_RUN_64BIT=y
 CONFIG_TARGET_QEMU_X86_64=y
 CONFIG_DEBUG_UART=y
@@ -55,18 +50,13 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
-CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
 CONFIG_CPU=y
 CONFIG_NVME=y
 CONFIG_SPL_DM_RTC=y
 CONFIG_SPI=y
-CONFIG_SPL_TIMER=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 61175e8..1bc3bd3 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SYS_TEXT_BASE=0
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_SANDBOX64=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
@@ -9,7 +10,6 @@
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index ff01315..4877f10 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SYS_TEXT_BASE=0
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
@@ -10,7 +11,6 @@
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index b4b5190..40593ee 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SYS_TEXT_BASE=0
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
@@ -8,7 +9,6 @@
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index 9a27198..24ff4b4 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SYS_TEXT_BASE=0
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
@@ -8,7 +9,6 @@
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_CONSOLE_RECORD=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index e2826a6..bebd78d 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_SANDBOX_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
@@ -15,7 +16,6 @@
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index a363070..915ba36 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -69,9 +69,24 @@
 CONFIG_LBLAW0_BASE=0xFF800000
 CONFIG_LBLAW0_NAME="FLASH"
 CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_PCI_64BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -92,19 +107,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFF800000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index 215f31d..c224fea 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -69,9 +69,24 @@
 CONFIG_LBLAW0_BASE=0xFF800000
 CONFIG_LBLAW0_NAME="FLASH"
 CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_PCI_64BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -92,19 +107,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFF800000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index d492b86..6231057 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -49,9 +49,24 @@
 CONFIG_LBLAW0_BASE=0xFF800000
 CONFIG_LBLAW0_NAME="FLASH"
 CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -70,19 +85,3 @@
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFF800000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index ffe50b1..656188f 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SPL_SYS_THUMB_BUILD=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_AT91=y
 CONFIG_SYS_TEXT_BASE=0x23000000
 CONFIG_TARGET_SMARTWEB=y
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 09a018c..69e492a 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -1,8 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_arria10"
+CONFIG_SPL_FS_FAT=y
 CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200"
 # CONFIG_USE_BOOTCOMMAND is not set
@@ -12,8 +16,8 @@
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
@@ -23,31 +27,21 @@
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_DM_MMC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_FS_LOADER=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_SPL_FIT=y
-CONFIG_FIT=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_FS_LOADER=y
 CONFIG_DM_MMC=y
-CONFIG_MTD_DEVICE=y
 CONFIG_MMC_DW=y
+CONFIG_MTD_DEVICE=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index c3a597a..f369301 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_TARGET_SOCFPGA_IS1=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_USE_BOOTARGS=y
@@ -33,7 +34,6 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_I2C=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index da7995b..741525f 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_TARGET_SOCFPGA_SR1500=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 # CONFIG_USE_BOOTCOMMAND is not set
@@ -36,7 +37,6 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_I2C=y
diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index 630b01c..b039ebb 100644
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -19,15 +19,18 @@
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi-flash.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs)"
+CONFIG_DEFAULT_DEVICE_TREE="stmark2"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_CS=y
 CONFIG_ENV_SPI_CS=1
 # CONFIG_NET is not set
 CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
 CONFIG_REGEX=y
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 9f05b56..1bdbe9e 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -53,13 +53,30 @@
 CONFIG_LBLAW1_BASE=0xE0600000
 CONFIG_LBLAW1_NAME="FPGA0"
 CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
-CONFIG_SICR_ETSEC1_A_TSEC2=y
-CONFIG_SICR_GPIO_A_GPIO=y
-CONFIG_SICR_GPIO_B_GPIO=y
 CONFIG_SICR_IEEE1588_A_GPIO=y
 CONFIG_SICR_GTM_GPIO=y
 CONFIG_SICR_ETSEC2_GPIO=y
@@ -69,6 +86,8 @@
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -107,28 +126,3 @@
 CONFIG_CONS_INDEX=2
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_SCY_5=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_EHTR_NORMAL=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
index a1f9662..424c915 100644
--- a/configs/strider_con_dp_defconfig
+++ b/configs/strider_con_dp_defconfig
@@ -53,13 +53,30 @@
 CONFIG_LBLAW1_BASE=0xE0600000
 CONFIG_LBLAW1_NAME="FPGA0"
 CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
-CONFIG_SICR_ETSEC1_A_TSEC2=y
-CONFIG_SICR_GPIO_A_GPIO=y
-CONFIG_SICR_GPIO_B_GPIO=y
 CONFIG_SICR_IEEE1588_A_GPIO=y
 CONFIG_SICR_GTM_GPIO=y
 CONFIG_SICR_ETSEC2_GPIO=y
@@ -69,6 +86,8 @@
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -107,28 +126,3 @@
 CONFIG_CONS_INDEX=2
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_SCY_5=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_EHTR_NORMAL=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index 2477ee5..1149b13 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -53,13 +53,30 @@
 CONFIG_LBLAW1_BASE=0xE0600000
 CONFIG_LBLAW1_NAME="FPGA0"
 CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
-CONFIG_SICR_ETSEC1_A_TSEC2=y
-CONFIG_SICR_GPIO_A_GPIO=y
-CONFIG_SICR_GPIO_B_GPIO=y
 CONFIG_SICR_IEEE1588_A_GPIO=y
 CONFIG_SICR_GTM_GPIO=y
 CONFIG_SICR_ETSEC2_GPIO=y
@@ -69,6 +86,8 @@
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -107,28 +126,3 @@
 CONFIG_CONS_INDEX=2
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_SCY_5=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_EHTR_NORMAL=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
index da16d5d..ec68d3d 100644
--- a/configs/strider_cpu_dp_defconfig
+++ b/configs/strider_cpu_dp_defconfig
@@ -53,13 +53,30 @@
 CONFIG_LBLAW1_BASE=0xE0600000
 CONFIG_LBLAW1_NAME="FPGA0"
 CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_DPM=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
-CONFIG_SICR_ETSEC1_A_TSEC2=y
-CONFIG_SICR_GPIO_A_GPIO=y
-CONFIG_SICR_GPIO_B_GPIO=y
 CONFIG_SICR_IEEE1588_A_GPIO=y
 CONFIG_SICR_GTM_GPIO=y
 CONFIG_SICR_ETSEC2_GPIO=y
@@ -69,6 +86,8 @@
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -107,28 +126,3 @@
 CONFIG_CONS_INDEX=2
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_SCY_5=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_EHTR_NORMAL=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
index c970cde..bb21bde 100644
--- a/configs/suvd3_defconfig
+++ b/configs/suvd3_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -92,6 +93,40 @@
 CONFIG_LBLAW3_BASE=0xB0000000
 CONFIG_LBLAW3_NAME="APP2"
 CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_PORTSIZE_16BIT=y
+CONFIG_BR2_MACHINE_UPMA=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_3=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -99,6 +134,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_ACR_APARK_MASTER=y
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
@@ -126,7 +163,6 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
@@ -136,45 +172,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_BR2_MACHINE_UPMA=y
-CONFIG_BR2_PORTSIZE_16BIT=y
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_SCY_3=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 5616b3e..f5c3fe1 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_SYS_VENDOR="opalkelly"
 CONFIG_SYS_CONFIG_NAME="syzygy_hub"
-CONFIG_ARCH_ZYNQ=y
 CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 8af7dd7..ee21811 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_THUMB_BUILD=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_AT91=y
 CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
 CONFIG_SYS_TEXT_BASE=0x21000000
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index bb8d37a..188c791 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
-CONFIG_ARCH_ZYNQ=y
 CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 87af8c8..ae65f9c 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
-CONFIG_ARCH_ZYNQ=y
 CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 874ca8a..a5cee67 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
-CONFIG_ARCH_ZYNQ=y
 CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index 1a95973..57f2221 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TQMA6S=y
 CONFIG_WRU4=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -37,7 +38,6 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
 CONFIG_LED_STATUS=y
 CONFIG_LED_STATUS0=y
 CONFIG_LED_STATUS_BIT=0
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 550f524..22ba192 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -78,6 +79,34 @@
 CONFIG_LBLAW2_BASE=0xA0000000
 CONFIG_LBLAW2_NAME="APP1"
 CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -85,6 +114,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_ACR_APARK_MASTER=y
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -111,7 +142,6 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
@@ -121,42 +151,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_4_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index d5ec8e5..94214a2 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -92,6 +93,42 @@
 CONFIG_LBLAW3_BASE=0xB0000000
 CONFIG_LBLAW3_NAME="APP2"
 CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_2=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
@@ -99,6 +136,8 @@
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_ACR_APARK_MASTER=y
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -125,7 +164,6 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
@@ -135,53 +173,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_BR2_MACHINE_GPCM=y
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_4_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_MACHINE_GPCM=y
-CONFIG_BR3_PORTSIZE_8BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_SCY_2=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_4_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index a1cdd05..f55c386 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -6,10 +6,9 @@
 CONFIG_TARGET_DART_6UL=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-# CONFIG_CMD_DEKBLOB is not set
-CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
 CONFIG_BOOTDELAY=3
@@ -26,7 +25,6 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_NET=y
 # CONFIG_ISO_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul"
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 0a9521b..5377709 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -74,11 +74,54 @@
 CONFIG_LBLAW1_BASE=0x61000000
 CONFIG_LBLAW1_NAME="NAND"
 CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0x61000000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_BCTLD_NOT_ASSERTED=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_RST_ONE_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="NVRAM"
+CONFIG_BR2_OR2_BASE=0x60000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_3=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="SRAM"
+CONFIG_BR3_OR3_BASE=0x62000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_32_MBYTES=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_3=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
@@ -100,50 +143,3 @@
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0x61000000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_BR1_PORTSIZE_8BIT=y
-CONFIG_OR1_AM_32_KBYTES=y
-CONFIG_OR1_BCTLD_NOT_ASSERTED=y
-CONFIG_OR1_RST_ONE_CLOCK=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="NVRAM"
-CONFIG_BR2_OR2_BASE=0x60000000
-CONFIG_BR2_PORTSIZE_8BIT=y
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_OR2_SCY_3=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="SRAM"
-CONFIG_BR3_OR3_BASE=0x62000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_32_MBYTES=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_LCRR_EADC_3=y
-CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index 24bbba1..77c7904 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -71,9 +71,29 @@
 CONFIG_LBLAW1_BASE=0xF0000000
 CONFIG_LBLAW1_NAME="WINDOW1"
 CONFIG_LBLAW1_LENGTH_256_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF8000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_128_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="WINDOW1"
+CONFIG_BR1_OR1_BASE=0xF0000000
+CONFIG_BR1_PORTSIZE_32BIT=y
+CONFIG_OR1_AM_256_KBYTES=y
+CONFIG_OR1_SETA_EXTERNAL=y
 CONFIG_HID0_FINAL_EMCP=y
 CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_PCI_64BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -97,25 +117,3 @@
 CONFIG_BAUDRATE=9600
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF8000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_128_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="WINDOW1"
-CONFIG_BR1_OR1_BASE=0xF0000000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_32BIT=y
-CONFIG_OR1_AM_256_KBYTES=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index 27c25d3..03574d0 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8
 CONFIG_IDENT_STRING="-SPEAr"
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -42,7 +43,6 @@
 CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_SPARTAN3=y
 CONFIG_SYS_I2C_DW=y
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 76b85d4..62ed8f73 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -3,7 +3,6 @@
 CONFIG_SYS_ICACHE_OFF=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x100000
 CONFIG_ENV_SIZE=0x190
 CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index fad7b5d..2e9a54e 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -3,7 +3,6 @@
 CONFIG_SYS_ICACHE_OFF=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0xFFFC0000
 CONFIG_ENV_SIZE=0x190
 CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 8adeffc..2aaa814 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_SIZE=0x190
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
+CONFIG_SYS_MALLOC_LEN=0x1000
 CONFIG_DEBUG_UART_BASE=0x0
 CONFIG_DEBUG_UART_CLOCK=0
 # CONFIG_ZYNQ_DDRC_INIT is not set
-CONFIG_SYS_MALLOC_LEN=0x1000
 # CONFIG_CMD_ZYNQ is not set
 CONFIG_DEBUG_UART=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt
index ffcf8cd..02e1460 100644
--- a/doc/device-tree-bindings/clock/st,stm32mp1.txt
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -1,185 +1,186 @@
 STMicroelectronics STM32MP1 clock tree initialization
 =====================================================
 
-The STM32MP clock tree initialization is based on device tree information
-for RCC IP and on fixed clocks.
+The STM32MP1 clock tree initialization is based on device tree information
+for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes.
 
--------------------------------
-RCC CLOCK = st,stm32mp1-rcc-clk
--------------------------------
+RCC IP = st,stm32mp1-rcc
+========================
 
 The RCC IP is both a reset and a clock controller but this documentation only
 describes the fields added for clock tree initialization which are not present
-in Linux binding.
+in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
+file.
 
-Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
-with Linux.
+The added properties for clock tree initialization are:
 
 Required properties:
+- st,clksrc : The clock sources configuration array in a platform specific
+              order.
 
-- compatible: Should be "st,stm32mp1-rcc-clk"
+  For the STM32MP15x family there are 9 clock sources selector which are
+  configured in the following order:
+	MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
 
-- st,clksrc : The clock source in this order
+  Clock source configuration values are defined by macros CLK_<NAME>_<SOURCE>
+  from dt-bindings/clock/stm32mp1-clksrc.h.
 
-	for STM32MP15x: 9 clock sources are requested
-		MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
+  Example:
+	st,clksrc = <
+		CLK_MPU_PLL1P
+		CLK_AXI_PLL2P
+		CLK_MCU_PLL3P
+		CLK_PLL12_HSE
+		CLK_PLL3_HSE
+		CLK_PLL4_HSE
+		CLK_RTC_LSE
+		CLK_MCO1_DISABLED
+		CLK_MCO2_DISABLED
+	>;
 
-	with value equals to RCC clock specifier as defined in
-	dt-bindings/clock/stm32mp1-clksrc.h: CLK_<NAME>_<SOURCE>
+- st,clkdiv : The clock main dividers value specified in an array
+              in a platform specific order.
 
-- st,clkdiv : The div parameters in this order
-	for STM32MP15x: 11 dividers value are requested
+  When used, it shall describe the whole clock dividers tree.
+
+  For the STM32MP15x family there are 11 dividers values expected.
+  They shall be configured in the following order:
 		MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
 
-	with DIV coding defined in RCC associated register RCC_xxxDIVR
-
-	most the case, it is:
+  The each divider value uses the DIV coding defined in RCC associated
+  register RCC_xxxDIVR. In most the case, it is:
 		0x0: not divided
 		0x1: division by 2
 		0x2: division by 4
 		0x3: division by 8
 		...
 
-	but for RTC MCO1 MCO2, the coding is different:
+  Note that for RTC MCO1 MCO2, the coding is different:
 		0x0: not divided
 		0x1: division by 2
 		0x2: division by 3
 		0x3: division by 4
 		...
 
-Optional Properties:
-- st,pll
-    PLL children node for PLL1 to PLL4 : (see ref manual for details)
-    with associated index 0 to 3 (st,pll@0 to st,pll@4)
-    PLLx is off when the associated node is absent
-
-    - Sub-nodes:
-
-	- cfg:	The parameters for PLL configuration in this order:
-		DIVM DIVN DIVP DIVQ DIVR Output
-
-		with DIV value as defined in RCC spec:
-			0x0: bypass (division by 1)
-			0x1: division by 2
-			0x2: division by 3
-			0x3: division by 4
-			...
-
-		and Output = bitfield for each output value = 1:ON/0:OFF
-			BIT(0) => output P : DIVPEN
-			BIT(1) => output Q : DIVQEN
-			BIT(2) => output R : DIVREN
-		  NB : macro PQR(p,q,r) can be used to build this value
-		       with p,p,r = 0 or 1
-
-	- frac : Fractional part of the multiplication factor
-		(optional, PLL is in integer mode when absent)
-
-	- csg : Clock Spreading Generator (optional)
-	        with parameters in this order:
-		MOD_PER INC_STEP SSCG_MODE
-
-		* MOD_PER: Modulation Period Adjustment
-		* INC_STEP: Modulation Depth Adjustment
-		* SSCG_MODE: Spread spectrum clock generator mode
-		  you can use associated defines from stm32mp1-clksrc.h
-		  * SSCG_MODE_CENTER_SPREAD = 0
-		  * SSCG_MODE_DOWN_SPREAD = 1
-
-
-- st,pkcs : used to configure the peripherals kernel clock selection
-  containing a list of peripheral kernel clock source identifier as defined
-  in the file dt-bindings/clock/stm32mp1-clksrc.h
-
   Example:
+	st,clkdiv = <
+		1 /*MPU*/
+		0 /*AXI*/
+		0 /*MCU*/
+		1 /*APB1*/
+		1 /*APB2*/
+		1 /*APB3*/
+		1 /*APB4*/
+		2 /*APB5*/
+		23 /*RTC*/
+		0 /*MCO1*/
+		0 /*MCO2*/
+	>;
 
-	rcc: rcc@50000000 {
-		compatible = "syscon", "simple-mfd";
+Optional Properties:
+- st,pll : A specific PLL configuration, including frequency.
 
-		reg = <0x50000000 0x1000>;
+  PLL children nodes for PLL1 to PLL4 (see ref manual for details)
+  are listed with associated index 0 to 3 (st,pll@0 to st,pll@3).
+  PLLx is off when the associated node is absent.
 
-		rcc_clk: rcc-clk@50000000 {
-			#clock-cells = <1>;
-			compatible = "st,stm32mp1-rcc-clk";
+  Here are the available properties for each PLL node:
 
-			st,clksrc = <	CLK_MPU_PLL1P
-					CLK_AXI_PLL2P
-					CLK_MCU_HSI
-					CLK_PLL12_HSE
-					CLK_PLL3_HSE
-					CLK_PLL4_HSE
-					CLK_RTC_HSE
-					CLK_MCO1_DISABLED
-					CLK_MCO2_DISABLED
-			>;
+    - cfg: The parameters for PLL configuration in the following order:
+           DIVM DIVN DIVP DIVQ DIVR Output.
 
-			st,clkdiv = <
-				1 /*MPU*/
-				0 /*AXI*/
-				0 /*MCU*/
-				1 /*APB1*/
-				1 /*APB2*/
-				1 /*APB3*/
-				1 /*APB4*/
-				5 /*APB5*/
-				23 /*RTC*/
-				0 /*MCO1*/
-				0 /*MCO2*/
-			>;
+	DIVx values are defined as in RCC spec:
+		0x0: bypass (division by 1)
+		0x1: division by 2
+		0x2: division by 3
+		0x3: division by 4
+		...
 
-			st,pll@0 {
-				cfg = < 1 53 0 0 0 1 >;
-				frac = < 0x810 >;
-			};
-			st,pll@1 {
-				cfg = < 1 43 1 0 0 PQR(0,1,1) >;
-				csg = < 10 20 1 >;
-			};
-			st,pll@2 {
-				cfg = < 2 85 3 13 3 0 >;
-				csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
-			};
-			st,pll@3 {
-				cfg = < 2 78 4 7 9 3 >;
-			};
-			st,pkcs = <
-					CLK_STGEN_HSE
-					CLK_CKPER_HSI
-					CLK_USBPHY_PLL2P
-					CLK_DSI_PLL2Q
-				  >;
+	Output contains a bitfield for each output value (1:ON/0:OFF)
+		BIT(0) => output P : DIVPEN
+		BIT(1) => output Q : DIVQEN
+		BIT(2) => output R : DIVREN
+	  NB: macro PQR(p,q,r) can be used to build this value
+	      with p,q,r = 0 or 1.
+
+    - frac : Fractional part of the multiplication factor
+             (optional, PLL is in integer mode when absent).
+
+    - csg : Clock Spreading Generator (optional) with parameters in the
+	    following order: MOD_PER INC_STEP SSCG_MODE.
+
+	MOD_PER: Modulation Period Adjustment
+	INC_STEP: Modulation Depth Adjustment
+	SSCG_MODE: Spread spectrum clock generator mode, with associated
+		   defined from stm32mp1-clksrc.h:
+			- SSCG_MODE_CENTER_SPREAD = 0
+			- SSCG_MODE_DOWN_SPREAD = 1
+
+    Example:
+	st,pll@0 {
+		cfg = < 1 53 0 0 0 1 >;
+		frac = < 0x810 >;
+	};
+	st,pll@1 {
+		cfg = < 1 43 1 0 0 PQR(0,1,1) >;
+		csg = < 10 20 1 >;
+	};
+	st,pll@2 {
+		cfg = < 2 85 3 13 3 0 >;
+		csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
 		};
+	st,pll@3 {
+		cfg = < 2 78 4 7 9 3 >;
 	};
 
---------------------------
+- st,pkcs : used to configure the peripherals kernel clock selection.
+
+  The property is a list of peripheral kernel clock source identifiers defined
+  by macros CLK_<KERNEL-CLOCK>_<PARENT-CLOCK> as defined by header file
+  dt-bindings/clock/stm32mp1-clksrc.h.
+
+  st,pkcs may not list all the kernel clocks and has no ordering requirements.
+
+  Example:
+	st,pkcs = <
+		CLK_STGEN_HSE
+		CLK_CKPER_HSI
+		CLK_USBPHY_PLL2P
+		CLK_DSI_PLL2Q
+		CLK_I2C46_HSI
+		CLK_UART1_HSI
+		CLK_UART24_HSI
+	>;
+
 other clocks = fixed-clock
---------------------------
+==========================
+
 The clock tree is also based on 5 fixed-clock in clocks node
 used to define the state of associated ST32MP1 oscillators:
-- clk-lsi
-- clk-lse
-- clk-hsi
-- clk-hse
-- clk-csi
+  - clk-lsi
+  - clk-lse
+  - clk-hsi
+  - clk-hse
+  - clk-csi
 
 At boot the clock tree initialization will
-- enable the oscillator present in device tree
-- disable HSI oscillator if the node is absent (always activated by bootrom)
+  - enable oscillators present in device tree
+  - disable HSI oscillator if the node is absent (always activated by bootrom)
 
 Optional properties :
 
 a) for external oscillator: "clk-lse", "clk-hse"
 
-	4 optional fields are managed
-	- "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP)
-	- "st,digbypass" Configure the bypass mode as full-swing digital signal
-	  (DIGBYP)
-	- "st,css" Activate the clock security system (HSECSSON, LSECSSON)
-	- "st,drive" (only for LSE) value of the drive for the oscillator
-	   (see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h)
+  4 optional fields are managed
+  - "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP)
+  - "st,digbypass" configures the bypass mode as full-swing digital
+    signal (DIGBYP)
+  - "st,css" activates the clock security system (HSECSSON, LSECSSON)
+  - "st,drive" (only for LSE) contains the value of the drive for the
+     oscillator (see LSEDRV_ defined in the file
+     dt-bindings/clock/stm32mp1-clksrc.h)
 
-	Example board file:
-
+  Example board file:
 	/ {
 		clocks {
 			clk_hse: clk-hse {
@@ -200,13 +201,12 @@
 
 b) for internal oscillator: "clk-hsi"
 
-	internally HSI clock is fixed to 64MHz for STM32MP157 soc
-	in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc)
-	So this clock frequency is used to compute the expected HSI_DIV
-	for the clock tree initialisation
+  Internally HSI clock is fixed to 64MHz for STM32MP157 SoC.
+  In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC
+  doc). So this clock frequency is used to compute the expected HSI_DIV
+  for the clock tree initialization.
 
-	ex: for HSIDIV = /1
-
+  Example with HSIDIV = /1:
 	/ {
 		clocks {
 			clk_hsi: clk-hsi {
@@ -216,8 +216,7 @@
 			};
 	};
 
-	ex: for HSIDIV = /2
-
+  Example with HSIDIV = /2
 	/ {
 		clocks {
 			clk_hsi: clk-hsi {
@@ -226,3 +225,151 @@
 				clock-frequency = <32000000>;
 			};
 	};
+
+Example of clock tree initialization
+====================================
+
+/ {
+	clocks {
+		u-boot,dm-pre-reloc;
+		clk_hse: clk-hse {
+			u-boot,dm-pre-reloc;
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			st,digbypass;
+		};
+
+		clk_hsi: clk-hsi {
+			u-boot,dm-pre-reloc;
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <64000000>;
+		};
+
+		clk_lse: clk-lse {
+			u-boot,dm-pre-reloc;
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+		};
+
+		clk_lsi: clk-lsi {
+			u-boot,dm-pre-reloc;
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+		};
+
+		clk_csi: clk-csi {
+			u-boot,dm-pre-reloc;
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <4000000>;
+		};
+	};
+
+	soc {
+
+		rcc: rcc@50000000 {
+			u-boot,dm-pre-reloc;
+			compatible = "st,stm32mp1-rcc", "syscon";
+			reg = <0x50000000 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+			st,clksrc = <
+				CLK_MPU_PLL1P
+				CLK_AXI_PLL2P
+				CLK_MCU_PLL3P
+				CLK_PLL12_HSE
+				CLK_PLL3_HSE
+				CLK_PLL4_HSE
+				CLK_RTC_LSE
+				CLK_MCO1_DISABLED
+				CLK_MCO2_DISABLED
+			>;
+
+			st,clkdiv = <
+				1 /*MPU*/
+				0 /*AXI*/
+				0 /*MCU*/
+				1 /*APB1*/
+				1 /*APB2*/
+				1 /*APB3*/
+				1 /*APB4*/
+				2 /*APB5*/
+				23 /*RTC*/
+				0 /*MCO1*/
+				0 /*MCO2*/
+			>;
+
+			st,pkcs = <
+				CLK_CKPER_HSE
+				CLK_FMC_ACLK
+				CLK_QSPI_ACLK
+				CLK_ETH_DISABLED
+				CLK_SDMMC12_PLL4P
+				CLK_DSI_DSIPLL
+				CLK_STGEN_HSE
+				CLK_USBPHY_HSE
+				CLK_SPI2S1_PLL3Q
+				CLK_SPI2S23_PLL3Q
+				CLK_SPI45_HSI
+				CLK_SPI6_HSI
+				CLK_I2C46_HSI
+				CLK_SDMMC3_PLL4P
+				CLK_USBO_USBPHY
+				CLK_ADC_CKPER
+				CLK_CEC_LSE
+				CLK_I2C12_HSI
+				CLK_I2C35_HSI
+				CLK_UART1_HSI
+				CLK_UART24_HSI
+				CLK_UART35_HSI
+				CLK_UART6_HSI
+				CLK_UART78_HSI
+				CLK_SPDIF_PLL4P
+				CLK_FDCAN_PLL4Q
+				CLK_SAI1_PLL3Q
+				CLK_SAI2_PLL3Q
+				CLK_SAI3_PLL3Q
+				CLK_SAI4_PLL3Q
+				CLK_RNG1_LSI
+				CLK_RNG2_LSI
+				CLK_LPTIM1_PCLK1
+				CLK_LPTIM23_PCLK3
+				CLK_LPTIM45_LSE
+			>;
+
+			/* VCO = 1300.0 MHz => P = 650 (CPU) */
+			pll1: st,pll@0 {
+				cfg = < 2 80 0 0 0 PQR(1,0,0) >;
+				frac = < 0x800 >;
+				u-boot,dm-pre-reloc;
+			};
+
+			/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
+			                       R = 533 (DDR) */
+			pll2: st,pll@1 {
+				cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+				frac = < 0x1400 >;
+				u-boot,dm-pre-reloc;
+			};
+
+			/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+			pll3: st,pll@2 {
+				cfg = < 1 33 1 16 36 PQR(1,1,1) >;
+				frac = < 0x1a04 >;
+				u-boot,dm-pre-reloc;
+			};
+
+			/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+			pll4: st,pll@3 {
+				cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+				u-boot,dm-pre-reloc;
+			};
+		};
+	};
+};
diff --git a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt
index 3028636..ee708ce 100644
--- a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt
+++ b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt
@@ -16,7 +16,7 @@
 info attributes:
 ----------------
 - st,mem-name	: name for DDR configuration, simple string for information
-- st,mem-speed	: DDR expected speed for the setting in MHz
+- st,mem-speed	: DDR expected speed for the setting in kHz
 - st,mem-size	: DDR mem size in byte
 
 
@@ -102,7 +102,7 @@
 phyc attributes:
 ----------------
 - st,phy-reg	: phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
-	for STM32MP15x: 10 values are requested in this order
+	for STM32MP15x: 11 values are requested in this order
 		PGCR
 		ACIOCR
 		DXCCR
@@ -173,7 +173,7 @@
 				      "ddrphycapb";
 
 			st,mem-name = "DDR3 2x4Gb 533MHz";
-			st,mem-speed = <533>;
+			st,mem-speed = <533000>;
 			st,mem-size = <0x40000000>;
 
 			st,ctl-reg = <
diff --git a/doc/device-tree-bindings/serial/mcf-uart.txt b/doc/device-tree-bindings/serial/mcf-uart.txt
new file mode 100644
index 0000000..d73f764
--- /dev/null
+++ b/doc/device-tree-bindings/serial/mcf-uart.txt
@@ -0,0 +1,19 @@
+Freescale ColdFire UART
+
+Required properties:
+- compatible : should be "fsl,mcf-uart"
+- reg: start address and size of the registers
+
+Example:
+
+soc {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	uart0: uart@fc060000 {
+		compatible = "fsl,mcf-uart";
+		reg = <0xfc060000 0x40>;
+		status = "disabled";
+	};
+};
diff --git a/doc/device-tree-bindings/spi/spi-mcf-dspi.txt b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt
new file mode 100644
index 0000000..860eb8a
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt
@@ -0,0 +1,30 @@
+Freescale ColdFire DSPI controller
+
+Required properties:
+- compatible : "fsl,mcf-dspi"
+- #address-cells: <1>, as required by generic SPI binding
+- #size-cells: <0>, also as required by generic SPI binding
+- reg : offset and length of the register set for the device
+
+Optional properties:
+- spi-max-frequency : max supported spi frequency
+- num-cs : the number of the chipselect signals
+- spi-mode: spi motorola mode, 0 to 3
+- ctar-params: CTAR0 to 7 register configuration, as an array
+  of 8 integer fields for each register, where each register
+  is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
+
+Example:
+
+dspi0: dspi@fc05c000 {
+	compatible = "fsl,mcf-dspi";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0xfc05c000 0x100>;
+	spi-max-frequency = <50000000>;
+	num-cs = <4>;
+	spi-mode = <0>;
+	ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>,
+		      <7, 0, 0, 0, 0, 0, 1, 6>,
+		      <7, 0, 0, 0, 0, 0, 1, 6>;
+};
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 4e95a68..87636ae 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -59,6 +59,16 @@
 	  Enable this driver to support Sata devices through
 	  Synopsys DWC AHCI module.
 
+config FSL_AHCI
+	bool "Enable Freescale AHCI driver support"
+	select SCSI_AHCI
+	depends on AHCI
+	depends on DM_SCSI
+	help
+	  Enable this driver to support Sata devices found in
+	  some Freescale PowerPC SoCs.
+
+
 config DWC_AHSATA
 	bool "Enable DWC AHSATA driver support"
 	select LIBATA
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index a69edb1..6e03384 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -4,6 +4,7 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
+obj-$(CONFIG_FSL_AHCI) += fsl_ahci.o
 obj-$(CONFIG_AHCI) += ahci-uclass.o
 obj-$(CONFIG_AHCI_PCI) += ahci-pci.o
 obj-$(CONFIG_SCSI_AHCI) += ahci.o
diff --git a/drivers/ata/fsl_ahci.c b/drivers/ata/fsl_ahci.c
new file mode 100644
index 0000000..d04cff3
--- /dev/null
+++ b/drivers/ata/fsl_ahci.c
@@ -0,0 +1,1030 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NXP PPC SATA platform driver
+ *
+ * (C) Copyright 2019 NXP, Inc.
+ *
+ */
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <dm/lists.h>
+#include <dm.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <libata.h>
+#include <sata.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <fis.h>
+
+#include "fsl_sata.h"
+
+struct fsl_ahci_priv {
+	u32 base;
+	u32 flag;
+	u32 number;
+	fsl_sata_t *fsl_sata;
+};
+
+static int fsl_ahci_bind(struct udevice *dev)
+{
+	return device_bind_driver(dev, "fsl_ahci_scsi", "fsl_ahci_scsi", NULL);
+}
+
+static int fsl_ahci_ofdata_to_platdata(struct udevice *dev)
+{
+	struct fsl_ahci_priv *priv = dev_get_priv(dev);
+
+	priv->number = dev_read_u32_default(dev, "sata-number", -1);
+	priv->flag = dev_read_u32_default(dev, "sata-fpdma", -1);
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int ata_wait_register(unsigned __iomem *addr, u32 mask,
+			     u32 val, u32 timeout_msec)
+{
+	int i;
+
+	for (i = 0; ((in_le32(addr) & mask) != val) && i < timeout_msec; i++)
+		mdelay(1);
+
+	return (i < timeout_msec) ? 0 : -1;
+}
+
+static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
+{
+	printf("Status FIS dump:\n\r");
+	printf("fis_type:		%02x\n\r", s->fis_type);
+	printf("pm_port_i:		%02x\n\r", s->pm_port_i);
+	printf("status:			%02x\n\r", s->status);
+	printf("error:			%02x\n\r", s->error);
+	printf("lba_low:		%02x\n\r", s->lba_low);
+	printf("lba_mid:		%02x\n\r", s->lba_mid);
+	printf("lba_high:		%02x\n\r", s->lba_high);
+	printf("device:			%02x\n\r", s->device);
+	printf("lba_low_exp:		%02x\n\r", s->lba_low_exp);
+	printf("lba_mid_exp:		%02x\n\r", s->lba_mid_exp);
+	printf("lba_high_exp:		%02x\n\r", s->lba_high_exp);
+	printf("res1:			%02x\n\r", s->res1);
+	printf("sector_count:		%02x\n\r", s->sector_count);
+	printf("sector_count_exp:	%02x\n\r", s->sector_count_exp);
+}
+
+static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
+{
+	printf("\n\rSATA:           %08x\n\r", (u32)reg);
+	printf("CQR:            %08x\n\r", in_le32(&reg->cqr));
+	printf("CAR:            %08x\n\r", in_le32(&reg->car));
+	printf("CCR:            %08x\n\r", in_le32(&reg->ccr));
+	printf("CER:            %08x\n\r", in_le32(&reg->cer));
+	printf("CQR:            %08x\n\r", in_le32(&reg->cqr));
+	printf("DER:            %08x\n\r", in_le32(&reg->der));
+	printf("CHBA:           %08x\n\r", in_le32(&reg->chba));
+	printf("HStatus:        %08x\n\r", in_le32(&reg->hstatus));
+	printf("HControl:       %08x\n\r", in_le32(&reg->hcontrol));
+	printf("CQPMP:          %08x\n\r", in_le32(&reg->cqpmp));
+	printf("SIG:            %08x\n\r", in_le32(&reg->sig));
+	printf("ICC:            %08x\n\r", in_le32(&reg->icc));
+	printf("SStatus:        %08x\n\r", in_le32(&reg->sstatus));
+	printf("SError:         %08x\n\r", in_le32(&reg->serror));
+	printf("SControl:       %08x\n\r", in_le32(&reg->scontrol));
+	printf("SNotification:  %08x\n\r", in_le32(&reg->snotification));
+	printf("TransCfg:       %08x\n\r", in_le32(&reg->transcfg));
+	printf("TransStatus:    %08x\n\r", in_le32(&reg->transstatus));
+	printf("LinkCfg:        %08x\n\r", in_le32(&reg->linkcfg));
+	printf("LinkCfg1:       %08x\n\r", in_le32(&reg->linkcfg1));
+	printf("LinkCfg2:       %08x\n\r", in_le32(&reg->linkcfg2));
+	printf("LinkStatus:     %08x\n\r", in_le32(&reg->linkstatus));
+	printf("LinkStatus1:    %08x\n\r", in_le32(&reg->linkstatus1));
+	printf("PhyCtrlCfg:     %08x\n\r", in_le32(&reg->phyctrlcfg));
+	printf("SYSPR:          %08x\n\r", in_be32(&reg->syspr));
+}
+
+static int init_sata(struct fsl_ahci_priv *priv)
+{
+	int i;
+	u32 cda;
+	u32 val32;
+	u32 sig;
+	fsl_sata_t *sata;
+	u32 length, align;
+	cmd_hdr_tbl_t *cmd_hdr;
+	fsl_sata_reg_t __iomem *reg;
+
+	int dev = priv->number;
+
+	if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
+		printf("the sata index %d is out of ranges\n\r", dev);
+		return -EINVAL;
+	}
+
+#ifdef CONFIG_MPC85xx
+	if (dev == 0 && (!is_serdes_configured(SATA1))) {
+		printf("SATA%d [dev = %d] is not enabled\n", dev + 1, dev);
+		return -EINVAL;
+	}
+	if (dev == 1 && (!is_serdes_configured(SATA2))) {
+		printf("SATA%d [dev = %d] is not enabled\n", dev + 1, dev);
+		return -EINVAL;
+	}
+#endif
+
+	/* Allocate SATA device driver struct */
+	sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
+	if (!sata) {
+		printf("alloc the sata device struct failed\n\r");
+		return -ENOMEM;
+	}
+	/* Zero all of the device driver struct */
+	memset((void *)sata, 0, sizeof(fsl_sata_t));
+
+	sata->dma_flag = priv->flag;
+	snprintf(sata->name, 12, "SATA%d", dev);
+
+	/* Set the controller register base address to device struct */
+	reg = (fsl_sata_reg_t *)priv->base;
+	sata->reg_base = reg;
+
+	/* Allocate the command header table, 4 bytes aligned */
+	length = sizeof(struct cmd_hdr_tbl);
+	align = SATA_HC_CMD_HDR_TBL_ALIGN;
+	sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
+	if (!sata->cmd_hdr_tbl_offset) {
+		printf("alloc the command header failed\n\r");
+		return -ENOMEM;
+	}
+
+	cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
+						& ~(align - 1));
+	sata->cmd_hdr = cmd_hdr;
+
+	/* Zero all of the command header table */
+	memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
+
+	/* Allocate command descriptor for all command */
+	length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
+	align = SATA_HC_CMD_DESC_ALIGN;
+	sata->cmd_desc_offset = (void *)malloc(length + align);
+	if (!sata->cmd_desc_offset) {
+		printf("alloc the command descriptor failed\n\r");
+		return -ENOMEM;
+	}
+	sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
+						& ~(align - 1));
+	/* Zero all of command descriptor */
+	memset((void *)sata->cmd_desc_offset, 0, length + align);
+
+	/* Link the command descriptor to command header */
+	for (i = 0; i < SATA_HC_MAX_CMD; i++) {
+		cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
+					 & ~(CMD_HDR_CDA_ALIGN - 1);
+		cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
+	}
+
+	/* To have safe state, force the controller offline */
+	val32 = in_le32(&reg->hcontrol);
+	val32 &= ~HCONTROL_ONOFF;
+	val32 |= HCONTROL_FORCE_OFFLINE;
+	out_le32(&reg->hcontrol, val32);
+
+	/* Wait the controller offline */
+	ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
+
+	/* Set the command header base address to CHBA register to tell DMA */
+	out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
+
+	/* Snoop for the command header */
+	val32 = in_le32(&reg->hcontrol);
+	val32 |= HCONTROL_HDR_SNOOP;
+	out_le32(&reg->hcontrol, val32);
+
+	/* Disable all of interrupts */
+	val32 = in_le32(&reg->hcontrol);
+	val32 &= ~HCONTROL_INT_EN_ALL;
+	out_le32(&reg->hcontrol, val32);
+
+	/* Clear all of interrupts */
+	val32 = in_le32(&reg->hstatus);
+	out_le32(&reg->hstatus, val32);
+
+	/* Set the ICC, no interrupt coalescing */
+	out_le32(&reg->icc, 0x01000000);
+
+	/* No PM attatched, the SATA device direct connect */
+	out_le32(&reg->cqpmp, 0);
+
+	/* Clear SError register */
+	val32 = in_le32(&reg->serror);
+	out_le32(&reg->serror, val32);
+
+	/* Clear CER register */
+	val32 = in_le32(&reg->cer);
+	out_le32(&reg->cer, val32);
+
+	/* Clear DER register */
+	val32 = in_le32(&reg->der);
+	out_le32(&reg->der, val32);
+
+	/* No device detection or initialization action requested */
+	out_le32(&reg->scontrol, 0x00000300);
+
+	/* Configure the transport layer, default value */
+	out_le32(&reg->transcfg, 0x08000016);
+
+	/* Configure the link layer, default value */
+	out_le32(&reg->linkcfg, 0x0000ff34);
+
+	/* Bring the controller online */
+	val32 = in_le32(&reg->hcontrol);
+	val32 |= HCONTROL_ONOFF;
+	out_le32(&reg->hcontrol, val32);
+
+	mdelay(100);
+
+	/* print sata device name */
+	printf("%s ", sata->name);
+
+	/* Wait PHY RDY signal changed for 500ms */
+	ata_wait_register(&reg->hstatus, HSTATUS_PHY_RDY,
+			  HSTATUS_PHY_RDY, 500);
+
+	/* Check PHYRDY */
+	val32 = in_le32(&reg->hstatus);
+	if (val32 & HSTATUS_PHY_RDY) {
+		sata->link = 1;
+	} else {
+		sata->link = 0;
+		printf("(No RDY)\n\r");
+		return -EINVAL;
+	}
+
+	/* Wait for signature updated, which is 1st D2H */
+	ata_wait_register(&reg->hstatus, HSTATUS_SIGNATURE,
+			  HSTATUS_SIGNATURE, 10000);
+
+	if (val32 & HSTATUS_SIGNATURE) {
+		sig = in_le32(&reg->sig);
+		debug("Signature updated, the sig =%08x\n\r", sig);
+		sata->ata_device_type = ata_dev_classify(sig);
+	}
+
+	/* Check the speed */
+	val32 = in_le32(&reg->sstatus);
+	if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
+		printf("(1.5 Gbps)\n\r");
+	else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
+		printf("(3 Gbps)\n\r");
+
+	priv->fsl_sata = sata;
+
+	return 0;
+}
+
+static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata,
+				struct sata_fis_h2d *cfis,
+				int is_ncq, int tag,
+				u8 *buffer, u32 len)
+{
+	cmd_hdr_entry_t *cmd_hdr;
+	cmd_desc_t *cmd_desc;
+	sata_fis_h2d_t *h2d;
+	prd_entry_t *prde;
+	u32 ext_c_ddc;
+	u32 prde_count;
+	u32 val32;
+	u32 ttl;
+	u32 der;
+	int i;
+
+	fsl_sata_reg_t *reg = sata->reg_base;
+
+	/* Check xfer length */
+	if (len > SATA_HC_MAX_XFER_LEN) {
+		printf("max transfer length is 64MB\n\r");
+		return 0;
+	}
+
+	/* Setup the command descriptor */
+	cmd_desc = sata->cmd_desc + tag;
+
+	/* Get the pointer cfis of command descriptor */
+	h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
+
+	/* Zero the cfis of command descriptor */
+	memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
+
+	/* Copy the cfis from user to command descriptor */
+	h2d->fis_type = cfis->fis_type;
+	h2d->pm_port_c = cfis->pm_port_c;
+	h2d->command = cfis->command;
+
+	h2d->features = cfis->features;
+	h2d->features_exp = cfis->features_exp;
+
+	h2d->lba_low = cfis->lba_low;
+	h2d->lba_mid = cfis->lba_mid;
+	h2d->lba_high = cfis->lba_high;
+	h2d->lba_low_exp = cfis->lba_low_exp;
+	h2d->lba_mid_exp = cfis->lba_mid_exp;
+	h2d->lba_high_exp = cfis->lba_high_exp;
+
+	if (!is_ncq) {
+		h2d->sector_count = cfis->sector_count;
+		h2d->sector_count_exp = cfis->sector_count_exp;
+	} else { /* NCQ */
+		h2d->sector_count = (u8)(tag << 3);
+	}
+
+	h2d->device = cfis->device;
+	h2d->control = cfis->control;
+
+	/* Setup the PRD table */
+	prde = (prd_entry_t *)cmd_desc->prdt;
+	memset((void *)prde, 0, sizeof(struct prdt));
+
+	prde_count = 0;
+	ttl = len;
+	for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
+		if (!len)
+			break;
+		prde->dba = cpu_to_le32((u32)buffer & ~0x3);
+		debug("dba = %08x\n\r", (u32)buffer);
+
+		if (len < PRD_ENTRY_MAX_XFER_SZ) {
+			ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
+			debug("ext_c_ddc1 = %08x, len = %08x\n\r",
+			      ext_c_ddc, len);
+			prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
+			prde_count++;
+			prde++;
+		} else {
+			ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
+			debug("ext_c_ddc2 = %08x, len = %08x\n\r",
+			      ext_c_ddc, len);
+			prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
+			buffer += PRD_ENTRY_MAX_XFER_SZ;
+			len -= PRD_ENTRY_MAX_XFER_SZ;
+			prde_count++;
+			prde++;
+		}
+	}
+
+	/* Setup the command slot of cmd hdr */
+	cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
+
+	cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
+
+	val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
+	val32 |= sizeof(sata_fis_h2d_t);
+	cmd_hdr->prde_fis_len = cpu_to_le32(val32);
+
+	cmd_hdr->ttl = cpu_to_le32(ttl);
+
+	if (!is_ncq)
+		val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
+	else
+		val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP |
+			CMD_HDR_ATTR_FPDMA;
+
+	tag &= CMD_HDR_ATTR_TAG;
+	val32 |= tag;
+
+	debug("attribute = %08x\n\r", val32);
+	cmd_hdr->attribute = cpu_to_le32(val32);
+
+	/* Make sure cmd desc and cmd slot valid before command issue */
+	sync();
+
+	/* PMP*/
+	val32 = (u32)(h2d->pm_port_c & 0x0f);
+	out_le32(&reg->cqpmp, val32);
+
+	/* Wait no active */
+	if (ata_wait_register(&reg->car, (1 << tag), 0, 10000))
+		printf("Wait no active time out\n\r");
+
+	/* Issue command */
+	if (!(in_le32(&reg->cqr) & (1 << tag))) {
+		val32 = 1 << tag;
+		out_le32(&reg->cqr, val32);
+	}
+
+	/* Wait command completed for 10s */
+	if (ata_wait_register(&reg->ccr, (1 << tag), (1 << tag), 10000)) {
+		if (!is_ncq)
+			printf("Non-NCQ command time out\n\r");
+		else
+			printf("NCQ command time out\n\r");
+	}
+
+	val32 = in_le32(&reg->cer);
+
+	if (val32) {
+		fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
+		printf("CE at device\n\r");
+		fsl_sata_dump_regs(reg);
+		der = in_le32(&reg->der);
+		out_le32(&reg->cer, val32);
+		out_le32(&reg->der, der);
+	}
+
+	/* Clear complete flags */
+	val32 = in_le32(&reg->ccr);
+	out_le32(&reg->ccr, val32);
+
+	return len;
+}
+
+static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
+			     enum cmd_type command_type, int tag, u8 *buffer,
+			     u32 len)
+{
+	int rc;
+
+	if (tag > SATA_HC_MAX_CMD || tag < 0) {
+		printf("tag is out of range, tag=%d\n\r", tag);
+		return -1;
+	}
+
+	switch (command_type) {
+	case CMD_ATA:
+		rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
+		return rc;
+	case CMD_NCQ:
+		rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
+		return rc;
+	case CMD_ATAPI:
+	case CMD_VENDOR_BIST:
+	case CMD_BIST:
+		printf("not support now\n\r");
+		return -1;
+	default:
+		break;
+	}
+
+	return -1;
+}
+
+static void fsl_sata_identify(fsl_sata_t *sata, u16 *id)
+{
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+	cfis->command = ATA_CMD_ID_ATA;
+
+	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
+	ata_swap_buf_le16(id, ATA_ID_WORDS);
+}
+
+static void fsl_sata_xfer_mode(fsl_sata_t *sata, u16 *id)
+{
+	sata->pio = id[ATA_ID_PIO_MODES];
+	sata->mwdma = id[ATA_ID_MWDMA_MODES];
+	sata->udma = id[ATA_ID_UDMA_MODES];
+	debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio,
+	      sata->mwdma, sata->udma);
+}
+
+static void fsl_sata_init_wcache(fsl_sata_t *sata, u16 *id)
+{
+	if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
+		sata->wcache = 1;
+	if (ata_id_has_flush(id))
+		sata->flush = 1;
+	if (ata_id_has_flush_ext(id))
+		sata->flush_ext = 1;
+}
+
+static void fsl_sata_set_features(fsl_sata_t *sata)
+{
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+	u8 udma_cap;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+	cfis->command = ATA_CMD_SET_FEATURES;
+	cfis->features = SETFEATURES_XFER;
+
+	/* First check the device capablity */
+	udma_cap = (u8)(sata->udma & 0xff);
+	debug("udma_cap %02x\n\r", udma_cap);
+
+	if (udma_cap == ATA_UDMA6)
+		cfis->sector_count = XFER_UDMA_6;
+	if (udma_cap == ATA_UDMA5)
+		cfis->sector_count = XFER_UDMA_5;
+	if (udma_cap == ATA_UDMA4)
+		cfis->sector_count = XFER_UDMA_4;
+	if (udma_cap == ATA_UDMA3)
+		cfis->sector_count = XFER_UDMA_3;
+
+	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
+}
+
+static u32 fsl_sata_rw_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
+			   u8 *buffer, int is_write)
+{
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+	u32 block;
+
+	block = start;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+	cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
+	cfis->device = ATA_LBA;
+
+	cfis->device |= (block >> 24) & 0xf;
+	cfis->lba_high = (block >> 16) & 0xff;
+	cfis->lba_mid = (block >> 8) & 0xff;
+	cfis->lba_low = block & 0xff;
+	cfis->sector_count = (u8)(blkcnt & 0xff);
+
+	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer,
+			  ATA_SECT_SIZE * blkcnt);
+	return blkcnt;
+}
+
+static void fsl_sata_flush_cache(fsl_sata_t *sata)
+{
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+	cfis->command = ATA_CMD_FLUSH;
+
+	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
+}
+
+static u32 fsl_sata_rw_cmd_ext(fsl_sata_t *sata, u32 start,
+			       u32 blkcnt, u8 *buffer, int is_write)
+{
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+	u64 block;
+
+	block = (u64)start;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+
+	cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
+				 : ATA_CMD_READ_EXT;
+
+	cfis->lba_high_exp = (block >> 40) & 0xff;
+	cfis->lba_mid_exp = (block >> 32) & 0xff;
+	cfis->lba_low_exp = (block >> 24) & 0xff;
+	cfis->lba_high = (block >> 16) & 0xff;
+	cfis->lba_mid = (block >> 8) & 0xff;
+	cfis->lba_low = block & 0xff;
+	cfis->device = ATA_LBA;
+	cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
+	cfis->sector_count = blkcnt & 0xff;
+
+	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer,
+			  ATA_SECT_SIZE * blkcnt);
+	return blkcnt;
+}
+
+static u32 fsl_sata_rw_ncq_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
+			       u8 *buffer,
+			       int is_write)
+{
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+	int ncq_channel;
+	u64 block;
+
+	if (sata->lba48 != 1) {
+		printf("execute FPDMA command on non-LBA48 hard disk\n\r");
+		return -1;
+	}
+
+	block = (u64)start;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+
+	cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
+				 : ATA_CMD_FPDMA_READ;
+
+	cfis->lba_high_exp = (block >> 40) & 0xff;
+	cfis->lba_mid_exp = (block >> 32) & 0xff;
+	cfis->lba_low_exp = (block >> 24) & 0xff;
+	cfis->lba_high = (block >> 16) & 0xff;
+	cfis->lba_mid = (block >> 8) & 0xff;
+	cfis->lba_low = block & 0xff;
+
+	cfis->device = ATA_LBA;
+	cfis->features_exp = (blkcnt >> 8) & 0xff;
+	cfis->features = blkcnt & 0xff;
+
+	if (sata->queue_depth >= SATA_HC_MAX_CMD)
+		ncq_channel = SATA_HC_MAX_CMD - 1;
+	else
+		ncq_channel = sata->queue_depth - 1;
+
+	/* Use the latest queue */
+	fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer,
+			  ATA_SECT_SIZE * blkcnt);
+	return blkcnt;
+}
+
+static void fsl_sata_flush_cache_ext(fsl_sata_t *sata)
+{
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+	cfis->command = ATA_CMD_FLUSH_EXT;
+
+	fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
+}
+
+static u32 ata_low_level_rw_lba48(fsl_sata_t *sata, u32 blknr, lbaint_t blkcnt,
+				  const void *buffer, int is_write)
+{
+	u32 start, blks;
+	u8 *addr;
+	int max_blks;
+
+	start = blknr;
+	blks = blkcnt;
+	addr = (u8 *)buffer;
+
+	max_blks = ATA_MAX_SECTORS_LBA48;
+	do {
+		if (blks > max_blks) {
+			if (sata->dma_flag != FLAGS_FPDMA)
+				fsl_sata_rw_cmd_ext(sata, start, max_blks,
+						    addr, is_write);
+			else
+				fsl_sata_rw_ncq_cmd(sata, start, max_blks,
+						    addr, is_write);
+			start += max_blks;
+			blks -= max_blks;
+			addr += ATA_SECT_SIZE * max_blks;
+		} else {
+			if (sata->dma_flag != FLAGS_FPDMA)
+				fsl_sata_rw_cmd_ext(sata, start, blks,
+						    addr, is_write);
+			else
+				fsl_sata_rw_ncq_cmd(sata, start, blks,
+						    addr, is_write);
+			start += blks;
+			blks = 0;
+			addr += ATA_SECT_SIZE * blks;
+		}
+	} while (blks != 0);
+
+	return blks;
+}
+
+static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt,
+				  const void *buffer, int is_write)
+{
+	u32 start, blks;
+	u8 *addr;
+	int max_blks;
+
+	start = blknr;
+	blks = blkcnt;
+	addr = (u8 *)buffer;
+
+	max_blks = ATA_MAX_SECTORS;
+	do {
+		if (blks > max_blks) {
+			fsl_sata_rw_cmd(sata, start, max_blks, addr, is_write);
+			start += max_blks;
+			blks -= max_blks;
+			addr += ATA_SECT_SIZE * max_blks;
+		} else {
+			fsl_sata_rw_cmd(sata, start, blks, addr, is_write);
+			start += blks;
+			blks = 0;
+			addr += ATA_SECT_SIZE * blks;
+		}
+	} while (blks != 0);
+
+	return blks;
+}
+
+/*
+ * SATA interface between low level driver and command layer
+ */
+static int sata_read(fsl_sata_t *sata, ulong blknr, lbaint_t blkcnt,
+		     void *buffer)
+{
+	u32 rc;
+
+	if (sata->lba48)
+		rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
+					    READ_CMD);
+	else
+		rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
+					    READ_CMD);
+	return rc;
+}
+
+static int sata_write(fsl_sata_t *sata, ulong blknr, lbaint_t blkcnt,
+		      const void *buffer)
+{
+	u32 rc;
+
+	if (sata->lba48) {
+		rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
+					    WRITE_CMD);
+		if (sata->wcache && sata->flush_ext)
+			fsl_sata_flush_cache_ext(sata);
+	} else {
+		rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
+					    WRITE_CMD);
+		if (sata->wcache && sata->flush)
+			fsl_sata_flush_cache(sata);
+	}
+
+	return rc;
+}
+
+int sata_getinfo(fsl_sata_t *sata, u16 *id)
+{
+	/* if no detected link */
+	if (!sata->link)
+		return -EINVAL;
+
+#ifdef CONFIG_LBA48
+	/* Check if support LBA48 */
+	if (ata_id_has_lba48(id)) {
+		sata->lba48 = 1;
+		debug("Device support LBA48\n\r");
+	} else {
+		debug("Device supports LBA28\n\r");
+	}
+#endif
+
+	/* Get the NCQ queue depth from device */
+	sata->queue_depth = ata_id_queue_depth(id);
+
+	/* Get the xfer mode from device */
+	fsl_sata_xfer_mode(sata, id);
+
+	/* Get the write cache status from device */
+	fsl_sata_init_wcache(sata, id);
+
+	/* Set the xfer mode to highest speed */
+	fsl_sata_set_features(sata);
+
+	return 0;
+}
+
+static int fsl_scsi_exec(fsl_sata_t *sata, struct scsi_cmd *pccb,
+			 bool is_write)
+{
+	int ret;
+	u32 temp;
+	u16 blocks = 0;
+	lbaint_t start = 0;
+	u8 *buffer = pccb->pdata;
+
+	/* Retrieve the base LBA number from the ccb structure. */
+	if (pccb->cmd[0] == SCSI_READ16) {
+		memcpy(&start, pccb->cmd + 2, 8);
+		start = be64_to_cpu(start);
+	} else {
+		memcpy(&temp, pccb->cmd + 2, 4);
+		start = be32_to_cpu(temp);
+	}
+
+	if (pccb->cmd[0] == SCSI_READ16)
+		blocks = (((u16)pccb->cmd[13]) << 8) | ((u16)pccb->cmd[14]);
+	else
+		blocks = (((u16)pccb->cmd[7]) << 8) | ((u16)pccb->cmd[8]);
+
+	debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
+	      is_write ?  "write" : "read", blocks, start);
+
+	if (is_write)
+		ret = sata_write(sata, start, blocks, buffer);
+	else
+		ret = sata_read(sata, start, blocks, buffer);
+
+	return ret;
+}
+
+static char *fsl_ata_id_strcpy(u16 *target, u16 *src, int len)
+{
+	int i;
+
+	for (i = 0; i < len / 2; i++)
+		target[i] = src[i];
+
+	return (char *)target;
+}
+
+static int fsl_ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
+				  struct scsi_cmd *pccb,
+				  fsl_sata_t *sata)
+{
+	u8 port;
+	u16 *idbuf;
+
+	ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
+
+	/* Clean ccb data buffer */
+	memset(pccb->pdata, 0, pccb->datalen);
+
+	if (pccb->datalen <= 35)
+		return 0;
+
+	/* Read id from sata */
+	port = pccb->target;
+
+	fsl_sata_identify(sata, (u16 *)tmpid);
+
+	if (!uc_priv->ataid[port]) {
+		uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
+		if (!uc_priv->ataid[port]) {
+			printf("%s: No memory for ataid[port]\n", __func__);
+			return -ENOMEM;
+		}
+	}
+
+	idbuf = uc_priv->ataid[port];
+
+	memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
+
+	memcpy(&pccb->pdata[8], "ATA     ", 8);
+	fsl_ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
+	fsl_ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
+
+	sata_getinfo(sata, (u16 *)idbuf);
+#ifdef DEBUG
+	ata_dump_id(idbuf);
+#endif
+	return 0;
+}
+
+/*
+ * SCSI READ CAPACITY10 command operation.
+ */
+static int fsl_ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
+					  struct scsi_cmd *pccb)
+{
+	u32 cap;
+	u64 cap64;
+	u32 block_size;
+
+	if (!uc_priv->ataid[pccb->target]) {
+		printf("scsi_ahci: SCSI READ CAPACITY10 command failure.");
+		printf("\tNo ATA info!\n");
+		printf("\tPlease run SCSI command INQUIRY first!\n");
+		return -EPERM;
+	}
+
+	cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
+	if (cap64 > 0x100000000ULL)
+		cap64 = 0xffffffff;
+
+	cap = cpu_to_be32(cap64);
+	memcpy(pccb->pdata, &cap, sizeof(cap));
+
+	block_size = cpu_to_be32((u32)512);
+	memcpy(&pccb->pdata[4], &block_size, 4);
+
+	return 0;
+}
+
+/*
+ * SCSI READ CAPACITY16 command operation.
+ */
+static int fsl_ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
+					  struct scsi_cmd *pccb)
+{
+	u64 cap;
+	u64 block_size;
+
+	if (!uc_priv->ataid[pccb->target]) {
+		printf("scsi_ahci: SCSI READ CAPACITY16 command failure.");
+		printf("\tNo ATA info!\n");
+		printf("\tPlease run SCSI command INQUIRY first!\n");
+		return -EPERM;
+	}
+
+	cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
+	cap = cpu_to_be64(cap);
+	memcpy(pccb->pdata, &cap, sizeof(cap));
+
+	block_size = cpu_to_be64((u64)512);
+	memcpy(&pccb->pdata[8], &block_size, 8);
+
+	return 0;
+}
+
+/*
+ * SCSI TEST UNIT READY command operation.
+ */
+static int fsl_ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
+					  struct scsi_cmd *pccb)
+{
+	return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
+}
+
+static int fsl_ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
+{
+	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev->parent);
+	struct fsl_ahci_priv *priv = dev_get_priv(dev->parent);
+	fsl_sata_t *sata = priv->fsl_sata;
+	int ret;
+
+	switch (pccb->cmd[0]) {
+	case SCSI_READ16:
+	case SCSI_READ10:
+		ret = fsl_scsi_exec(sata, pccb, 0);
+		break;
+	case SCSI_WRITE10:
+		ret = fsl_scsi_exec(sata, pccb, 1);
+		break;
+	case SCSI_RD_CAPAC10:
+		ret = fsl_ata_scsiop_read_capacity10(uc_priv, pccb);
+		break;
+	case SCSI_RD_CAPAC16:
+		ret = fsl_ata_scsiop_read_capacity16(uc_priv, pccb);
+		break;
+	case SCSI_TST_U_RDY:
+		ret = fsl_ata_scsiop_test_unit_ready(uc_priv, pccb);
+		break;
+	case SCSI_INQUIRY:
+		ret = fsl_ata_scsiop_inquiry(uc_priv, pccb, sata);
+		break;
+	default:
+		printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
+		return -ENOTSUPP;
+	}
+
+	if (ret) {
+		debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int fsl_ahci_probe(struct udevice *dev)
+{
+	struct fsl_ahci_priv *priv = dev_get_priv(dev);
+	struct udevice *child_dev;
+	struct scsi_platdata *uc_plat;
+
+	device_find_first_child(dev, &child_dev);
+	if (!child_dev)
+		return -ENODEV;
+	uc_plat = dev_get_uclass_platdata(child_dev);
+	uc_plat->base = priv->base;
+	uc_plat->max_lun = 1;
+	uc_plat->max_id = 1;
+
+	return init_sata(priv);
+}
+
+struct scsi_ops fsl_scsi_ops = {
+	.exec		= fsl_ahci_scsi_exec,
+};
+
+static const struct udevice_id fsl_ahci_ids[] = {
+	{ .compatible = "fsl,pq-sata-v2" },
+	{ }
+};
+
+U_BOOT_DRIVER(fsl_ahci_scsi) = {
+	.name		= "fsl_ahci_scsi",
+	.id		= UCLASS_SCSI,
+	.ops		= &fsl_scsi_ops,
+};
+
+U_BOOT_DRIVER(fsl_ahci) = {
+	.name	= "fsl_ahci",
+	.id	= UCLASS_AHCI,
+	.of_match = fsl_ahci_ids,
+	.bind	= fsl_ahci_bind,
+	.ofdata_to_platdata = fsl_ahci_ofdata_to_platdata,
+	.probe	= fsl_ahci_probe,
+	.priv_auto_alloc_size = sizeof(struct fsl_ahci_priv),
+};
diff --git a/drivers/ata/fsl_sata.h b/drivers/ata/fsl_sata.h
index 1e2da10..a4ee83d 100644
--- a/drivers/ata/fsl_sata.h
+++ b/drivers/ata/fsl_sata.h
@@ -312,6 +312,7 @@
 	int		wcache;
 	int		flush;
 	int		flush_ext;
+	u32		dma_flag;
 } fsl_sata_t;
 
 #define READ_CMD	0
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index 8887be9..2d49630 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -8,6 +8,7 @@
 #include <ahci.h>
 #include <scsi.h>
 #include <asm/io.h>
+#include <linux/ioport.h>
 
 /* Vendor Specific Register Offsets */
 #define AHCI_VEND_PCFG  0xA4
@@ -88,20 +89,16 @@
 #define LS1021_CEVA_PHY4_CFG	0x064a080b
 #define LS1021_CEVA_PHY5_CFG	0x2aa86470
 
-/* for ls1088a */
-#define LS1088_ECC_DIS_ADDR_CH2	0x100520
-#define LS1088_ECC_DIS_VAL_CH2	0x40000000
-
-/* ecc addr-val pair */
-#define ECC_DIS_ADDR_CH2	0x20140520
+/* ecc val pair */
+#define ECC_DIS_VAL_CH1		0x00020000
 #define ECC_DIS_VAL_CH2		0x80000000
-#define SATA_ECC_REG_ADDR	0x20220520
-#define SATA_ECC_DISABLE	0x00020000
+#define ECC_DIS_VAL_CH3		0x40000000
 
 enum ceva_soc {
 	CEVA_1V84,
 	CEVA_LS1012A,
 	CEVA_LS1021A,
+	CEVA_LS1028A,
 	CEVA_LS1043A,
 	CEVA_LS1046A,
 	CEVA_LS1088A,
@@ -110,12 +107,14 @@
 
 struct ceva_sata_priv {
 	ulong base;
+	ulong ecc_base;
 	enum ceva_soc soc;
 	ulong flag;
 };
 
 static int ceva_init_sata(struct ceva_sata_priv *priv)
 {
+	ulong ecc_addr = priv->ecc_base;
 	ulong base = priv->base;
 	ulong tmp;
 
@@ -132,38 +131,42 @@
 		break;
 
 	case CEVA_LS1021A:
-		writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR);
+		if (!ecc_addr)
+			return -EINVAL;
+		writel(ECC_DIS_VAL_CH1, ecc_addr);
 		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
 		writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
 		writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
 		writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
 		writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
 		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
-		if (priv->flag & FLAG_COHERENT)
-			writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC);
 		break;
 
 	case CEVA_LS1012A:
 	case CEVA_LS1043A:
 	case CEVA_LS1046A:
-		writel(ECC_DIS_VAL_CH2, ECC_DIS_ADDR_CH2);
+		if (!ecc_addr)
+			return -EINVAL;
+		writel(ECC_DIS_VAL_CH2, ecc_addr);
 		/* fallthrough */
 	case CEVA_LS2080A:
 		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
 		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
-		if (priv->flag & FLAG_COHERENT)
-			writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
 		break;
 
+	case CEVA_LS1028A:
 	case CEVA_LS1088A:
-		writel(LS1088_ECC_DIS_VAL_CH2, LS1088_ECC_DIS_ADDR_CH2);
+		if (!ecc_addr)
+			return -EINVAL;
+		writel(ECC_DIS_VAL_CH3, ecc_addr);
 		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
 		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
-		if (priv->flag & FLAG_COHERENT)
-			writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
 		break;
 	}
 
+	if (priv->flag & FLAG_COHERENT)
+		writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
+
 	return 0;
 }
 
@@ -187,6 +190,7 @@
 	{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
 	{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
 	{ .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
+	{ .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A },
 	{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
 	{ .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
 	{ .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
@@ -197,6 +201,8 @@
 static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ceva_sata_priv *priv = dev_get_priv(dev);
+	struct resource res_regs;
+	int ret;
 
 	if (dev_read_bool(dev, "dma-coherent"))
 		priv->flag |= FLAG_COHERENT;
@@ -205,8 +211,18 @@
 	if (priv->base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
+	ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs);
+	if (ret)
+		priv->ecc_base = 0;
+	else
+		priv->ecc_base = res_regs.start;
+
 	priv->soc = dev_get_driver_data(dev);
 
+	debug("ccsr-sata-base %lx\t ecc-base %lx\n",
+	      priv->base,
+	      priv->ecc_base);
+
 	return 0;
 }
 
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 24859fd..6272b00 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -1448,6 +1448,71 @@
 	setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
 }
 
+static  __maybe_unused int pll_set_rate(struct udevice *dev,
+					int pll_id,
+					int div_id,
+					unsigned long clk_rate)
+{
+	struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+	unsigned int pllcfg[PLLCFG_NB];
+	ofnode plloff;
+	char name[12];
+	const struct stm32mp1_clk_pll *pll = priv->data->pll;
+	enum stm32mp1_plltype type = pll[pll_id].plltype;
+	int divm, divn, divy;
+	int ret;
+	ulong fck_ref;
+	u32 fracv;
+	u64 value;
+
+	if (div_id > _DIV_NB)
+		return -EINVAL;
+
+	sprintf(name, "st,pll@%d", pll_id);
+	plloff = dev_read_subnode(dev, name);
+	if (!ofnode_valid(plloff))
+		return -FDT_ERR_NOTFOUND;
+
+	ret = ofnode_read_u32_array(plloff, "cfg",
+				    pllcfg, PLLCFG_NB);
+	if (ret < 0)
+		return -FDT_ERR_NOTFOUND;
+
+	fck_ref = pll_get_fref_ck(priv, pll_id);
+
+	divm = pllcfg[PLLCFG_M];
+	/* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
+	divy = pllcfg[PLLCFG_P + div_id];
+
+	/* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
+	 * So same final result than PLL2 et 4
+	 * with FRACV
+	 * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
+	 *             / (DIVy + 1) * (DIVM + 1)
+	 * value = (DIVN + 1) * 2^13 + FRACV / 2^13
+	 *       = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
+	 */
+	value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
+	value = lldiv(value, fck_ref);
+
+	divn = (value >> 13) - 1;
+	if (divn < DIVN_MIN ||
+	    divn > stm32mp1_pll[type].divn_max) {
+		pr_err("divn invalid = %d", divn);
+		return -EINVAL;
+	}
+	fracv = value - ((divn + 1) << 13);
+	pllcfg[PLLCFG_N] = divn;
+
+	/* reconfigure PLL */
+	pll_stop(priv, pll_id);
+	pll_config(priv, pll_id, pllcfg, fracv);
+	pll_start(priv, pll_id);
+	pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
+
+	return 0;
+}
+
 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
 {
 	u32 address = priv->base + (clksrc >> 4);
@@ -1820,6 +1885,11 @@
 	int p;
 
 	switch (clk->id) {
+#if defined(STM32MP1_CLOCK_TREE_INIT) && \
+	defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
+	case DDRPHYC:
+		break;
+#endif
 	case LTDC_PX:
 	case DSI_PX:
 		break;
@@ -1833,6 +1903,19 @@
 		return -EINVAL;
 
 	switch (p) {
+#if defined(STM32MP1_CLOCK_TREE_INIT) && \
+	defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
+	case _PLL2_R: /* DDRPHYC */
+	{
+		/* only for change DDR clock in interactive mode */
+		ulong result;
+
+		set_clksrc(priv, CLK_AXI_HSI);
+		result = pll_set_rate(clk->dev,  _PLL2, _DIV_R, clk_rate);
+		set_clksrc(priv, CLK_AXI_PLL2P);
+		return result;
+	}
+#endif
 	case _PLL4_Q:
 		/* for LTDC_PX and DSI_PX case */
 		return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index cc0c031..c72c6e2 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -39,7 +39,7 @@
 	return 0;
 }
 
-int ofnode_read_u32_default(ofnode node, const char *propname, u32 def)
+u32 ofnode_read_u32_default(ofnode node, const char *propname, u32 def)
 {
 	assert(ofnode_valid(node));
 	ofnode_read_u32(node, propname, &def);
@@ -251,7 +251,7 @@
 	return -EINVAL;
 }
 
-fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
+fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size)
 {
 	int na, ns;
 
@@ -260,7 +260,7 @@
 		uint flags;
 
 		prop_val = of_get_address(ofnode_to_np(node), index,
-					  NULL, &flags);
+					  (u64 *)size, &flags);
 		if (!prop_val)
 			return FDT_ADDR_T_NONE;
 
@@ -277,12 +277,19 @@
 		ns = ofnode_read_simple_size_cells(ofnode_get_parent(node));
 		return fdtdec_get_addr_size_fixed(gd->fdt_blob,
 						  ofnode_to_offset(node), "reg",
-						  index, na, ns, NULL, true);
+						  index, na, ns, size, true);
 	}
 
 	return FDT_ADDR_T_NONE;
 }
 
+fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
+{
+	fdt_size_t size;
+
+	return ofnode_get_addr_size_index(node, index, &size);
+}
+
 fdt_addr_t ofnode_get_addr(ofnode node)
 {
 	return ofnode_get_addr_index(node, 0);
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 8fa0966..aa5ca40 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -342,7 +342,7 @@
 {
 	int ret;
 
-	ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
+	ret = dm_scan_fdt(blob, pre_reloc_only);
 	if (ret) {
 		debug("dm_scan_fdt() failed: %d\n", ret);
 		return ret;
diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c
index 04a2381..2eb1547 100644
--- a/drivers/gpio/dwapb_gpio.c
+++ b/drivers/gpio/dwapb_gpio.c
@@ -185,12 +185,11 @@
 			plat->name = ofnode_get_name(node);
 		}
 
-		ret = device_bind(dev, dev->driver, plat->name,
-				  plat, -1, &subdev);
+		ret = device_bind_ofnode(dev, dev->driver, plat->name,
+					 plat, node, &subdev);
 		if (ret)
 			return ret;
 
-		dev->node = node;
 		bank++;
 	}
 
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index 3872364..50c4fd0 100644
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -500,7 +500,7 @@
 	af_delay_max = setup->analog_filter ?
 		       STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
 
-	sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
+	sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
 		     af_delay_min - (setup->dnf + 3) * i2cclk;
 
 	sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
@@ -540,8 +540,12 @@
 					p_prev = p;
 
 					list_add_tail(&v->node, solutions);
+					break;
 				}
 			}
+
+			if (p_prev == p)
+				break;
 		}
 	}
 
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 0e645f5..cb8b5c0 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -13,6 +13,24 @@
 	  set of generic read, write and ioctl methods may be used to
 	  access the device.
 
+config SPL_MISC
+	bool "Enable Driver Model for Misc drivers in SPL"
+	depends on SPL_DM
+	help
+	  Enable driver model for miscellaneous devices. This class is
+	  used only for those do not fit other more general classes. A
+	  set of generic read, write and ioctl methods may be used to
+	  access the device.
+
+config TPL_MISC
+	bool "Enable Driver Model for Misc drivers in TPL"
+	depends on TPL_DM
+	help
+	  Enable driver model for miscellaneous devices. This class is
+	  used only for those do not fit other more general classes. A
+	  set of generic read, write and ioctl methods may be used to
+	  access the device.
+
 config ALTERA_SYSID
 	bool "Altera Sysid support"
 	depends on MISC
@@ -68,6 +86,24 @@
 	  control access to the battery and main PMIC depending on the
 	  device. You can use the 'crosec' command to access it.
 
+config SPL_CROS_EC
+	bool "Enable Chrome OS EC in SPL"
+	help
+	  Enable access to the Chrome OS EC in SPL. This is a separate
+	  microcontroller typically available on a SPI bus on Chromebooks. It
+	  provides access to the keyboard, some internal storage and may
+	  control access to the battery and main PMIC depending on the
+	  device. You can use the 'crosec' command to access it.
+
+config TPL_CROS_EC
+	bool "Enable Chrome OS EC in TPL"
+	help
+	  Enable access to the Chrome OS EC in TPL. This is a separate
+	  microcontroller typically available on a SPI bus on Chromebooks. It
+	  provides access to the keyboard, some internal storage and may
+	  control access to the battery and main PMIC depending on the
+	  device. You can use the 'crosec' command to access it.
+
 config CROS_EC_I2C
 	bool "Enable Chrome OS EC I2C driver"
 	depends on CROS_EC
@@ -86,6 +122,24 @@
 	  through a legacy port interface, so on x86 machines the main
 	  function of the EC is power and thermal management.
 
+config SPL_CROS_EC_LPC
+	bool "Enable Chrome OS EC LPC driver in SPL"
+	depends on CROS_EC
+	help
+	  Enable I2C access to the Chrome OS EC. This is used on x86
+	  Chromebooks such as link and falco. The keyboard is provided
+	  through a legacy port interface, so on x86 machines the main
+	  function of the EC is power and thermal management.
+
+config TPL_CROS_EC_LPC
+	bool "Enable Chrome OS EC LPC driver in TPL"
+	depends on CROS_EC
+	help
+	  Enable I2C access to the Chrome OS EC. This is used on x86
+	  Chromebooks such as link and falco. The keyboard is provided
+	  through a legacy port interface, so on x86 machines the main
+	  function of the EC is power and thermal management.
+
 config CROS_EC_SANDBOX
 	bool "Enable Chrome OS EC sandbox driver"
 	depends on CROS_EC && SANDBOX
@@ -95,6 +149,24 @@
 	  EC flash read/write/erase support and a few other things. It is
 	  enough to perform a Chrome OS verified boot on sandbox.
 
+config SPL_CROS_EC_SANDBOX
+	bool "Enable Chrome OS EC sandbox driver in SPL"
+	depends on SPL_CROS_EC && SANDBOX
+	help
+	  Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
+	  keyboard (use the -l flag to enable the LCD), verified boot context,
+	  EC flash read/write/erase support and a few other things. It is
+	  enough to perform a Chrome OS verified boot on sandbox.
+
+config TPL_CROS_EC_SANDBOX
+	bool "Enable Chrome OS EC sandbox driver in TPL"
+	depends on TPL_CROS_EC && SANDBOX
+	help
+	  Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
+	  keyboard (use the -l flag to enable the LCD), verified boot context,
+	  EC flash read/write/erase support and a few other things. It is
+	  enough to perform a Chrome OS verified boot on sandbox.
+
 config CROS_EC_SPI
 	bool "Enable Chrome OS EC SPI driver"
 	depends on CROS_EC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 6bdf505..509c588 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -4,11 +4,13 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 obj-$(CONFIG_MISC) += misc-uclass.o
+
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC) += cros_ec.o
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o
+
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_CROS_EC) += cros_ec.o
-obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
 obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
-obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
 obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
 endif
 
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 377b267..672691f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -1435,7 +1435,9 @@
 #endif
 
 #if CONFIG_IS_ENABLED(DM_MMC)
+#ifndef CONFIG_PPC
 #include <asm/arch/clock.h>
+#endif
 __weak void init_clk_usdhc(u32 index)
 {
 }
@@ -1460,8 +1462,11 @@
 	addr = dev_read_addr(dev);
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
-
+#ifdef CONFIG_PPC
+	priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
+#else
 	priv->esdhc_regs = (struct fsl_esdhc *)addr;
+#endif
 	priv->dev = dev;
 	priv->mode = -1;
 	if (data) {
@@ -1568,7 +1573,11 @@
 
 		priv->sdhc_clk = clk_get_rate(&priv->per_clk);
 	} else {
+#ifndef CONFIG_PPC
 		priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+#else
+		priv->sdhc_clk = gd->arch.sdhc_clk;
+#endif
 		if (priv->sdhc_clk <= 0) {
 			dev_err(dev, "Unable to get clk for %s\n", dev->name);
 			return -EINVAL;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 64cdc58..e6a4fdf 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -195,6 +195,12 @@
 	  This driver supports the 10/100 Fast Ethernet controller for
 	  NXP i.MX processors.
 
+config FMAN_ENET
+	bool "Freescale FMan ethernet support"
+	depends on ARM || PPC
+	help
+	  This driver support the Freescale FMan Ethernet controller
+
 config FTMAC100
 	bool "Ftmac100 Ethernet Support"
 	help
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index e19d777..0a43dfe 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -459,7 +459,7 @@
 		printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
 			CONFIG_SYS_FMAN_FW_ADDR, rc);
 	}
-#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
 	struct spi_flash *ucode_flash;
 	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
 	int ret = 0;
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index bfc43fe..429bb83 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -113,6 +113,14 @@
 	  PCIe controllers. The PCIe may works in RC or EP mode according to
 	  RCW[HOST_AGT_PEX] setting.
 
+config PCIE_LAYERSCAPE_GEN4
+	bool "Layerscape Gen4 PCIe support"
+	depends on DM_PCI
+	help
+	  Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or
+	  several PCIe controllers. The PCIe controller can work in RC or
+	  EP mode according to RCW[HOST_AGT_PEX] setting.
+
 config PCIE_INTEL_FPGA
 	bool "Intel FPGA PCIe support"
 	depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index e551f20..bd392ed 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -33,5 +33,7 @@
 obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
+				pcie_layerscape_gen4_fixup.o
 obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
new file mode 100644
index 0000000..1fd8761
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -0,0 +1,572 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * PCIe Gen4 driver for NXP Layerscape SoCs
+ * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm.h>
+#include <linux/sizes.h>
+
+#include "pcie_layerscape_gen4.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+LIST_HEAD(ls_pcie_g4_list);
+
+static u64 bar_size[4] = {
+	PCIE_BAR0_SIZE,
+	PCIE_BAR1_SIZE,
+	PCIE_BAR2_SIZE,
+	PCIE_BAR4_SIZE
+};
+
+static int ls_pcie_g4_ltssm(struct ls_pcie_g4 *pcie)
+{
+	u32 state;
+
+	state = pf_ctrl_readl(pcie, PCIE_LTSSM_STA) & LTSSM_STATE_MASK;
+
+	return state;
+}
+
+static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie)
+{
+	int ltssm;
+
+	ltssm = ls_pcie_g4_ltssm(pcie);
+	if (ltssm != LTSSM_PCIE_L0)
+		return 0;
+
+	return 1;
+}
+
+static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie)
+{
+	ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY);
+}
+
+static void ls_pcie_g4_cfg_set_target(struct ls_pcie_g4 *pcie, u32 target)
+{
+	ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target);
+	ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0);
+}
+
+static int ls_pcie_g4_outbound_win_set(struct ls_pcie_g4 *pcie, int idx,
+				       int type, u64 phys, u64 bus_addr,
+				       pci_size_t size)
+{
+	u32 val;
+	u32 size_h, size_l;
+
+	if (idx >= PAB_WINS_NUM)
+		return -EINVAL;
+
+	size_h = upper_32_bits(~(size - 1));
+	size_l = lower_32_bits(~(size - 1));
+
+	val = ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
+	val &= ~((AXI_AMAP_CTRL_TYPE_MASK << AXI_AMAP_CTRL_TYPE_SHIFT) |
+		(AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT) |
+		AXI_AMAP_CTRL_EN);
+	val |= ((type & AXI_AMAP_CTRL_TYPE_MASK) << AXI_AMAP_CTRL_TYPE_SHIFT) |
+		((size_l >> AXI_AMAP_CTRL_SIZE_SHIFT) <<
+		AXI_AMAP_CTRL_SIZE_SHIFT) | AXI_AMAP_CTRL_EN;
+
+	ccsr_writel(pcie, PAB_AXI_AMAP_CTRL(idx), val);
+
+	ccsr_writel(pcie, PAB_AXI_AMAP_AXI_WIN(idx), lower_32_bits(phys));
+	ccsr_writel(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(idx), upper_32_bits(phys));
+	ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
+	ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
+	ccsr_writel(pcie, PAB_EXT_AXI_AMAP_SIZE(idx), size_h);
+
+	return 0;
+}
+
+static int ls_pcie_g4_rc_inbound_win_set(struct ls_pcie_g4 *pcie, int idx,
+					 int type, u64 phys, u64 bus_addr,
+					 pci_size_t size)
+{
+	u32 val;
+	pci_size_t win_size = ~(size - 1);
+
+	val = ccsr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
+
+	val &= ~(PEX_AMAP_CTRL_TYPE_MASK << PEX_AMAP_CTRL_TYPE_SHIFT);
+	val &= ~(PEX_AMAP_CTRL_EN_MASK << PEX_AMAP_CTRL_EN_SHIFT);
+	val = (val | (type << PEX_AMAP_CTRL_TYPE_SHIFT));
+	val = (val | (1 << PEX_AMAP_CTRL_EN_SHIFT));
+
+	ccsr_writel(pcie, PAB_PEX_AMAP_CTRL(idx),
+		    val | lower_32_bits(win_size));
+
+	ccsr_writel(pcie, PAB_EXT_PEX_AMAP_SIZE(idx), upper_32_bits(win_size));
+	ccsr_writel(pcie, PAB_PEX_AMAP_AXI_WIN(idx), lower_32_bits(phys));
+	ccsr_writel(pcie, PAB_EXT_PEX_AMAP_AXI_WIN(idx), upper_32_bits(phys));
+	ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
+	ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
+
+	return 0;
+}
+
+static void ls_pcie_g4_dump_wins(struct ls_pcie_g4 *pcie, int wins)
+{
+	int i;
+
+	for (i = 0; i < wins; i++) {
+		debug("APIO Win%d:\n", i);
+		debug("\tLOWER PHYS:	0x%08x\n",
+		      ccsr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(i)));
+		debug("\tUPPER PHYS:	0x%08x\n",
+		      ccsr_readl(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(i)));
+		debug("\tLOWER BUS:	0x%08x\n",
+		      ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_L(i)));
+		debug("\tUPPER BUS:	0x%08x\n",
+		      ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(i)));
+		debug("\tSIZE:		0x%08x\n",
+		      ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)) &
+		      (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT));
+		debug("\tEXT_SIZE:	0x%08x\n",
+		      ccsr_readl(pcie, PAB_EXT_AXI_AMAP_SIZE(i)));
+		debug("\tPARAM:		0x%08x\n",
+		      ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(i)));
+		debug("\tCTRL:		0x%08x\n",
+		      ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)));
+	}
+}
+
+static void ls_pcie_g4_setup_wins(struct ls_pcie_g4 *pcie)
+{
+	struct pci_region *io, *mem, *pref;
+	int idx = 1;
+
+	/* INBOUND WIN */
+	ls_pcie_g4_rc_inbound_win_set(pcie, 0, IB_TYPE_MEM_F, 0, 0, SIZE_1T);
+
+	/* OUTBOUND WIN 0: CFG */
+	ls_pcie_g4_outbound_win_set(pcie, 0, PAB_AXI_TYPE_CFG,
+				    pcie->cfg_res.start, 0,
+				    fdt_resource_size(&pcie->cfg_res));
+
+	pci_get_regions(pcie->bus, &io, &mem, &pref);
+
+	if (io)
+		/* OUTBOUND WIN: IO */
+		ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_IO,
+					    io->phys_start, io->bus_start,
+					    io->size);
+
+	if (mem)
+		/* OUTBOUND WIN: MEM */
+		ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
+					    mem->phys_start, mem->bus_start,
+					    mem->size);
+
+	if (pref)
+		/* OUTBOUND WIN: perf MEM */
+		ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
+					    pref->phys_start, pref->bus_start,
+					    pref->size);
+
+	ls_pcie_g4_dump_wins(pcie, idx);
+}
+
+/* Return 0 if the address is valid, -errno if not valid */
+static int ls_pcie_g4_addr_valid(struct ls_pcie_g4 *pcie, pci_dev_t bdf)
+{
+	struct udevice *bus = pcie->bus;
+
+	if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+		return -ENODEV;
+
+	if (!pcie->enabled)
+		return -ENXIO;
+
+	if (PCI_BUS(bdf) < bus->seq)
+		return -EINVAL;
+
+	if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_g4_link_up(pcie)))
+		return -EINVAL;
+
+	if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
+		return -EINVAL;
+
+	return 0;
+}
+
+void *ls_pcie_g4_conf_address(struct ls_pcie_g4 *pcie, pci_dev_t bdf,
+			      int offset)
+{
+	struct udevice *bus = pcie->bus;
+	u32 target;
+
+	if (PCI_BUS(bdf) == bus->seq) {
+		if (offset < INDIRECT_ADDR_BNDRY) {
+			ccsr_set_page(pcie, 0);
+			return pcie->ccsr + offset;
+		}
+
+		ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
+		return pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset);
+	}
+
+	target = PAB_TARGET_BUS(PCI_BUS(bdf) - bus->seq) |
+		 PAB_TARGET_DEV(PCI_DEV(bdf)) |
+		 PAB_TARGET_FUNC(PCI_FUNC(bdf));
+
+	ls_pcie_g4_cfg_set_target(pcie, target);
+
+	return pcie->cfg + offset;
+}
+
+static int ls_pcie_g4_read_config(struct udevice *bus, pci_dev_t bdf,
+				  uint offset, ulong *valuep,
+				  enum pci_size_t size)
+{
+	struct ls_pcie_g4 *pcie = dev_get_priv(bus);
+	void *address;
+	int ret = 0;
+
+	if (ls_pcie_g4_addr_valid(pcie, bdf)) {
+		*valuep = pci_get_ff(size);
+		return 0;
+	}
+
+	address = ls_pcie_g4_conf_address(pcie, bdf, offset);
+
+	switch (size) {
+	case PCI_SIZE_8:
+		*valuep = readb(address);
+		break;
+	case PCI_SIZE_16:
+		*valuep = readw(address);
+		break;
+	case PCI_SIZE_32:
+		*valuep = readl(address);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static int ls_pcie_g4_write_config(struct udevice *bus, pci_dev_t bdf,
+				   uint offset, ulong value,
+				   enum pci_size_t size)
+{
+	struct ls_pcie_g4 *pcie = dev_get_priv(bus);
+	void *address;
+
+	if (ls_pcie_g4_addr_valid(pcie, bdf))
+		return 0;
+
+	address = ls_pcie_g4_conf_address(pcie, bdf, offset);
+
+	switch (size) {
+	case PCI_SIZE_8:
+		writeb(value, address);
+		return 0;
+	case PCI_SIZE_16:
+		writew(value, address);
+		return 0;
+	case PCI_SIZE_32:
+		writel(value, address);
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie)
+{
+	u32 val;
+
+	/* Fix class code */
+	val = ccsr_readl(pcie, GPEX_CLASSCODE);
+	val &= ~(GPEX_CLASSCODE_MASK << GPEX_CLASSCODE_SHIFT);
+	val |= PCI_CLASS_BRIDGE_PCI << GPEX_CLASSCODE_SHIFT;
+	ccsr_writel(pcie, GPEX_CLASSCODE, val);
+
+	/* Enable APIO and Memory/IO/CFG Wins */
+	val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
+	val |= APIO_EN | MEM_WIN_EN | IO_WIN_EN | CFG_WIN_EN;
+	ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
+
+	ls_pcie_g4_setup_wins(pcie);
+
+	pcie->stream_id_cur = 0;
+}
+
+static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf,
+					  int bar, u64 phys)
+{
+	u32 val;
+
+	/* PF BAR1 is for MSI-X and only need to enable */
+	if (bar == 1) {
+		ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), BAR_AMAP_EN);
+		return;
+	}
+
+	val = upper_32_bits(phys);
+	ccsr_writel(pcie, PAB_EXT_PEX_BAR_AMAP(pf, bar), val);
+	val = lower_32_bits(phys) | BAR_AMAP_EN;
+	ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), val);
+}
+
+static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)
+{
+	u64 phys;
+	int bar;
+	u32 val;
+
+	if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1)
+		return;
+
+	phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
+	for (bar = 0; bar < PF_BAR_NUM; bar++) {
+		ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys);
+		phys += PCIE_BAR_SIZE;
+	}
+
+	/* OUTBOUND: map MEM */
+	ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM,
+				    pcie->cfg_res.start +
+				    CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
+				    CONFIG_SYS_PCI_MEMORY_SIZE);
+
+	val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf));
+	val &= ~FUNC_NUM_PCIE_MASK;
+	val |= pf;
+	ccsr_writel(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf), val);
+}
+
+static void ls_pcie_g4_ep_enable_bar(struct ls_pcie_g4 *pcie, int pf,
+				     int bar, bool vf_bar, bool enable)
+{
+	u32 val;
+	u32 bar_pos = BAR_POS(bar, pf, vf_bar);
+
+	val = ccsr_readl(pcie, GPEX_BAR_ENABLE);
+	if (enable)
+		val |= 1 << bar_pos;
+	else
+		val &= ~(1 << bar_pos);
+	ccsr_writel(pcie, GPEX_BAR_ENABLE, val);
+}
+
+static void ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4 *pcie, int pf,
+				       int bar, bool vf_bar, u64 size)
+{
+	u32 bar_pos = BAR_POS(bar, pf, vf_bar);
+	u32 mask_l = lower_32_bits(~(size - 1));
+	u32 mask_h = upper_32_bits(~(size - 1));
+
+	ccsr_writel(pcie, GPEX_BAR_SELECT, bar_pos);
+	ccsr_writel(pcie, GPEX_BAR_SIZE_LDW, mask_l);
+	ccsr_writel(pcie, GPEX_BAR_SIZE_UDW, mask_h);
+}
+
+static void ls_pcie_g4_ep_setup_bar(struct ls_pcie_g4 *pcie, int pf,
+				    int bar, bool vf_bar, u64 size)
+{
+	bool en = size ? true : false;
+
+	ls_pcie_g4_ep_enable_bar(pcie, pf, bar, vf_bar, en);
+	ls_pcie_g4_ep_set_bar_size(pcie, pf, bar, vf_bar, size);
+}
+
+static void ls_pcie_g4_ep_setup_bars(struct ls_pcie_g4 *pcie, int pf)
+{
+	int bar;
+
+	/* Setup PF BARs */
+	for (bar = 0; bar < PF_BAR_NUM; bar++)
+		ls_pcie_g4_ep_setup_bar(pcie, pf, bar, false, bar_size[bar]);
+
+	if (!pcie->sriov_support)
+		return;
+
+	/* Setup VF BARs */
+	for (bar = 0; bar < VF_BAR_NUM; bar++)
+		ls_pcie_g4_ep_setup_bar(pcie, pf, bar, true, bar_size[bar]);
+}
+
+static void ls_pcie_g4_set_sriov(struct ls_pcie_g4 *pcie, int pf)
+{
+	unsigned int val;
+
+	val =  ccsr_readl(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf));
+	val &= ~(TTL_VF_MASK << TTL_VF_SHIFT);
+	val |= PCIE_VF_NUM << TTL_VF_SHIFT;
+	val &= ~(INI_VF_MASK << INI_VF_SHIFT);
+	val |= PCIE_VF_NUM << INI_VF_SHIFT;
+	ccsr_writel(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf), val);
+
+	val =  ccsr_readl(pcie, PCIE_SRIOV_VF_OFFSET_STRIDE);
+	val += PCIE_VF_NUM * pf - pf;
+	ccsr_writel(pcie, GPEX_SRIOV_VF_OFFSET_STRIDE(pf), val);
+}
+
+static void ls_pcie_g4_setup_ep(struct ls_pcie_g4 *pcie)
+{
+	u32 pf, sriov;
+	u32 val;
+	int i;
+
+	/* Enable APIO and Memory Win */
+	val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
+	val |= APIO_EN | MEM_WIN_EN;
+	ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
+
+	sriov = ccsr_readl(pcie, PCIE_SRIOV_CAPABILITY);
+	if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
+		pcie->sriov_support = 1;
+
+	pf = pcie->sriov_support ? PCIE_PF_NUM : 1;
+
+	for (i = 0; i < pf; i++) {
+		ls_pcie_g4_ep_setup_bars(pcie, i);
+		ls_pcie_g4_ep_setup_wins(pcie, i);
+		if (pcie->sriov_support)
+			ls_pcie_g4_set_sriov(pcie, i);
+	}
+
+	ls_pcie_g4_ep_enable_cfg(pcie);
+	ls_pcie_g4_dump_wins(pcie, pf);
+}
+
+static int ls_pcie_g4_probe(struct udevice *dev)
+{
+	struct ls_pcie_g4 *pcie = dev_get_priv(dev);
+	const void *fdt = gd->fdt_blob;
+	int node = dev_of_offset(dev);
+	u32 link_ctrl_sta;
+	u32 val;
+	int ret;
+
+	pcie->bus = dev;
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "ccsr", &pcie->ccsr_res);
+	if (ret) {
+		printf("ls-pcie-g4: resource \"ccsr\" not found\n");
+		return ret;
+	}
+
+	pcie->idx = (pcie->ccsr_res.start - PCIE_SYS_BASE_ADDR) /
+		    PCIE_CCSR_SIZE;
+
+	list_add(&pcie->list, &ls_pcie_g4_list);
+
+	pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
+	if (!pcie->enabled) {
+		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+		return 0;
+	}
+
+	pcie->ccsr = map_physmem(pcie->ccsr_res.start,
+				 fdt_resource_size(&pcie->ccsr_res),
+				 MAP_NOCACHE);
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "config", &pcie->cfg_res);
+	if (ret) {
+		printf("%s: resource \"config\" not found\n", dev->name);
+		return ret;
+	}
+
+	pcie->cfg = map_physmem(pcie->cfg_res.start,
+				fdt_resource_size(&pcie->cfg_res),
+				MAP_NOCACHE);
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "lut", &pcie->lut_res);
+	if (ret) {
+		printf("ls-pcie-g4: resource \"lut\" not found\n");
+		return ret;
+	}
+
+	pcie->lut = map_physmem(pcie->lut_res.start,
+				fdt_resource_size(&pcie->lut_res),
+				MAP_NOCACHE);
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "pf_ctrl", &pcie->pf_ctrl_res);
+	if (ret) {
+		printf("ls-pcie-g4: resource \"pf_ctrl\" not found\n");
+		return ret;
+	}
+
+	pcie->pf_ctrl = map_physmem(pcie->pf_ctrl_res.start,
+				    fdt_resource_size(&pcie->pf_ctrl_res),
+				    MAP_NOCACHE);
+
+	pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
+
+	debug("%s ccsr:%lx, cfg:0x%lx, big-endian:%d\n",
+	      dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg,
+	      pcie->big_endian);
+
+	pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
+
+	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
+		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+		ls_pcie_g4_setup_ep(pcie);
+	} else {
+		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+		ls_pcie_g4_setup_ctrl(pcie);
+	}
+
+	/* Enable Amba & PEX PIO */
+	val = ccsr_readl(pcie, PAB_CTRL);
+	val |= PAB_CTRL_APIO_EN | PAB_CTRL_PPIO_EN;
+	ccsr_writel(pcie, PAB_CTRL, val);
+
+	val = ccsr_readl(pcie, PAB_PEX_PIO_CTRL(0));
+	val |= PPIO_EN;
+	ccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val);
+
+	if (!ls_pcie_g4_link_up(pcie)) {
+		/* Let the user know there's no PCIe link */
+		printf(": no link\n");
+		return 0;
+	}
+
+	/* Print the negotiated PCIe link width */
+	link_ctrl_sta = ccsr_readl(pcie, PCIE_LINK_CTRL_STA);
+	printf(": x%d gen%d\n",
+	       (link_ctrl_sta >> PCIE_LINK_WIDTH_SHIFT & PCIE_LINK_WIDTH_MASK),
+	       (link_ctrl_sta >> PCIE_LINK_SPEED_SHIFT) & PCIE_LINK_SPEED_MASK);
+
+	return 0;
+}
+
+static const struct dm_pci_ops ls_pcie_g4_ops = {
+	.read_config	= ls_pcie_g4_read_config,
+	.write_config	= ls_pcie_g4_write_config,
+};
+
+static const struct udevice_id ls_pcie_g4_ids[] = {
+	{ .compatible = "fsl,lx2160a-pcie" },
+	{ }
+};
+
+U_BOOT_DRIVER(pcie_layerscape_gen4) = {
+	.name = "pcie_layerscape_gen4",
+	.id = UCLASS_PCI,
+	.of_match = ls_pcie_g4_ids,
+	.ops = &ls_pcie_g4_ops,
+	.probe	= ls_pcie_g4_probe,
+	.priv_auto_alloc_size = sizeof(struct ls_pcie_g4),
+};
diff --git a/drivers/pci/pcie_layerscape_gen4.h b/drivers/pci/pcie_layerscape_gen4.h
new file mode 100644
index 0000000..27c2d09
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_gen4.h
@@ -0,0 +1,264 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * PCIe Gen4 driver for NXP Layerscape SoCs
+ * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
+ */
+
+#ifndef _PCIE_LAYERSCAPE_GEN4_H_
+#define _PCIE_LAYERSCAPE_GEN4_H_
+#include <pci.h>
+#include <dm.h>
+
+#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
+#define CONFIG_SYS_PCI_MEMORY_SIZE		(4 * 1024 * 1024 * 1024ULL)
+#endif
+
+#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
+#define CONFIG_SYS_PCI_EP_MEMORY_BASE		CONFIG_SYS_LOAD_ADDR
+#endif
+
+#define PCIE_PF_NUM				2
+#define PCIE_VF_NUM				32
+
+#define LS_G4_PF0				0
+#define LS_G4_PF1				1
+#define PF_BAR_NUM				4
+#define VF_BAR_NUM				4
+#define PCIE_BAR_SIZE				(8 * 1024)		/* 8K */
+#define PCIE_BAR0_SIZE				PCIE_BAR_SIZE
+#define PCIE_BAR1_SIZE				PCIE_BAR_SIZE
+#define PCIE_BAR2_SIZE				PCIE_BAR_SIZE
+#define PCIE_BAR4_SIZE				PCIE_BAR_SIZE
+#define SIZE_1T					(1024 * 1024 * 1024 * 1024ULL)
+
+/* GPEX CSR */
+#define GPEX_CLASSCODE				0x474
+#define GPEX_CLASSCODE_SHIFT			16
+#define GPEX_CLASSCODE_MASK			0xffff
+
+#define GPEX_CFG_READY				0x4b0
+#define PCIE_CONFIG_READY			BIT(0)
+
+#define GPEX_BAR_ENABLE				0x4d4
+#define GPEX_BAR_SIZE_LDW			0x4d8
+#define GPEX_BAR_SIZE_UDW			0x4dC
+#define GPEX_BAR_SELECT				0x4e0
+
+#define BAR_POS(bar, pf, vf_bar)		\
+	((bar) + (pf) * PF_BAR_NUM + (vf_bar) * PCIE_PF_NUM * PF_BAR_NUM)
+
+#define GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf)	(0x644 + (pf) * 4)
+#define TTL_VF_MASK				0xffff
+#define TTL_VF_SHIFT				16
+#define INI_VF_MASK				0xffff
+#define INI_VF_SHIFT				0
+#define GPEX_SRIOV_VF_OFFSET_STRIDE(pf)		(0x704 + (pf) * 4)
+
+/* PAB CSR */
+#define PAB_CTRL				0x808
+#define PAB_CTRL_APIO_EN			BIT(0)
+#define PAB_CTRL_PPIO_EN			BIT(1)
+#define PAB_CTRL_MAX_BRST_LEN_SHIFT		4
+#define PAB_CTRL_MAX_BRST_LEN_MASK		0x3
+#define PAB_CTRL_PAGE_SEL_SHIFT			13
+#define PAB_CTRL_PAGE_SEL_MASK			0x3f
+#define PAB_CTRL_FUNC_SEL_SHIFT			19
+#define PAB_CTRL_FUNC_SEL_MASK			0x1ff
+
+#define PAB_RST_CTRL				0x820
+#define PAB_BR_STAT				0x80c
+
+/* AXI PIO Engines */
+#define PAB_AXI_PIO_CTRL(idx)			(0x840 + 0x10 * (idx))
+#define APIO_EN					BIT(0)
+#define MEM_WIN_EN				BIT(1)
+#define IO_WIN_EN				BIT(2)
+#define CFG_WIN_EN				BIT(3)
+#define PAB_AXI_PIO_STAT(idx)			(0x844 + 0x10 * (idx))
+#define PAB_AXI_PIO_SL_CMD_STAT(idx)		(0x848 + 0x10 * (idx))
+#define PAB_AXI_PIO_SL_ADDR_STAT(idx)		(0x84c + 0x10 * (idx))
+#define PAB_AXI_PIO_SL_EXT_ADDR_STAT(idx)	(0xb8a0 + 0x4 * (idx))
+
+/* PEX PIO Engines */
+#define PAB_PEX_PIO_CTRL(idx)			(0x8c0 + 0x10 * (idx))
+#define PPIO_EN					BIT(0)
+#define PAB_PEX_PIO_STAT(idx)			(0x8c4 + 0x10 * (idx))
+#define PAB_PEX_PIO_MT_STAT(idx)		(0x8c8 + 0x10 * (idx))
+
+#define INDIRECT_ADDR_BNDRY			0xc00
+#define PAGE_IDX_SHIFT				10
+#define PAGE_ADDR_MASK				0x3ff
+
+#define OFFSET_TO_PAGE_IDX(off)			\
+	(((off) >> PAGE_IDX_SHIFT) & PAB_CTRL_PAGE_SEL_MASK)
+
+#define OFFSET_TO_PAGE_ADDR(off)		\
+	(((off) & PAGE_ADDR_MASK) | INDIRECT_ADDR_BNDRY)
+
+/* APIO WINs */
+#define PAB_AXI_AMAP_CTRL(idx)			(0xba0 + 0x10 * (idx))
+#define PAB_EXT_AXI_AMAP_SIZE(idx)		(0xbaf0 + 0x4 * (idx))
+#define PAB_AXI_AMAP_AXI_WIN(idx)		(0xba4 + 0x10 * (idx))
+#define PAB_EXT_AXI_AMAP_AXI_WIN(idx)		(0x80a0 + 0x4 * (idx))
+#define PAB_AXI_AMAP_PEX_WIN_L(idx)		(0xba8 + 0x10 * (idx))
+#define PAB_AXI_AMAP_PEX_WIN_H(idx)		(0xbac + 0x10 * (idx))
+#define PAB_AXI_AMAP_PCI_HDR_PARAM(idx)		(0x5ba0 + 0x4 * (idx))
+#define FUNC_NUM_PCIE_MASK			GENMASK(7, 0)
+
+#define AXI_AMAP_CTRL_EN			BIT(0)
+#define AXI_AMAP_CTRL_TYPE_SHIFT		1
+#define AXI_AMAP_CTRL_TYPE_MASK			0x3
+#define AXI_AMAP_CTRL_SIZE_SHIFT		10
+#define AXI_AMAP_CTRL_SIZE_MASK			0x3fffff
+
+#define PAB_TARGET_BUS(x)			(((x) & 0xff) << 24)
+#define PAB_TARGET_DEV(x)			(((x) & 0x1f) << 19)
+#define PAB_TARGET_FUNC(x)			(((x) & 0x7) << 16)
+
+#define PAB_AXI_TYPE_CFG			0x00
+#define PAB_AXI_TYPE_IO				0x01
+#define PAB_AXI_TYPE_MEM			0x02
+#define PAB_AXI_TYPE_ATOM			0x03
+
+#define PAB_WINS_NUM				256
+
+/* PPIO WINs RC mode */
+#define PAB_PEX_AMAP_CTRL(idx)			(0x4ba0 + 0x10 * (idx))
+#define PAB_EXT_PEX_AMAP_SIZE(idx)		(0xbef0 + 0x04 * (idx))
+#define PAB_PEX_AMAP_AXI_WIN(idx)		(0x4ba4 + 0x10 * (idx))
+#define PAB_EXT_PEX_AMAP_AXI_WIN(idx)		(0xb4a0 + 0x04 * (idx))
+#define PAB_PEX_AMAP_PEX_WIN_L(idx)		(0x4ba8 + 0x10 * (idx))
+#define PAB_PEX_AMAP_PEX_WIN_H(idx)		(0x4bac + 0x10 * (idx))
+
+#define IB_TYPE_MEM_F				0x2
+#define IB_TYPE_MEM_NF				0x3
+
+#define PEX_AMAP_CTRL_TYPE_SHIFT		0x1
+#define PEX_AMAP_CTRL_EN_SHIFT			0x0
+#define PEX_AMAP_CTRL_TYPE_MASK			0x3
+#define PEX_AMAP_CTRL_EN_MASK			0x1
+
+/* PPIO WINs EP mode */
+#define PAB_PEX_BAR_AMAP(pf, bar)		\
+	(0x1ba0 + 0x20 * (pf) + 4 * (bar))
+#define BAR_AMAP_EN				BIT(0)
+#define PAB_EXT_PEX_BAR_AMAP(pf, bar)		\
+	(0x84a0 + 0x20 * (pf) + 4 * (bar))
+
+/* CCSR registers */
+#define PCIE_LINK_CTRL_STA			0x5c
+#define PCIE_LINK_SPEED_SHIFT			16
+#define PCIE_LINK_SPEED_MASK			0x0f
+#define PCIE_LINK_WIDTH_SHIFT			20
+#define PCIE_LINK_WIDTH_MASK			0x3f
+#define PCIE_SRIOV_CAPABILITY			0x2a0
+#define PCIE_SRIOV_VF_OFFSET_STRIDE		0x2b4
+
+/* LUT registers */
+#define PCIE_LUT_UDR(n)				(0x800 + (n) * 8)
+#define PCIE_LUT_LDR(n)				(0x804 + (n) * 8)
+#define PCIE_LUT_ENABLE				BIT(31)
+#define PCIE_LUT_ENTRY_COUNT			32
+
+/* PF control registers */
+#define PCIE_LTSSM_STA				0x7fc
+#define LTSSM_STATE_MASK			0x7f
+#define LTSSM_PCIE_L0				0x2d /* L0 state */
+
+#define PCIE_SRDS_PRTCL(idx)			(PCIE1 + (idx))
+#define PCIE_SYS_BASE_ADDR			0x3400000
+#define PCIE_CCSR_SIZE				0x0100000
+
+struct ls_pcie_g4 {
+	int idx;
+	struct list_head list;
+	struct udevice *bus;
+	struct fdt_resource ccsr_res;
+	struct fdt_resource cfg_res;
+	struct fdt_resource lut_res;
+	struct fdt_resource pf_ctrl_res;
+	void __iomem *ccsr;
+	void __iomem *cfg;
+	void __iomem *lut;
+	void __iomem *pf_ctrl;
+	bool big_endian;
+	bool enabled;
+	int next_lut_index;
+	struct pci_controller hose;
+	int stream_id_cur;
+	int mode;
+	int sriov_support;
+};
+
+extern struct list_head ls_pcie_g4_list;
+
+static inline void lut_writel(struct ls_pcie_g4 *pcie, unsigned int value,
+			      unsigned int offset)
+{
+	if (pcie->big_endian)
+		out_be32(pcie->lut + offset, value);
+	else
+		out_le32(pcie->lut + offset, value);
+}
+
+static inline u32 lut_readl(struct ls_pcie_g4 *pcie, unsigned int offset)
+{
+	if (pcie->big_endian)
+		return in_be32(pcie->lut + offset);
+	else
+		return in_le32(pcie->lut + offset);
+}
+
+static inline void ccsr_set_page(struct ls_pcie_g4 *pcie, u8 pg_idx)
+{
+	u32 val;
+
+	val = in_le32(pcie->ccsr + PAB_CTRL);
+	val &= ~(PAB_CTRL_PAGE_SEL_MASK << PAB_CTRL_PAGE_SEL_SHIFT);
+	val |= (pg_idx & PAB_CTRL_PAGE_SEL_MASK) << PAB_CTRL_PAGE_SEL_SHIFT;
+
+	out_le32(pcie->ccsr + PAB_CTRL, val);
+}
+
+static inline unsigned int ccsr_readl(struct ls_pcie_g4 *pcie, u32 offset)
+{
+	if (offset < INDIRECT_ADDR_BNDRY) {
+		ccsr_set_page(pcie, 0);
+		return in_le32(pcie->ccsr + offset);
+	}
+
+	ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
+	return in_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset));
+}
+
+static inline void ccsr_writel(struct ls_pcie_g4 *pcie, u32 offset, u32 value)
+{
+	if (offset < INDIRECT_ADDR_BNDRY) {
+		ccsr_set_page(pcie, 0);
+		out_le32(pcie->ccsr + offset, value);
+	} else {
+		ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
+		out_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset), value);
+	}
+}
+
+static inline unsigned int pf_ctrl_readl(struct ls_pcie_g4 *pcie, u32 offset)
+{
+	if (pcie->big_endian)
+		return in_be32(pcie->pf_ctrl + offset);
+	else
+		return in_le32(pcie->pf_ctrl + offset);
+}
+
+static inline void pf_ctrl_writel(struct ls_pcie_g4 *pcie, u32 offset,
+				  u32 value)
+{
+	if (pcie->big_endian)
+		out_be32(pcie->pf_ctrl + offset, value);
+	else
+		out_le32(pcie->pf_ctrl + offset, value);
+}
+
+#endif /* _PCIE_LAYERSCAPE_GEN4_H_ */
diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c
new file mode 100644
index 0000000..1c9e575
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * PCIe Gen4 driver for NXP Layerscape SoCs
+ * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/io.h>
+#include <errno.h>
+#ifdef CONFIG_OF_BOARD_SETUP
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#ifdef CONFIG_ARM
+#include <asm/arch/clock.h>
+#endif
+#include "pcie_layerscape_gen4.h"
+
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+/*
+ * Return next available LUT index.
+ */
+static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
+{
+	if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
+		return pcie->next_lut_index++;
+
+	return -ENOSPC;  /* LUT is full */
+}
+
+/* returns the next available streamid for pcie, -errno if failed */
+static int ls_pcie_g4_next_streamid(struct ls_pcie_g4 *pcie)
+{
+	int stream_id = pcie->stream_id_cur;
+
+	if (stream_id > FSL_PEX_STREAM_ID_NUM)
+		return -EINVAL;
+
+	pcie->stream_id_cur++;
+
+	return stream_id | ((pcie->idx + 1) << 11);
+}
+
+/*
+ * Program a single LUT entry
+ */
+static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
+				       u32 devid, u32 streamid)
+{
+	/* leave mask as all zeroes, want to match all bits */
+	lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
+	lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
+}
+
+/*
+ * An msi-map is a property to be added to the pci controller
+ * node.  It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ *      msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
+ *                 [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie_g4 *pcie,
+				       u32 devid, u32 streamid)
+{
+	u32 *prop;
+	u32 phandle;
+	int nodeoff;
+
+#ifdef CONFIG_FSL_PCIE_COMPAT
+	nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
+						pcie->ccsr_res.start);
+#else
+#error "No CONFIG_FSL_PCIE_COMPAT defined"
+#endif
+	if (nodeoff < 0) {
+		debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
+		return;
+	}
+
+	/* get phandle to MSI controller */
+	prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0);
+	if (!prop) {
+		debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
+		      __func__, pcie->idx);
+		return;
+	}
+	phandle = fdt32_to_cpu(*prop);
+
+	/* set one msi-map row */
+	fdt_appendprop_u32(blob, nodeoff, "msi-map", devid);
+	fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle);
+	fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid);
+	fdt_appendprop_u32(blob, nodeoff, "msi-map", 1);
+}
+
+/*
+ * An iommu-map is a property to be added to the pci controller
+ * node.  It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ *      iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
+ *                 [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie_g4 *pcie,
+					 u32 devid, u32 streamid)
+{
+	u32 *prop;
+	u32 iommu_map[4];
+	int nodeoff;
+	int lenp;
+
+#ifdef CONFIG_FSL_PCIE_COMPAT
+	nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
+						pcie->ccsr_res.start);
+#else
+#error "No CONFIG_FSL_PCIE_COMPAT defined"
+#endif
+	if (nodeoff < 0) {
+		debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
+		return;
+	}
+
+	/* get phandle to iommu controller */
+	prop = fdt_getprop_w(blob, nodeoff, "iommu-map", &lenp);
+	if (!prop) {
+		debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
+		      __func__, pcie->idx);
+		return;
+	}
+
+	/* set iommu-map row */
+	iommu_map[0] = cpu_to_fdt32(devid);
+	iommu_map[1] = *++prop;
+	iommu_map[2] = cpu_to_fdt32(streamid);
+	iommu_map[3] = cpu_to_fdt32(1);
+
+	if (devid == 0)
+		fdt_setprop_inplace(blob, nodeoff, "iommu-map", iommu_map, 16);
+	else
+		fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16);
+}
+
+static void fdt_fixup_pcie(void *blob)
+{
+	struct udevice *dev, *bus;
+	struct ls_pcie_g4 *pcie;
+	int streamid;
+	int index;
+	pci_dev_t bdf;
+
+	/* Scan all known buses */
+	for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {
+		for (bus = dev; device_is_on_pci_bus(bus);)
+			bus = bus->parent;
+		pcie = dev_get_priv(bus);
+
+		streamid = ls_pcie_g4_next_streamid(pcie);
+		if (streamid < 0) {
+			debug("ERROR: no stream ids free\n");
+			continue;
+		}
+
+		index = ls_pcie_g4_next_lut_index(pcie);
+		if (index < 0) {
+			debug("ERROR: no LUT indexes free\n");
+			continue;
+		}
+
+		/* the DT fixup must be relative to the hose first_busno */
+		bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
+		/* map PCI b.d.f to streamID in LUT */
+		ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);
+		/* update msi-map in device tree */
+		fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, streamid);
+		/* update iommu-map in device tree */
+		fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8, streamid);
+	}
+}
+#endif
+
+static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
+{
+	int off;
+
+	off = fdt_node_offset_by_compat_reg(blob, "fsl,lx2160a-pcie-ep",
+					    pcie->ccsr_res.start);
+
+	if (off < 0) {
+		debug("%s: ERROR: failed to find pcie compatiable\n",
+		      __func__);
+		return;
+	}
+
+	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
+		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+	else
+		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
+{
+	int off;
+
+#ifdef CONFIG_FSL_PCIE_COMPAT
+	off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
+					    pcie->ccsr_res.start);
+#else
+#error "No CONFIG_FSL_PCIE_COMPAT defined"
+#endif
+	if (off < 0) {
+		debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
+		return;
+	}
+
+	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
+		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+	else
+		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
+{
+	ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
+	ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
+}
+
+/* Fixup Kernel DT for PCIe */
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+	struct ls_pcie_g4 *pcie;
+
+	list_for_each_entry(pcie, &ls_pcie_g4_list, list)
+		ft_pcie_layerscape_gen4_setup(blob, pcie);
+
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+	fdt_fixup_pcie(blob);
+#endif
+}
+
+#else /* !CONFIG_OF_BOARD_SETUP */
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+}
+#endif
diff --git a/drivers/qe/Kconfig b/drivers/qe/Kconfig
index 49a6e32..864b36b 100644
--- a/drivers/qe/Kconfig
+++ b/drivers/qe/Kconfig
@@ -1,6 +1,14 @@
 #
 # QUICC Engine Drivers
 #
+config QE
+	bool "Enable support for QUICC Engine"
+	depends on PPC
+	default y if ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || ARCH_P1021 \
+		|| ARCH_P1025
+	help
+	  Chose this option to add support for the QUICC Engine.
+
 config U_QE
 	bool "Enable support for U QUICC Engine"
 	default y if (ARCH_LS1021A && !SD_BOOT && !NAND_BOOT && !QSPI_BOOT) \
@@ -10,3 +18,28 @@
 		|| (TARGET_LS1043ARDB && !SPL_NO_QE && !NAND_BOOT && !QSPI_BOOT)
 	help
 	  Choose this option to add support for U QUICC Engine.
+
+choice
+	prompt "QUICC Engine FMan ethernet firmware location"
+	depends on FMAN_ENET || QE
+	default SYS_QE_FMAN_FW_IN_ROM
+
+config SYS_QE_FMAN_FW_IN_NOR
+	bool "NOR flash"
+
+config SYS_QE_FMAN_FW_IN_NAND
+	bool "NAND flash"
+
+config SYS_QE_FMAN_FW_IN_SPIFLASH
+	bool "SPI flash"
+
+config SYS_QE_FMAN_FW_IN_MMC
+	bool "MMC"
+
+config SYS_QE_FMAN_FW_IN_REMOTE
+	bool "Remote memory location (PCI)"
+
+config SYS_QE_FMAN_FW_IN_ROM
+	bool "Firmware is already in ROM"
+
+endchoice
diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig
index b9c8166..2fd8c7b 100644
--- a/drivers/ram/stm32mp1/Kconfig
+++ b/drivers/ram/stm32mp1/Kconfig
@@ -10,3 +10,40 @@
 		family:	support for LPDDR2, LPDDR3 and DDR3
 		the SDRAM parameters for controleur and phy need to be provided
 		in device tree (computed by DDR tuning tools)
+
+config STM32MP1_DDR_INTERACTIVE
+	bool "STM32MP1 DDR driver : interactive support"
+	depends on STM32MP1_DDR
+	help
+		activate interactive support in STM32MP1 DDR controller driver
+		used for DDR tuning tools
+		to enter in intercative mode type 'd' during SPL DDR driver
+		initialisation
+
+config STM32MP1_DDR_INTERACTIVE_FORCE
+	bool "STM32MP1 DDR driver : force interactive mode"
+	depends on STM32MP1_DDR_INTERACTIVE
+	default n
+	help
+		force interactive mode in STM32MP1 DDR controller driver
+		skip the polling of character 'd' in console
+		useful when SPL is loaded in sysram
+		directly by programmer
+
+config STM32MP1_DDR_TESTS
+	bool "STM32MP1 DDR driver : tests support"
+	depends on STM32MP1_DDR_INTERACTIVE
+	default y
+	help
+		activate test support for interactive support in
+		STM32MP1 DDR controller driver: command test
+
+config STM32MP1_DDR_TUNING
+	bool "STM32MP1 DDR driver : support of tuning"
+	depends on STM32MP1_DDR_INTERACTIVE
+	default y
+	help
+		activate tuning command in STM32MP1 DDR interactive mode
+		used for DDR tuning tools
+		- DQ Deskew algorithm
+		- DQS Trimming
diff --git a/drivers/ram/stm32mp1/Makefile b/drivers/ram/stm32mp1/Makefile
index 79eb028..e1e9135 100644
--- a/drivers/ram/stm32mp1/Makefile
+++ b/drivers/ram/stm32mp1/Makefile
@@ -5,3 +5,11 @@
 
 obj-y += stm32mp1_ram.o
 obj-y += stm32mp1_ddr.o
+
+obj-$(CONFIG_STM32MP1_DDR_INTERACTIVE) += stm32mp1_interactive.o
+obj-$(CONFIG_STM32MP1_DDR_TESTS) += stm32mp1_tests.o
+obj-$(CONFIG_STM32MP1_DDR_TUNING) += stm32mp1_tuning.o
+
+ifneq ($(DDR_INTERACTIVE),)
+CFLAGS_stm32mp1_interactive.o += -DCONFIG_STM32MP1_DDR_INTERACTIVE_FORCE=y
+endif
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
index c7c3ba7..d765a46 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -41,8 +41,32 @@
 	 offsetof(struct stm32mp1_ddrphy, x),\
 	 offsetof(struct y, x)}
 
+#define DDR_REG_DYN(x) \
+	{#x,\
+	 offsetof(struct stm32mp1_ddrctl, x),\
+	 INVALID_OFFSET}
+
+#define DDRPHY_REG_DYN(x) \
+	{#x,\
+	 offsetof(struct stm32mp1_ddrphy, x),\
+	 INVALID_OFFSET}
+
+/***********************************************************
+ * PARAMETERS: value get from device tree :
+ *             size / order need to be aligned with binding
+ *             modification NOT ALLOWED !!!
+ ***********************************************************/
+#define DDRCTL_REG_REG_SIZE	25	/* st,ctl-reg */
+#define DDRCTL_REG_TIMING_SIZE	12	/* st,ctl-timing */
+#define DDRCTL_REG_MAP_SIZE	9	/* st,ctl-map */
+#define DDRCTL_REG_PERF_SIZE	17	/* st,ctl-perf */
+
+#define DDRPHY_REG_REG_SIZE	11	/* st,phy-reg */
+#define	DDRPHY_REG_TIMING_SIZE	10	/* st,phy-timing */
+#define	DDRPHY_REG_CAL_SIZE	12	/* st,phy-cal */
+
 #define DDRCTL_REG_REG(x)	DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
-static const struct reg_desc ddr_reg[] = {
+static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
 	DDRCTL_REG_REG(mstr),
 	DDRCTL_REG_REG(mrctrl0),
 	DDRCTL_REG_REG(mrctrl1),
@@ -71,7 +95,7 @@
 };
 
 #define DDRCTL_REG_TIMING(x)	DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
-static const struct reg_desc ddr_timing[] = {
+static const struct reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
 	DDRCTL_REG_TIMING(rfshtmg),
 	DDRCTL_REG_TIMING(dramtmg0),
 	DDRCTL_REG_TIMING(dramtmg1),
@@ -87,7 +111,7 @@
 };
 
 #define DDRCTL_REG_MAP(x)	DDRCTL_REG(x, stm32mp1_ddrctrl_map)
-static const struct reg_desc ddr_map[] = {
+static const struct reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
 	DDRCTL_REG_MAP(addrmap1),
 	DDRCTL_REG_MAP(addrmap2),
 	DDRCTL_REG_MAP(addrmap3),
@@ -100,7 +124,7 @@
 };
 
 #define DDRCTL_REG_PERF(x)	DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
-static const struct reg_desc ddr_perf[] = {
+static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
 	DDRCTL_REG_PERF(sched),
 	DDRCTL_REG_PERF(sched1),
 	DDRCTL_REG_PERF(perfhpr1),
@@ -121,7 +145,7 @@
 };
 
 #define DDRPHY_REG_REG(x)	DDRPHY_REG(x, stm32mp1_ddrphy_reg)
-static const struct reg_desc ddrphy_reg[] = {
+static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {
 	DDRPHY_REG_REG(pgcr),
 	DDRPHY_REG_REG(aciocr),
 	DDRPHY_REG_REG(dxccr),
@@ -136,7 +160,7 @@
 };
 
 #define DDRPHY_REG_TIMING(x)	DDRPHY_REG(x, stm32mp1_ddrphy_timing)
-static const struct reg_desc ddrphy_timing[] = {
+static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {
 	DDRPHY_REG_TIMING(ptr0),
 	DDRPHY_REG_TIMING(ptr1),
 	DDRPHY_REG_TIMING(ptr2),
@@ -150,7 +174,7 @@
 };
 
 #define DDRPHY_REG_CAL(x)	DDRPHY_REG(x, stm32mp1_ddrphy_cal)
-static const struct reg_desc ddrphy_cal[] = {
+static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = {
 	DDRPHY_REG_CAL(dx0dllcr),
 	DDRPHY_REG_CAL(dx0dqtr),
 	DDRPHY_REG_CAL(dx0dqstr),
@@ -165,6 +189,45 @@
 	DDRPHY_REG_CAL(dx3dqstr),
 };
 
+/**************************************************************
+ * DYNAMIC REGISTERS: only used for debug purpose (read/modify)
+ **************************************************************/
+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
+static const struct reg_desc ddr_dyn[] = {
+	DDR_REG_DYN(stat),
+	DDR_REG_DYN(init0),
+	DDR_REG_DYN(dfimisc),
+	DDR_REG_DYN(dfistat),
+	DDR_REG_DYN(swctl),
+	DDR_REG_DYN(swstat),
+	DDR_REG_DYN(pctrl_0),
+	DDR_REG_DYN(pctrl_1),
+};
+
+#define DDR_REG_DYN_SIZE	ARRAY_SIZE(ddr_dyn)
+
+static const struct reg_desc ddrphy_dyn[] = {
+	DDRPHY_REG_DYN(pir),
+	DDRPHY_REG_DYN(pgsr),
+	DDRPHY_REG_DYN(zq0sr0),
+	DDRPHY_REG_DYN(zq0sr1),
+	DDRPHY_REG_DYN(dx0gsr0),
+	DDRPHY_REG_DYN(dx0gsr1),
+	DDRPHY_REG_DYN(dx1gsr0),
+	DDRPHY_REG_DYN(dx1gsr1),
+	DDRPHY_REG_DYN(dx2gsr0),
+	DDRPHY_REG_DYN(dx2gsr1),
+	DDRPHY_REG_DYN(dx3gsr0),
+	DDRPHY_REG_DYN(dx3gsr1),
+};
+
+#define DDRPHY_REG_DYN_SIZE	ARRAY_SIZE(ddrphy_dyn)
+
+#endif
+
+/*****************************************************************
+ * REGISTERS ARRAY: used to parse device tree and interactive mode
+ *****************************************************************/
 enum reg_type {
 	REG_REG,
 	REG_TIMING,
@@ -173,6 +236,13 @@
 	REGPHY_REG,
 	REGPHY_TIMING,
 	REGPHY_CAL,
+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
+/* dynamic registers => managed in driver or not changed,
+ * can be dumped in interactive mode
+ */
+	REG_DYN,
+	REGPHY_DYN,
+#endif
 	REG_TYPE_NB
 };
 
@@ -193,19 +263,26 @@
 
 const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
 [REG_REG] = {
-	"static", ddr_reg, ARRAY_SIZE(ddr_reg), DDR_BASE},
+	"static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
 [REG_TIMING] = {
-	"timing", ddr_timing, ARRAY_SIZE(ddr_timing), DDR_BASE},
+	"timing", ddr_timing, DDRCTL_REG_TIMING_SIZE, DDR_BASE},
 [REG_PERF] = {
-	"perf", ddr_perf, ARRAY_SIZE(ddr_perf), DDR_BASE},
+	"perf", ddr_perf, DDRCTL_REG_PERF_SIZE, DDR_BASE},
 [REG_MAP] = {
-	"map", ddr_map, ARRAY_SIZE(ddr_map), DDR_BASE},
+	"map", ddr_map, DDRCTL_REG_MAP_SIZE, DDR_BASE},
 [REGPHY_REG] = {
-	"static", ddrphy_reg, ARRAY_SIZE(ddrphy_reg), DDRPHY_BASE},
+	"static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
 [REGPHY_TIMING] = {
-	"timing", ddrphy_timing, ARRAY_SIZE(ddrphy_timing), DDRPHY_BASE},
+	"timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
 [REGPHY_CAL] = {
-	"cal", ddrphy_cal, ARRAY_SIZE(ddrphy_cal), DDRPHY_BASE},
+	"cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE},
+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
+[REG_DYN] = {
+	"dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
+[REGPHY_DYN] = {
+	"dyn", ddrphy_dyn, DDRPHY_REG_DYN_SIZE, DDRPHY_BASE},
+#endif
+
 };
 
 const char *base_name[] = {
@@ -246,6 +323,231 @@
 	}
 }
 
+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
+static void stm32mp1_dump_reg_desc(u32 base_addr, const struct reg_desc *desc)
+{
+	unsigned int *ptr;
+
+	ptr = (unsigned int *)(base_addr + desc->offset);
+	printf("%s= 0x%08x\n", desc->name, readl(ptr));
+}
+
+static void stm32mp1_dump_param_desc(u32 par_addr, const struct reg_desc *desc)
+{
+	unsigned int *ptr;
+
+	ptr = (unsigned int *)(par_addr + desc->par_offset);
+	printf("%s= 0x%08x\n", desc->name, readl(ptr));
+}
+
+static const struct reg_desc *found_reg(const char *name, enum reg_type *type)
+{
+	unsigned int i, j;
+	const struct reg_desc *desc;
+
+	for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
+		desc = ddr_registers[i].desc;
+		for (j = 0; j < ddr_registers[i].size; j++) {
+			if (strcmp(name, desc[j].name) == 0) {
+				*type = i;
+				return &desc[j];
+			}
+		}
+	}
+	*type = REG_TYPE_NB;
+	return NULL;
+}
+
+int stm32mp1_dump_reg(const struct ddr_info *priv,
+		      const char *name)
+{
+	unsigned int i, j;
+	const struct reg_desc *desc;
+	u32 base_addr;
+	enum base_type p_base;
+	enum reg_type type;
+	const char *p_name;
+	enum base_type filter = NONE_BASE;
+	int result = -1;
+
+	if (name) {
+		if (strcmp(name, base_name[DDR_BASE]) == 0)
+			filter = DDR_BASE;
+		else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
+			filter = DDRPHY_BASE;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
+		p_base = ddr_registers[i].base;
+		p_name = ddr_registers[i].name;
+		if (!name || (filter == p_base || !strcmp(name, p_name))) {
+			result = 0;
+			desc = ddr_registers[i].desc;
+			base_addr = get_base_addr(priv, p_base);
+			printf("==%s.%s==\n", base_name[p_base], p_name);
+			for (j = 0; j < ddr_registers[i].size; j++)
+				stm32mp1_dump_reg_desc(base_addr, &desc[j]);
+		}
+	}
+	if (result) {
+		desc = found_reg(name, &type);
+		if (desc) {
+			p_base = ddr_registers[type].base;
+			base_addr = get_base_addr(priv, p_base);
+			stm32mp1_dump_reg_desc(base_addr, desc);
+			result = 0;
+		}
+	}
+	return result;
+}
+
+void stm32mp1_edit_reg(const struct ddr_info *priv,
+		       char *name, char *string)
+{
+	unsigned long *ptr, value;
+	enum reg_type type;
+	enum base_type base;
+	const struct reg_desc *desc;
+	u32 base_addr;
+
+	desc = found_reg(name, &type);
+
+	if (!desc) {
+		printf("%s not found\n", name);
+		return;
+	}
+	if (strict_strtoul(string, 16, &value) < 0) {
+		printf("invalid value %s\n", string);
+		return;
+	}
+	base = ddr_registers[type].base;
+	base_addr = get_base_addr(priv, base);
+	ptr = (unsigned long *)(base_addr + desc->offset);
+	writel(value, ptr);
+	printf("%s= 0x%08x\n", desc->name, readl(ptr));
+}
+
+static u32 get_par_addr(const struct stm32mp1_ddr_config *config,
+			enum reg_type type)
+{
+	u32 par_addr = 0x0;
+
+	switch (type) {
+	case REG_REG:
+		par_addr = (u32)&config->c_reg;
+		break;
+	case REG_TIMING:
+		par_addr = (u32)&config->c_timing;
+		break;
+	case REG_PERF:
+		par_addr = (u32)&config->c_perf;
+		break;
+	case REG_MAP:
+		par_addr = (u32)&config->c_map;
+		break;
+	case REGPHY_REG:
+		par_addr = (u32)&config->p_reg;
+		break;
+	case REGPHY_TIMING:
+		par_addr = (u32)&config->p_timing;
+		break;
+	case REGPHY_CAL:
+		par_addr = (u32)&config->p_cal;
+		break;
+	case REG_DYN:
+	case REGPHY_DYN:
+	case REG_TYPE_NB:
+		par_addr = (u32)NULL;
+		break;
+	}
+
+	return par_addr;
+}
+
+int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
+			const char *name)
+{
+	unsigned int i, j;
+	const struct reg_desc *desc;
+	u32 par_addr;
+	enum base_type p_base;
+	enum reg_type type;
+	const char *p_name;
+	enum base_type filter = NONE_BASE;
+	int result = -EINVAL;
+
+	if (name) {
+		if (strcmp(name, base_name[DDR_BASE]) == 0)
+			filter = DDR_BASE;
+		else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
+			filter = DDRPHY_BASE;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
+		par_addr = get_par_addr(config, i);
+		if (!par_addr)
+			continue;
+		p_base = ddr_registers[i].base;
+		p_name = ddr_registers[i].name;
+		if (!name || (filter == p_base || !strcmp(name, p_name))) {
+			result = 0;
+			desc = ddr_registers[i].desc;
+			printf("==%s.%s==\n", base_name[p_base], p_name);
+			for (j = 0; j < ddr_registers[i].size; j++)
+				stm32mp1_dump_param_desc(par_addr, &desc[j]);
+		}
+	}
+	if (result) {
+		desc = found_reg(name, &type);
+		if (desc) {
+			par_addr = get_par_addr(config, type);
+			if (par_addr) {
+				stm32mp1_dump_param_desc(par_addr, desc);
+				result = 0;
+			}
+		}
+	}
+	return result;
+}
+
+void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
+			 char *name, char *string)
+{
+	unsigned long *ptr, value;
+	enum reg_type type;
+	const struct reg_desc *desc;
+	u32 par_addr;
+
+	desc = found_reg(name, &type);
+	if (!desc) {
+		printf("%s not found\n", name);
+		return;
+	}
+	if (strict_strtoul(string, 16, &value) < 0) {
+		printf("invalid value %s\n", string);
+		return;
+	}
+	par_addr = get_par_addr(config, type);
+	if (!par_addr) {
+		printf("no parameter %s\n", name);
+		return;
+	}
+	ptr = (unsigned long *)(par_addr + desc->par_offset);
+	writel(value, ptr);
+	printf("%s= 0x%08x\n", desc->name, readl(ptr));
+}
+#endif
+
+__weak bool stm32mp1_ddr_interactive(void *priv,
+				     enum stm32mp1_ddr_interact_step step,
+				     const struct stm32mp1_ddr_config *config)
+{
+	return false;
+}
+
+#define INTERACTIVE(step)\
+	stm32mp1_ddr_interactive(priv, step, config)
+
 static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
 {
 	u32 pgsr;
@@ -312,7 +614,7 @@
 	/* self-refresh due to software => check also STAT.selfref_type */
 	if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
 		mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
-		stat |= DDRCTRL_STAT_SELFREF_TYPE_SR;
+		val |= DDRCTRL_STAT_SELFREF_TYPE_SR;
 	} else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
 		/* normal mode: handle also automatic self refresh */
 		mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
@@ -355,7 +657,7 @@
 }
 
 /* board-specific DDR power initializations. */
-__weak int board_ddr_power_init(void)
+__weak int board_ddr_power_init(enum ddr_type ddr_type)
 {
 	return 0;
 }
@@ -365,15 +667,21 @@
 		       const struct stm32mp1_ddr_config *config)
 {
 	u32 pir;
-	int ret;
+	int ret = -EINVAL;
 
-	ret = board_ddr_power_init();
+	if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
+		ret = board_ddr_power_init(STM32MP_DDR3);
+	else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2)
+		ret = board_ddr_power_init(STM32MP_LPDDR2);
+	else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3)
+		ret = board_ddr_power_init(STM32MP_LPDDR3);
 
 	if (ret)
 		panic("ddr power init failed\n");
 
+start:
 	debug("name = %s\n", config->info.name);
-	debug("speed = %d MHz\n", config->info.speed);
+	debug("speed = %d kHz\n", config->info.speed);
 	debug("size  = 0x%x\n", config->info.size);
 /*
  * 1. Program the DWC_ddr_umctl2 registers
@@ -389,7 +697,7 @@
 
 /* 1.2. start CLOCK */
 	if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
-		panic("invalid DRAM clock : %d MHz\n",
+		panic("invalid DRAM clock : %d kHz\n",
 		      config->info.speed);
 
 /* 1.3. deassert reset */
@@ -401,11 +709,12 @@
 	 */
 	clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
 
-/* 1.4. wait 4 cycles for synchronization */
-	asm(" nop");
-	asm(" nop");
-	asm(" nop");
-	asm(" nop");
+/* 1.4. wait 128 cycles to permit initialization of end logic */
+	udelay(2);
+	/* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
+
+	if (INTERACTIVE(STEP_DDR_RESET))
+		goto start;
 
 /* 1.5. initialize registers ddr_umctl2 */
 	/* Stop uMCTL2 before PHY is ready */
@@ -424,6 +733,9 @@
 
 	set_reg(priv, REG_PERF, &config->c_perf);
 
+	if (INTERACTIVE(STEP_CTL_INIT))
+		goto start;
+
 /*  2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
 	clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
 	clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
@@ -436,6 +748,9 @@
 	set_reg(priv, REGPHY_TIMING, &config->p_timing);
 	set_reg(priv, REGPHY_CAL, &config->p_cal);
 
+	if (INTERACTIVE(STEP_PHY_INIT))
+		goto start;
+
 /*  4. Monitor PHY init status by polling PUBL register PGSR.IDONE
  *     Perform DDR PHY DRAM initialization and Gate Training Evaluation
  */
@@ -492,4 +807,7 @@
 	/* enable uMCTL2 AXI port 0 and 1 */
 	setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
 	setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
+
+	if (INTERACTIVE(STEP_DDR_READY))
+		goto start;
 }
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h
index 3cd0161..a8eed89 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.h
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h
@@ -157,7 +157,7 @@
 
 struct stm32mp1_ddr_info {
 	const char *name;
-	u16 speed; /* in MHZ */
+	u32 speed; /* in kHZ */
 	u32 size;  /* memory size in byte = col * row * width */
 };
 
@@ -172,7 +172,7 @@
 	struct stm32mp1_ddrphy_cal p_cal;
 };
 
-int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u16 mem_speed);
+int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
 void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
 void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl);
 void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
index a606b2b..9d33186 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
@@ -234,6 +234,8 @@
 
 /* DDRCTRL REGISTERS */
 #define DDRCTRL_MSTR_DDR3			BIT(0)
+#define DDRCTRL_MSTR_LPDDR2			BIT(2)
+#define DDRCTRL_MSTR_LPDDR3			BIT(3)
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK	GENMASK(13, 12)
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL	(0 << 12)
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF	(1 << 12)
@@ -330,6 +332,7 @@
 
 #define DDRPHYC_DXNGCR_DXEN			BIT(0)
 
+#define DDRPHYC_DXNDLLCR_DLLSRST		BIT(30)
 #define DDRPHYC_DXNDLLCR_DLLDIS			BIT(31)
 #define DDRPHYC_DXNDLLCR_SDPHASE_MASK		GENMASK(17, 14)
 #define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT		14
diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c
new file mode 100644
index 0000000..cc9b2e7
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c
@@ -0,0 +1,483 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <console.h>
+#include <cli.h>
+#include <clk.h>
+#include <malloc.h>
+#include <ram.h>
+#include <reset.h>
+#include "stm32mp1_ddr.h"
+#include "stm32mp1_tests.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ddr_command {
+	DDR_CMD_HELP,
+	DDR_CMD_INFO,
+	DDR_CMD_FREQ,
+	DDR_CMD_RESET,
+	DDR_CMD_PARAM,
+	DDR_CMD_PRINT,
+	DDR_CMD_EDIT,
+	DDR_CMD_STEP,
+	DDR_CMD_NEXT,
+	DDR_CMD_GO,
+	DDR_CMD_TEST,
+	DDR_CMD_TUNING,
+	DDR_CMD_UNKNOWN,
+};
+
+const char *step_str[] = {
+	[STEP_DDR_RESET] = "DDR_RESET",
+	[STEP_CTL_INIT] = "DDR_CTRL_INIT_DONE",
+	[STEP_PHY_INIT] = "DDR PHY_INIT_DONE",
+	[STEP_DDR_READY] = "DDR_READY",
+	[STEP_RUN] = "RUN"
+};
+
+enum ddr_command stm32mp1_get_command(char *cmd, int argc)
+{
+	const char *cmd_string[DDR_CMD_UNKNOWN] = {
+		[DDR_CMD_HELP] = "help",
+		[DDR_CMD_INFO] = "info",
+		[DDR_CMD_FREQ] = "freq",
+		[DDR_CMD_RESET] = "reset",
+		[DDR_CMD_PARAM] = "param",
+		[DDR_CMD_PRINT] = "print",
+		[DDR_CMD_EDIT] = "edit",
+		[DDR_CMD_STEP] = "step",
+		[DDR_CMD_NEXT] = "next",
+		[DDR_CMD_GO] = "go",
+#ifdef CONFIG_STM32MP1_DDR_TESTS
+		[DDR_CMD_TEST] = "test",
+#endif
+#ifdef CONFIG_STM32MP1_DDR_TUNING
+		[DDR_CMD_TUNING] = "tuning",
+#endif
+	};
+	/* min and max number of argument */
+	const char cmd_arg[DDR_CMD_UNKNOWN][2] = {
+		[DDR_CMD_HELP] = { 0, 0 },
+		[DDR_CMD_INFO] = { 0, 255 },
+		[DDR_CMD_FREQ] = { 0, 1 },
+		[DDR_CMD_RESET] = { 0, 0 },
+		[DDR_CMD_PARAM] = { 0, 2 },
+		[DDR_CMD_PRINT] = { 0, 1 },
+		[DDR_CMD_EDIT] = { 2, 2 },
+		[DDR_CMD_STEP] = { 0, 1 },
+		[DDR_CMD_NEXT] = { 0, 0 },
+		[DDR_CMD_GO] = { 0, 0 },
+#ifdef CONFIG_STM32MP1_DDR_TESTS
+		[DDR_CMD_TEST] = { 0, 255 },
+#endif
+#ifdef CONFIG_STM32MP1_DDR_TUNING
+		[DDR_CMD_TUNING] = { 0, 255 },
+#endif
+	};
+	int i;
+
+	for (i = 0; i < DDR_CMD_UNKNOWN; i++)
+		if (!strcmp(cmd, cmd_string[i])) {
+			if (argc - 1 < cmd_arg[i][0]) {
+				printf("no enought argument (min=%d)\n",
+				       cmd_arg[i][0]);
+				return DDR_CMD_UNKNOWN;
+			} else if (argc - 1 > cmd_arg[i][1]) {
+				printf("too many argument (max=%d)\n",
+				       cmd_arg[i][1]);
+				return DDR_CMD_UNKNOWN;
+			} else {
+				return i;
+			}
+		}
+
+	printf("unknown command %s\n", cmd);
+	return DDR_CMD_UNKNOWN;
+}
+
+static void stm32mp1_do_usage(void)
+{
+	const char *usage = {
+		"commands:\n\n"
+		"help                       displays help\n"
+		"info                       displays DDR information\n"
+		"info  <param> <val>        changes DDR information\n"
+		"      with <param> = step, name, size or speed\n"
+		"freq                       displays the DDR PHY frequency in kHz\n"
+		"freq  <freq>               changes the DDR PHY frequency\n"
+		"param [type|reg]           prints input parameters\n"
+		"param <reg> <val>          edits parameters in step 0\n"
+		"print [type|reg]           dumps registers\n"
+		"edit <reg> <val>           modifies one register\n"
+		"step                       lists the available step\n"
+		"step <n>                   go to the step <n>\n"
+		"next                       goes to the next step\n"
+		"go                         continues the U-Boot SPL execution\n"
+		"reset                      reboots machine\n"
+#ifdef CONFIG_STM32MP1_DDR_TESTS
+		"test [help] | <n> [...]    lists (with help) or executes test <n>\n"
+#endif
+#ifdef CONFIG_STM32MP1_DDR_TUNING
+		"tuning [help] | <n> [...]  lists (with help) or execute tuning <n>\n"
+#endif
+		"\nwith for [type|reg]:\n"
+		"  all registers if absent\n"
+		"  <type> = ctl, phy\n"
+		"           or one category (static, timing, map, perf, cal, dyn)\n"
+		"  <reg> = name of the register\n"
+	};
+
+	puts(usage);
+}
+
+static bool stm32mp1_check_step(enum stm32mp1_ddr_interact_step step,
+				enum stm32mp1_ddr_interact_step expected)
+{
+	if (step != expected) {
+		printf("invalid step %d:%s expecting %d:%s\n",
+		       step, step_str[step],
+		       expected,
+		       step_str[expected]);
+		return false;
+	}
+	return true;
+}
+
+static void stm32mp1_do_info(struct ddr_info *priv,
+			     struct stm32mp1_ddr_config *config,
+			     enum stm32mp1_ddr_interact_step step,
+			     int argc, char * const argv[])
+{
+	unsigned long value;
+	static char *ddr_name;
+
+	if (argc == 1) {
+		printf("step = %d : %s\n", step, step_str[step]);
+		printf("name = %s\n", config->info.name);
+		printf("size = 0x%x\n", config->info.size);
+		printf("speed = %d kHz\n", config->info.speed);
+		return;
+	}
+
+	if (argc < 3) {
+		printf("no enought parameter\n");
+		return;
+	}
+	if (!strcmp(argv[1], "name")) {
+		u32 i, name_len = 0;
+
+		for (i = 2; i < argc; i++)
+			name_len += strlen(argv[i]) + 1;
+		if (ddr_name)
+			free(ddr_name);
+		ddr_name = malloc(name_len);
+		config->info.name = ddr_name;
+		if (!ddr_name) {
+			printf("alloc error, length %d\n", name_len);
+			return;
+		}
+		strcpy(ddr_name, argv[2]);
+		for (i = 3; i < argc; i++) {
+			strcat(ddr_name, " ");
+			strcat(ddr_name, argv[i]);
+		}
+		printf("name = %s\n", ddr_name);
+		return;
+	}
+	if (!strcmp(argv[1], "size")) {
+		if (strict_strtoul(argv[2], 16, &value) < 0) {
+			printf("invalid value %s\n", argv[2]);
+		} else {
+			config->info.size = value;
+			printf("size = 0x%x\n", config->info.size);
+		}
+		return;
+	}
+	if (!strcmp(argv[1], "speed")) {
+		if (strict_strtoul(argv[2], 10, &value) < 0) {
+			printf("invalid value %s\n", argv[2]);
+		} else {
+			config->info.speed = value;
+			printf("speed = %d kHz\n", config->info.speed);
+			value = clk_get_rate(&priv->clk);
+			printf("DDRPHY = %ld kHz\n", value / 1000);
+		}
+		return;
+	}
+	printf("argument %s invalid\n", argv[1]);
+}
+
+static bool stm32mp1_do_freq(struct ddr_info *priv,
+			     int argc, char * const argv[])
+{
+	unsigned long ddrphy_clk;
+
+	if (argc == 2) {
+		if (strict_strtoul(argv[1], 0, &ddrphy_clk) < 0) {
+			printf("invalid argument %s", argv[1]);
+			return false;
+		}
+		if (clk_set_rate(&priv->clk, ddrphy_clk * 1000)) {
+			printf("ERROR: update failed!\n");
+			return false;
+		}
+	}
+	ddrphy_clk = clk_get_rate(&priv->clk);
+	printf("DDRPHY = %ld kHz\n", ddrphy_clk / 1000);
+	if (argc == 2)
+		return true;
+	return false;
+}
+
+static void stm32mp1_do_param(enum stm32mp1_ddr_interact_step step,
+			      const struct stm32mp1_ddr_config *config,
+			      int argc, char * const argv[])
+{
+	switch (argc) {
+	case 1:
+		stm32mp1_dump_param(config, NULL);
+		break;
+	case 2:
+		if (stm32mp1_dump_param(config, argv[1]))
+			printf("invalid argument %s\n",
+			       argv[1]);
+		break;
+	case 3:
+		if (!stm32mp1_check_step(step, STEP_DDR_RESET))
+			return;
+		stm32mp1_edit_param(config, argv[1], argv[2]);
+		break;
+	}
+}
+
+static void stm32mp1_do_print(struct ddr_info *priv,
+			      int argc, char * const argv[])
+{
+	switch (argc) {
+	case 1:
+		stm32mp1_dump_reg(priv, NULL);
+		break;
+	case 2:
+		if (stm32mp1_dump_reg(priv, argv[1]))
+			printf("invalid argument %s\n",
+			       argv[1]);
+		break;
+	}
+}
+
+static int stm32mp1_do_step(enum stm32mp1_ddr_interact_step step,
+			    int argc, char * const argv[])
+{
+	int i;
+	unsigned long value;
+
+	switch (argc) {
+	case 1:
+		for (i = 0; i < ARRAY_SIZE(step_str); i++)
+			printf("%d:%s\n", i, step_str[i]);
+		break;
+
+	case 2:
+		if ((strict_strtoul(argv[1], 0,
+				    &value) < 0) ||
+				    value >= ARRAY_SIZE(step_str)) {
+			printf("invalid argument %s\n",
+			       argv[1]);
+			goto end;
+		}
+
+		if (value != STEP_DDR_RESET &&
+		    value <= step) {
+			printf("invalid target %d:%s, current step is %d:%s\n",
+			       (int)value, step_str[value],
+			       step, step_str[step]);
+			goto end;
+		}
+		printf("step to %d:%s\n",
+		       (int)value, step_str[value]);
+		return (int)value;
+	};
+
+end:
+	return step;
+}
+
+#if defined(CONFIG_STM32MP1_DDR_TESTS) || defined(CONFIG_STM32MP1_DDR_TUNING)
+static const char * const s_result[] = {
+		[TEST_PASSED] = "Pass",
+		[TEST_FAILED] = "Failed",
+		[TEST_ERROR] = "Error"
+};
+
+static void stm32mp1_ddr_subcmd(struct ddr_info *priv,
+				int argc, char *argv[],
+				const struct test_desc array[],
+				const int array_nb)
+{
+	int i;
+	unsigned long value;
+	int result;
+	char string[50] = "";
+
+	if (argc == 1) {
+		printf("%s:%d\n", argv[0], array_nb);
+		for (i = 0; i < array_nb; i++)
+			printf("%d:%s:%s\n",
+			       i, array[i].name, array[i].usage);
+		return;
+	}
+	if (argc > 1 && !strcmp(argv[1], "help")) {
+		printf("%s:%d\n", argv[0], array_nb);
+		for (i = 0; i < array_nb; i++)
+			printf("%d:%s:%s:%s\n", i,
+			       array[i].name, array[i].usage, array[i].help);
+		return;
+	}
+
+	if ((strict_strtoul(argv[1], 0, &value) <  0) ||
+	    value >= array_nb) {
+		sprintf(string, "invalid argument %s",
+			argv[1]);
+		result = TEST_FAILED;
+		goto end;
+	}
+
+	if (argc > (array[value].max_args + 2)) {
+		sprintf(string, "invalid nb of args %d, max %d",
+			argc - 2, array[value].max_args);
+		result = TEST_FAILED;
+		goto end;
+	}
+
+	printf("execute %d:%s\n", (int)value, array[value].name);
+	clear_ctrlc();
+	result = array[value].fct(priv->ctl, priv->phy,
+				  string, argc - 2, &argv[2]);
+
+end:
+	printf("Result: %s [%s]\n", s_result[result], string);
+}
+#endif
+
+bool stm32mp1_ddr_interactive(void *priv,
+			      enum stm32mp1_ddr_interact_step step,
+			      const struct stm32mp1_ddr_config *config)
+{
+	const char *prompt = "DDR>";
+	char buffer[CONFIG_SYS_CBSIZE];
+	char *argv[CONFIG_SYS_MAXARGS + 1];	/* NULL terminated */
+	int argc;
+	static int next_step = -1;
+
+	if (next_step < 0 && step == STEP_DDR_RESET) {
+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE_FORCE
+		gd->flags &= ~(GD_FLG_SILENT |
+			       GD_FLG_DISABLE_CONSOLE);
+		next_step = STEP_DDR_RESET;
+#else
+		unsigned long start = get_timer(0);
+
+		while (1) {
+			if (tstc() && (getc() == 'd')) {
+				next_step = STEP_DDR_RESET;
+				break;
+			}
+			if (get_timer(start) > 100)
+				break;
+		}
+#endif
+	}
+
+	debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
+
+	if (next_step < 0)
+		return false;
+
+	if (step < 0 || step > ARRAY_SIZE(step_str)) {
+		printf("** step %d ** INVALID\n", step);
+		return false;
+	}
+
+	printf("%d:%s\n", step, step_str[step]);
+	printf("%s\n", prompt);
+
+	if (next_step > step)
+		return false;
+
+	while (next_step == step) {
+		cli_readline_into_buffer(prompt, buffer, 0);
+		argc = cli_simple_parse_line(buffer, argv);
+		if (!argc)
+			continue;
+
+		switch (stm32mp1_get_command(argv[0], argc)) {
+		case DDR_CMD_HELP:
+			stm32mp1_do_usage();
+			break;
+
+		case DDR_CMD_INFO:
+			stm32mp1_do_info(priv,
+					 (struct stm32mp1_ddr_config *)config,
+					 step, argc, argv);
+			break;
+
+		case DDR_CMD_FREQ:
+			if (stm32mp1_do_freq(priv, argc, argv))
+				next_step = STEP_DDR_RESET;
+			break;
+
+		case DDR_CMD_RESET:
+			do_reset(NULL, 0, 0, NULL);
+			break;
+
+		case DDR_CMD_PARAM:
+			stm32mp1_do_param(step, config, argc, argv);
+			break;
+
+		case DDR_CMD_PRINT:
+			stm32mp1_do_print(priv, argc, argv);
+			break;
+
+		case DDR_CMD_EDIT:
+			stm32mp1_edit_reg(priv, argv[1], argv[2]);
+			break;
+
+		case DDR_CMD_GO:
+			next_step = STEP_RUN;
+			break;
+
+		case DDR_CMD_NEXT:
+			next_step = step + 1;
+			break;
+
+		case DDR_CMD_STEP:
+			next_step = stm32mp1_do_step(step, argc, argv);
+			break;
+
+#ifdef CONFIG_STM32MP1_DDR_TESTS
+		case DDR_CMD_TEST:
+			if (!stm32mp1_check_step(step, STEP_DDR_READY))
+				continue;
+			stm32mp1_ddr_subcmd(priv, argc, argv, test, test_nb);
+			break;
+#endif
+
+#ifdef CONFIG_STM32MP1_DDR_TUNING
+		case DDR_CMD_TUNING:
+			if (!stm32mp1_check_step(step, STEP_DDR_READY))
+				continue;
+			stm32mp1_ddr_subcmd(priv, argc, argv,
+					    tuning, tuning_nb);
+			break;
+#endif
+
+		default:
+			break;
+		}
+	}
+	return next_step == STEP_DDR_RESET;
+}
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
index e45a3b2..84e39d0 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -20,7 +20,7 @@
 	"ddrphyc" /* LAST clock => used for get_rate() */
 };
 
-int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed)
+int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
 {
 	unsigned long ddrphy_clk;
 	unsigned long ddr_clk;
@@ -43,13 +43,13 @@
 	priv->clk = clk;
 	ddrphy_clk = clk_get_rate(&priv->clk);
 
-	debug("DDR: mem_speed (%d MHz), RCC %d MHz\n",
-	      mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
+	debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
+	      mem_speed, (u32)(ddrphy_clk / 1000));
 	/* max 10% frequency delta */
-	ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000);
-	if (ddr_clk > (mem_speed * 1000 * 100)) {
-		pr_err("DDR expected freq %d MHz, current is %d MHz\n",
-		       mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
+	ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
+	if (ddr_clk > (mem_speed * 100)) {
+		pr_err("DDR expected freq %d kHz, current is %d kHz\n",
+		       mem_speed, (u32)(ddrphy_clk / 1000));
 		return -EINVAL;
 	}
 
@@ -102,8 +102,8 @@
 		debug("%s: %s[0x%x] = %d\n", __func__,
 		      param[idx].name, param[idx].size, ret);
 		if (ret) {
-			pr_err("%s: Cannot read %s\n",
-			       __func__, param[idx].name);
+			pr_err("%s: Cannot read %s, error=%d\n",
+			       __func__, param[idx].name, ret);
 			return -EINVAL;
 		}
 	}
diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c
new file mode 100644
index 0000000..b6fb2a9
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_tests.c
@@ -0,0 +1,1426 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+#include <common.h>
+#include <console.h>
+#include <asm/io.h>
+#include <linux/log2.h>
+#include "stm32mp1_tests.h"
+
+#define ADDR_INVALID	0xFFFFFFFF
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int get_bufsize(char *string, int argc, char *argv[], int arg_nb,
+		       size_t *bufsize, size_t default_size)
+{
+	unsigned long value;
+
+	if (argc > arg_nb) {
+		if (strict_strtoul(argv[arg_nb], 0, &value) < 0) {
+			sprintf(string, "invalid %d parameter %s",
+				arg_nb, argv[arg_nb]);
+			return -1;
+		}
+		if (value > STM32_DDR_SIZE || value == 0) {
+			sprintf(string, "invalid size %s", argv[arg_nb]);
+			return -1;
+		}
+		if (value & 0x3) {
+			sprintf(string, "unaligned size %s",
+				argv[arg_nb]);
+			return -1;
+		}
+		*bufsize = value;
+	} else {
+		if (default_size != STM32_DDR_SIZE)
+			*bufsize = default_size;
+		else
+			*bufsize = get_ram_size((long *)STM32_DDR_BASE,
+						STM32_DDR_SIZE);
+	}
+	return 0;
+}
+
+static int get_nb_loop(char *string, int argc, char *argv[], int arg_nb,
+		       u32 *nb_loop, u32 default_nb_loop)
+{
+	unsigned long value;
+
+	if (argc > arg_nb) {
+		if (strict_strtoul(argv[arg_nb], 0, &value) < 0) {
+			sprintf(string, "invalid %d parameter %s",
+				arg_nb, argv[arg_nb]);
+			return -1;
+		}
+		if (value == 0)
+			printf("WARNING: infinite loop requested\n");
+		*nb_loop = value;
+	} else {
+		*nb_loop = default_nb_loop;
+	}
+
+	return 0;
+}
+
+static int get_addr(char *string, int argc, char *argv[], int arg_nb,
+		    u32 *addr)
+{
+	unsigned long value;
+
+	if (argc > arg_nb) {
+		if (strict_strtoul(argv[arg_nb], 16, &value) < 0) {
+			sprintf(string, "invalid %d parameter %s",
+				arg_nb, argv[arg_nb]);
+			return -1;
+		}
+		if (value < STM32_DDR_BASE) {
+			sprintf(string, "too low address %s", argv[arg_nb]);
+			return -1;
+		}
+		if (value & 0x3 && value != ADDR_INVALID) {
+			sprintf(string, "unaligned address %s",
+				argv[arg_nb]);
+			return -1;
+		}
+		*addr = value;
+	} else {
+		*addr = STM32_DDR_BASE;
+	}
+
+	return 0;
+}
+
+static int get_pattern(char *string, int argc, char *argv[], int arg_nb,
+		       u32 *pattern, u32 default_pattern)
+{
+	unsigned long value;
+
+	if (argc > arg_nb) {
+		if (strict_strtoul(argv[arg_nb], 16, &value) < 0) {
+			sprintf(string, "invalid %d parameter %s",
+				arg_nb, argv[arg_nb]);
+			return -1;
+		}
+		*pattern = value;
+	} else {
+		*pattern = default_pattern;
+	}
+
+	return 0;
+}
+
+static u32 check_addr(u32 addr, u32 value)
+{
+	u32 data = readl(addr);
+
+	if (value !=  data) {
+		printf("0x%08x: 0x%08x <=> 0x%08x", addr, data, value);
+		data = readl(addr);
+		printf("(2nd read: 0x%08x)", data);
+		if (value == data)
+			printf("- read error");
+		else
+			printf("- write error");
+		printf("\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int progress(u32 offset)
+{
+	if (!(offset & 0xFFFFFF)) {
+		putc('.');
+		if (ctrlc()) {
+			printf("\ntest interrupted!\n");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+static int test_loop_end(u32 *loop, u32 nb_loop, u32 progress)
+{
+	(*loop)++;
+	if (nb_loop && *loop >= nb_loop)
+		return 1;
+	if ((*loop) % progress)
+		return 0;
+	/* allow to interrupt the test only for progress step */
+	if (ctrlc()) {
+		printf("test interrupted!\n");
+		return 1;
+	}
+	printf("loop #%d\n", *loop);
+	return 0;
+}
+
+/**********************************************************************
+ *
+ * Function:    memTestDataBus()
+ *
+ * Description: Test the data bus wiring in a memory region by
+ *              performing a walking 1's test at a fixed address
+ *              within that region.  The address is selected
+ *              by the caller.
+ *
+ * Notes:
+ *
+ * Returns:     0 if the test succeeds.
+ *              A non-zero result is the first pattern that failed.
+ *
+ **********************************************************************/
+static u32 databus(u32 *address)
+{
+	u32 pattern;
+	u32 read_value;
+
+	/* Perform a walking 1's test at the given address. */
+	for (pattern = 1; pattern != 0; pattern <<= 1) {
+		/* Write the test pattern. */
+		writel(pattern, address);
+
+		/* Read it back (immediately is okay for this test). */
+		read_value = readl(address);
+		debug("%x: %x <=> %x\n",
+		      (u32)address, read_value, pattern);
+
+		if (read_value != pattern)
+			return pattern;
+	}
+
+	return 0;
+}
+
+/**********************************************************************
+ *
+ * Function:    memTestAddressBus()
+ *
+ * Description: Test the address bus wiring in a memory region by
+ *              performing a walking 1's test on the relevant bits
+ *              of the address and checking for aliasing. This test
+ *              will find single-bit address failures such as stuck
+ *              -high, stuck-low, and shorted pins.  The base address
+ *              and size of the region are selected by the caller.
+ *
+ * Notes:       For best results, the selected base address should
+ *              have enough LSB 0's to guarantee single address bit
+ *              changes.  For example, to test a 64-Kbyte region,
+ *              select a base address on a 64-Kbyte boundary.  Also,
+ *              select the region size as a power-of-two--if at all
+ *              possible.
+ *
+ * Returns:     NULL if the test succeeds.
+ *              A non-zero result is the first address at which an
+ *              aliasing problem was uncovered.  By examining the
+ *              contents of memory, it may be possible to gather
+ *              additional information about the problem.
+ *
+ **********************************************************************/
+static u32 *addressbus(u32 *address, u32 nb_bytes)
+{
+	u32 mask = (nb_bytes / sizeof(u32) - 1);
+	u32 offset;
+	u32 test_offset;
+	u32 read_value;
+
+	u32 pattern     = 0xAAAAAAAA;
+	u32 antipattern = 0x55555555;
+
+	/* Write the default pattern at each of the power-of-two offsets. */
+	for (offset = 1; (offset & mask) != 0; offset <<= 1)
+		writel(pattern, &address[offset]);
+
+	/* Check for address bits stuck high. */
+	test_offset = 0;
+	writel(antipattern, &address[test_offset]);
+
+	for (offset = 1; (offset & mask) != 0; offset <<= 1) {
+		read_value = readl(&address[offset]);
+		debug("%x: %x <=> %x\n",
+		      (u32)&address[offset], read_value, pattern);
+		if (read_value != pattern)
+			return &address[offset];
+	}
+
+	writel(pattern, &address[test_offset]);
+
+	/* Check for address bits stuck low or shorted. */
+	for (test_offset = 1; (test_offset & mask) != 0; test_offset <<= 1) {
+		writel(antipattern, &address[test_offset]);
+		if (readl(&address[0]) != pattern)
+			return &address[test_offset];
+
+		for (offset = 1; (offset & mask) != 0; offset <<= 1) {
+			if (readl(&address[offset]) != pattern &&
+			    offset != test_offset)
+				return &address[test_offset];
+		}
+		writel(pattern, &address[test_offset]);
+	}
+
+	return NULL;
+}
+
+/**********************************************************************
+ *
+ * Function:    memTestDevice()
+ *
+ * Description: Test the integrity of a physical memory device by
+ *              performing an increment/decrement test over the
+ *              entire region.  In the process every storage bit
+ *              in the device is tested as a zero and a one.  The
+ *              base address and the size of the region are
+ *              selected by the caller.
+ *
+ * Notes:
+ *
+ * Returns:     NULL if the test succeeds.
+ *
+ *              A non-zero result is the first address at which an
+ *              incorrect value was read back.  By examining the
+ *              contents of memory, it may be possible to gather
+ *              additional information about the problem.
+ *
+ **********************************************************************/
+static u32 *memdevice(u32 *address, u32 nb_bytes)
+{
+	u32 offset;
+	u32 nb_words = nb_bytes / sizeof(u32);
+
+	u32 pattern;
+	u32 antipattern;
+
+	puts("Fill with pattern");
+	/* Fill memory with a known pattern. */
+	for (pattern = 1, offset = 0; offset < nb_words; pattern++, offset++) {
+		writel(pattern, &address[offset]);
+		if (progress(offset))
+			return NULL;
+	}
+
+	puts("\nCheck and invert pattern");
+	/* Check each location and invert it for the second pass. */
+	for (pattern = 1, offset = 0; offset < nb_words; pattern++, offset++) {
+		if (readl(&address[offset]) != pattern)
+			return &address[offset];
+
+		antipattern = ~pattern;
+		writel(antipattern, &address[offset]);
+		if (progress(offset))
+			return NULL;
+	}
+
+	puts("\nCheck inverted pattern");
+	/* Check each location for the inverted pattern and zero it. */
+	for (pattern = 1, offset = 0; offset < nb_words; pattern++, offset++) {
+		antipattern = ~pattern;
+		if (readl(&address[offset]) != antipattern)
+			return &address[offset];
+		if (progress(offset))
+			return NULL;
+	}
+	printf("\n");
+
+	return NULL;
+}
+
+static enum test_result databuswalk0(struct stm32mp1_ddrctl *ctl,
+				     struct stm32mp1_ddrphy *phy,
+				     char *string, int argc, char *argv[])
+{
+	int i;
+	u32 loop = 0, nb_loop;
+	u32 addr;
+	u32 error = 0;
+	u32 data;
+
+	if (get_nb_loop(string, argc, argv, 0, &nb_loop, 100))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 1, &addr))
+		return TEST_ERROR;
+
+	printf("running %d loops at 0x%x\n", nb_loop, addr);
+	while (!error) {
+		for (i = 0; i < 32; i++)
+			writel(~(1 << i), addr + 4 * i);
+		for (i = 0; i < 32; i++) {
+			data = readl(addr + 4 * i);
+			if (~(1 << i) !=  data) {
+				error |= 1 << i;
+				debug("%x: error %x expected %x => error:%x\n",
+				      addr + 4 * i, data, ~(1 << i), error);
+			}
+		}
+		if (test_loop_end(&loop, nb_loop, 1000))
+			break;
+		for (i = 0; i < 32; i++)
+			writel(0, addr + 4 * i);
+	}
+	if (error) {
+		sprintf(string, "loop %d: error for bits 0x%x",
+			loop, error);
+		return TEST_FAILED;
+	}
+	sprintf(string, "no error for %d loops", loop);
+	return TEST_PASSED;
+}
+
+static enum test_result databuswalk1(struct stm32mp1_ddrctl *ctl,
+				     struct stm32mp1_ddrphy *phy,
+				     char *string, int argc, char *argv[])
+{
+	int i;
+	u32 loop = 0, nb_loop;
+	u32 addr;
+	u32 error = 0;
+	u32 data;
+
+	if (get_nb_loop(string, argc, argv, 0, &nb_loop, 100))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 1, &addr))
+		return TEST_ERROR;
+	printf("running %d loops at 0x%x\n", nb_loop, addr);
+	while (!error) {
+		for (i = 0; i < 32; i++)
+			writel(1 << i, addr + 4 * i);
+		for (i = 0; i < 32; i++) {
+			data = readl(addr + 4 * i);
+			if ((1 << i) !=  data) {
+				error |= 1 << i;
+				debug("%x: error %x expected %x => error:%x\n",
+				      addr + 4 * i, data, (1 << i), error);
+			}
+		}
+		if (test_loop_end(&loop, nb_loop, 1000))
+			break;
+		for (i = 0; i < 32; i++)
+			writel(0, addr + 4 * i);
+	}
+	if (error) {
+		sprintf(string, "loop %d: error for bits 0x%x",
+			loop, error);
+		return TEST_FAILED;
+	}
+	sprintf(string, "no error for %d loops", loop);
+	return TEST_PASSED;
+}
+
+static enum test_result test_databus(struct stm32mp1_ddrctl *ctl,
+				     struct stm32mp1_ddrphy *phy,
+				     char *string, int argc, char *argv[])
+{
+	u32 addr;
+	u32 error;
+
+	if (get_addr(string, argc, argv, 0, &addr))
+		return TEST_ERROR;
+	error = databus((u32 *)addr);
+	if (error) {
+		sprintf(string, "0x%x: error for bits 0x%x",
+			addr, error);
+		return TEST_FAILED;
+	}
+	sprintf(string, "address 0x%x", addr);
+	return TEST_PASSED;
+}
+
+static enum test_result test_addressbus(struct stm32mp1_ddrctl *ctl,
+					struct stm32mp1_ddrphy *phy,
+					char *string, int argc, char *argv[])
+{
+	u32 addr;
+	u32 bufsize;
+	u32 error;
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+	if (!is_power_of_2(bufsize)) {
+		sprintf(string, "size 0x%x is not a power of 2",
+			(u32)bufsize);
+		return TEST_ERROR;
+	}
+	if (get_addr(string, argc, argv, 1, &addr))
+		return TEST_ERROR;
+
+	error = (u32)addressbus((u32 *)addr, bufsize);
+	if (error) {
+		sprintf(string, "0x%x: error for address 0x%x",
+			addr, error);
+		return TEST_FAILED;
+	}
+	sprintf(string, "address 0x%x, size 0x%x",
+		addr, bufsize);
+	return TEST_PASSED;
+}
+
+static enum test_result test_memdevice(struct stm32mp1_ddrctl *ctl,
+				       struct stm32mp1_ddrphy *phy,
+				       char *string, int argc, char *argv[])
+{
+	u32 addr;
+	size_t bufsize;
+	u32 error;
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 1, &addr))
+		return TEST_ERROR;
+	error = (u32)memdevice((u32 *)addr, (unsigned long)bufsize);
+	if (error) {
+		sprintf(string, "0x%x: error for address 0x%x",
+			addr, error);
+		return TEST_FAILED;
+	}
+	sprintf(string, "address 0x%x, size 0x%x",
+		addr, bufsize);
+	return TEST_PASSED;
+}
+
+/**********************************************************************
+ *
+ * Function:    sso
+ *
+ * Description: Test the Simultaneous Switching Output.
+ *              Verifies succes sive reads and writes to the same memory word,
+ *              holding one bit constant while toggling all other data bits
+ *              simultaneously
+ *              => stress the data bus over an address range
+ *
+ *              The CPU writes to each address in the given range.
+ *              For each bit, first the CPU holds the bit at 1 while
+ *              toggling the other bits, and then the CPU holds the bit at 0
+ *              while toggling the other bits.
+ *              After each write, the CPU reads the address that was written
+ *              to verify that it contains the correct data
+ *
+ **********************************************************************/
+static enum test_result test_sso(struct stm32mp1_ddrctl *ctl,
+				 struct stm32mp1_ddrphy *phy,
+				 char *string, int argc, char *argv[])
+{
+	int i, j;
+	u32 addr, bufsize, remaining, offset;
+	u32 error = 0;
+	u32 data;
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 1, &addr))
+		return TEST_ERROR;
+
+	printf("running sso at 0x%x length 0x%x", addr, bufsize);
+	offset = addr;
+	remaining = bufsize;
+	while (remaining) {
+		for (i = 0; i < 32; i++) {
+			/* write pattern. */
+			for (j = 0; j < 6; j++) {
+				switch (j) {
+				case 0:
+				case 2:
+					data = 1 << i;
+					break;
+				case 3:
+				case 5:
+					data = ~(1 << i);
+					break;
+				case 1:
+					data = ~0x0;
+					break;
+				case 4:
+					data = 0x0;
+					break;
+				}
+
+				writel(data, offset);
+				error = check_addr(offset, data);
+				if (error)
+					goto end;
+			}
+		}
+		offset += 4;
+		remaining -= 4;
+		if (progress(offset << 7))
+			goto end;
+	}
+	puts("\n");
+
+end:
+	if (error) {
+		sprintf(string, "error for pattern 0x%x @0x%x",
+			data, offset);
+		return TEST_FAILED;
+	}
+	sprintf(string, "no error for sso at 0x%x length 0x%x", addr, bufsize);
+	return TEST_PASSED;
+}
+
+/**********************************************************************
+ *
+ * Function:    Random
+ *
+ * Description: Verifies r/w with pseudo-ramdom value on one region
+ *              + write the region (individual access)
+ *              + memcopy to the 2nd region (try to use burst)
+ *              + verify the 2 regions
+ *
+ **********************************************************************/
+static enum test_result test_random(struct stm32mp1_ddrctl *ctl,
+				    struct stm32mp1_ddrphy *phy,
+				    char *string, int argc, char *argv[])
+{
+	u32 addr, offset, value = 0;
+	size_t bufsize;
+	u32 loop = 0, nb_loop;
+	u32 error = 0;
+	unsigned int seed;
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+	if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 2, &addr))
+		return TEST_ERROR;
+
+	printf("running %d loops at 0x%x\n", nb_loop, addr);
+	while (!error) {
+		seed = rand();
+		for (offset = addr; offset < addr + bufsize; offset += 4)
+			writel(rand(), offset);
+
+		memcpy((void *)addr + bufsize, (void *)addr, bufsize);
+
+		srand(seed);
+		for (offset = addr; offset < addr + 2 * bufsize; offset += 4) {
+			if (offset == (addr + bufsize))
+				srand(seed);
+			value = rand();
+			error = check_addr(offset, value);
+			if (error)
+				break;
+			if (progress(offset))
+				return TEST_FAILED;
+		}
+		if (test_loop_end(&loop, nb_loop, 100))
+			break;
+	}
+
+	if (error) {
+		sprintf(string,
+			"loop %d: error for address 0x%x: 0x%x expected 0x%x",
+			loop, offset, readl(offset), value);
+		return TEST_FAILED;
+	}
+	sprintf(string, "no error for %d loops, size 0x%x",
+		loop, bufsize);
+	return TEST_PASSED;
+}
+
+/**********************************************************************
+ *
+ * Function:    noise
+ *
+ * Description: Verifies r/w while forcing switching of all data bus lines.
+ *              optimised 4 iteration write/read/write/read cycles...
+ *              for pattern and inversed pattern
+ *
+ **********************************************************************/
+void do_noise(u32 addr, u32 pattern, u32 *result)
+{
+	__asm__("push {R0-R11}");
+	__asm__("mov r0, %0" : : "r" (addr));
+	__asm__("mov r1, %0" : : "r" (pattern));
+	__asm__("mov r11, %0" : : "r" (result));
+
+	__asm__("mvn r2, r1");
+
+	__asm__("str r1, [r0]");
+	__asm__("ldr r3, [r0]");
+	__asm__("str r2, [r0]");
+	__asm__("ldr r4, [r0]");
+
+	__asm__("str r1, [r0]");
+	__asm__("ldr r5, [r0]");
+	__asm__("str r2, [r0]");
+	__asm__("ldr r6, [r0]");
+
+	__asm__("str r1, [r0]");
+	__asm__("ldr r7, [r0]");
+	__asm__("str r2, [r0]");
+	__asm__("ldr r8, [r0]");
+
+	__asm__("str r1, [r0]");
+	__asm__("ldr r9, [r0]");
+	__asm__("str r2, [r0]");
+	__asm__("ldr r10, [r0]");
+
+	__asm__("stmia R11!, {R3-R10}");
+
+	__asm__("pop {R0-R11}");
+}
+
+static enum test_result test_noise(struct stm32mp1_ddrctl *ctl,
+				   struct stm32mp1_ddrphy *phy,
+				   char *string, int argc, char *argv[])
+{
+	u32 addr, pattern;
+	u32 result[8];
+	int i;
+	enum test_result res = TEST_PASSED;
+
+	if (get_pattern(string, argc, argv, 0, &pattern, 0xFFFFFFFF))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 1, &addr))
+		return TEST_ERROR;
+
+	printf("running noise for 0x%x at 0x%x\n", pattern, addr);
+
+	do_noise(addr, pattern, result);
+
+	for (i = 0; i < 0x8;) {
+		if (check_addr((u32)&result[i++], pattern))
+			res = TEST_FAILED;
+		if (check_addr((u32)&result[i++], ~pattern))
+			res = TEST_FAILED;
+	}
+
+	return res;
+}
+
+/**********************************************************************
+ *
+ * Function:    noise_burst
+ *
+ * Description: Verifies r/w while forcing switching of all data bus lines.
+ *              optimised write loop witrh store multiple to use burst
+ *              for pattern and inversed pattern
+ *
+ **********************************************************************/
+void do_noise_burst(u32 addr, u32 pattern, size_t bufsize)
+{
+	__asm__("push {R0-R9}");
+	__asm__("mov r0, %0" : : "r" (addr));
+	__asm__("mov r1, %0" : : "r" (pattern));
+	__asm__("mov r9, %0" : : "r" (bufsize));
+
+	__asm__("mvn r2, r1");
+	__asm__("mov r3, r1");
+	__asm__("mov r4, r2");
+	__asm__("mov r5, r1");
+	__asm__("mov r6, r2");
+	__asm__("mov r7, r1");
+	__asm__("mov r8, r2");
+
+	__asm__("loop1:");
+	__asm__("stmia R0!, {R1-R8}");
+	__asm__("stmia R0!, {R1-R8}");
+	__asm__("stmia R0!, {R1-R8}");
+	__asm__("stmia R0!, {R1-R8}");
+	__asm__("subs r9, r9, #128");
+	__asm__("bge loop1");
+	__asm__("pop {R0-R9}");
+}
+
+/* chunk size enough to allow interruption with Ctrl-C*/
+#define CHUNK_SIZE	0x8000000
+static enum test_result test_noise_burst(struct stm32mp1_ddrctl *ctl,
+					 struct stm32mp1_ddrphy *phy,
+					 char *string, int argc, char *argv[])
+{
+	u32 addr, offset, pattern;
+	size_t bufsize, remaining, size;
+	int i;
+	enum test_result res = TEST_PASSED;
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+	if (get_pattern(string, argc, argv, 1, &pattern, 0xFFFFFFFF))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 2, &addr))
+		return TEST_ERROR;
+
+	printf("running noise burst for 0x%x at 0x%x + 0x%x",
+	       pattern, addr, bufsize);
+
+	offset = addr;
+	remaining = bufsize;
+	size = CHUNK_SIZE;
+	while (remaining) {
+		if (remaining < size)
+			size = remaining;
+		do_noise_burst(offset, pattern, size);
+		remaining -= size;
+		offset += size;
+		if (progress(offset)) {
+			res = TEST_FAILED;
+			goto end;
+		}
+	}
+	puts("\ncheck buffer");
+	for (i = 0; i < bufsize;) {
+		if (check_addr(addr + i, pattern))
+			res = TEST_FAILED;
+		i += 4;
+		if (check_addr(addr + i, ~pattern))
+			res = TEST_FAILED;
+		i += 4;
+		if (progress(i)) {
+			res = TEST_FAILED;
+			goto end;
+		}
+	}
+end:
+	puts("\n");
+	return res;
+}
+
+/**********************************************************************
+ *
+ * Function:    pattern test
+ *
+ * Description: optimized loop for read/write pattern (array of 8 u32)
+ *
+ **********************************************************************/
+#define PATTERN_SIZE	8
+static enum test_result test_loop(const u32 *pattern, u32 *address,
+				  const u32 bufsize)
+{
+	int i;
+	int j;
+	enum test_result res = TEST_PASSED;
+	u32 *offset, testsize, remaining;
+
+	offset = address;
+	remaining = bufsize;
+	while (remaining) {
+		testsize = bufsize > 0x1000000 ? 0x1000000 : bufsize;
+
+		__asm__("push {R0-R10}");
+		__asm__("mov r0, %0" : : "r" (pattern));
+		__asm__("mov r1, %0" : : "r" (offset));
+		__asm__("mov r2, %0" : : "r" (testsize));
+		__asm__("ldmia r0!, {R3-R10}");
+
+		__asm__("loop2:");
+		__asm__("stmia r1!, {R3-R10}");
+		__asm__("stmia r1!, {R3-R10}");
+		__asm__("stmia r1!, {R3-R10}");
+		__asm__("stmia r1!, {R3-R10}");
+		__asm__("subs r2, r2, #8");
+		__asm__("bge loop2");
+		__asm__("pop {R0-R10}");
+
+		offset += testsize;
+		remaining -= testsize;
+		if (progress((u32)offset)) {
+			res = TEST_FAILED;
+			goto end;
+		}
+	}
+
+	puts("\ncheck buffer");
+	for (i = 0; i < bufsize; i += PATTERN_SIZE * 4) {
+		for (j = 0; j < PATTERN_SIZE; j++, address++)
+			if (check_addr((u32)address, pattern[j])) {
+				res = TEST_FAILED;
+				goto end;
+			}
+		if (progress(i)) {
+			res = TEST_FAILED;
+			goto end;
+		}
+	}
+
+end:
+	puts("\n");
+	return res;
+}
+
+const u32 pattern_div1_x16[PATTERN_SIZE] = {
+	0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,
+	0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF
+};
+
+const u32 pattern_div2_x16[PATTERN_SIZE] = {
+	0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
+	0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000
+};
+
+const u32 pattern_div4_x16[PATTERN_SIZE] = {
+	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000
+};
+
+const u32 pattern_div4_x32[PATTERN_SIZE] = {
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+const u32 pattern_mostly_zero_x16[PATTERN_SIZE] = {
+	0x00000000, 0x00000000, 0x00000000, 0x0000FFFF,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+const u32 pattern_mostly_zero_x32[PATTERN_SIZE] = {
+	0x00000000, 0x00000000, 0x00000000, 0xFFFFFFFF,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+const u32 pattern_mostly_one_x16[PATTERN_SIZE] = {
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000FFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
+};
+
+const u32 pattern_mostly_one_x32[PATTERN_SIZE] = {
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
+};
+
+#define NB_PATTERN	5
+static enum test_result test_freq_pattern(struct stm32mp1_ddrctl *ctl,
+					  struct stm32mp1_ddrphy *phy,
+					  char *string, int argc, char *argv[])
+{
+	const u32 * const patterns_x16[NB_PATTERN] = {
+		pattern_div1_x16,
+		pattern_div2_x16,
+		pattern_div4_x16,
+		pattern_mostly_zero_x16,
+		pattern_mostly_one_x16,
+	};
+	const u32 * const patterns_x32[NB_PATTERN] = {
+		pattern_div2_x16,
+		pattern_div4_x16,
+		pattern_div4_x32,
+		pattern_mostly_zero_x32,
+		pattern_mostly_one_x32
+	};
+	const char *patterns_comments[NB_PATTERN] = {
+		"switching at frequency F/1",
+		"switching at frequency F/2",
+		"switching at frequency F/4",
+		"mostly zero",
+		"mostly one"
+	};
+
+	enum test_result res = TEST_PASSED, pattern_res;
+	int i, bus_width;
+	const u32 **patterns;
+	u32 bufsize;
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+
+	switch (readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) {
+	case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
+	case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
+		bus_width = 16;
+		break;
+	default:
+		bus_width = 32;
+		break;
+	}
+
+	printf("running test pattern at 0x%08x length 0x%x width = %d\n",
+	       STM32_DDR_BASE, bufsize, bus_width);
+
+	patterns =
+		(const u32 **)(bus_width == 16 ? patterns_x16 : patterns_x32);
+
+	for (i = 0; i < NB_PATTERN; i++) {
+		printf("test data pattern %s:", patterns_comments[i]);
+		pattern_res = test_loop(patterns[i], (u32 *)STM32_DDR_BASE,
+					bufsize);
+		if (pattern_res != TEST_PASSED)	{
+			printf("Failed\n");
+			return pattern_res;
+		}
+		printf("Passed\n");
+	}
+
+	return res;
+}
+
+/**********************************************************************
+ *
+ * Function:    pattern test with size
+ *
+ * Description: loop for write pattern
+ *
+ **********************************************************************/
+
+static enum test_result test_loop_size(const u32 *pattern, u32 size,
+				       u32 *address,
+				       const u32 bufsize)
+{
+	int i, j;
+	enum test_result res = TEST_PASSED;
+	u32 *p = address;
+
+	for (i = 0; i < bufsize; i += size * 4) {
+		for (j = 0; j < size ; j++, p++)
+			*p = pattern[j];
+		if (progress(i)) {
+			res = TEST_FAILED;
+			goto end;
+		}
+	}
+
+	puts("\ncheck buffer");
+	p = address;
+	for (i = 0; i < bufsize; i += size * 4) {
+		for (j = 0; j < size; j++, p++)
+			if (check_addr((u32)p, pattern[j])) {
+				res = TEST_FAILED;
+				goto end;
+			}
+		if (progress(i)) {
+			res = TEST_FAILED;
+			goto end;
+		}
+	}
+
+end:
+	puts("\n");
+	return res;
+}
+
+static enum test_result test_checkboard(struct stm32mp1_ddrctl *ctl,
+					struct stm32mp1_ddrphy *phy,
+					char *string, int argc, char *argv[])
+{
+	enum test_result res = TEST_PASSED;
+	u32 bufsize, nb_loop, loop = 0, addr;
+	int i;
+
+	u32 checkboard[2] = {0x55555555, 0xAAAAAAAA};
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+	if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 2, &addr))
+		return TEST_ERROR;
+
+	printf("running %d loops at 0x%08x length 0x%x\n",
+	       nb_loop, addr, bufsize);
+	while (1) {
+		for (i = 0; i < 2; i++) {
+			res = test_loop_size(checkboard, 2, (u32 *)addr,
+					     bufsize);
+			if (res)
+				return res;
+			checkboard[0] = ~checkboard[0];
+			checkboard[1] = ~checkboard[1];
+		}
+		if (test_loop_end(&loop, nb_loop, 1))
+			break;
+	}
+	sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+		loop, addr, bufsize);
+
+	return res;
+}
+
+static enum test_result test_blockseq(struct stm32mp1_ddrctl *ctl,
+				      struct stm32mp1_ddrphy *phy,
+				      char *string, int argc, char *argv[])
+{
+	enum test_result res = TEST_PASSED;
+	u32 bufsize, nb_loop, loop = 0, addr, value;
+	int i;
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+	if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 2, &addr))
+		return TEST_ERROR;
+
+	printf("running %d loops at 0x%08x length 0x%x\n",
+	       nb_loop, addr, bufsize);
+	while (1) {
+		for (i = 0; i < 256; i++) {
+			value = i | i << 8 | i << 16 | i << 24;
+			printf("pattern = %08x", value);
+			res = test_loop_size(&value, 1, (u32 *)addr, bufsize);
+			if (res != TEST_PASSED)
+				return res;
+		}
+		if (test_loop_end(&loop, nb_loop, 1))
+			break;
+	}
+	sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+		loop, addr, bufsize);
+
+	return res;
+}
+
+static enum test_result test_walkbit0(struct stm32mp1_ddrctl *ctl,
+				      struct stm32mp1_ddrphy *phy,
+				      char *string, int argc, char *argv[])
+{
+	enum test_result res = TEST_PASSED;
+	u32 bufsize, nb_loop, loop = 0, addr, value;
+	int i;
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+	if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 2, &addr))
+		return TEST_ERROR;
+
+	printf("running %d loops at 0x%08x length 0x%x\n",
+	       nb_loop, addr, bufsize);
+	while (1) {
+		for (i = 0; i < 64; i++) {
+			if (i < 32)
+				value = 1 << i;
+			else
+				value = 1 << (63 - i);
+
+			printf("pattern = %08x", value);
+			res = test_loop_size(&value, 1, (u32 *)addr, bufsize);
+			if (res != TEST_PASSED)
+				return res;
+		}
+		if (test_loop_end(&loop, nb_loop, 1))
+			break;
+	}
+	sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+		loop, addr, bufsize);
+
+	return res;
+}
+
+static enum test_result test_walkbit1(struct stm32mp1_ddrctl *ctl,
+				      struct stm32mp1_ddrphy *phy,
+				      char *string, int argc, char *argv[])
+{
+	enum test_result res = TEST_PASSED;
+	u32 bufsize, nb_loop, loop = 0, addr, value;
+	int i;
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+	if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 2, &addr))
+		return TEST_ERROR;
+
+	printf("running %d loops at 0x%08x length 0x%x\n",
+	       nb_loop, addr, bufsize);
+	while (1) {
+		for (i = 0; i < 64; i++) {
+			if (i < 32)
+				value = ~(1 << i);
+			else
+				value = ~(1 << (63 - i));
+
+			printf("pattern = %08x", value);
+			res = test_loop_size(&value, 1, (u32 *)addr, bufsize);
+			if (res != TEST_PASSED)
+				return res;
+		}
+		if (test_loop_end(&loop, nb_loop, 1))
+			break;
+	}
+	sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+		loop, addr, bufsize);
+
+	return res;
+}
+
+/*
+ * try to catch bad bits which are dependent on the current values of
+ * surrounding bits in either the same word32
+ */
+static enum test_result test_bitspread(struct stm32mp1_ddrctl *ctl,
+				       struct stm32mp1_ddrphy *phy,
+				       char *string, int argc, char *argv[])
+{
+	enum test_result res = TEST_PASSED;
+	u32 bufsize, nb_loop, loop = 0, addr, bitspread[4];
+	int i, j;
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+	if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 2, &addr))
+		return TEST_ERROR;
+
+	printf("running %d loops at 0x%08x length 0x%x\n",
+	       nb_loop, addr, bufsize);
+	while (1) {
+		for (i = 1; i < 32; i++) {
+			for (j = 0; j < i; j++) {
+				if (i < 32)
+					bitspread[0] = (1 << i) | (1 << j);
+				else
+					bitspread[0] = (1 << (63 - i)) |
+						       (1 << (63 - j));
+				bitspread[1] = bitspread[0];
+				bitspread[2] = ~bitspread[0];
+				bitspread[3] = ~bitspread[0];
+				printf("pattern = %08x", bitspread[0]);
+
+				res = test_loop_size(bitspread, 4, (u32 *)addr,
+						     bufsize);
+				if (res != TEST_PASSED)
+					return res;
+			}
+		}
+		if (test_loop_end(&loop, nb_loop, 1))
+			break;
+	}
+	sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+		loop, addr, bufsize);
+
+	return res;
+}
+
+static enum test_result test_bitflip(struct stm32mp1_ddrctl *ctl,
+				     struct stm32mp1_ddrphy *phy,
+				     char *string, int argc, char *argv[])
+{
+	enum test_result res = TEST_PASSED;
+	u32 bufsize, nb_loop, loop = 0, addr;
+	int i;
+
+	u32 bitflip[4];
+
+	if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+		return TEST_ERROR;
+	if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+		return TEST_ERROR;
+	if (get_addr(string, argc, argv, 2, &addr))
+		return TEST_ERROR;
+
+	printf("running %d loops at 0x%08x length 0x%x\n",
+	       nb_loop, addr, bufsize);
+	while (1) {
+		for (i = 0; i < 32; i++) {
+			bitflip[0] = 1 << i;
+			bitflip[1] = bitflip[0];
+			bitflip[2] = ~bitflip[0];
+			bitflip[3] = bitflip[2];
+			printf("pattern = %08x", bitflip[0]);
+
+			res = test_loop_size(bitflip, 4, (u32 *)addr, bufsize);
+			if (res != TEST_PASSED)
+				return res;
+		}
+		if (test_loop_end(&loop, nb_loop, 1))
+			break;
+	}
+	sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+		loop, addr, bufsize);
+
+	return res;
+}
+
+/**********************************************************************
+ *
+ * Function: infinite read access to DDR
+ *
+ * Description: continuous read the same pattern at the same address
+ *
+ **********************************************************************/
+static enum test_result test_read(struct stm32mp1_ddrctl *ctl,
+				  struct stm32mp1_ddrphy *phy,
+				  char *string, int argc, char *argv[])
+{
+	u32 *addr;
+	u32 data;
+	u32 loop = 0;
+	bool random = false;
+
+	if (get_addr(string, argc, argv, 0, (u32 *)&addr))
+		return TEST_ERROR;
+
+	if ((u32)addr == ADDR_INVALID) {
+		printf("random ");
+		random = true;
+	}
+
+	printf("running at 0x%08x\n", (u32)addr);
+
+	while (1) {
+		if (random)
+			addr = (u32 *)(STM32_DDR_BASE +
+			       (rand() & (STM32_DDR_SIZE - 1) & ~0x3));
+		data = readl(addr);
+		if (test_loop_end(&loop, 0, 1000))
+			break;
+	}
+	sprintf(string, "0x%x: %x", (u32)addr, data);
+
+	return TEST_PASSED;
+}
+
+/**********************************************************************
+ *
+ * Function: infinite write access to DDR
+ *
+ * Description: continuous write the same pattern at the same address
+ *
+ **********************************************************************/
+static enum test_result test_write(struct stm32mp1_ddrctl *ctl,
+				   struct stm32mp1_ddrphy *phy,
+				   char *string, int argc, char *argv[])
+{
+	u32 *addr;
+	u32 data = 0xA5A5AA55;
+	u32 loop = 0;
+	bool random = false;
+
+	if (get_addr(string, argc, argv, 0, (u32 *)&addr))
+		return TEST_ERROR;
+
+	if ((u32)addr == ADDR_INVALID) {
+		printf("random ");
+		random = true;
+	}
+
+	printf("running at 0x%08x\n", (u32)addr);
+
+	while (1) {
+		if (random) {
+			addr = (u32 *)(STM32_DDR_BASE +
+			       (rand() & (STM32_DDR_SIZE - 1) & ~0x3));
+			data = rand();
+		}
+		writel(data, addr);
+		if (test_loop_end(&loop, 0, 1000))
+			break;
+	}
+	sprintf(string, "0x%x: %x", (u32)addr, data);
+
+	return TEST_PASSED;
+}
+
+#define NB_TEST_INFINITE 2
+static enum test_result test_all(struct stm32mp1_ddrctl *ctl,
+				 struct stm32mp1_ddrphy *phy,
+				 char *string, int argc, char *argv[])
+{
+	enum test_result res = TEST_PASSED, result;
+	int i, nb_error = 0;
+	u32 loop = 0, nb_loop;
+
+	if (get_nb_loop(string, argc, argv, 0, &nb_loop, 1))
+		return TEST_ERROR;
+
+	while (!nb_error) {
+		/* execute all the test except the lasts which are infinite */
+		for (i = 1; i < test_nb - NB_TEST_INFINITE; i++) {
+			printf("execute %d:%s\n", (int)i, test[i].name);
+			result = test[i].fct(ctl, phy, string, 0, NULL);
+			printf("result %d:%s = ", (int)i, test[i].name);
+			if (result != TEST_PASSED) {
+				nb_error++;
+				res = TEST_FAILED;
+				puts("Failed");
+			} else {
+				puts("Passed");
+			}
+			puts("\n\n");
+		}
+		printf("loop %d: %d/%d test failed\n\n\n",
+		       loop + 1, nb_error, test_nb - NB_TEST_INFINITE);
+		if (test_loop_end(&loop, nb_loop, 1))
+			break;
+	}
+	if (res != TEST_PASSED) {
+		sprintf(string, "loop %d: %d/%d test failed", loop, nb_error,
+			test_nb - NB_TEST_INFINITE);
+	} else {
+		sprintf(string, "loop %d: %d tests passed", loop,
+			test_nb - NB_TEST_INFINITE);
+	}
+	return res;
+}
+
+/****************************************************************
+ * TEST Description
+ ****************************************************************/
+
+const struct test_desc test[] = {
+	{test_all, "All", "[loop]", "Execute all tests", 1 },
+	{test_databus, "Simple DataBus", "[addr]",
+	 "Verifies each data line by walking 1 on fixed address",
+	 1
+	 },
+	{databuswalk0, "DataBusWalking0", "[loop] [addr]",
+	 "Verifies each data bus signal can be driven low (32 word burst)",
+	 2
+	},
+	{databuswalk1, "DataBusWalking1", "[loop] [addr]",
+	 "Verifies each data bus signal can be driven high (32 word burst)",
+	 2
+	},
+	{test_addressbus, "AddressBus", "[size] [addr]",
+	 "Verifies each relevant bits of the address and checking for aliasing",
+	 2
+	 },
+	{test_memdevice, "MemDevice", "[size] [addr]",
+	 "Test the integrity of a physical memory (test every storage bit in the region)",
+	 2
+	 },
+	{test_sso, "SimultaneousSwitchingOutput", "[size] [addr] ",
+	 "Stress the data bus over an address range",
+	 2
+	},
+	{test_noise, "Noise", "[pattern] [addr]",
+	 "Verifies r/w while forcing switching of all data bus lines.",
+	 3
+	},
+	{test_noise_burst, "NoiseBurst", "[size] [pattern] [addr]",
+	 "burst transfers while forcing switching of the data bus lines",
+	 3
+	},
+	{test_random, "Random", "[size] [loop] [addr]",
+	 "Verifies r/w and memcopy(burst for pseudo random value.",
+	 3
+	},
+	{test_freq_pattern, "FrequencySelectivePattern ", "[size]",
+	 "write & test patterns: Mostly Zero, Mostly One and F/n",
+	 1
+	},
+	{test_blockseq, "BlockSequential", "[size] [loop] [addr]",
+	 "test incremental pattern",
+	 3
+	},
+	{test_checkboard, "Checkerboard", "[size] [loop] [addr]",
+	 "test checker pattern",
+	 3
+	},
+	{test_bitspread, "BitSpread", "[size] [loop] [addr]",
+	 "test Bit Spread pattern",
+	 3
+	},
+	{test_bitflip, "BitFlip", "[size] [loop] [addr]",
+	 "test Bit Flip pattern",
+	 3
+	},
+	{test_walkbit0, "WalkingOnes", "[size] [loop] [addr]",
+	 "test Walking Ones pattern",
+	 3
+	},
+	{test_walkbit1, "WalkingZeroes", "[size] [loop] [addr]",
+	 "test Walking Zeroes pattern",
+	 3
+	},
+	/* need to the the 2 last one (infinite) : skipped for test all */
+	{test_read, "infinite read", "[addr]",
+	 "basic test : infinite read access", 1},
+	{test_write, "infinite write", "[addr]",
+	 "basic test : infinite write access", 1},
+};
+
+const int test_nb = ARRAY_SIZE(test);
diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.h b/drivers/ram/stm32mp1/stm32mp1_tests.h
new file mode 100644
index 0000000..55f5d6d
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_tests.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _RAM_STM32MP1_TESTS_H_
+#define _RAM_STM32MP1_TESTS_H_
+
+#include "stm32mp1_ddr_regs.h"
+
+enum test_result {
+	TEST_PASSED,
+	TEST_FAILED,
+	TEST_ERROR
+};
+
+struct test_desc {
+	enum test_result (*fct)(struct stm32mp1_ddrctl *ctl,
+				struct stm32mp1_ddrphy *phy,
+				char *string,
+				int argc, char *argv[]);
+	const char *name;
+	const char *usage;
+	const char *help;
+	u8 max_args;
+};
+
+extern const struct test_desc test[];
+extern const int test_nb;
+
+extern const struct test_desc tuning[];
+extern const int tuning_nb;
+
+#endif
diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c
new file mode 100644
index 0000000..4e1c1fa
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c
@@ -0,0 +1,1380 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+#include <common.h>
+#include <console.h>
+#include <clk.h>
+#include <ram.h>
+#include <reset.h>
+#include <asm/io.h>
+
+#include "stm32mp1_ddr_regs.h"
+#include "stm32mp1_ddr.h"
+#include "stm32mp1_tests.h"
+
+#define MAX_DQS_PHASE_IDX _144deg
+#define MAX_DQS_UNIT_IDX 7
+#define MAX_GSL_IDX 5
+#define MAX_GPS_IDX 3
+
+/* Number of bytes used in this SW. ( min 1--> max 4). */
+#define NUM_BYTES 4
+
+enum dqs_phase_enum {
+	_36deg = 0,
+	_54deg = 1,
+	_72deg = 2,
+	_90deg = 3,
+	_108deg = 4,
+	_126deg = 5,
+	_144deg = 6
+};
+
+/* BIST Result struct */
+struct BIST_result {
+	/* Overall test result:
+	 * 0 Fail (any bit failed) ,
+	 * 1 Success (All bits success)
+	 */
+	bool test_result;
+	/* 1: true, all fail /  0: False, not all bits fail */
+	bool all_bits_fail;
+	bool bit_i_test_result[8];  /* 0 fail / 1 success */
+};
+
+/* a struct that defines tuning parameters of a byte. */
+struct tuning_position {
+	u8 phase; /* DQS phase */
+	u8 unit; /* DQS unit delay */
+	u32 bits_delay; /* Bits deskew in this byte */
+};
+
+/* 36deg, 54deg, 72deg, 90deg, 108deg, 126deg, 144deg */
+const u8 dx_dll_phase[7] = {3, 2, 1, 0, 14, 13, 12};
+
+static u8 BIST_error_max = 1;
+static u32 BIST_seed = 0x1234ABCD;
+
+static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl)
+{
+	u32 data_bus = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
+	u8 nb_bytes = NUM_BYTES;
+
+	switch (data_bus) {
+	case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
+		nb_bytes /= 2;
+		break;
+	case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
+		nb_bytes /= 4;
+		break;
+	default:
+		break;
+	}
+
+	return nb_bytes;
+}
+
+static void itm_soft_reset(struct stm32mp1_ddrphy *phy)
+{
+	stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
+}
+
+/* Read DQ unit delay register and provides the retrieved value for DQS
+ * We are assuming that we have the same delay when clocking
+ * by DQS and when clocking by DQSN
+ */
+static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
+{
+	u32 index;
+	u32 addr = DXNDQTR(phy, byte);
+
+	/* We are assuming that we have the same delay when clocking by DQS
+	 * and when clocking by DQSN : use only the low bits
+	 */
+	index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
+		& DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
+
+	pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
+		 __func__, addr, readl(addr), index);
+
+	return index;
+}
+
+/* Sets the DQS phase delay for a byte lane.
+ *phase delay is specified by giving the index of the desired delay
+ * in the dx_dll_phase array.
+ */
+static void DQS_phase_delay(struct stm32mp1_ddrphy *phy, u8 byte, u8 phase_idx)
+{
+	u8 sdphase_val = 0;
+
+	/*	Write DXNDLLCR.SDPHASE = dx_dll_phase(phase_index); */
+	sdphase_val = dx_dll_phase[phase_idx];
+	clrsetbits_le32(DXNDLLCR(phy, byte),
+			DDRPHYC_DXNDLLCR_SDPHASE_MASK,
+			sdphase_val << DDRPHYC_DXNDLLCR_SDPHASE_SHIFT);
+}
+
+/* Sets the DQS unit delay for a byte lane.
+ * unit delay is specified by giving the index of the desired delay
+ * for dgsdly and dqsndly (same value).
+ */
+static void DQS_unit_delay(struct stm32mp1_ddrphy *phy,
+			   u8 byte, u8 unit_dly_idx)
+{
+	/* Write the same value in DXNDQSTR.DQSDLY and DXNDQSTR.DQSNDLY */
+	clrsetbits_le32(DXNDQSTR(phy, byte),
+			DDRPHYC_DXNDQSTR_DQSDLY_MASK |
+			DDRPHYC_DXNDQSTR_DQSNDLY_MASK,
+			(unit_dly_idx << DDRPHYC_DXNDQSTR_DQSDLY_SHIFT) |
+			(unit_dly_idx << DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT));
+
+	/* After changing this value, an ITM soft reset (PIR.ITMSRST=1,
+	 * plus PIR.INIT=1) must be issued.
+	 */
+	stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
+}
+
+/* Sets the DQ unit delay for a bit line in particular byte lane.
+ * unit delay is specified by giving the desired delay
+ */
+static void set_DQ_unit_delay(struct stm32mp1_ddrphy *phy,
+			      u8 byte, u8 bit,
+			      u8 dq_delay_index)
+{
+	u8 dq_bit_delay_val = dq_delay_index | (dq_delay_index << 2);
+
+	/* same value on delay for clock DQ an DQS_b */
+	clrsetbits_le32(DXNDQTR(phy, byte),
+			DDRPHYC_DXNDQTR_DQDLY_MASK
+			<< DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit),
+			dq_bit_delay_val << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit));
+}
+
+static void set_r0dgsl_delay(struct stm32mp1_ddrphy *phy,
+			     u8 byte, u8 r0dgsl_idx)
+{
+	clrsetbits_le32(DXNDQSTR(phy, byte),
+			DDRPHYC_DXNDQSTR_R0DGSL_MASK,
+			r0dgsl_idx << DDRPHYC_DXNDQSTR_R0DGSL_SHIFT);
+}
+
+static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy,
+			     u8 byte, u8 r0dgps_idx)
+{
+	clrsetbits_le32(DXNDQSTR(phy, byte),
+			DDRPHYC_DXNDQSTR_R0DGPS_MASK,
+			r0dgps_idx << DDRPHYC_DXNDQSTR_R0DGPS_SHIFT);
+}
+
+/* Basic BIST configuration for data lane tests. */
+static void config_BIST(struct stm32mp1_ddrphy *phy)
+{
+	/* Selects the SDRAM bank address to be used during BIST. */
+	u32 bbank = 0;
+	/* Selects the SDRAM row address to be used during BIST. */
+	u32 brow = 0;
+	/* Selects the SDRAM column address to be used during BIST. */
+	u32 bcol = 0;
+	/* Selects the value by which the SDRAM address is incremented
+	 * for each write/read access.
+	 */
+	u32 bainc = 0x00000008;
+	/* Specifies the maximum SDRAM rank to be used during BIST.
+	 * The default value is set to maximum ranks minus 1.
+	 * must be 0 with single rank
+	 */
+	u32 bmrank = 0;
+	/* Selects the SDRAM rank to be used during BIST.
+	 * must be 0 with single rank
+	 */
+	u32 brank = 0;
+	/* Specifies the maximum SDRAM bank address to be used during
+	 * BIST before the address & increments to the next rank.
+	 */
+	u32 bmbank = 1;
+	/* Specifies the maximum SDRAM row address to be used during
+	 * BIST before the address & increments to the next bank.
+	 */
+	u32 bmrow = 0x7FFF; /* To check */
+	/* Specifies the maximum SDRAM column address to be used during
+	 * BIST before the address & increments to the next row.
+	 */
+	u32 bmcol = 0x3FF;  /* To check */
+	u32 bmode_conf = 0x00000001;  /* DRam mode */
+	u32 bdxen_conf = 0x00000001;  /* BIST on Data byte */
+	u32 bdpat_conf = 0x00000002;  /* Select LFSR pattern */
+
+	/*Setup BIST for DRAM mode,  and LFSR-random data pattern.*/
+	/*Write BISTRR.BMODE = 1?b1;*/
+	/*Write BISTRR.BDXEN = 1?b1;*/
+	/*Write BISTRR.BDPAT = 2?b10;*/
+
+	/* reset BIST */
+	writel(0x3, &phy->bistrr);
+
+	writel((bmode_conf << 3) | (bdxen_conf << 14) | (bdpat_conf << 17),
+	       &phy->bistrr);
+
+	/*Setup BIST Word Count*/
+	/*Write BISTWCR.BWCNT = 16?b0008;*/
+	writel(0x00000200, &phy->bistwcr); /* A multiple of BL/2 */
+
+	writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0);
+	writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1);
+
+	/* To check this line : */
+	writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2);
+}
+
+/* Select the Byte lane to be tested by BIST. */
+static void BIST_datx8_sel(struct stm32mp1_ddrphy *phy, u8 datx8)
+{
+	clrsetbits_le32(&phy->bistrr,
+			DDRPHYC_BISTRR_BDXSEL_MASK,
+			datx8 << DDRPHYC_BISTRR_BDXSEL_SHIFT);
+
+	/*(For example, selecting Byte Lane 3, BISTRR.BDXSEL = 4?b0011)*/
+	/* Write BISTRR.BDXSEL = datx8; */
+}
+
+/* Perform BIST Write_Read test on a byte lane and return test result. */
+static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte,
+		      struct BIST_result *bist)
+{
+	bool result = true; /* BIST_SUCCESS */
+	u32 cnt = 0;
+	u32 error = 0;
+
+	bist->test_result = true;
+
+run:
+	itm_soft_reset(phy);
+
+	/*Perform BIST Reset*/
+	/* Write BISTRR.BINST = 3?b011; */
+	clrsetbits_le32(&phy->bistrr,
+			0x00000007,
+			0x00000003);
+
+	/*Re-seed LFSR*/
+	/* Write BISTLSR.SEED = 32'h1234ABCD; */
+	if (BIST_seed)
+		writel(BIST_seed, &phy->bistlsr);
+	else
+		writel(rand(), &phy->bistlsr);
+
+	/* some delay to reset BIST */
+	mdelay(1);
+
+	/*Perform BIST Run*/
+	clrsetbits_le32(&phy->bistrr,
+			0x00000007,
+			0x00000001);
+	/* Write BISTRR.BINST = 3?b001; */
+
+	/* Wait for a number of CTL clocks before reading BIST register*/
+	/* Wait 300 ctl_clk cycles;  ... IS it really needed?? */
+	/* Perform BIST Instruction Stop*/
+	/* Write BISTRR.BINST = 3?b010;*/
+
+	/* poll on BISTGSR.BDONE. If 0, wait.  ++TODO Add timeout */
+	while (!(readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDDONE))
+		;
+
+	/*Check if received correct number of words*/
+	/* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */
+	if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT) ==
+	    readl(&phy->bistwcr)) {
+		/*Determine if there is a data comparison error*/
+		/* if (Read BISTGSR.BDXERR = 1?b0) */
+		if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR)
+			result = false; /* BIST_FAIL; */
+		else
+			result = true; /* BIST_SUCCESS; */
+	} else {
+		result = false; /* BIST_FAIL; */
+	}
+
+	/* loop while success */
+	cnt++;
+	if (result && cnt != 1000)
+		goto run;
+
+	if (!result)
+		error++;
+
+	if (error < BIST_error_max) {
+		if (cnt != 1000)
+			goto run;
+		bist->test_result = true;
+	} else {
+		bist->test_result = false;
+	}
+}
+
+/* After running the deskew algo, this function applies the new DQ delays
+ * by reading them from the array "deskew_delay"and writing in PHY registers.
+ * The bits that are not deskewed parfectly (too much skew on them,
+ * or data eye very wide) are marked in the array deskew_non_converge.
+ */
+static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
+				 u8 deskew_delay[NUM_BYTES][8],
+				 u8 deskew_non_converge[NUM_BYTES][8])
+{
+	u8  bit_i;
+	u8  index;
+
+	for (bit_i = 0; bit_i < 8; bit_i++) {
+		set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
+		index = DQ_unit_index(phy, byte, bit_i);
+		pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
+			 byte, bit_i, deskew_delay[byte][bit_i],
+			 index, index - 3);
+		printf("Byte %d, bit %d, DQ delay = %d",
+		       byte, bit_i, deskew_delay[byte][bit_i]);
+		if (deskew_non_converge[byte][bit_i] == 1)
+			pr_debug(" - not converged : still more skew");
+		printf("\n");
+	}
+}
+
+/* DQ Bit de-skew algorithm.
+ * Deskews data lines as much as possible.
+ * 1. Add delay to DQS line until finding the failure
+ *    (normally a hold time violation)
+ * 2. Reduce DQS line by small steps until finding the very first time
+ *    we go back to "Pass" condition.
+ * 3. For each DQ line, Reduce DQ delay until finding the very first failure
+ *    (normally a hold time fail)
+ * 4. When all bits are at their first failure delay, we can consider them
+ *    aligned.
+ * Handle conrer situation (Can't find Pass-fail, or fail-pass transitions
+ * at any step)
+ * TODO Provide a return Status. Improve doc
+ */
+static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
+				   struct stm32mp1_ddrphy *phy, char *string)
+{
+	/* New DQ delay value (index), set during Deskew algo */
+	u8 deskew_delay[NUM_BYTES][8];
+	/*If there is still skew on a bit, mark this bit. */
+	u8 deskew_non_converge[NUM_BYTES][8];
+	struct BIST_result result;
+	s8 dqs_unit_delay_index = 0;
+	u8 datx8 = 0;
+	u8 bit_i = 0;
+	s8 phase_idx = 0;
+	s8 bit_i_delay_index = 0;
+	u8 success = 0;
+	struct tuning_position last_right_ok;
+	u8 force_stop = 0;
+	u8 fail_found;
+	u8 error = 0;
+	u8 nb_bytes = get_nb_bytes(ctl);
+	/* u8 last_pass_dqs_unit = 0; */
+
+	memset(deskew_delay, 0, sizeof(deskew_delay));
+	memset(deskew_non_converge, 0, sizeof(deskew_non_converge));
+
+	/*Disable DQS Drift Compensation*/
+	clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
+	/*Disable all bytes*/
+	/* Disable automatic power down of DLL and IOs when disabling
+	 * a byte (To avoid having to add programming and  delay
+	 * for a DLL re-lock when later re-enabling a disabled Byte Lane)
+	 */
+	clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
+
+	/* Disable all data bytes */
+	clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
+	clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
+	clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
+	clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
+
+	/* Config the BIST block */
+	config_BIST(phy);
+	pr_debug("BIST Config done.\n");
+
+	/* Train each byte */
+	for (datx8 = 0; datx8 < nb_bytes; datx8++) {
+		if (ctrlc()) {
+			sprintf(string, "interrupted at byte %d/%d, error=%d",
+				datx8 + 1, nb_bytes, error);
+			return TEST_FAILED;
+		}
+		pr_debug("\n======================\n");
+		pr_debug("Start deskew byte %d .\n", datx8);
+		pr_debug("======================\n");
+		/* Enable Byte (DXNGCR, bit DXEN) */
+		setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
+
+		/* Select the byte lane for comparison of read data */
+		BIST_datx8_sel(phy, datx8);
+
+		/* Set all DQDLYn to maximum value. All bits within the byte
+		 * will be delayed with DQSTR = 2 instead of max = 3
+		 * to avoid inter bits fail influence
+		 */
+		writel(0xAAAAAAAA, DXNDQTR(phy, datx8));
+
+		/* Set the DQS phase delay to 90 DEG (default).
+		 * What is defined here is the index of the desired config
+		 * in the PHASE array.
+		 */
+		phase_idx = _90deg;
+
+		/* Set DQS unit delay to the max value. */
+		dqs_unit_delay_index = MAX_DQS_UNIT_IDX;
+		DQS_unit_delay(phy, datx8, dqs_unit_delay_index);
+		DQS_phase_delay(phy, datx8, phase_idx);
+
+		/* Issue a DLL soft reset */
+		clrbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
+		setbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
+
+		/* Test this typical init condition */
+		BIST_test(phy, datx8, &result);
+		success = result.test_result;
+
+		/* If the test pass in this typical condition,
+		 * start the algo with it.
+		 * Else, look for Pass init condition
+		 */
+		if (!success) {
+			pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
+			success = 0; /* init */
+			/* Make sure we start with a PASS condition before
+			 * looking for a fail condition.
+			 * Find the first PASS PHASE condition
+			 */
+
+			/* escape if we find a PASS */
+			pr_debug("increase Phase idx\n");
+			while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
+				DQS_phase_delay(phy, datx8, phase_idx);
+				BIST_test(phy, datx8, &result);
+				success = result.test_result;
+				phase_idx++;
+			}
+			/* if ended with success
+			 * ==>> Restore the fist success condition
+			 */
+			if (success)
+				phase_idx--; /* because it ended with ++ */
+		}
+		if (ctrlc()) {
+			sprintf(string, "interrupted at byte %d/%d, error=%d",
+				datx8 + 1, nb_bytes, error);
+			return TEST_FAILED;
+		}
+		/* We couldn't find a successful condition, its seems
+		 * we have hold violation, lets try reduce DQS_unit Delay
+		 */
+		if (!success) {
+			/* We couldn't find a successful condition, its seems
+			 * we have hold violation, lets try reduce DQS_unit
+			 * Delay
+			 */
+			pr_debug("Still fail. Try decrease DQS Unit delay\n");
+
+			phase_idx = 0;
+			dqs_unit_delay_index = 0;
+			DQS_phase_delay(phy, datx8, phase_idx);
+
+			/* escape if we find a PASS */
+			while (!success &&
+			       (dqs_unit_delay_index <=
+				MAX_DQS_UNIT_IDX)) {
+				DQS_unit_delay(phy, datx8,
+					       dqs_unit_delay_index);
+				BIST_test(phy, datx8, &result);
+				success = result.test_result;
+				dqs_unit_delay_index++;
+			}
+			if (success) {
+				/* Restore the first success condition*/
+				dqs_unit_delay_index--;
+				/* last_pass_dqs_unit = dqs_unit_delay_index;*/
+				DQS_unit_delay(phy, datx8,
+					       dqs_unit_delay_index);
+			} else {
+				/* No need to continue,
+				 * there is no pass region.
+				 */
+				force_stop = 1;
+			}
+		}
+
+		/* There is an initial PASS condition
+		 * Look for the first failing condition by PHASE stepping.
+		 * This part of the algo can finish without converging.
+		 */
+		if (force_stop) {
+			printf("Result: Failed ");
+			printf("[Cannot Deskew lines, ");
+			printf("there is no PASS region]\n");
+			error++;
+			continue;
+		}
+		if (ctrlc()) {
+			sprintf(string, "interrupted at byte %d/%d, error=%d",
+				datx8 + 1, nb_bytes, error);
+			return TEST_FAILED;
+		}
+
+		pr_debug("there is a pass region for phase idx %d\n",
+			 phase_idx);
+		pr_debug("Step1: Find the first failing condition\n");
+		/* Look for the first failing condition by PHASE stepping.
+		 * This part of the algo can finish without converging.
+		 */
+
+		/* escape if we find a fail (hold time violation)
+		 * condition at any bit or if out of delay range.
+		 */
+		while (success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
+			DQS_phase_delay(phy, datx8, phase_idx);
+			BIST_test(phy, datx8, &result);
+			success = result.test_result;
+			phase_idx++;
+		}
+		if (ctrlc()) {
+			sprintf(string, "interrupted at byte %d/%d, error=%d",
+				datx8 + 1, nb_bytes, error);
+			return TEST_FAILED;
+		}
+
+		/* if the loop ended with a failing condition at any bit,
+		 * lets look for the first previous success condition by unit
+		 * stepping (minimal delay)
+		 */
+		if (!success) {
+			pr_debug("Fail region (PHASE) found phase idx %d\n",
+				 phase_idx);
+			pr_debug("Let's look for first success by DQS Unit steps\n");
+			/* This part, the algo always converge */
+			phase_idx--;
+
+			/* escape if we find a success condition
+			 * or if out of delay range.
+			 */
+			while (!success && dqs_unit_delay_index >= 0) {
+				DQS_unit_delay(phy, datx8,
+					       dqs_unit_delay_index);
+				BIST_test(phy, datx8, &result);
+				success = result.test_result;
+				dqs_unit_delay_index--;
+			}
+			/* if the loop ended with a success condition,
+			 * the last delay Right OK (before hold violation)
+			 *  condition is then defined as following:
+			 */
+			if (success) {
+				/* Hold the dely parameters of the the last
+				 * delay Right OK condition.
+				 * -1 to get back to current condition
+				 */
+				last_right_ok.phase = phase_idx;
+				/*+1 to get back to current condition */
+				last_right_ok.unit = dqs_unit_delay_index + 1;
+				last_right_ok.bits_delay = 0xFFFFFFFF;
+				pr_debug("Found %d\n", dqs_unit_delay_index);
+			} else {
+				/* the last OK condition is then with the
+				 * previous phase_idx.
+				 * -2 instead of -1 because at the last
+				 * iteration of the while(),
+				 * we incremented phase_idx
+				 */
+				last_right_ok.phase = phase_idx - 1;
+				/* Nominal+1. Because we want the previous
+				 * delay after reducing the phase delay.
+				 */
+				last_right_ok.unit = 1;
+				last_right_ok.bits_delay = 0xFFFFFFFF;
+				pr_debug("Not Found : try previous phase %d\n",
+					 phase_idx - 1);
+
+				DQS_phase_delay(phy, datx8, phase_idx - 1);
+				dqs_unit_delay_index = 0;
+				success = true;
+				while (success &&
+				       (dqs_unit_delay_index <
+					MAX_DQS_UNIT_IDX)) {
+					DQS_unit_delay(phy, datx8,
+						       dqs_unit_delay_index);
+					BIST_test(phy, datx8, &result);
+					success = result.test_result;
+					dqs_unit_delay_index++;
+					pr_debug("dqs_unit_delay_index = %d, result = %d\n",
+						 dqs_unit_delay_index, success);
+				}
+
+				if (!success) {
+					last_right_ok.unit =
+						 dqs_unit_delay_index - 1;
+				} else {
+					last_right_ok.unit = 0;
+					pr_debug("ERROR: failed region not FOUND");
+				}
+			}
+		} else {
+			/* we can't find a failing  condition at all bits
+			 * ==> Just hold the last test condition
+			 * (the max DQS delay)
+			 * which is the most likely,
+			 * the closest to a hold violation
+			 * If we can't find a Fail condition after
+			 * the Pass region, stick at this position
+			 * In order to have max chances to find a fail
+			 * when reducing DQ delays.
+			 */
+			last_right_ok.phase = MAX_DQS_PHASE_IDX;
+			last_right_ok.unit = MAX_DQS_UNIT_IDX;
+			last_right_ok.bits_delay = 0xFFFFFFFF;
+			pr_debug("Can't find the a fail condition\n");
+		}
+
+		/* step 2:
+		 * if we arrive at this stage, it means that we found the last
+		 * Right OK condition (by tweeking the DQS delay). Or we simply
+		 * pushed DQS delay to the max
+		 * This means that by reducing the delay on some DQ bits,
+		 * we should find a failing condition.
+		 */
+		printf("Byte %d, DQS unit = %d, phase = %d\n",
+		       datx8, last_right_ok.unit, last_right_ok.phase);
+		pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
+			 last_right_ok.unit, last_right_ok.phase,
+			 last_right_ok.bits_delay);
+
+		/* Restore the last_right_ok condtion. */
+		DQS_unit_delay(phy, datx8, last_right_ok.unit);
+		DQS_phase_delay(phy, datx8, last_right_ok.phase);
+		writel(last_right_ok.bits_delay, DXNDQTR(phy, datx8));
+
+		/* train each bit
+		 * reduce delay on each bit, and perform a write/read test
+		 * and stop at the very first time it fails.
+		 * the goal is the find the first failing condition
+		 * for each bit.
+		 * When we achieve this condition<  for all the bits,
+		 * we are sure they are aligned (+/- step resolution)
+		 */
+		fail_found = 0;
+		for (bit_i = 0; bit_i < 8; bit_i++) {
+			if (ctrlc()) {
+				sprintf(string,
+					"interrupted at byte %d/%d, error=%d",
+					datx8 + 1, nb_bytes, error);
+				return error;
+			}
+			pr_debug("deskewing bit %d:\n", bit_i);
+			success = 1; /* init */
+			/* Set all DQDLYn to maximum value.
+			 * Only bit_i will be down-delayed
+			 * ==> if we have a fail, it will be definitely
+			 *     from bit_i
+			 */
+			writel(0xFFFFFFFF, DXNDQTR(phy, datx8));
+			/* Arriving at this stage,
+			 * we have a success condition with delay = 3;
+			 */
+			bit_i_delay_index = 3;
+
+			/* escape if bit delay is out of range or
+			 * if a fatil occurs
+			 */
+			while ((bit_i_delay_index >= 0) && success) {
+				set_DQ_unit_delay(phy, datx8,
+						  bit_i,
+						  bit_i_delay_index);
+				BIST_test(phy, datx8, &result);
+				success = result.test_result;
+				bit_i_delay_index--;
+			}
+
+			/* if escape with a fail condition
+			 * ==> save this position for bit_i
+			 */
+			if (!success) {
+				/* save the delay position.
+				 * Add 1 because the while loop ended with a --,
+				 * and that we need to hold the last success
+				 *  delay
+				 */
+				deskew_delay[datx8][bit_i] =
+					bit_i_delay_index + 2;
+				if (deskew_delay[datx8][bit_i] > 3)
+					deskew_delay[datx8][bit_i] = 3;
+
+				/* A flag that states we found at least a fail
+				 * at one bit.
+				 */
+				fail_found = 1;
+				pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
+					 bit_i, bit_i_delay_index + 1,
+					 datx8, bit_i,
+					 deskew_delay[datx8][bit_i]);
+			} else {
+				/* if we can find a success condition by
+				 * back-delaying this bit, just set the delay
+				 * to 0 (the best deskew
+				 * possible) and mark the bit.
+				 */
+				deskew_delay[datx8][bit_i] = 0;
+				/* set a flag that will be used later
+				 * in the report.
+				 */
+				deskew_non_converge[datx8][bit_i] = 1;
+				pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
+					 bit_i, datx8, bit_i,
+					 deskew_delay[datx8][bit_i]);
+			}
+		}
+		pr_debug("**********byte %d tuning complete************\n",
+			 datx8);
+		/* If we can't find any failure by back delaying DQ lines,
+		 * hold the default values
+		 */
+		if (!fail_found) {
+			for (bit_i = 0; bit_i < 8; bit_i++)
+				deskew_delay[datx8][bit_i] = 0;
+			pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
+		}
+
+		apply_deskew_results(phy, datx8, deskew_delay,
+				     deskew_non_converge);
+		/* Restore nominal value for DQS delay */
+		DQS_phase_delay(phy, datx8, 3);
+		DQS_unit_delay(phy, datx8, 3);
+		/* disable byte after byte bits deskew */
+		clrbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
+	}  /* end of byte deskew */
+
+	/* re-enable all data bytes */
+	setbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
+	setbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
+	setbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
+	setbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
+
+	if (error) {
+		sprintf(string, "error = %d", error);
+		return TEST_FAILED;
+	}
+
+	return TEST_PASSED;
+} /* end function */
+
+/* Trim DQS timings and set it in the centre of data eye.
+ * Look for a PPPPF region, then look for a FPPP region and finally select
+ * the mid of the FPPPPPF region
+ */
+static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
+				     struct stm32mp1_ddrphy *phy, char *string)
+{
+	/*Stores the DQS trim values (PHASE index, unit index) */
+	u8 eye_training_val[NUM_BYTES][2];
+	u8 byte = 0;
+	struct BIST_result result;
+	s8 dqs_unit_delay_index = 0;
+	s8 phase_idx = 0;
+	s8 dqs_unit_delay_index_pass = 0;
+	s8 phase_idx_pass = 0;
+	u8 success = 0;
+	u8 left_phase_bound_found, right_phase_bound_found;
+	u8 left_unit_bound_found, right_unit_bound_found;
+	u8 left_bound_found, right_bound_found;
+	struct tuning_position left_bound, right_bound;
+	u8 error = 0;
+	u8 nb_bytes = get_nb_bytes(ctl);
+
+	/*Disable DQS Drift Compensation*/
+	clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
+	/*Disable all bytes*/
+	/* Disable automatic power down of DLL and IOs when disabling a byte
+	 * (To avoid having to add programming and  delay
+	 * for a DLL re-lock when later re-enabling a disabled Byte Lane)
+	 */
+	clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
+
+	/*Disable all data bytes */
+	clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
+	clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
+	clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
+	clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
+
+	/* Config the BIST block */
+	config_BIST(phy);
+
+	for (byte = 0; byte < nb_bytes; byte++) {
+		if (ctrlc()) {
+			sprintf(string, "interrupted at byte %d/%d, error=%d",
+				byte + 1, nb_bytes, error);
+			return TEST_FAILED;
+		}
+		right_bound.phase = 0;
+		right_bound.unit = 0;
+
+		left_bound.phase = 0;
+		left_bound.unit = 0;
+
+		left_phase_bound_found = 0;
+		right_phase_bound_found = 0;
+
+		left_unit_bound_found = 0;
+		right_unit_bound_found = 0;
+
+		left_bound_found = 0;
+		right_bound_found = 0;
+
+		/* Enable Byte (DXNGCR, bit DXEN) */
+		setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
+
+		/* Select the byte lane for comparison of read data */
+		BIST_datx8_sel(phy, byte);
+
+		/* Set DQS phase delay to the nominal value. */
+		phase_idx = _90deg;
+		phase_idx_pass = phase_idx;
+
+		/* Set DQS unit delay to the nominal value. */
+		dqs_unit_delay_index = 3;
+		dqs_unit_delay_index_pass = dqs_unit_delay_index;
+		success = 0;
+
+		pr_debug("STEP0: Find Init delay\n");
+		/* STEP0: Find Init delay: a delay that put the system
+		 * in a "Pass" condition then (TODO) update
+		 * dqs_unit_delay_index_pass & phase_idx_pass
+		 */
+		DQS_unit_delay(phy, byte, dqs_unit_delay_index);
+		DQS_phase_delay(phy, byte, phase_idx);
+		BIST_test(phy, byte, &result);
+		success = result.test_result;
+		/* If we have a fail in the nominal condition */
+		if (!success) {
+			/* Look at the left */
+			while (phase_idx >= 0 && !success) {
+				phase_idx--;
+				DQS_phase_delay(phy, byte, phase_idx);
+				BIST_test(phy, byte, &result);
+				success = result.test_result;
+			}
+		}
+		if (!success) {
+			/* if we can't find pass condition,
+			 * then look at the right
+			 */
+			phase_idx = _90deg;
+			while (phase_idx <= MAX_DQS_PHASE_IDX &&
+			       !success) {
+				phase_idx++;
+				DQS_phase_delay(phy, byte,
+						phase_idx);
+				BIST_test(phy, byte, &result);
+				success = result.test_result;
+			}
+		}
+		/* save the pass condition */
+		if (success) {
+			phase_idx_pass = phase_idx;
+		} else {
+			printf("Result: Failed ");
+			printf("[Cannot DQS timings, ");
+			printf("there is no PASS region]\n");
+			error++;
+			continue;
+		}
+
+		if (ctrlc()) {
+			sprintf(string, "interrupted at byte %d/%d, error=%d",
+				byte + 1, nb_bytes, error);
+			return TEST_FAILED;
+		}
+		pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
+		/* STEP1: Find LEFT PHASE DQS Bound */
+		while ((phase_idx >= 0) &&
+		       (phase_idx <= MAX_DQS_PHASE_IDX) &&
+		       !left_phase_bound_found) {
+			DQS_unit_delay(phy, byte,
+				       dqs_unit_delay_index);
+			DQS_phase_delay(phy, byte,
+					phase_idx);
+			BIST_test(phy, byte, &result);
+			success = result.test_result;
+
+			/*TODO: Manage the case were at the beginning
+			 * there is already a fail
+			 */
+			if (!success) {
+				/* the last pass condition */
+				left_bound.phase = ++phase_idx;
+				left_phase_bound_found = 1;
+			} else if (success) {
+				phase_idx--;
+			}
+		}
+		if (!left_phase_bound_found) {
+			left_bound.phase = 0;
+			phase_idx = 0;
+		}
+		/* If not found, lets take 0 */
+
+		if (ctrlc()) {
+			sprintf(string, "interrupted at byte %d/%d, error=%d",
+				byte + 1, nb_bytes, error);
+			return TEST_FAILED;
+		}
+		pr_debug("STEP2: Find UNIT left bound\n");
+		/* STEP2: Find UNIT left bound */
+		while ((dqs_unit_delay_index >= 0) &&
+		       !left_unit_bound_found) {
+			DQS_unit_delay(phy, byte,
+				       dqs_unit_delay_index);
+			DQS_phase_delay(phy, byte, phase_idx);
+			BIST_test(phy, byte, &result);
+			success = result.test_result;
+			if (!success) {
+				left_bound.unit =
+					++dqs_unit_delay_index;
+				left_unit_bound_found = 1;
+				left_bound_found = 1;
+			} else if (success) {
+				dqs_unit_delay_index--;
+			}
+		}
+
+		/* If not found, lets take 0 */
+		if (!left_unit_bound_found)
+			left_bound.unit = 0;
+
+		if (ctrlc()) {
+			sprintf(string, "interrupted at byte %d/%d, error=%d",
+				byte + 1, nb_bytes, error);
+			return TEST_FAILED;
+		}
+		pr_debug("STEP3: Find PHase right bound\n");
+		/* STEP3: Find PHase right bound, start with "pass"
+		 * condition
+		 */
+
+		/* Set DQS phase delay to the pass value. */
+		phase_idx = phase_idx_pass;
+
+		/* Set DQS unit delay to the pass value. */
+		dqs_unit_delay_index = dqs_unit_delay_index_pass;
+
+		while ((phase_idx <= MAX_DQS_PHASE_IDX) &&
+		       !right_phase_bound_found) {
+			DQS_unit_delay(phy, byte,
+				       dqs_unit_delay_index);
+			DQS_phase_delay(phy, byte, phase_idx);
+			BIST_test(phy, byte, &result);
+			success = result.test_result;
+			if (!success) {
+				/* the last pass condition */
+				right_bound.phase = --phase_idx;
+				right_phase_bound_found = 1;
+			} else if (success) {
+				phase_idx++;
+			}
+		}
+
+		/* If not found, lets take the max value */
+		if (!right_phase_bound_found) {
+			right_bound.phase = MAX_DQS_PHASE_IDX;
+			phase_idx = MAX_DQS_PHASE_IDX;
+		}
+
+		if (ctrlc()) {
+			sprintf(string, "interrupted at byte %d/%d, error=%d",
+				byte + 1, nb_bytes, error);
+			return TEST_FAILED;
+		}
+		pr_debug("STEP4: Find UNIT right bound\n");
+		/* STEP4: Find UNIT right bound */
+		while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
+		       !right_unit_bound_found) {
+			DQS_unit_delay(phy, byte,
+				       dqs_unit_delay_index);
+			DQS_phase_delay(phy, byte, phase_idx);
+			BIST_test(phy, byte, &result);
+			success = result.test_result;
+			if (!success) {
+				right_bound.unit =
+					--dqs_unit_delay_index;
+				right_unit_bound_found = 1;
+				right_bound_found = 1;
+			} else if (success) {
+				dqs_unit_delay_index++;
+			}
+		}
+		/* If not found, lets take the max value */
+		if (!right_unit_bound_found)
+			right_bound.unit = MAX_DQS_UNIT_IDX;
+
+		/* If we found a regular FAil Pass FAil pattern
+		 * FFPPPPPPFF
+		 * OR PPPPPFF  Or FFPPPPP
+		 */
+
+		if (left_bound_found || right_bound_found) {
+			eye_training_val[byte][0] = (right_bound.phase +
+						 left_bound.phase) / 2;
+			eye_training_val[byte][1] = (right_bound.unit +
+						 left_bound.unit) / 2;
+
+			/* If we already lost 1/2PHASE Tuning,
+			 * let's try to recover by ++ on unit
+			 */
+			if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
+			    eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
+				eye_training_val[byte][1]++;
+			pr_debug("** found phase : %d -  %d & unit %d - %d\n",
+				 right_bound.phase, left_bound.phase,
+				 right_bound.unit, left_bound.unit);
+			pr_debug("** calculating mid region: phase: %d  unit: %d (nominal is 3)\n",
+				 eye_training_val[byte][0],
+				 eye_training_val[byte][1]);
+		} else {
+			/* PPPPPPPPPP, we're already good.
+			 * Set nominal values.
+			 */
+			eye_training_val[byte][0] = 3;
+			eye_training_val[byte][1] = 3;
+		}
+		DQS_phase_delay(phy, byte, eye_training_val[byte][0]);
+		DQS_unit_delay(phy, byte, eye_training_val[byte][1]);
+
+		printf("Byte %d, DQS unit = %d, phase = %d\n",
+		       byte,
+		       eye_training_val[byte][1],
+		       eye_training_val[byte][0]);
+	}
+
+	if (error) {
+		sprintf(string, "error = %d", error);
+		return TEST_FAILED;
+	}
+
+	return TEST_PASSED;
+}
+
+static void display_reg_results(struct stm32mp1_ddrphy *phy, u8 byte)
+{
+	u8 i = 0;
+
+	printf("Byte %d Dekew result, bit0 delay, bit1 delay...bit8 delay\n  ",
+	       byte);
+
+	for (i = 0; i < 8; i++)
+		printf("%d ", DQ_unit_index(phy, byte, i));
+	printf("\n");
+
+	printf("dxndllcr: [%08x] val:%08x\n",
+	       DXNDLLCR(phy, byte),
+	       readl(DXNDLLCR(phy, byte)));
+	printf("dxnqdstr: [%08x] val:%08x\n",
+	       DXNDQSTR(phy, byte),
+	       readl(DXNDQSTR(phy, byte)));
+	printf("dxndqtr: [%08x] val:%08x\n",
+	       DXNDQTR(phy, byte),
+	       readl(DXNDQTR(phy, byte)));
+}
+
+/* analyse the dgs gating log table, and determine the midpoint.*/
+static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
+				       u8 dqs_gating[NUM_BYTES]
+						    [MAX_GSL_IDX + 1]
+						    [MAX_GPS_IDX + 1])
+{
+	/* stores the dqs gate values (gsl index, gps index) */
+	u8 dqs_gate_values[NUM_BYTES][2];
+	u8 gsl_idx, gps_idx = 0;
+	u8 left_bound_idx[2] = {0, 0};
+	u8 right_bound_idx[2] = {0, 0};
+	u8 left_bound_found = 0;
+	u8 right_bound_found = 0;
+	u8 intermittent = 0;
+	u8 value;
+
+	for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
+		for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
+			value = dqs_gating[byte][gsl_idx][gps_idx];
+			if (value == 1 && left_bound_found == 0) {
+				left_bound_idx[0] = gsl_idx;
+				left_bound_idx[1] = gps_idx;
+				left_bound_found = 1;
+			} else if (value == 0 &&
+				   left_bound_found == 1 &&
+				   !right_bound_found) {
+				if (gps_idx == 0) {
+					right_bound_idx[0] = gsl_idx - 1;
+					right_bound_idx[1] = MAX_GPS_IDX;
+				} else {
+					right_bound_idx[0] = gsl_idx;
+					right_bound_idx[1] = gps_idx - 1;
+				}
+				right_bound_found = 1;
+			} else if (value == 1 &&
+				   right_bound_found == 1) {
+				intermittent = 1;
+			}
+		}
+	}
+
+	/* if only ppppppp is found, there is no mid region. */
+	if (left_bound_idx[0] == 0 && left_bound_idx[1] == 0 &&
+	    right_bound_idx[0] == 0 && right_bound_idx[1] == 0)
+		intermittent = 1;
+
+	/*if we found a regular fail pass fail pattern ffppppppff
+	 * or pppppff  or ffppppp
+	 */
+	if (!intermittent) {
+		/*if we found a regular fail pass fail pattern ffppppppff
+		 * or pppppff  or ffppppp
+		 */
+		if (left_bound_found || right_bound_found) {
+			pr_debug("idx0(%d): %d %d      idx1(%d) : %d %d\n",
+				 left_bound_found,
+				 right_bound_idx[0], left_bound_idx[0],
+				 right_bound_found,
+				 right_bound_idx[1], left_bound_idx[1]);
+			dqs_gate_values[byte][0] =
+				(right_bound_idx[0] + left_bound_idx[0]) / 2;
+			dqs_gate_values[byte][1] =
+				(right_bound_idx[1] + left_bound_idx[1]) / 2;
+			/* if we already lost 1/2gsl tuning,
+			 * let's try to recover by ++ on gps
+			 */
+			if (((right_bound_idx[0] +
+			      left_bound_idx[0]) % 2 == 1) &&
+			    dqs_gate_values[byte][1] != MAX_GPS_IDX)
+				dqs_gate_values[byte][1]++;
+			/* if we already lost 1/2gsl tuning and gps is on max*/
+			else if (((right_bound_idx[0] +
+				   left_bound_idx[0]) % 2 == 1) &&
+				 dqs_gate_values[byte][1] == MAX_GPS_IDX) {
+				dqs_gate_values[byte][1] = 0;
+				dqs_gate_values[byte][0]++;
+			}
+			/* if we have gsl left and write limit too close
+			 * (difference=1)
+			 */
+			if (((right_bound_idx[0] - left_bound_idx[0]) == 1)) {
+				dqs_gate_values[byte][1] = (left_bound_idx[1] +
+							    right_bound_idx[1] +
+							    4) / 2;
+				if (dqs_gate_values[byte][1] >= 4) {
+					dqs_gate_values[byte][0] =
+						right_bound_idx[0];
+					dqs_gate_values[byte][1] -= 4;
+				} else {
+					dqs_gate_values[byte][0] =
+						left_bound_idx[0];
+				}
+			}
+			pr_debug("*******calculating mid region: system latency: %d  phase: %d********\n",
+				 dqs_gate_values[byte][0],
+				 dqs_gate_values[byte][1]);
+			pr_debug("*******the nominal values were system latency: 0  phase: 2*******\n");
+			set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
+			set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
+		}
+	} else {
+		/* if intermitant, restore defaut values */
+		pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
+		set_r0dgsl_delay(phy, byte, 0);
+		set_r0dgps_delay(phy, byte, 2);
+	}
+
+	/* return 0 if intermittent or if both left_bound
+	 * and right_bound are not found
+	 */
+	return !(intermittent || (left_bound_found && right_bound_found));
+}
+
+static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl,
+					struct stm32mp1_ddrphy *phy,
+					char *string)
+{
+	/* stores the log of pass/fail */
+	u8 dqs_gating[NUM_BYTES][MAX_GSL_IDX + 1][MAX_GPS_IDX + 1];
+	u8 byte, gsl_idx, gps_idx = 0;
+	struct BIST_result result;
+	u8 success = 0;
+	u8 nb_bytes = get_nb_bytes(ctl);
+
+	memset(dqs_gating, 0x0, sizeof(dqs_gating));
+
+	/*disable dqs drift compensation*/
+	clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
+	/*disable all bytes*/
+	/* disable automatic power down of dll and ios when disabling a byte
+	 * (to avoid having to add programming and  delay
+	 * for a dll re-lock when later re-enabling a disabled byte lane)
+	 */
+	clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
+
+	/* disable all data bytes */
+	clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
+	clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
+	clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
+	clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
+
+	/* config the bist block */
+	config_BIST(phy);
+
+	for (byte = 0; byte < nb_bytes; byte++) {
+		if (ctrlc()) {
+			sprintf(string, "interrupted at byte %d/%d",
+				byte + 1, nb_bytes);
+			return TEST_FAILED;
+		}
+		/* enable byte x (dxngcr, bit dxen) */
+		setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
+
+		/* select the byte lane for comparison of read data */
+		BIST_datx8_sel(phy, byte);
+		for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
+			for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
+				if (ctrlc()) {
+					sprintf(string,
+						"interrupted at byte %d/%d",
+						byte + 1, nb_bytes);
+					return TEST_FAILED;
+				}
+				/* write cfg to dxndqstr */
+				set_r0dgsl_delay(phy, byte, gsl_idx);
+				set_r0dgps_delay(phy, byte, gps_idx);
+
+				BIST_test(phy, byte, &result);
+				success = result.test_result;
+				if (success)
+					dqs_gating[byte][gsl_idx][gps_idx] = 1;
+				itm_soft_reset(phy);
+			}
+		}
+		set_midpoint_read_dqs_gating(phy, byte, dqs_gating);
+		/* dummy reads */
+		readl(0xc0000000);
+		readl(0xc0000000);
+	}
+
+	/* re-enable drift compensation */
+	/* setbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); */
+	return TEST_PASSED;
+}
+
+/****************************************************************
+ * TEST
+ ****************************************************************
+ */
+static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl,
+					   struct stm32mp1_ddrphy *phy,
+					   char *string, int argc,
+					   char *argv[])
+{
+	u32 rfshctl3 = readl(&ctl->rfshctl3);
+	u32 pwrctl = readl(&ctl->pwrctl);
+	enum test_result res;
+
+	stm32mp1_refresh_disable(ctl);
+	res = read_dqs_gating(ctl, phy, string);
+	stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
+
+	return res;
+}
+
+static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl,
+				      struct stm32mp1_ddrphy *phy,
+				      char *string, int argc, char *argv[])
+{
+	u32 rfshctl3 = readl(&ctl->rfshctl3);
+	u32 pwrctl = readl(&ctl->pwrctl);
+	enum test_result res;
+
+	stm32mp1_refresh_disable(ctl);
+	res = bit_deskew(ctl, phy, string);
+	stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
+
+	return res;
+}
+
+static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl,
+					struct stm32mp1_ddrphy *phy,
+					char *string, int argc, char *argv[])
+{
+	u32 rfshctl3 = readl(&ctl->rfshctl3);
+	u32 pwrctl = readl(&ctl->pwrctl);
+	enum test_result res;
+
+	stm32mp1_refresh_disable(ctl);
+	res = eye_training(ctl, phy, string);
+	stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
+
+	return res;
+}
+
+static enum test_result do_display(struct stm32mp1_ddrctl *ctl,
+				   struct stm32mp1_ddrphy *phy,
+				   char *string, int argc, char *argv[])
+{
+	int byte;
+	u8 nb_bytes = get_nb_bytes(ctl);
+
+	for (byte = 0; byte < nb_bytes; byte++)
+		display_reg_results(phy, byte);
+
+	return TEST_PASSED;
+}
+
+static enum test_result do_bist_config(struct stm32mp1_ddrctl *ctl,
+				       struct stm32mp1_ddrphy *phy,
+				       char *string, int argc, char *argv[])
+{
+	unsigned long value;
+
+	if (argc > 0) {
+		if (strict_strtoul(argv[0], 0, &value) < 0) {
+			sprintf(string, "invalid nbErr %s", argv[0]);
+			return TEST_FAILED;
+		}
+		BIST_error_max = value;
+	}
+	if (argc > 1) {
+		if (strict_strtoul(argv[1], 0, &value) < 0) {
+			sprintf(string, "invalid Seed %s", argv[1]);
+			return TEST_FAILED;
+		}
+		BIST_seed = value;
+	}
+	printf("Bist.nbErr = %d\n", BIST_error_max);
+	if (BIST_seed)
+		printf("Bist.Seed = 0x%x\n", BIST_seed);
+	else
+		printf("Bist.Seed = random\n");
+
+	return TEST_PASSED;
+}
+
+/****************************************************************
+ * TEST Description
+ ****************************************************************
+ */
+
+const struct test_desc tuning[] = {
+	{do_read_dqs_gating, "Read DQS gating",
+		"software read DQS Gating", "", 0 },
+	{do_bit_deskew, "Bit de-skew", "", "", 0 },
+	{do_eye_training, "Eye Training", "or DQS training", "", 0 },
+	{do_display, "Display registers", "", "", 0 },
+	{do_bist_config, "Bist config", "[nbErr] [seed]",
+	 "configure Bist test", 2},
+};
+
+const int tuning_nb = ARRAY_SIZE(tuning);
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index fcbb0a8..8a447fd 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -559,6 +559,14 @@
 	  Choose this option to add support for UART driver on the Marvell
 	  Armada 3700 SoC. The base address is configured via DT.
 
+config MCFUART
+	bool "Freescale ColdFire UART support"
+        help
+          Choose this option to add support for UART driver on the ColdFire
+          SoC's family. The serial communication channel provides a full-duplex
+          asynchronous/synchronous receiver and transmitter deriving an
+          operating frequency from the internal bus clock or an external clock.
+
 config MXC_UART
 	bool "IMX serial port support"
 	depends on MX5 || MX6
diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index 1371049..066e5a1 100644
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -5,6 +5,9 @@
  *
  * Modified to add device model (DM) support
  * (C) Copyright 2015  Angelo Dureghello <angelo@sysam.it>
+ *
+ * Modified to add DM and fdt support, removed non DM code
+ * (C) Copyright 2018  Angelo Dureghello <angelo@sysam.it>
  */
 
 /*
@@ -78,83 +81,6 @@
 	writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
 }
 
-#ifndef CONFIG_DM_SERIAL
-
-static int mcf_serial_init(void)
-{
-	uart_t *uart_base;
-	int port_idx;
-
-	uart_base = (uart_t *)CONFIG_SYS_UART_BASE;
-	port_idx = CONFIG_SYS_UART_PORT;
-
-	return mcf_serial_init_common(uart_base, port_idx, gd->baudrate);
-}
-
-static void mcf_serial_putc(const char c)
-{
-	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
-	if (c == '\n')
-		serial_putc('\r');
-
-	/* Wait for last character to go. */
-	while (!(readb(&uart->usr) & UART_USR_TXRDY))
-		;
-
-	writeb(c, &uart->utb);
-}
-
-static int mcf_serial_getc(void)
-{
-	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
-	/* Wait for a character to arrive. */
-	while (!(readb(&uart->usr) & UART_USR_RXRDY))
-		;
-
-	return readb(&uart->urb);
-}
-
-static void mcf_serial_setbrg(void)
-{
-	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
-	mcf_serial_setbrg_common(uart, gd->baudrate);
-}
-
-static int mcf_serial_tstc(void)
-{
-	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
-	return readb(&uart->usr) & UART_USR_RXRDY;
-}
-
-static struct serial_device mcf_serial_drv = {
-	.name	= "mcf_serial",
-	.start	= mcf_serial_init,
-	.stop	= NULL,
-	.setbrg	= mcf_serial_setbrg,
-	.putc	= mcf_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= mcf_serial_getc,
-	.tstc	= mcf_serial_tstc,
-};
-
-void mcf_serial_initialize(void)
-{
-	serial_register(&mcf_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &mcf_serial_drv;
-}
-
-#endif
-
-#ifdef CONFIG_DM_SERIAL
-
 static int coldfire_serial_probe(struct udevice *dev)
 {
 	struct coldfire_serial_platdata *plat = dev->platdata;
@@ -212,6 +138,23 @@
 	return 0;
 }
 
+static int coldfire_ofdata_to_platdata(struct udevice *dev)
+{
+	struct coldfire_serial_platdata *plat = dev_get_platdata(dev);
+	fdt_addr_t addr_base;
+
+	addr_base = devfdt_get_addr(dev);
+	if (addr_base == FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	plat->base = (uint32_t)addr_base;
+
+	plat->port = dev->seq;
+	plat->baudrate = gd->baudrate;
+
+	return 0;
+}
+
 static const struct dm_serial_ops coldfire_serial_ops = {
 	.putc = coldfire_serial_putc,
 	.pending = coldfire_serial_pending,
@@ -219,11 +162,18 @@
 	.setbrg = coldfire_serial_setbrg,
 };
 
+static const struct udevice_id coldfire_serial_ids[] = {
+	{ .compatible = "fsl,mcf-uart" },
+	{ }
+};
+
 U_BOOT_DRIVER(serial_coldfire) = {
 	.name = "serial_coldfire",
 	.id = UCLASS_SERIAL,
+	.of_match = coldfire_serial_ids,
+	.ofdata_to_platdata = coldfire_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct coldfire_serial_platdata),
 	.probe = coldfire_serial_probe,
 	.ops = &coldfire_serial_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-#endif
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index e31c87b..cca8b70 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -269,7 +269,6 @@
 	_stm32_serial_setbrg(base, uart_info,
 			     CONFIG_DEBUG_UART_CLOCK,
 			     CONFIG_BAUDRATE);
-	printf("DEBUG done\n");
 }
 
 static inline void _debug_uart_putc(int c)
@@ -278,7 +277,7 @@
 	struct stm32_uart_info *uart_info = _debug_uart_info();
 
 	while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
-		WATCHDOG_RESET();
+		;
 }
 
 DEBUG_UART_FUNCS
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c3a829d..7044da3 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -87,6 +87,12 @@
 	  used to access the SPI NOR flash on platforms embedding this
 	  Cadence IP core.
 
+config CF_SPI
+        bool "ColdFire SPI driver"
+        help
+          Enable the ColdFire SPI driver. This driver can be used on
+          some m68k SoCs.
+
 config DESIGNWARE_SPI
 	bool "Designware SPI driver"
 	help
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
index 522631c..923ff6f 100644
--- a/drivers/spi/cf_spi.c
+++ b/drivers/spi/cf_spi.c
@@ -6,23 +6,28 @@
  *
  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * Support for DM and DT, non-DM code removed.
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ *
+ * TODO: fsl_dspi.c should work as a driver for the DSPI module.
  */
 
 #include <common.h>
+#include <dm.h>
+#include <dm/platform_data/spi_coldfire.h>
 #include <spi.h>
 #include <malloc.h>
-#include <asm/immap.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/io.h>
 
-struct cf_spi_slave {
-	struct spi_slave slave;
+struct coldfire_spi_priv {
+	struct dspi *regs;
 	uint baudrate;
+	int mode;
 	int charbit;
 };
 
-extern void cfspi_port_conf(void);
-extern int cfspi_claim_bus(uint bus, uint cs);
-extern void cfspi_release_bus(uint bus, uint cs);
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SPI_IDLE_VAL
@@ -33,163 +38,193 @@
 #endif
 #endif
 
-#if defined(CONFIG_CF_DSPI)
-/* DSPI specific mode */
-#define SPI_MODE_MOD	0x00200000
-#define SPI_DBLRATE	0x00100000
+/*
+ * DSPI specific mode
+ *
+ * bit 31 - 28: Transfer size 3 to 16 bits
+ *     27 - 26: PCS to SCK delay prescaler
+ *     25 - 24: After SCK delay prescaler
+ *     23 - 22: Delay after transfer prescaler
+ *     21     : Allow overwrite for bit 31-22 and bit 20-8
+ *     20     : Double baud rate
+ *     19 - 16: PCS to SCK delay scaler
+ *     15 - 12: After SCK delay scaler
+ *     11 -  8: Delay after transfer scaler
+ *      7 -  0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
+ */
+#define SPI_MODE_MOD			0x00200000
+#define SPI_MODE_DBLRATE		0x00100000
 
-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
+#define SPI_MODE_XFER_SZ_MASK		0xf0000000
+#define SPI_MODE_DLY_PRE_MASK		0x0fc00000
+#define SPI_MODE_DLY_SCA_MASK		0x000fff00
+
+#define MCF_FRM_SZ_16BIT		DSPI_CTAR_TRSZ(0xf)
+#define MCF_DSPI_SPEED_BESTMATCH	0x7FFFFFFF
+#define MCF_DSPI_MAX_CTAR_REGS		8
+
+/* Default values */
+#define MCF_DSPI_DEFAULT_SCK_FREQ	10000000
+#define MCF_DSPI_DEFAULT_MAX_CS		4
+#define MCF_DSPI_DEFAULT_MODE		0
+
+#define MCF_DSPI_DEFAULT_CTAR		(DSPI_CTAR_TRSZ(7) | \
+					DSPI_CTAR_PCSSCK_1CLK | \
+					DSPI_CTAR_PASC(0) | \
+					DSPI_CTAR_PDT(0) | \
+					DSPI_CTAR_CSSCK(0) | \
+					DSPI_CTAR_ASC(0) | \
+					DSPI_CTAR_DT(1) | \
+					DSPI_CTAR_BR(6))
+
+#define MCF_CTAR_MODE_MASK		(MCF_FRM_SZ_16BIT | \
+					DSPI_CTAR_PCSSCK(3) | \
+					DSPI_CTAR_PASC_7CLK | \
+					DSPI_CTAR_PDT(3) | \
+					DSPI_CTAR_CSSCK(0x0f) | \
+					DSPI_CTAR_ASC(0x0f) | \
+					DSPI_CTAR_DT(0x0f))
+
+#define setup_ctrl(ctrl, cs)	((ctrl & 0xFF000000) | ((1 << cs) << 16))
+
+static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
+			    u32 ctrl, u16 data)
 {
-	return container_of(slave, struct cf_spi_slave, slave);
+	/*
+	 * Need to check fifo level here
+	 */
+	while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
+		;
+
+	writel(ctrl | data, &cfspi->regs->tfr);
 }
 
-static void cfspi_init(void)
+static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
 {
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
 
-	cfspi_port_conf();	/* port configuration */
+	while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
+		;
 
-	dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
-	    DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
-	    DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
-	    DSPI_MCR_CRXF | DSPI_MCR_CTXF;
-
-	/* Default setting in platform configuration */
-#ifdef CONFIG_SYS_DSPI_CTAR0
-	dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR1
-	dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR2
-	dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR3
-	dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR4
-	dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR5
-	dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR6
-	dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR7
-	dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
-#endif
+	return readw(&cfspi->regs->rfr);
 }
 
-static void cfspi_tx(u32 ctrl, u16 data)
+static int coldfire_spi_claim_bus(struct udevice *dev)
 {
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	struct udevice *bus = dev->parent;
+	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+	struct dspi *dspi = cfspi->regs;
+	struct dm_spi_slave_platdata *slave_plat =
+		dev_get_parent_platdata(dev);
 
-	while ((dspi->sr & 0x0000F000) >= 4) ;
+	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+		return -1;
 
-	dspi->tfr = (ctrl | data);
+	/* Clear FIFO and resume transfer */
+	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+	dspi_chip_select(slave_plat->cs);
+
+	return 0;
 }
 
-static u16 cfspi_rx(void)
+static int coldfire_spi_release_bus(struct udevice *dev)
 {
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	struct udevice *bus = dev->parent;
+	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+	struct dspi *dspi = cfspi->regs;
+	struct dm_spi_slave_platdata *slave_plat =
+		dev_get_parent_platdata(dev);
 
-	while ((dspi->sr & 0x000000F0) == 0) ;
+	/* Clear FIFO */
+	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
-	return (dspi->rfr & 0xFFFF);
+	dspi_chip_unselect(slave_plat->cs);
+
+	return 0;
 }
 
-static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
-		      void *din, ulong flags)
+static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			     const void *dout, void *din,
+			     unsigned long flags)
 {
-	struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+	struct udevice *bus = dev_get_parent(dev);
+	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 	u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
 	u8 *spi_rd = NULL, *spi_wr = NULL;
-	static u32 ctrl = 0;
+	static u32 ctrl;
 	uint len = bitlen >> 3;
 
-	if (cfslave->charbit == 16) {
+	if (cfspi->charbit == 16) {
 		bitlen >>= 1;
-		spi_wr16 = (u16 *) dout;
-		spi_rd16 = (u16 *) din;
+		spi_wr16 = (u16 *)dout;
+		spi_rd16 = (u16 *)din;
 	} else {
-		spi_wr = (u8 *) dout;
-		spi_rd = (u8 *) din;
+		spi_wr = (u8 *)dout;
+		spi_rd = (u8 *)din;
 	}
 
 	if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
 		ctrl |= DSPI_TFR_CONT;
 
-	ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
+	ctrl = setup_ctrl(ctrl, slave_plat->cs);
 
 	if (len > 1) {
 		int tmp_len = len - 1;
+
 		while (tmp_len--) {
-			if (dout != NULL) {
-				if (cfslave->charbit == 16)
-					cfspi_tx(ctrl, *spi_wr16++);
+			if (dout) {
+				if (cfspi->charbit == 16)
+					cfspi_tx(cfspi, ctrl, *spi_wr16++);
 				else
-					cfspi_tx(ctrl, *spi_wr++);
-				cfspi_rx();
+					cfspi_tx(cfspi, ctrl, *spi_wr++);
+				cfspi_rx(cfspi);
 			}
 
-			if (din != NULL) {
-				cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
-				if (cfslave->charbit == 16)
-					*spi_rd16++ = cfspi_rx();
+			if (din) {
+				cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+				if (cfspi->charbit == 16)
+					*spi_rd16++ = cfspi_rx(cfspi);
 				else
-					*spi_rd++ = cfspi_rx();
+					*spi_rd++ = cfspi_rx(cfspi);
 			}
 		}
 
 		len = 1;	/* remaining byte */
 	}
 
-	if ((flags & SPI_XFER_END) == SPI_XFER_END)
+	if (flags & SPI_XFER_END)
 		ctrl &= ~DSPI_TFR_CONT;
 
 	if (len) {
-		if (dout != NULL) {
-			if (cfslave->charbit == 16)
-				cfspi_tx(ctrl, *spi_wr16);
+		if (dout) {
+			if (cfspi->charbit == 16)
+				cfspi_tx(cfspi, ctrl, *spi_wr16);
 			else
-				cfspi_tx(ctrl, *spi_wr);
-			cfspi_rx();
+				cfspi_tx(cfspi, ctrl, *spi_wr);
+			cfspi_rx(cfspi);
 		}
 
-		if (din != NULL) {
-			cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
-			if (cfslave->charbit == 16)
-				*spi_rd16 = cfspi_rx();
+		if (din) {
+			cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+			if (cfspi->charbit == 16)
+				*spi_rd16 = cfspi_rx(cfspi);
 			else
-				*spi_rd = cfspi_rx();
+				*spi_rd = cfspi_rx(cfspi);
 		}
 	} else {
 		/* dummy read */
-		cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
-		cfspi_rx();
+		cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+		cfspi_rx(cfspi);
 	}
 
 	return 0;
 }
 
-static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
-					   uint mode)
+static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
 {
-	/*
-	 * bit definition for mode:
-	 * bit 31 - 28: Transfer size 3 to 16 bits
-	 *     27 - 26: PCS to SCK delay prescaler
-	 *     25 - 24: After SCK delay prescaler
-	 *     23 - 22: Delay after transfer prescaler
-	 *     21     : Allow overwrite for bit 31-22 and bit 20-8
-	 *     20     : Double baud rate
-	 *     19 - 16: PCS to SCK delay scaler
-	 *     15 - 12: After SCK delay scaler
-	 *     11 -  8: Delay after transfer scaler
-	 *      7 -  0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
-	 */
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+	struct dspi *dspi = cfspi->regs;
 	int prescaler[] = { 2, 3, 5, 7 };
 	int scaler[] = {
 		2, 4, 6, 8,
@@ -198,57 +233,41 @@
 		4096, 8192, 16384, 32768
 	};
 	int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
-	int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
-	u32 bus_setup = 0;
+	int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
+	u32 bus_setup;
+
+	cfspi->baudrate = max_hz;
+
+	/* Read current setup */
+	bus_setup = readl(&dspi->ctar[bus->seq]);
 
 	tmp = (prescaler[3] * scaler[15]);
 	/* Maximum and minimum baudrate it can handle */
-	if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
-	    (cfslave->baudrate < (gd->bus_clk / tmp))) {
+	if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
+	    (cfspi->baudrate < (gd->bus_clk / tmp))) {
 		printf("Exceed baudrate limitation: Max %d - Min %d\n",
 		       (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
-		return NULL;
+		return -1;
 	}
 
 	/* Activate Double Baud when it exceed 1/4 the bus clk */
-	if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
-	    (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
+	if ((bus_setup & DSPI_CTAR_DBR) ||
+	    (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
 		bus_setup |= DSPI_CTAR_DBR;
 		dbr = 1;
 	}
 
-	if (mode & SPI_CPOL)
-		bus_setup |= DSPI_CTAR_CPOL;
-	if (mode & SPI_CPHA)
-		bus_setup |= DSPI_CTAR_CPHA;
-	if (mode & SPI_LSB_FIRST)
-		bus_setup |= DSPI_CTAR_LSBFE;
-
 	/* Overwrite default value set in platform configuration file */
-	if (mode & SPI_MODE_MOD) {
-
-		if ((mode & 0xF0000000) == 0)
-			bus_setup |=
-			    dspi->ctar[cfslave->slave.bus] & 0x78000000;
-		else
-			bus_setup |= ((mode & 0xF0000000) >> 1);
-
+	if (cfspi->mode & SPI_MODE_MOD) {
 		/*
 		 * Check to see if it is enabled by default in platform
 		 * config, or manual setting passed by mode parameter
 		 */
-		if (mode & SPI_DBLRATE) {
+		if (cfspi->mode & SPI_MODE_DBLRATE) {
 			bus_setup |= DSPI_CTAR_DBR;
 			dbr = 1;
 		}
-		bus_setup |= (mode & 0x0FC00000) >> 4;	/* PSCSCK, PASC, PDT */
-		bus_setup |= (mode & 0x000FFF00) >> 4;	/* CSSCK, ASC, DT */
-	} else
-		bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
-
-	cfslave->charbit =
-	    ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
-	     0x78000000) ? 16 : 8;
+	}
 
 	pbrcnt = sizeof(prescaler) / sizeof(int);
 	brcnt = sizeof(scaler) / sizeof(int);
@@ -259,10 +278,10 @@
 		for (j = 0; j < brcnt; j++) {
 			tmp = (baud_speed / scaler[j]) * (1 + dbr);
 
-			if (tmp > cfslave->baudrate)
-				diff = tmp - cfslave->baudrate;
+			if (tmp > cfspi->baudrate)
+				diff = tmp - cfspi->baudrate;
 			else
-				diff = cfslave->baudrate - tmp;
+				diff = cfspi->baudrate - tmp;
 
 			if (diff < bestmatch) {
 				bestmatch = diff;
@@ -271,65 +290,174 @@
 			}
 		}
 	}
+
+	bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
 	bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
-	dspi->ctar[cfslave->slave.bus] = bus_setup;
+	writel(bus_setup, &dspi->ctar[bus->seq]);
 
-	return &cfslave->slave;
+	return 0;
 }
-#endif				/* CONFIG_CF_DSPI */
 
-#ifdef CONFIG_CMD_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
 {
-	if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
-		return 1;
-	else
-		return 0;
+	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+	struct dspi *dspi = cfspi->regs;
+	u32 bus_setup = 0;
+
+	cfspi->mode = mode;
+
+	if (cfspi->mode & SPI_CPOL)
+		bus_setup |= DSPI_CTAR_CPOL;
+	if (cfspi->mode & SPI_CPHA)
+		bus_setup |= DSPI_CTAR_CPHA;
+	if (cfspi->mode & SPI_LSB_FIRST)
+		bus_setup |= DSPI_CTAR_LSBFE;
+
+	/* Overwrite default value set in platform configuration file */
+	if (cfspi->mode & SPI_MODE_MOD) {
+		if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
+			bus_setup |=
+			    readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT;
+		else
+			bus_setup |=
+			    ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
+
+		/* PSCSCK, PASC, PDT */
+		bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
+		/* CSSCK, ASC, DT */
+		bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
+	} else {
+		bus_setup |=
+			(readl(&dspi->ctar[bus->seq]) & MCF_CTAR_MODE_MASK);
+	}
+
+	cfspi->charbit =
+		((readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT) ==
+			MCF_FRM_SZ_16BIT) ? 16 : 8;
+
+	setbits_be32(&dspi->ctar[bus->seq], bus_setup);
+
+	return 0;
+}
+
+static int coldfire_spi_probe(struct udevice *bus)
+{
+	struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+	struct dspi *dspi = cfspi->regs;
+	int i;
+
+	cfspi->regs = (struct dspi *)plat->regs_addr;
+
+	cfspi->baudrate = plat->speed_hz;
+	cfspi->mode = plat->mode;
+
+	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
+		unsigned int ctar = 0;
+
+		if (plat->ctar[i][0] == 0)
+			break;
+
+		ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
+			DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
+			DSPI_CTAR_PASC(plat->ctar[i][2]) |
+			DSPI_CTAR_PDT(plat->ctar[i][3]) |
+			DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
+			DSPI_CTAR_ASC(plat->ctar[i][5]) |
+			DSPI_CTAR_DT(plat->ctar[i][6]) |
+			DSPI_CTAR_BR(plat->ctar[i][7]);
+
+		writel(ctar, &cfspi->regs->ctar[i]);
+	}
+
+	/* Default CTARs */
+	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
+		writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
+
+	dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
+	    DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
+	    DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
+	    DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+
+	return 0;
 }
 
 void spi_init(void)
 {
-	cfspi_init();
 }
 
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
 {
-	struct cf_spi_slave *cfslave;
+	fdt_addr_t addr;
+	struct coldfire_spi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = dev_of_offset(bus);
+	int *ctar, len;
 
-	if (!spi_cs_is_valid(bus, cs))
-		return NULL;
+	addr = devfdt_get_addr(bus);
+	if (addr == FDT_ADDR_T_NONE)
+		return -ENOMEM;
 
-	cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
-	if (!cfslave)
-		return NULL;
+	plat->regs_addr = addr;
 
-	cfslave->baudrate = max_hz;
+	plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
+				      MCF_DSPI_DEFAULT_MAX_CS);
 
-	/* specific setup */
-	return cfspi_setup_slave(cfslave, mode);
+	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+					MCF_DSPI_DEFAULT_SCK_FREQ);
+
+	plat->mode = fdtdec_get_int(blob, node, "spi-mode",
+				    MCF_DSPI_DEFAULT_MODE);
+
+	memset(plat->ctar, 0, sizeof(plat->ctar));
+
+	ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
+
+	if (ctar && len) {
+		int i, q, ctar_regs;
+
+		ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
+
+		if (ctar_regs > MAX_CTAR_REGS)
+			ctar_regs = MAX_CTAR_REGS;
+
+		for (i = 0; i < ctar_regs; i++) {
+			for (q = 0; q < MAX_CTAR_FIELDS; q++)
+				plat->ctar[i][q] = *ctar++;
+		}
+	}
+
+	debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
+	      (void *)plat->regs_addr,
+	       plat->speed_hz, plat->num_cs, plat->mode);
+
+	return 0;
 }
 
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+static const struct udevice_id coldfire_spi_ids[] = {
+	{ .compatible = "fsl,mcf-dspi" },
+	{ }
+};
+#endif
 
-	free(cfslave);
-}
+static const struct dm_spi_ops coldfire_spi_ops = {
+	.claim_bus	= coldfire_spi_claim_bus,
+	.release_bus	= coldfire_spi_release_bus,
+	.xfer		= coldfire_spi_xfer,
+	.set_speed	= coldfire_spi_set_speed,
+	.set_mode	= coldfire_spi_set_mode,
+};
 
-int spi_claim_bus(struct spi_slave *slave)
-{
-	return cfspi_claim_bus(slave->bus, slave->cs);
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-	cfspi_release_bus(slave->bus, slave->cs);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-	     void *din, unsigned long flags)
-{
-	return cfspi_xfer(slave, bitlen, dout, din, flags);
-}
-#endif				/* CONFIG_CMD_SPI */
+U_BOOT_DRIVER(coldfire_spi) = {
+	.name = "spi_coldfire",
+	.id = UCLASS_SPI,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+	.of_match = coldfire_spi_ids,
+	.ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
+#endif
+	.probe = coldfire_spi_probe,
+	.ops = &coldfire_spi_ops,
+	.priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
+};
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 23e7e71..b8f8e7a 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -75,8 +75,12 @@
 	struct usb_ehci *ehci = NULL;
 	struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
 						   ehci);
-
+#ifdef CONFIG_PPC
+	ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
+#else
 	ehci = (struct usb_ehci *)priv->hcd_base;
+#endif
+
 	if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
 		return -ENXIO;
 
@@ -103,7 +107,11 @@
 		debug("Can't get the EHCI register base address\n");
 		return -ENXIO;
 	}
+#ifdef CONFIG_PPC
+	ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
+#else
 	ehci = (struct usb_ehci *)priv->hcd_base;
+#endif
 	hccr = (struct ehci_hccr *)(&ehci->caplength);
 	hcor = (struct ehci_hcor *)
 		((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index f909d40..b01dbc4 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -103,6 +103,13 @@
 	   Select this to enable Orion watchdog timer, which can be found on some
 	   Marvell Armada chips.
 
+config WDT_SP805
+	bool "SP805 watchdog timer support"
+	depends on WDT
+	help
+	   Select this to enable SP805 watchdog timer, which can be found on some
+	   nxp layerscape chips.
+
 config WDT_CDNS
 	bool "Cadence watchdog timer support"
 	depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 40b2f4b..6f20e73 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -27,3 +27,4 @@
 obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
 obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
 obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
new file mode 100644
index 0000000..9661282
--- /dev/null
+++ b/drivers/watchdog/sp805_wdt.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Watchdog driver for SP805 on some Layerscape SoC
+ *
+ * Copyright 2019 NXP
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm/device.h>
+#include <dm/fdtaddr.h>
+#include <dm/read.h>
+#include <linux/bitops.h>
+#include <watchdog.h>
+#include <wdt.h>
+
+#define WDTLOAD			0x000
+#define WDTCONTROL		0x008
+#define WDTINTCLR		0x00C
+#define WDTLOCK			0xC00
+
+#define TIME_OUT_MIN_MSECS	1
+#define TIME_OUT_MAX_MSECS	120000
+#define SYS_FSL_WDT_CLK_DIV	16
+#define INT_ENABLE		BIT(0)
+#define RESET_ENABLE		BIT(1)
+#define DISABLE			0
+#define UNLOCK			0x1ACCE551
+#define LOCK			0x00000001
+#define INT_MASK		BIT(0)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sp805_wdt_priv {
+	void __iomem *reg;
+};
+
+static int sp805_wdt_reset(struct udevice *dev)
+{
+	struct sp805_wdt_priv *priv = dev_get_priv(dev);
+
+	writel(UNLOCK, priv->reg + WDTLOCK);
+	writel(INT_MASK, priv->reg + WDTINTCLR);
+	writel(LOCK, priv->reg + WDTLOCK);
+	readl(priv->reg + WDTLOCK);
+
+	return 0;
+}
+
+static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+	u32 load_value;
+	u32 load_time;
+	struct sp805_wdt_priv *priv = dev_get_priv(dev);
+
+	load_time = (u32)timeout;
+	if (timeout < TIME_OUT_MIN_MSECS)
+		load_time = TIME_OUT_MIN_MSECS;
+	else if (timeout > TIME_OUT_MAX_MSECS)
+		load_time = TIME_OUT_MAX_MSECS;
+	/* sp805 runs counter with given value twice, so when the max timeout is
+	 * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
+	 * not overflow.
+	 */
+	load_value = (gd->bus_clk) /
+		(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
+
+	writel(UNLOCK, priv->reg + WDTLOCK);
+	writel(load_value, priv->reg + WDTLOAD);
+	writel(INT_MASK, priv->reg + WDTINTCLR);
+	writel(INT_ENABLE | RESET_ENABLE, priv->reg + WDTCONTROL);
+	writel(LOCK, priv->reg + WDTLOCK);
+	readl(priv->reg + WDTLOCK);
+
+	return 0;
+}
+
+static int sp805_wdt_stop(struct udevice *dev)
+{
+	struct sp805_wdt_priv *priv = dev_get_priv(dev);
+
+	writel(UNLOCK, priv->reg + WDTLOCK);
+	writel(DISABLE, priv->reg + WDTCONTROL);
+	writel(LOCK, priv->reg + WDTLOCK);
+	readl(priv->reg + WDTLOCK);
+
+	return 0;
+}
+
+static int sp805_wdt_probe(struct udevice *dev)
+{
+	debug("%s: Probing wdt%u\n", __func__, dev->seq);
+
+	return 0;
+}
+
+static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
+{
+	struct sp805_wdt_priv *priv = dev_get_priv(dev);
+
+	priv->reg = (void __iomem *)dev_read_addr(dev);
+	if (IS_ERR(priv->reg))
+		return PTR_ERR(priv->reg);
+
+	return 0;
+}
+
+static const struct wdt_ops sp805_wdt_ops = {
+	.start = sp805_wdt_start,
+	.reset = sp805_wdt_reset,
+	.stop = sp805_wdt_stop,
+};
+
+static const struct udevice_id sp805_wdt_ids[] = {
+	{ .compatible = "arm,sp805-wdt" },
+	{}
+};
+
+U_BOOT_DRIVER(sp805_wdt) = {
+	.name = "sp805_wdt",
+	.id = UCLASS_WDT,
+	.of_match = sp805_wdt_ids,
+	.probe = sp805_wdt_probe,
+	.priv_auto_alloc_size = sizeof(struct sp805_wdt_priv),
+	.ofdata_to_platdata = sp805_wdt_ofdata_to_platdata,
+	.ops = &sp805_wdt_ops,
+};
diff --git a/env/Kconfig b/env/Kconfig
index 70858d3..1e10c7a 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -470,7 +470,7 @@
 	  It's a string of the EXT4 file name. This file use to store the
 	  environment (explicit path to the file)
 
-if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARC
+if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARC || ARCH_STM32MP
 
 config ENV_OFFSET
 	hex "Environment Offset"
diff --git a/env/common.c b/env/common.c
index 324502e..bd340fe 100644
--- a/env/common.c
+++ b/env/common.c
@@ -23,7 +23,10 @@
 #include <env_default.h>
 
 struct hsearch_data env_htab = {
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
+	/* defined in flags.c, only compile with ENV_SUPPORT */
 	.change_ok = env_flags_validate,
+#endif
 };
 
 /*
@@ -225,7 +228,9 @@
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	env_reloc();
 	env_fix_drivers();
-	env_htab.change_ok += gd->reloc_off;
+
+	if (env_htab.change_ok)
+		env_htab.change_ok += gd->reloc_off;
 #endif
 	if (gd->env_valid == ENV_INVALID) {
 #if defined(CONFIG_ENV_IS_NOWHERE) || defined(CONFIG_SPL_BUILD)
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 87c88e7..d5fe053 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -580,7 +580,6 @@
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
@@ -588,10 +587,8 @@
  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1130)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
@@ -601,10 +598,8 @@
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
@@ -612,7 +607,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_TERANETICS
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 514733e..a9c260d 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -103,17 +103,6 @@
 /* DSPI and Serial Flash */
 #define CONFIG_CF_DSPI
 #define CONFIG_SYS_SBFHDR_SIZE		0x7
-#ifdef CONFIG_CMD_SPI
-#	define CONFIG_SYS_DSPI_CS2
-
-#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
-					 DSPI_CTAR_PCSSCK_1CLK | \
-					 DSPI_CTAR_PASC(0) | \
-					 DSPI_CTAR_PDT(0) | \
-					 DSPI_CTAR_CSSCK(0) | \
-					 DSPI_CTAR_ASC(0) | \
-					 DSPI_CTAR_DT(1))
-#endif
 
 /* Input, PCI, Flexbus, and VCO */
 #define CONFIG_EXTRA_CLOCK
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index f7b0669..e07684d 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -152,18 +152,6 @@
 #define CONFIG_CF_DSPI
 #define CONFIG_SERIAL_FLASH
 #define CONFIG_SYS_SBFHDR_SIZE		0x7
-#ifdef CONFIG_CMD_SPI
-
-#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
-					 DSPI_CTAR_PCSSCK_1CLK | \
-					 DSPI_CTAR_PASC(0) | \
-					 DSPI_CTAR_PDT(0) | \
-					 DSPI_CTAR_CSSCK(0) | \
-					 DSPI_CTAR_ASC(0) | \
-					 DSPI_CTAR_DT(1))
-#	define CONFIG_SYS_DSPI_CTAR1	(CONFIG_SYS_DSPI_CTAR0)
-#	define CONFIG_SYS_DSPI_CTAR2	(CONFIG_SYS_DSPI_CTAR0)
-#endif
 
 /* Input, PCI, Flexbus, and VCO */
 #define CONFIG_EXTRA_CLOCK
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 57c8572..2bd0e62 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -117,18 +117,6 @@
 #define CONFIG_CF_DSPI
 #define CONFIG_SERIAL_FLASH
 #define CONFIG_SYS_SBFHDR_SIZE		0x7
-#ifdef CONFIG_CMD_SPI
-
-#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
-					 DSPI_CTAR_PCSSCK_1CLK | \
-					 DSPI_CTAR_PASC(0) | \
-					 DSPI_CTAR_PDT(0) | \
-					 DSPI_CTAR_CSSCK(0) | \
-					 DSPI_CTAR_ASC(0) | \
-					 DSPI_CTAR_DT(1))
-#	define CONFIG_SYS_DSPI_CTAR1	(CONFIG_SYS_DSPI_CTAR0)
-#	define CONFIG_SYS_DSPI_CTAR2	(CONFIG_SYS_DSPI_CTAR0)
-#endif
 
 /* Input, PCI, Flexbus, and VCO */
 #define CONFIG_EXTRA_CLOCK
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 448dfc9..d73101f 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -143,16 +143,6 @@
 /* DSPI and Serial Flash */
 #define CONFIG_CF_DSPI
 #define CONFIG_SYS_SBFHDR_SIZE		0x13
-#ifdef CONFIG_CMD_SPI
-
-#	define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
-					 DSPI_CTAR_PCSSCK_1CLK | \
-					 DSPI_CTAR_PASC(0) | \
-					 DSPI_CTAR_PDT(0) | \
-					 DSPI_CTAR_CSSCK(0) | \
-					 DSPI_CTAR_ASC(0) | \
-					 DSPI_CTAR_DT(1))
-#endif
 
 /* PCI */
 #ifdef CONFIG_CMD_PCI
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 418c672..94c2a61 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -13,7 +13,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 family */
-#define CONFIG_QE		1	/* Has QE */
 
 /*
  * System IO Config
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index df9cc48..26a4407 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -10,7 +10,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 family */
-#define CONFIG_QE		1	/* Has QE */
 
 /*
  * System IO Config
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 9b3485e..5515b92 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -18,7 +18,6 @@
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-#define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
 
 #ifndef __ASSEMBLY__
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index de5a7ca..3c6661f 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -17,7 +17,6 @@
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-#define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
 
 #ifndef __ASSEMBLY__
@@ -422,7 +421,6 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FW_ADDR	0xfff00000
 
 /*
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 4f6ee22..7fe34c3 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -283,13 +283,11 @@
 #define CONFIG_SYS_DPAA_FMAN
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHY_ATHEROS
 #endif
 
 /* Default address of microcode for the Linux Fman driver */
 /* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index b433308..e196f3c 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -451,7 +451,6 @@
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
@@ -459,10 +458,8 @@
  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
@@ -472,17 +469,14 @@
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_TERANETICS
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 58c1c80..c43cdd8 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -641,14 +641,12 @@
 
 #define CONFIG_SYS_DPAA_FMAN
 
-#define CONFIG_QE
 /* Default address of microcode for the Linux FMan driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #define CONFIG_SYS_QE_FW_ADDR	0x130000
 #elif defined(CONFIG_SDCARD)
@@ -657,11 +655,9 @@
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
 #define CONFIG_SYS_QE_FW_ADDR		(512 * 0x920)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_SYS_QE_FW_ADDR		(12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@@ -672,10 +668,8 @@
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #define CONFIG_SYS_QE_FW_ADDR		0xEFE00000
 #endif
@@ -684,7 +678,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index cce65f5..d90181f 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -649,16 +649,12 @@
 
 #define CONFIG_SYS_DPAA_FMAN
 
-#ifdef CONFIG_TARGET_T1024RDB
-#define CONFIG_QE
-#endif
 /* Default address of microcode for the Linux FMan driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #define CONFIG_SYS_QE_FW_ADDR	0x130000
 #elif defined(CONFIG_SDCARD)
@@ -667,11 +663,9 @@
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
 #define CONFIG_SYS_QE_FW_ADDR		(512 * 0x920)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #if defined(CONFIG_TARGET_T1024RDB)
 #define CONFIG_SYS_FMAN_FW_ADDR		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_SYS_QE_FW_ADDR		(4 * CONFIG_SYS_NAND_BLOCK_SIZE)
@@ -687,10 +681,8 @@
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR		0xFFE00000
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #define CONFIG_SYS_QE_FW_ADDR		0xEFE00000
 #endif
@@ -699,7 +691,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHY_REALTEK
 #if defined(CONFIG_TARGET_T1024RDB)
 #define RGMII_PHY1_ADDR		0x2
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 417383c..d8b65e6 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -531,14 +531,12 @@
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 
-#define CONFIG_QE
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
@@ -546,13 +544,10 @@
  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #define CONFIG_SYS_QE_FW_ADDR		0xEFF10000
 #endif
@@ -561,7 +556,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 470f60a..eeb09d2 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -635,7 +635,6 @@
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 
-#define CONFIG_QE
 #define CONFIG_U_QE
 
 /* Default address of microcode for the Linux Fman driver */
@@ -644,7 +643,6 @@
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
@@ -652,13 +650,10 @@
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #endif
 
@@ -677,7 +672,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #endif
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 8d909de..b8cc9cc 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -584,7 +584,6 @@
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
@@ -592,10 +591,8 @@
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
@@ -605,10 +602,8 @@
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
@@ -616,7 +611,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_TERANETICS
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index fc0007d..84b3e00 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -526,7 +526,6 @@
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR		0x110000
 #define CONFIG_CORTINA_FW_ADDR		0x120000
@@ -537,13 +536,11 @@
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
 #define CONFIG_CORTINA_FW_ADDR		(512 * 0x8a0)
 
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_CORTINA_FW_ADDR		(4 * CONFIG_SYS_NAND_BLOCK_SIZE)
@@ -555,12 +552,10 @@
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR		0xFFE00000
 #define CONFIG_CORTINA_FW_ADDR		0xFFE10000
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #define CONFIG_CORTINA_FW_ADDR		0xEFE00000
@@ -570,7 +565,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHY_CORTINA
 #define CONFIG_PHY_REALTEK
 #define CONFIG_CORTINA_FW_LENGTH	0x40000
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index ff2ba7b..ec31116 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -398,7 +398,6 @@
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
@@ -406,10 +405,8 @@
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
@@ -419,10 +416,8 @@
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
@@ -430,7 +425,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_TERANETICS
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index a818f0c..ecdd077 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -543,7 +543,6 @@
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
@@ -551,13 +550,10 @@
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
@@ -565,7 +561,6 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_CORTINA
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index f974291..e5c3a0c 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -467,7 +467,6 @@
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
@@ -475,10 +474,8 @@
  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
@@ -488,17 +485,14 @@
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_TERANETICS
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 007356b..d152f23 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -342,16 +342,11 @@
  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
 
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#endif
-
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 
diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h
index e89b7af..9aaea27 100644
--- a/include/configs/km/km-mpc8309.h
+++ b/include/configs/km/km-mpc8309.h
@@ -2,7 +2,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 family */
-#define CONFIG_QE		1	/* Has QE */
 
 #define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
 
@@ -14,7 +13,6 @@
 #define CONFIG_83XX_PCICLK		66000000
 
 /* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 /* between the u-boot partition and env */
 #ifndef CONFIG_SYS_QE_FW_ADDR
 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h
index 3c2173d..d7186ab 100644
--- a/include/configs/km/km-mpc832x.h
+++ b/include/configs/km/km-mpc832x.h
@@ -1,7 +1,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_QE	/* Has QE */
 #define CONFIG_KM8321	/* Keymile PBEC8321 board specific */
 
 /*
diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h
index 8f26e05..bdbb8bf 100644
--- a/include/configs/km/km-mpc8360.h
+++ b/include/configs/km/km-mpc8360.h
@@ -5,7 +5,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_QE			/* Has QE */
 
 /*
  * QE UEC ethernet configuration
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index a52d1df..3eff380 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -306,12 +306,10 @@
  * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
  * ucode is stored after env, so we got 0x120000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x120000
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 
 #define CONFIG_PCI_INDIRECT_BRIDGE
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 3a42210..5581cfd 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -38,7 +38,6 @@
 
 /*SPI device */
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT)
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
 #define CONFIG_SPI_FLASH_SPANSION
 #define CONFIG_FSL_SPI_INTERFACE
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index ebb1df4..12e6437 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -98,7 +98,8 @@
 			"${scriptaddr} ${prefix}${script}; "    \
 		"env exists secureboot && load ${devtype} "     \
 			"${devnum}:${distro_bootpart} "		\
-			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
 			"&& esbc_validate ${scripthdraddr};"    \
 		"source ${scriptaddr}\0"	  \
 	"installer=load mmc 0:2 $load_addr "	\
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index f149a60..f6640fa 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -98,7 +98,8 @@
 			"${scriptaddr} ${prefix}${script}; "    \
 		"env exists secureboot && load ${devtype} "     \
 			"${devnum}:${distro_bootpart} "		\
-			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
 			"&& esbc_validate ${scripthdraddr};"    \
 		"source ${scriptaddr}\0"	  \
 	"installer=load mmc 0:2 $load_addr "	\
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 3cbbd73..66771e2 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -102,11 +102,6 @@
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 #endif
 
-#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
-	!defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#endif
-
 /*
  * IFC Definitions
  */
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 7fe7bab..de0c9c7 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -105,11 +105,6 @@
 
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
 
-#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
-	!defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#endif
-
 /*
  * IFC Definitions
  */
@@ -363,7 +358,8 @@
 			"${scriptaddr} ${prefix}${script}; "    \
 		"env exists secureboot && load ${devtype} "     \
 			"${devnum}:${distro_bootpart} "		\
-			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
 			"&& esbc_validate ${scripthdraddr};"    \
 		"source ${scriptaddr}\0"	  \
 	"installer=load mmc 0:2 $load_addr "	\
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
new file mode 100644
index 0000000..0db8639
--- /dev/null
+++ b/include/configs/ls1028a_common.h
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __L1028A_COMMON_H
+#define __L1028A_COMMON_H
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_MP
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE	0x2080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	1
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START        0x80000000
+#define CONFIG_SYS_MEMTEST_END          0x9fffffff
+
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR		secondary_boot_func
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0)
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"board=ls1028ardb\0"			\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x00f00000\0"                 \
+	"kernel_addr=0x01000000\0"              \
+	"scriptaddr=0x80000000\0"               \
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"         \
+	"kernelheader_addr_r=0x80200000\0"      \
+	"load_addr=0xa0000000\0"            \
+	"kernel_addr_r=0x81000000\0"            \
+	"fdt_addr_r=0x90000000\0"               \
+	"ramdisk_addr_r=0xa0000000\0"           \
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x800000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernel_size_sd=0x14000\0"		\
+	"kernelhdr_addr_sd=0x4000\0"		\
+	"kernelhdr_size_sd=0x10\0"		\
+	"console=ttyS0,115200\0"                \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"	\
+	BOOTENV					\
+	"boot_scripts=ls1028ardb_boot.scr\0"    \
+	"boot_script_hdr=hdr_ls1028ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="               \
+		"part list ${devtype} ${devnum} devplist; "   \
+		"env exists devplist || setenv devplist 1; "  \
+		"for distro_bootpart in ${devplist}; do "     \
+		  "if fstype ${devtype} "                  \
+			"${devnum}:${distro_bootpart} "      \
+			"bootfstype; then "                  \
+			"run scan_dev_for_boot; "            \
+		  "fi; "                                   \
+		"done\0"                                   \
+	"scan_dev_for_boot="				  \
+		"echo Scanning ${devtype} "		  \
+				"${devnum}:${distro_bootpart}...; "  \
+		"for prefix in ${boot_prefixes}; do "	  \
+			"run scan_dev_for_scripts; "	  \
+		"done;"					  \
+		"\0"					  \
+	"boot_a_script="				  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "  \
+			"${scriptaddr} ${prefix}${script}; "    \
+		"env exists secureboot && load ${devtype} "     \
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+			"&& esbc_validate ${scripthdraddr};"    \
+		"source ${scriptaddr}\0"	  \
+	"sd_bootcmd=echo Trying load from SD ..;"	\
+		"mmcinfo; mmc read $load_addr "		\
+		"$kernel_addr_sd $kernel_size_sd && "	\
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"		\
+	"emmc_bootcmd=echo Trying load from EMMC ..;"	\
+		"mmcinfo; mmc dev 1; mmc read $load_addr "		\
+		"$kernel_addr_sd $kernel_size_sd && "	\
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+
+#define SD_BOOTCOMMAND	\
+	"run distro_bootcmd;run sd_bootcmd; " \
+	"env exists secureboot && esbc_halt;"
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+
+#ifndef CONFIG_CMDLINE_EDITING
+#define CONFIG_CMDLINE_EDITING		1
+#endif
+
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define OCRAM_NONSECURE_SIZE		0x00010000
+#define CONFIG_ENV_OFFSET              0x500000        /* 5MB */
+#define CONFIG_SYS_FSL_QSPI_BASE	0x20000000
+#define CONFIG_ENV_ADDR	CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_SECT_SIZE           0x40000
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
+#define I2C_MUX_CH_DEFAULT              0x8
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+#endif /* __L1028A_COMMON_H */
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
new file mode 100644
index 0000000..be018ef
--- /dev/null
+++ b/include/configs/ls1028aqds.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1028A_QDS_H
+#define __LS1028A_QDS_H
+
+#include "ls1028a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ / 4)
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		2
+
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE			0x7fb00000
+#define QIXIS_BASE_PHYS			QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_SWITCH		1
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		5
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x00
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_LBMAP_EMMC		0x00
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_SD		0x8
+#define QIXIS_RCW_SRC_EMMC		0x9
+#define QIXIS_RCW_SRC_QSPI		0xf
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+#endif
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM         1
+#define I2C_MUX_CH_RTC                 0xB
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_SIZE			0x2000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+/* DSPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifndef SPL_NO_ENV
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"board=ls1028aqds\0" \
+	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
+	"ramdisk_addr=0x800000\0" \
+	"ramdisk_size=0x2000000\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"fdt_addr=0x00f00000\0" \
+	"kernel_addr=0x01000000\0" \
+	"scriptaddr=0x80000000\0" \
+	"scripthdraddr=0x80080000\0" \
+	"fdtheader_addr_r=0x80100000\0" \
+	"kernelheader_addr_r=0x80200000\0" \
+	"load_addr=0xa0000000\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"fdt_addr_r=0x90000000\0" \
+	"ramdisk_addr_r=0xa0000000\0" \
+	"kernel_start=0x1000000\0" \
+	"kernelheader_start=0x800000\0" \
+	"kernel_load=0xa0000000\0" \
+	"kernel_size=0x2800000\0" \
+	"kernelheader_size=0x40000\0" \
+	"kernel_addr_sd=0x8000\0" \
+	"kernel_size_sd=0x14000\0" \
+	"kernelhdr_addr_sd=0x4000\0" \
+	"kernelhdr_size_sd=0x10\0" \
+	"console=ttyS0,115200\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	BOOTENV \
+	"boot_scripts=ls1028aqds_boot.scr\0" \
+	"boot_script_hdr=hdr_ls1028aqds_bs.out\0" \
+	"scan_dev_for_boot_part=" \
+		"part list ${devtype} ${devnum} devplist; " \
+		"env exists devplist || setenv devplist 1; " \
+		"for distro_bootpart in ${devplist}; do " \
+		  "if fstype ${devtype} " \
+			"${devnum}:${distro_bootpart} " \
+			"bootfstype; then " \
+			"run scan_dev_for_boot; " \
+		  "fi; " \
+		"done\0" \
+	"scan_dev_for_boot=" \
+		"echo Scanning ${devtype} " \
+				"${devnum}:${distro_bootpart}...; " \
+		"for prefix in ${boot_prefixes}; do " \
+			"run scan_dev_for_scripts; " \
+		"done;" \
+		"\0" \
+	"boot_a_script=" \
+		"load ${devtype} ${devnum}:${distro_bootpart} " \
+			"${scriptaddr} ${prefix}${script}; " \
+		"env exists secureboot && load ${devtype} " \
+			"${devnum}:${distro_bootpart} " \
+			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+			"&& esbc_validate ${scripthdraddr};" \
+		"source ${scriptaddr}\0" \
+	"sd_bootcmd=echo Trying load from SD ..;" \
+		"mmcinfo; mmc read $load_addr " \
+		"$kernel_addr_sd $kernel_size_sd && " \
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd " \
+		" && esbc_validate ${kernelheader_addr_r};" \
+		"bootm $load_addr#$board\0" \
+	"emmc_bootcmd=echo Trying load from EMMC ..;" \
+		"mmcinfo; mmc dev 1; mmc read $load_addr " \
+		"$kernel_addr_sd $kernel_size_sd && " \
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd " \
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"
+#endif
+#endif /* __LS1028A_QDS_H */
diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h
new file mode 100644
index 0000000..10791be
--- /dev/null
+++ b/include/configs/ls1028ardb.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1028A_RDB_H
+#define __LS1028A_RDB_H
+
+#include "ls1028a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ / 4)
+
+#define CONFIG_SYS_RTC_BUS_NUM         0
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_SIZE			0x2000
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR          1
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE			0x7fb00000
+#define QIXIS_BASE_PHYS			QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_SWITCH		2
+#define QIXIS_LBMAP_MASK		0xe0
+#define QIXIS_LBMAP_SHIFT		0x5
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x00
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_LBMAP_EMMC		0x00
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_SD		0xf8
+#define QIXIS_RCW_SRC_EMMC		0xf9
+#define QIXIS_RCW_SRC_QSPI		0xff
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x10
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x11
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+#endif
+
+/* SATA */
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define SCSI_VEND_ID 0x1b4b
+#define SCSI_DEV_ID  0x9170
+#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
+
+#endif /* __LS1028A_RDB_H */
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index dc688f3..70447a2 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -188,7 +188,6 @@
 #else
 #ifdef CONFIG_NAND_BOOT
 /* Store Fman ucode at offeset 0x900000(72 blocks). */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SD_BOOT)
 /*
@@ -196,14 +195,11 @@
  * about 1MB (2040 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
 #define CONFIG_SYS_QE_FW_ADDR		(512 * 0x4A00)
 #elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 /* FMan fireware Pre-load address */
 #define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
 #define CONFIG_SYS_QE_FW_ADDR		0x60940000
@@ -273,7 +269,8 @@
 			"${scriptaddr} ${prefix}${script}; "	\
 		"env exists secureboot && load ${devtype} "	\
 			"${devnum}:${distro_bootpart} "		\
-			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
 			"&& esbc_validate ${scripthdraddr};"	\
 		"source ${scriptaddr}\0"			\
 	"qspi_bootcmd=echo Trying load from qspi..;"	\
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 52b47ad..0e4e370 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -35,7 +35,6 @@
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHYLIB_10G
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 6ab83d0..d2979ef 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -277,8 +277,6 @@
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
 
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index ea6209a..34b4756 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -174,16 +174,12 @@
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
 #elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
 #elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(36 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
 #endif
 #endif
@@ -253,8 +249,9 @@
 			"${scriptaddr} ${prefix}${script}; "    \
 		"env exists secureboot && load ${devtype} "     \
 			"${devnum}:${distro_bootpart} "		\
-			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
-			"&& esbc_validate ${scripthdraddr};"    \
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
+			"&& esbc_validate ${scripthdraddr};"	\
 		"source ${scriptaddr}\0"	  \
 	"qspi_bootcmd=echo Trying load from qspi..;"      \
 		"sf probe && sf read $load_addr "         \
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 58dd9fb..eea738e 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -52,7 +52,6 @@
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHYLIB_10G
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index f22e863..8317672 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -183,7 +183,6 @@
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
 
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 45af087..322adb5 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -398,7 +398,8 @@
 		"${scriptaddr} ${prefix}${script}; "		\
 	"env exists secureboot && load ${devtype} "		\
 		"${devnum}:${distro_bootpart} "			\
-		"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+		"${scripthdraddr} ${prefix}${boot_script_hdr}; "\
+		"env exists secureboot "			\
 		"&& esbc_validate ${scripthdraddr};"		\
 		"source ${scriptaddr}\0"			\
 	"installer=load mmc 0:2 $load_addr "			\
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index e41ace6..2e8a8bb 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -495,7 +495,8 @@
 			"${scriptaddr} ${prefix}${script}; "	\
 		"env exists secureboot && load ${devtype} "	\
 			"${devnum}:${distro_bootpart} "		\
-			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
 			"&& esbc_validate ${scripthdraddr};"	\
 		"source ${scriptaddr}\0"			\
 	"qspi_bootcmd=echo Trying load from qspi..;"		\
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 637619c..eb0b176 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -187,7 +187,6 @@
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
-#define CONFIG_CMDLINE_EDITING		1
 #define CONFIG_SYS_MAXARGS		64	/* max command args */
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 972bb5e..c6bacb6 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -60,6 +60,7 @@
 
 #define AQR107_PHY_ADDR1	0x04
 #define AQR107_PHY_ADDR2	0x05
+#define AQR107_IRQ_MASK		0x0C
 
 #define CORTINA_NO_FW_UPLOAD
 #define CORTINA_PHY_ADDR1	0x0
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 8c870b0..19ba022 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -74,7 +74,6 @@
 #if defined(CONFIG_TARGET_P1021RDB)
 #define CONFIG_BOARDNAME "P1021RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_QE
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
 						addresses in the LBC */
@@ -105,7 +104,6 @@
 #if defined(CONFIG_TARGET_P1025RDB)
 #define CONFIG_BOARDNAME "P1025RDB"
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_QE
 #define CONFIG_SLIC
 
 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
@@ -652,7 +650,6 @@
 
 #ifdef CONFIG_QE
 /* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FW_ADDR	0xefec0000
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #endif /* CONFIG_QE */
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 4f48370..e42b9b0 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -12,7 +12,6 @@
 #if defined(CONFIG_TWR_P1025)
 #define CONFIG_BOARDNAME "TWR-P1025"
 #define CONFIG_PHY_ATHEROS
-#define CONFIG_QE
 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Conversion of LBC addr */
 #define CONFIG_SYS_LBC_LCRR	0x80000002	/* LB clock ratio reg */
 #endif
@@ -275,7 +274,6 @@
 
 #ifdef CONFIG_QE
 /* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FW_ADDR	0xefec0000
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #endif /* CONFIG_QE */
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index fd6c97a..e8be51a 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -23,11 +23,6 @@
 #endif
 
 /*
- * malloc() pool size
- */
-#define CONFIG_SYS_MALLOC_LEN			SZ_32M
-
-/*
  * Configuration of the external SRAM memory used by U-Boot
  */
 #define CONFIG_SYS_SDRAM_BASE			STM32_DDR_BASE
@@ -43,11 +38,6 @@
  */
 #define CONFIG_SYS_LOAD_ADDR			STM32_DDR_BASE
 
-/*
- * Env parameters
- */
-#define CONFIG_ENV_SIZE				SZ_4K
-
 /* ATAGs */
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
@@ -95,8 +85,6 @@
  * for nand boot, boot with on ubifs partition on nand
  * for nor boot, use the default order
  */
-#define CONFIG_PREBOOT
-
 #define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
 	"echo \"Boot over ${boot_device}${boot_instance}!\";" \
 	"if test ${boot_device} = serial || test ${boot_device} = usb;" \
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index 17f92d8..3596658 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -68,17 +68,6 @@
 
 #define CONFIG_SYS_SBFHDR_SIZE		0x7
 
-#define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
-					DSPI_CTAR_PCSSCK_1CLK | \
-					DSPI_CTAR_PASC(0) | \
-					DSPI_CTAR_PDT(0) | \
-					DSPI_CTAR_CSSCK(0) | \
-					DSPI_CTAR_ASC(0) | \
-					DSPI_CTAR_DT(1) | \
-					DSPI_CTAR_BR(6))
-#define CONFIG_SYS_DSPI_CTAR1		(CONFIG_SYS_DSPI_CTAR0)
-#define CONFIG_SYS_DSPI_CTAR2		(CONFIG_SYS_DSPI_CTAR0)
-
 /* Input, PCI, Flexbus, and VCO */
 #define CONFIG_EXTRA_CLOCK
 
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index d206ee2..4ab2ae1 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -224,7 +224,7 @@
  * @def:	default value to return if the property has no value
  * @return property value, or @def if not found
  */
-int ofnode_read_u32_default(ofnode ref, const char *propname, u32 def);
+u32 ofnode_read_u32_default(ofnode ref, const char *propname, u32 def);
 
 /**
  * ofnode_read_s32_default() - Read a 32-bit integer from a property
@@ -355,6 +355,20 @@
 int ofnode_read_size(ofnode node, const char *propname);
 
 /**
+ * ofnode_get_addr_size_index() - get an address/size from a node
+ *				  based on index
+ *
+ * This reads the register address/size from a node based on index
+ *
+ * @node: node to read from
+ * @index: Index of address to read (0 for first)
+ * @size: Pointer to size of the address
+ * @return address, or FDT_ADDR_T_NONE if not present or invalid
+ */
+phys_addr_t ofnode_get_addr_size_index(ofnode node, int index,
+				       fdt_size_t *size);
+
+/**
  * ofnode_get_addr_index() - get an address from a node
  *
  * This reads the register address from a node
diff --git a/include/dm/platform_data/spi_coldfire.h b/include/dm/platform_data/spi_coldfire.h
new file mode 100644
index 0000000..8ad8eae
--- /dev/null
+++ b/include/dm/platform_data/spi_coldfire.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018  Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __spi_coldfire_h
+#define __spi_coldfire_h
+
+#define MAX_CTAR_REGS		8
+#define MAX_CTAR_FIELDS		8
+
+/*
+ * struct coldfire_spi_platdata - information about a coldfire spi module
+ *
+ * @regs_addr: base address for module registers
+ * @speed_hz: default SCK frequency
+ * @mode: default SPI mode
+ * @num_cs: number of DSPI chipselect signals
+ */
+struct coldfire_spi_platdata {
+	fdt_addr_t regs_addr;
+	uint speed_hz;
+	uint mode;
+	uint num_cs;
+	uint ctar[MAX_CTAR_REGS][MAX_CTAR_FIELDS];
+};
+
+#endif /* __spi_coldfire_h */
+
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 8167e6f..43d3a08 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -160,27 +160,36 @@
 extern unsigned int __efi_runtime_start, __efi_runtime_stop;
 extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
 
-/*
+/**
+ * struct efi_open_protocol_info_item - open protocol info item
+ *
  * When a protocol is opened a open protocol info entry is created.
  * These are maintained in a list.
+ *
+ * @link:	link to the list of open protocol info entries of a protocol
+ * @info:	information about the opening of a protocol
  */
 struct efi_open_protocol_info_item {
-	/* Link to the list of open protocol info entries of a protocol */
 	struct list_head link;
 	struct efi_open_protocol_info_entry info;
 };
 
-/*
+/**
+ * struct efi_handler - single protocol interface of a handle
+ *
  * When the UEFI payload wants to open a protocol on an object to get its
  * interface (usually a struct with callback functions), this struct maps the
  * protocol GUID to the respective protocol interface
+ *
+ * @link:		link to the list of protocols of a handle
+ * @guid:		GUID of the protocol
+ * @protocol_interface:	protocol interface
+ * @open_infos		link to the list of open protocol info items
  */
 struct efi_handler {
-	/* Link to the list of protocols of a handle */
 	struct list_head link;
 	const efi_guid_t *guid;
 	void *protocol_interface;
-	/* Link to the list of open protocol info items */
 	struct list_head open_infos;
 };
 
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 110aa6a..fa8e34f 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -24,30 +24,6 @@
 typedef phys_addr_t fdt_addr_t;
 typedef phys_size_t fdt_size_t;
 
-static inline fdt32_t fdt_addr_unpack(fdt_addr_t addr, fdt32_t *upper)
-{
-	if (upper)
-#ifdef CONFIG_PHYS_64BIT
-		*upper = addr >> 32;
-#else
-		*upper = 0;
-#endif
-
-	return addr;
-}
-
-static inline fdt32_t fdt_size_unpack(fdt_size_t size, fdt32_t *upper)
-{
-	if (upper)
-#ifdef CONFIG_PHYS_64BIT
-		*upper = size >> 32;
-#else
-		*upper = 0;
-#endif
-
-	return size;
-}
-
 #ifdef CONFIG_PHYS_64BIT
 #define FDT_ADDR_T_NONE (-1U)
 #define fdt_addr_to_cpu(reg) be64_to_cpu(reg)
diff --git a/include/stdint.h b/include/stdint.h
new file mode 100644
index 0000000..2e126d1
--- /dev/null
+++ b/include/stdint.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Dummy file to allow libraries linked with U-Boot to include stdint.h without
+ * getting the system version.
+ *
+ * U-Boot uses linux types (linux/types.h) so does not make use of stdint.h
+ */
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 971bd5f..54fff85 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -2360,7 +2360,10 @@
 
 			r = EFI_CALL(efi_locate_device_path(protocol, &dp,
 							    &old_handle));
-			if (r == EFI_SUCCESS) {
+			if (r == EFI_SUCCESS &&
+			    dp->type == DEVICE_PATH_TYPE_END) {
+				EFI_PRINT("Path %pD already installed\n",
+					  protocol_interface);
 				r = EFI_ALREADY_STARTED;
 				break;
 			}
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 636dfda..058b40a 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -169,7 +169,6 @@
 {
 #ifdef CONFIG_DM_RTC
 	efi_status_t ret = EFI_SUCCESS;
-	int r;
 	struct rtc_time tm;
 	struct udevice *dev;
 
@@ -179,11 +178,12 @@
 		ret = EFI_INVALID_PARAMETER;
 		goto out;
 	}
-
-	r = uclass_get_device(UCLASS_RTC, 0, &dev);
-	if (!r)
-		r = dm_rtc_get(dev, &tm);
-	if (r) {
+	if (uclass_get_device(UCLASS_RTC, 0, &dev) ||
+	    dm_rtc_get(dev, &tm)) {
+		ret = EFI_UNSUPPORTED;
+		goto out;
+	}
+	if (dm_rtc_get(dev, &tm)) {
 		ret = EFI_DEVICE_ERROR;
 		goto out;
 	}
@@ -210,11 +210,61 @@
 	return EFI_EXIT(ret);
 #else
 	EFI_ENTRY("%p %p", time, capabilities);
-	return EFI_EXIT(EFI_DEVICE_ERROR);
+	return EFI_EXIT(EFI_UNSUPPORTED);
 #endif
 }
 
+/**
+ * efi_set_time_boottime() - set current time
+ *
+ * This function implements the SetTime() runtime service before
+ * SetVirtualAddressMap() is called.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @time:		pointer to structure to with current time
+ * Returns:		status code
+ */
+static efi_status_t EFIAPI efi_set_time_boottime(struct efi_time *time)
+{
+#ifdef CONFIG_DM_RTC
+	efi_status_t ret = EFI_SUCCESS;
+	struct rtc_time tm;
+	struct udevice *dev;
 
+	EFI_ENTRY("%p", time);
+
+	if (!time) {
+		ret = EFI_INVALID_PARAMETER;
+		goto out;
+	}
+
+	if (uclass_get_device(UCLASS_RTC, 0, &dev)) {
+		ret = EFI_UNSUPPORTED;
+		goto out;
+	}
+
+	memset(&tm, 0, sizeof(tm));
+	tm.tm_year = time->year;
+	tm.tm_mon = time->month;
+	tm.tm_mday = time->day;
+	tm.tm_hour = time->hour;
+	tm.tm_min = time->minute;
+	tm.tm_sec = time->second;
+	tm.tm_isdst = time->daylight == EFI_TIME_IN_DAYLIGHT;
+	/* Calculate day of week */
+	rtc_calc_weekday(&tm);
+
+	if (dm_rtc_set(dev, &tm))
+		ret = EFI_DEVICE_ERROR;
+out:
+	return EFI_EXIT(ret);
+#else
+	EFI_ENTRY("%p", time);
+	return EFI_EXIT(EFI_UNSUPPORTED);
+#endif
+}
 /**
  * efi_reset_system() - reset system
  *
@@ -271,6 +321,24 @@
 	return EFI_DEVICE_ERROR;
 }
 
+/**
+ * efi_set_time() - set current time
+ *
+ * This function implements the SetTime runtime service after
+ * SetVirtualAddressMap() is called. As the U-Boot driver are not available
+ * anymore only an error code is returned.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @time:		pointer to structure to with current time
+ * Returns:		status code
+ */
+efi_status_t __weak __efi_runtime EFIAPI efi_set_time(struct efi_time *time)
+{
+	return EFI_UNSUPPORTED;
+}
+
 struct efi_runtime_detach_list_struct {
 	void *ptr;
 	void *patchto;
@@ -290,6 +358,9 @@
 		.ptr = &efi_runtime_services.get_time,
 		.patchto = &efi_get_time,
 	}, {
+		.ptr = &efi_runtime_services.set_time,
+		.patchto = &efi_set_time,
+	}, {
 		/* Clean up system table */
 		.ptr = &systab.con_in,
 		.patchto = NULL,
@@ -697,7 +768,7 @@
 		.headersize = sizeof(struct efi_runtime_services),
 	},
 	.get_time = &efi_get_time_boottime,
-	.set_time = (void *)&efi_device_error,
+	.set_time = &efi_set_time_boottime,
 	.get_wakeup_time = (void *)&efi_unimplemented,
 	.set_wakeup_time = (void *)&efi_unimplemented,
 	.set_virtual_address_map = &efi_set_virtual_address_map,
diff --git a/lib/efi_loader/efi_unicode_collation.c b/lib/efi_loader/efi_unicode_collation.c
index 06fddca..f293b42 100644
--- a/lib/efi_loader/efi_unicode_collation.c
+++ b/lib/efi_loader/efi_unicode_collation.c
@@ -12,7 +12,7 @@
 #include <efi_loader.h>
 
 /* Characters that may not be used in file names */
-static const char illegal[] = "<>:\"/\\|?*";
+static const char illegal[] = "<>:\"/\\|?*\x7f";
 
 /*
  * EDK2 assumes codepage 1250 when creating FAT 8.3 file names.
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 28b1aa7..50bc105 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -427,7 +427,9 @@
 	EFI_ENTRY("\"%ls\" %pUl %x %zu %p", variable_name, vendor, attributes,
 		  data_size, data);
 
-	if (!variable_name || !vendor) {
+	/* TODO: implement APPEND_WRITE */
+	if (!variable_name || !vendor ||
+	    (attributes & EFI_VARIABLE_APPEND_WRITE)) {
 		ret = EFI_INVALID_PARAMETER;
 		goto out;
 	}
@@ -449,12 +451,21 @@
 	if (val) {
 		parse_attr(val, &attr);
 
+		/* We should not free val */
+		val = NULL;
 		if (attr & READ_ONLY) {
-			/* We should not free val */
-			val = NULL;
 			ret = EFI_WRITE_PROTECTED;
 			goto out;
 		}
+
+		/*
+		 * attributes won't be changed
+		 * TODO: take care of APPEND_WRITE once supported
+		 */
+		if (attr != attributes) {
+			ret = EFI_INVALID_PARAMETER;
+			goto out;
+		}
 	}
 
 	val = malloc(2 * data_size + strlen("{ro,run,boot}(blob)") + 1);
diff --git a/lib/efi_selftest/efi_selftest_rtc.c b/lib/efi_selftest/efi_selftest_rtc.c
index 8d440dc..9eb29ad 100644
--- a/lib/efi_selftest/efi_selftest_rtc.c
+++ b/lib/efi_selftest/efi_selftest_rtc.c
@@ -10,6 +10,7 @@
 #include <efi_selftest.h>
 
 #define EFI_ST_NO_RTC "Could not read real time clock\n"
+#define EFI_ST_NO_RTC_SET "Could not set real time clock\n"
 
 static struct efi_runtime_services *runtime;
 
@@ -30,17 +31,26 @@
 /*
  * Execute unit test.
  *
- * Display current time.
+ * Read and display current time.
+ * Set a new value and read it back.
+ * Set the real time clock back the current time.
  *
  * @return:	EFI_ST_SUCCESS for success
  */
 static int execute(void)
 {
 	efi_status_t ret;
-	struct efi_time tm;
+	struct efi_time tm, tm_old, tm_new = {
+		.year = 2017,
+		.month = 5,
+		.day = 19,
+		.hour = 13,
+		.minute = 47,
+		.second = 53,
+	};
 
 	/* Display current time */
-	ret = runtime->get_time(&tm, NULL);
+	ret = runtime->get_time(&tm_old, NULL);
 	if (ret != EFI_SUCCESS) {
 #ifdef CONFIG_CMD_DATE
 		efi_st_error(EFI_ST_NO_RTC);
@@ -49,11 +59,41 @@
 		efi_st_todo(EFI_ST_NO_RTC);
 		return EFI_ST_SUCCESS;
 #endif
-	} else {
-		efi_st_printf("Time according to real time clock: "
-			      "%.4u-%.2u-%.2u %.2u:%.2u:%.2u\n",
-			      tm.year, tm.month, tm.day,
-			      tm.hour, tm.minute, tm.second);
+	}
+	efi_st_printf("Time according to real time clock: "
+		      "%.4u-%.2u-%.2u %.2u:%.2u:%.2u\n",
+		      tm_old.year, tm_old.month, tm_old.day,
+		      tm_old.hour, tm_old.minute, tm_old.second);
+	ret = runtime->set_time(&tm_new);
+	if (ret != EFI_SUCCESS) {
+#ifdef CONFIG_CMD_DATE
+		efi_st_error(EFI_ST_NO_RTC_SET);
+		return EFI_ST_FAILURE;
+#else
+		efi_st_todo(EFI_ST_NO_RTC_SET);
+		return EFI_ST_SUCCESS;
+#endif
+	}
+	ret = runtime->get_time(&tm, NULL);
+	if (ret != EFI_SUCCESS) {
+		efi_st_error(EFI_ST_NO_RTC);
+		return EFI_ST_FAILURE;
+	}
+	if (tm.year != tm_new.year ||
+	    tm.month != tm_new.month ||
+	    tm.day != tm_new.day ||
+	    tm.hour !=  tm_new.hour ||
+	    tm.minute != tm_new.minute ||
+	    tm.second < tm_new.second ||
+	    tm.second > tm_new.second + 2) {
+		efi_st_error(EFI_ST_NO_RTC_SET);
+		return EFI_ST_FAILURE;
+	}
+	/* Set time back to old value */
+	ret = runtime->set_time(&tm_old);
+	if (ret != EFI_SUCCESS) {
+		efi_st_error(EFI_ST_NO_RTC_SET);
+		return EFI_ST_FAILURE;
 	}
 
 	return EFI_ST_SUCCESS;
diff --git a/lib/efi_selftest/efi_selftest_variables.c b/lib/efi_selftest/efi_selftest_variables.c
index b028c64..06c1a03 100644
--- a/lib/efi_selftest/efi_selftest_variables.c
+++ b/lib/efi_selftest/efi_selftest_variables.c
@@ -116,21 +116,21 @@
 				    EFI_VARIABLE_APPEND_WRITE,
 				    7, v + 8);
 	if (ret != EFI_SUCCESS) {
-		efi_st_error("SetVariable failed\n");
-		return EFI_ST_FAILURE;
+		efi_st_todo("SetVariable(APPEND_WRITE) failed\n");
+	} else {
+		len = EFI_ST_MAX_DATA_SIZE;
+		ret = runtime->get_variable(L"efi_st_var1", &guid_vendor1,
+					    &attr, &len, data);
+		if (ret != EFI_SUCCESS) {
+			efi_st_error("GetVariable failed\n");
+			return EFI_ST_FAILURE;
+		}
+		if (len != 15)
+			efi_st_todo("GetVariable returned wrong length %u\n",
+				    (unsigned int)len);
+		if (memcmp(data, v, len))
+			efi_st_todo("GetVariable returned wrong value\n");
 	}
-	len = EFI_ST_MAX_DATA_SIZE;
-	ret = runtime->get_variable(L"efi_st_var1", &guid_vendor1,
-				    &attr, &len, data);
-	if (ret != EFI_SUCCESS) {
-		efi_st_error("GetVariable failed\n");
-		return EFI_ST_FAILURE;
-	}
-	if (len != 15)
-		efi_st_todo("GetVariable returned wrong length %u\n",
-			    (unsigned int)len);
-	if (memcmp(data, v, len))
-		efi_st_todo("GetVariable returned wrong value\n");
 	/* Enumerate variables */
 	boottime->set_mem(&guid, 16, 0);
 	*varname = 0;
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index fea44a9..d0ba888 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1300,6 +1300,7 @@
 	fdt32_t cells[4] = {}, *ptr = cells;
 	uint32_t upper, lower, phandle;
 	int parent, node, na, ns, err;
+	fdt_size_t size;
 	char name[64];
 
 	/* create an empty /reserved-memory node if one doesn't exist */
@@ -1340,7 +1341,8 @@
 	 * Unpack the start address and generate the name of the new node
 	 * base on the basename and the unit-address.
 	 */
-	lower = fdt_addr_unpack(carveout->start, &upper);
+	upper = upper_32_bits(carveout->start);
+	lower = lower_32_bits(carveout->start);
 
 	if (na > 1 && upper > 0)
 		snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
@@ -1374,7 +1376,9 @@
 	*ptr++ = cpu_to_fdt32(lower);
 
 	/* store one or two size cells */
-	lower = fdt_size_unpack(carveout->end - carveout->start + 1, &upper);
+	size = carveout->end - carveout->start + 1;
+	upper = upper_32_bits(size);
+	lower = lower_32_bits(size);
 
 	if (ns > 1)
 		*ptr++ = cpu_to_fdt32(upper);
diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c
index f6defe1..1f4f270 100644
--- a/lib/fdtdec_test.c
+++ b/lib/fdtdec_test.c
@@ -155,11 +155,13 @@
 	};
 	fdt32_t cells[4], *ptr = cells;
 	uint32_t upper, lower;
+	fdt_size_t size;
 	char name[32];
 	int offset;
 
 	/* store one or two address cells */
-	lower = fdt_addr_unpack(carveout.start, &upper);
+	upper = upper_32_bits(carveout.start);
+	lower = lower_32_bits(carveout.start);
 
 	if (na > 1 && upper > 0)
 		snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
@@ -173,7 +175,9 @@
 	*ptr++ = cpu_to_fdt32(lower);
 
 	/* store one or two size cells */
-	lower = fdt_size_unpack(carveout.end - carveout.start + 1, &upper);
+	size = carveout.end - carveout.start + 1;
+	upper = upper_32_bits(size);
+	lower = lower_32_bits(size);
 
 	if (ns > 1)
 		*ptr++ = cpu_to_fdt32(upper);
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 5ec4ffb..2c41baa 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -177,7 +177,6 @@
 CONFIG_BUILD_ENVCRC
 CONFIG_BUS_WIDTH
 CONFIG_BZIP2
-CONFIG_CADDY2
 CONFIG_CALXEDA_XGMAC
 CONFIG_CDP_APPLIANCE_VLAN_TYPE
 CONFIG_CDP_CAPABILITIES
@@ -243,7 +242,6 @@
 CONFIG_CONS_SCIF3
 CONFIG_CONS_SCIF4
 CONFIG_CONS_SCIF5
-CONFIG_CONS_SCIF7
 CONFIG_CONTROL
 CONFIG_CONTROLCENTERD
 CONFIG_CON_ROT
@@ -348,7 +346,6 @@
 CONFIG_DISCONTIGMEM
 CONFIG_DISCOVER_PHY
 CONFIG_DISPLAY_AER_xxxx
-CONFIG_DLVISION_10G
 CONFIG_DM9000_BASE
 CONFIG_DM9000_BYTE_SWAPPED
 CONFIG_DM9000_DEBUG
@@ -371,7 +368,6 @@
 CONFIG_DRIVER_AX88796L
 CONFIG_DRIVER_DM9000
 CONFIG_DRIVER_EP93XX_MAC
-CONFIG_DRIVER_ETHER
 CONFIG_DRIVER_NE2000
 CONFIG_DRIVER_NE2000_BASE
 CONFIG_DRIVER_NE2000_CCR
@@ -379,9 +375,6 @@
 CONFIG_DRIVER_SMC911X_BASE
 CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
 CONFIG_DRIVER_TI_EMAC_USE_RMII
-CONFIG_DRIVE_MMC
-CONFIG_DRIVE_SATA
-CONFIG_DRIVE_TYPES
 CONFIG_DSP_CLUSTER_START
 CONFIG_DUOVERO
 CONFIG_DWC2_DFLT_SPEED_FULL
@@ -449,7 +442,6 @@
 CONFIG_EHCI_MXS_PORT0
 CONFIG_EHCI_MXS_PORT1
 CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
-CONFIG_EMMC_BOOT
 CONFIG_EMU
 CONFIG_ENABLE_36BIT_PHYS
 CONFIG_ENABLE_MMU
@@ -485,10 +477,6 @@
 CONFIG_ENV_SETTINGS_V2
 CONFIG_ENV_SIZE_FLEX
 CONFIG_ENV_SIZE_REDUND
-CONFIG_ENV_SPI_BUS
-CONFIG_ENV_SPI_CS
-CONFIG_ENV_SPI_MAX_HZ
-CONFIG_ENV_SPI_MODE
 CONFIG_ENV_SROM_BANK
 CONFIG_ENV_TOTAL_SIZE
 CONFIG_ENV_UBIFS_OPTION
@@ -507,7 +495,6 @@
 CONFIG_ESBC_HDR_LS
 CONFIG_ESDHC_DETECT_8_BIT_QUIRK
 CONFIG_ESDHC_DETECT_QUIRK
-CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1
 CONFIG_ESDHC_HC_BLK_ADDR
 CONFIG_ESPRESSO7420
 CONFIG_ET1100_BASE
@@ -598,7 +585,6 @@
 CONFIG_FLASH_SHOW_PROGRESS
 CONFIG_FLASH_SPANSION_S29WS_N
 CONFIG_FLASH_VERIFY
-CONFIG_FMAN_ENET
 CONFIG_FM_PLAT_CLK_DIV
 CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
 CONFIG_FORMIKE
@@ -708,7 +694,6 @@
 CONFIG_GREEN_LED
 CONFIG_GURNARD_FPGA
 CONFIG_GURNARD_SPLASH
-CONFIG_GZIP
 CONFIG_GZIP_COMPRESSED
 CONFIG_GZIP_COMPRESS_DEF_SZ
 CONFIG_G_DNL_THOR_PRODUCT_NUM
@@ -716,7 +701,6 @@
 CONFIG_G_DNL_UMS_PRODUCT_NUM
 CONFIG_G_DNL_UMS_VENDOR_NUM
 CONFIG_H264_FREQ
-CONFIG_H8300
 CONFIG_HAS_ETH0
 CONFIG_HAS_ETH1
 CONFIG_HAS_ETH2
@@ -910,7 +894,6 @@
 CONFIG_I2C_TIMEOUT
 CONFIG_ICACHE
 CONFIG_ICS307_REFCLK_HZ
-CONFIG_IDE_PCMCIA
 CONFIG_IDE_PREINIT
 CONFIG_IDE_RESET
 CONFIG_IDE_SWAP_IO
@@ -933,9 +916,6 @@
 CONFIG_INI_MAX_SECTION
 CONFIG_INTEGRITY
 CONFIG_INTERRUPTS
-CONFIG_IO
-CONFIG_IO64
-CONFIG_IOCON
 CONFIG_IODELAY_RECALIBRATION
 CONFIG_IOMUX_LPSR
 CONFIG_IOMUX_SHARE_CONF_REG
@@ -984,14 +964,9 @@
 CONFIG_KIRQ_EN
 CONFIG_KM8321
 CONFIG_KMCOGE4
-CONFIG_KMCOGE5NE
-CONFIG_KMETER1
 CONFIG_KMLION1
-CONFIG_KMOPTI2
 CONFIG_KMP204X
-CONFIG_KMSUPX5
 CONFIG_KMTEGR1
-CONFIG_KMTEPR2
 CONFIG_KMVECT1
 CONFIG_KM_BOARD_EXTRA_ENV
 CONFIG_KM_BOARD_NAME
@@ -1177,7 +1152,6 @@
 CONFIG_MCFPIT
 CONFIG_MCFRTC
 CONFIG_MCFTMR
-CONFIG_MCFUART
 CONFIG_MCLK_DIS
 CONFIG_MDIO_TIMEOUT
 CONFIG_MEMSIZE
@@ -1340,7 +1314,6 @@
 CONFIG_NO_ETH
 CONFIG_NO_RELOCATION
 CONFIG_NO_WAIT
-CONFIG_NR_CPUS
 CONFIG_NR_DRAM_POPULATED
 CONFIG_NS16550_MIN_FUNCTIONS
 CONFIG_NS8382X
@@ -1497,7 +1470,6 @@
 CONFIG_PQ_MDS_PIB
 CONFIG_PQ_MDS_PIB_ATM
 CONFIG_PRAM
-CONFIG_PREBOOT
 CONFIG_PRINTK
 CONFIG_PROC_FS
 CONFIG_PROFILE_ALL_BRANCHES
@@ -1520,7 +1492,6 @@
 CONFIG_PXA_VGA
 CONFIG_PXA_VIDEO
 CONFIG_QBMAN_CLK_DIV
-CONFIG_QE
 CONFIG_QEMU_MIPS
 CONFIG_QIXIS_I2C_ACCESS
 CONFIG_QSPI
@@ -1546,7 +1517,6 @@
 CONFIG_RD_LVL
 CONFIG_REALMODE_DEBUG
 CONFIG_RED_LED
-CONFIG_REFCLK_FREQ
 CONFIG_REG
 CONFIG_REG_0
 CONFIG_REG_1_BASE
@@ -1635,7 +1605,6 @@
 CONFIG_SCF0403_LCD
 CONFIG_SCIF
 CONFIG_SCIF_A
-CONFIG_SCIF_EXT_CLOCK
 CONFIG_SCIF_USE_EXT_CLK
 CONFIG_SCSI_AHCI_PLAT
 CONFIG_SCSI_DEV_LIST
@@ -1678,7 +1647,6 @@
 CONFIG_SHARP_LQ035Q7DH06
 CONFIG_SHEEVA_88SV131
 CONFIG_SHEEVA_88SV331xV5
-CONFIG_SHMIN
 CONFIG_SHOW_ACTIVITY
 CONFIG_SHOW_BOOT_PROGRESS
 CONFIG_SH_CMT_CLK_FREQ
@@ -1735,10 +1703,7 @@
 CONFIG_SMSTP8_ENA
 CONFIG_SMSTP9_ENA
 CONFIG_SOCRATES
-CONFIG_SOC_DM355
-CONFIG_SOC_DM365
 CONFIG_SOC_DM644X
-CONFIG_SOC_DM646X
 CONFIG_SOC_K2E
 CONFIG_SOC_K2G
 CONFIG_SOC_K2HK
@@ -1906,7 +1871,6 @@
 CONFIG_ST_SMI
 CONFIG_SUNXI_GPIO
 CONFIG_SUNXI_MAX_FB_SIZE
-CONFIG_SUPERH_ON_CHIP_R8A66597
 CONFIG_SUVD3
 CONFIG_SXNI855T
 CONFIG_SYSFLAGS_ADDR
@@ -2396,13 +2360,6 @@
 CONFIG_SYS_DIRECT_FLASH_TFTP
 CONFIG_SYS_DISCOVER_PHY
 CONFIG_SYS_DIU_ADDR
-CONFIG_SYS_DM36x_PINMUX0
-CONFIG_SYS_DM36x_PINMUX1
-CONFIG_SYS_DM36x_PINMUX2
-CONFIG_SYS_DM36x_PINMUX3
-CONFIG_SYS_DM36x_PINMUX4
-CONFIG_SYS_DM36x_PLL1_PREDIV
-CONFIG_SYS_DM36x_PLL2_PREDIV
 CONFIG_SYS_DMA_USE_INTSRAM
 CONFIG_SYS_DP501_BASE
 CONFIG_SYS_DP501_DIFFERENTIAL
@@ -2564,8 +2521,6 @@
 CONFIG_SYS_FORM_PMC_XMC
 CONFIG_SYS_FORM_VME
 CONFIG_SYS_FORM_XMC
-CONFIG_SYS_FPGA0_BASE
-CONFIG_SYS_FPGA0_SIZE
 CONFIG_SYS_FPGAREG_DATE
 CONFIG_SYS_FPGAREG_DIPSW
 CONFIG_SYS_FPGAREG_FREQ
@@ -2883,8 +2838,6 @@
 CONFIG_SYS_GAFR2_U_VAL
 CONFIG_SYS_GAFR3_L_VAL
 CONFIG_SYS_GAFR3_U_VAL
-CONFIG_SYS_GBIT_MII1_BUSNAME
-CONFIG_SYS_GBIT_MII_BUSNAME
 CONFIG_SYS_GBL_DATA_OFFSET
 CONFIG_SYS_GBL_DATA_SIZE
 CONFIG_SYS_GIC400_ADDR
@@ -2925,9 +2878,7 @@
 CONFIG_SYS_HELP_CMD_WIDTH
 CONFIG_SYS_HIGH
 CONFIG_SYS_HMI_BASE
-CONFIG_SYS_HOSTNAME
 CONFIG_SYS_HRCW_HIGH
-CONFIG_SYS_HRCW_HIGH_BASE
 CONFIG_SYS_HRCW_LOW
 CONFIG_SYS_HZ_CLOCK
 CONFIG_SYS_I2C
@@ -3209,7 +3160,6 @@
 CONFIG_SYS_LOAD_ADDR
 CONFIG_SYS_LOAD_ADDR2
 CONFIG_SYS_LOW
-CONFIG_SYS_LOWBOOT
 CONFIG_SYS_LOWMEM_BASE
 CONFIG_SYS_LOW_RES_TIMER
 CONFIG_SYS_LPAE_SDRAM_BASE
@@ -3244,10 +3194,6 @@
 CONFIG_SYS_MAPLE
 CONFIG_SYS_MAPLE_MEM_PHYS
 CONFIG_SYS_MAPPED_RAM_BASE
-CONFIG_SYS_MARUBUN_IO
-CONFIG_SYS_MARUBUN_MRSHPC
-CONFIG_SYS_MARUBUN_MW1
-CONFIG_SYS_MARUBUN_MW2
 CONFIG_SYS_MASTER_CLOCK
 CONFIG_SYS_MATRIX_EBI0CSA_VAL
 CONFIG_SYS_MATRIX_EBICSA_VAL
@@ -3282,13 +3228,9 @@
 CONFIG_SYS_MCLINK_MAX
 CONFIG_SYS_MCMEM0_VAL
 CONFIG_SYS_MCMEM1_VAL
-CONFIG_SYS_MDC1_PIN
 CONFIG_SYS_MDCNFG_VAL
-CONFIG_SYS_MDC_PIN
 CONFIG_SYS_MDIO1_OFFSET
-CONFIG_SYS_MDIO1_PIN
 CONFIG_SYS_MDIO_BASE_ADDR
-CONFIG_SYS_MDIO_PIN
 CONFIG_SYS_MDMRS_VAL
 CONFIG_SYS_MDREFR_VAL
 CONFIG_SYS_MECR_VAL
@@ -3499,7 +3441,6 @@
 CONFIG_SYS_NOR1_CSPR_EXT
 CONFIG_SYS_NOR_AMASK
 CONFIG_SYS_NOR_AMASK_EARLY
-CONFIG_SYS_NOR_BR_PRELIM
 CONFIG_SYS_NOR_CSOR
 CONFIG_SYS_NOR_CSPR
 CONFIG_SYS_NOR_CSPR_EXT
@@ -3507,7 +3448,6 @@
 CONFIG_SYS_NOR_FTIM1
 CONFIG_SYS_NOR_FTIM2
 CONFIG_SYS_NOR_FTIM3
-CONFIG_SYS_NOR_OR_PRELIM
 CONFIG_SYS_NO_DCACHE
 CONFIG_SYS_NS16550_CLK
 CONFIG_SYS_NS16550_CLK_DIV
@@ -3584,7 +3524,6 @@
 CONFIG_SYS_OR1_REMAP
 CONFIG_SYS_OR6_64M
 CONFIG_SYS_OR6_8M
-CONFIG_SYS_OR_TIMING_FLASH
 CONFIG_SYS_OR_TIMING_MRAM
 CONFIG_SYS_OSCIN_FREQ
 CONFIG_SYS_OSD_DH
@@ -3893,7 +3832,6 @@
 CONFIG_SYS_POST_WORD_ADDR
 CONFIG_SYS_PPC_DDR_WIMGE
 CONFIG_SYS_PQSPAR
-CONFIG_SYS_PRELIM_OR_AM
 CONFIG_SYS_PROMPT_HUSH_PS2
 CONFIG_SYS_PSDPAR
 CONFIG_SYS_PSSR_VAL
@@ -3901,13 +3839,8 @@
 CONFIG_SYS_PTDPAR
 CONFIG_SYS_PTV
 CONFIG_SYS_PUAPAR
-CONFIG_SYS_QE_FMAN_FW_IN_MMC
-CONFIG_SYS_QE_FMAN_FW_IN_NAND
-CONFIG_SYS_QE_FMAN_FW_IN_NOR
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 CONFIG_SYS_QE_FMAN_FW_LENGTH
 CONFIG_SYS_QE_FW_ADDR
-CONFIG_SYS_QE_FW_IN_SPIFLASH
 CONFIG_SYS_QMAN_CENA_BASE
 CONFIG_SYS_QMAN_CENA_SIZE
 CONFIG_SYS_QMAN_CINH_BASE
@@ -4008,13 +3941,11 @@
 CONFIG_SYS_SDRAM_DRVSTRENGTH
 CONFIG_SYS_SDRAM_DRV_STRENGTH
 CONFIG_SYS_SDRAM_EMOD
-CONFIG_SYS_SDRAM_LOWER
 CONFIG_SYS_SDRAM_MODE
 CONFIG_SYS_SDRAM_SIZE
 CONFIG_SYS_SDRAM_SIZE0
 CONFIG_SYS_SDRAM_SIZE1
 CONFIG_SYS_SDRAM_SIZE_LAW
-CONFIG_SYS_SDRAM_UPPER
 CONFIG_SYS_SDRAM_VAL
 CONFIG_SYS_SDRAM_VAL1
 CONFIG_SYS_SDRAM_VAL10
@@ -4244,7 +4175,6 @@
 CONFIG_SYS_USE_DATAFLASH_CS0
 CONFIG_SYS_USE_DATAFLASH_CS1
 CONFIG_SYS_USE_DATAFLASH_CS3
-CONFIG_SYS_USE_DSPLINK
 CONFIG_SYS_USE_FLASH
 CONFIG_SYS_USE_MAIN_OSCILLATOR
 CONFIG_SYS_USE_MMC
@@ -4350,12 +4280,10 @@
 CONFIG_TSECV2_1
 CONFIG_TSEC_TBI
 CONFIG_TSEC_TBICR_SETTINGS
-CONFIG_TUGE1
 CONFIG_TULIP
 CONFIG_TULIP_FIX_DAVICOM
 CONFIG_TULIP_SELECT_MEDIA
 CONFIG_TULIP_USE_IO
-CONFIG_TUXX1
 CONFIG_TWL6030_INPUT
 CONFIG_TWL6030_POWER
 CONFIG_TWR
@@ -4472,7 +4400,6 @@
 CONFIG_USB_OTG_BLACKLIST_HUB
 CONFIG_USB_PHY_TYPE
 CONFIG_USB_PXA25X_SMALL
-CONFIG_USB_R8A66597_HCD
 CONFIG_USB_SERIALNO
 CONFIG_USB_TI_CPPI_DMA
 CONFIG_USB_TTY
@@ -4512,7 +4439,6 @@
 CONFIG_VIDEO_VCXK
 CONFIG_VID_FLS_ENV
 CONFIG_VM86
-CONFIG_VME8349
 CONFIG_VOIPAC_LCD
 CONFIG_VOL_MONITOR_INA220
 CONFIG_VOL_MONITOR_IR36021_READ
@@ -4549,9 +4475,7 @@
 CONFIG_YAFFS_UTIL
 CONFIG_YAFFS_WINCE
 CONFIG_YELLOW_LED
-CONFIG_ZLIB
 CONFIG_ZLT
 CONFIG_ZM7300
-CONFIG_ZYNQMP_EEPROM
 CONFIG_ZYNQ_HISPD_BROKEN
 CONFIG_eTSEC_MDIO_BUS
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 6a6c83b..fbb2366 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -673,7 +673,12 @@
         environment = {}
         if os.path.exists(done_file):
             with open(done_file, 'r') as fd:
-                return_code = int(fd.readline())
+                try:
+                    return_code = int(fd.readline())
+                except ValueError:
+                    # The file may be empty due to running out of disk space.
+                    # Try a rebuild
+                    return_code = 1
                 err_lines = []
                 err_file = self.GetErrFile(commit_upto, target)
                 if os.path.exists(err_file):
diff --git a/tools/stm32image.c b/tools/stm32image.c
index 08b32ba..ff3ec5f 100644
--- a/tools/stm32image.c
+++ b/tools/stm32image.c
@@ -14,6 +14,8 @@
 #define HEADER_VERSION_V1	0x1
 /* default option : bit0 => no signature */
 #define HEADER_DEFAULT_OPTION	(cpu_to_le32(0x00000001))
+/* default binary type for U-Boot */
+#define HEADER_TYPE_UBOOT	(cpu_to_le32(0x00000000))
 
 struct stm32_header {
 	uint32_t magic_number;
@@ -29,7 +31,8 @@
 	uint32_t option_flags;
 	uint32_t ecdsa_algorithm;
 	uint32_t ecdsa_public_key[64 / 4];
-	uint32_t padding[84 / 4];
+	uint32_t padding[83 / 4];
+	uint32_t binary_type;
 };
 
 static struct stm32_header stm32image_header;
@@ -43,6 +46,7 @@
 	ptr->header_version[VER_MAJOR_IDX] = HEADER_VERSION_V1;
 	ptr->option_flags = HEADER_DEFAULT_OPTION;
 	ptr->ecdsa_algorithm = 1;
+	ptr->binary_type = HEADER_TYPE_UBOOT;
 }
 
 static uint32_t stm32image_checksum(void *start, uint32_t len)
@@ -112,6 +116,8 @@
 	       le32_to_cpu(stm32hdr->image_checksum));
 	printf("Option     : 0x%08x\n",
 	       le32_to_cpu(stm32hdr->option_flags));
+	printf("BinaryType : 0x%08x\n",
+	       le32_to_cpu(stm32hdr->binary_type));
 }
 
 static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd,