// SPDX-License-Identifier: GPL-2.0
/*
 * phyCORE-AM62x dts file for R5 SPL with 2GB RAM
 * Copyright (C) 2022 - 2023 Phytec Messtechnik GmbH
 * Author: Wadim Egorov <w.egorov@phytec.de>
 */

#include "k3-am625-phyboard-lyra-rdk.dts"
#include "k3-am62-phycore-som-ddr4-2gb.dtsi"
#include "k3-am62-ddr.dtsi"

#include "k3-am625-phyboard-lyra-rdk-u-boot.dtsi"

/ {
	aliases {
		remoteproc0 = &sysctrler;
		remoteproc1 = &a53_0;
		serial0 = &wkup_uart0;
		serial3 = &main_uart1;
	};

	a53_0: a53@0 {
		compatible = "ti,am654-rproc";
		reg = <0x00 0x00a90000 0x00 0x10>;
		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
		resets = <&k3_reset 135 0>;
		clocks = <&k3_clks 61 0>;
		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
		assigned-clock-parents = <&k3_clks 61 2>;
		assigned-clock-rates = <200000000>, <1200000000>;
		ti,sci = <&dmsc>;
		ti,sci-proc-id = <32>;
		ti,sci-host-id = <10>;
		bootph-pre-ram;
	};

	dm_tifs: dm-tifs {
		compatible = "ti,j721e-dm-sci";
		ti,host-id = <36>;
		ti,secure-host;
		mbox-names = "rx", "tx";
		mboxes= <&secure_proxy_main 22>,
			<&secure_proxy_main 23>;
		bootph-pre-ram;
	};

	memory@80000000 {
		device_type = "memory";
		/* 2G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
		bootph-pre-ram;
	};
};

&secure_proxy_sa3 {
	/* We require this for boot handshake */
	status = "okay";
};

&cbass_main {
	sysctrler: sysctrler {
		compatible = "ti,am654-system-controller";
		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
		mbox-names = "tx", "rx", "boot_notify";
		bootph-pre-ram;
	};
};

&dmsc {
	mboxes= <&secure_proxy_main 0>,
		<&secure_proxy_main 1>,
		<&secure_proxy_main 0>;
	mbox-names = "rx", "tx", "notify";
	ti,host-id = <35>;
	ti,secure-host;
};

&main_bcdma {
	ti,sci = <&dm_tifs>;
};

&main_pktdma {
	ti,sci = <&dm_tifs>;
};

/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart1_pins_default>;
	status = "okay";
	bootph-pre-ram;
};

&mcu_pmx0 {
	wkup_uart0_pins_default: wkup-uart0-pins-default {
		pinctrl-single,pins = <
			AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
			AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
			AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
			AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
		>;
		bootph-pre-ram;
	};
};

&ospi0 {
	reg = <0x00 0x0fc40000 0x00 0x100>,
	      <0x00 0x60000000 0x00 0x08000000>;
};

/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
	status = "okay";
	bootph-pre-ram;
};