)]}'
{
  "commit": "a6c8e8bbdf24ece39e4f55c8ab464d28e5e44745",
  "tree": "2af63ab3f0564407f768de701f95ead6241dafa7",
  "parents": [
    "9029a010ec413e6c3c0eb52c29c252a5b9a9f774"
  ],
  "author": {
    "name": "Jiaxun Yang",
    "email": "jiaxun.yang@flygoat.com",
    "time": "Wed May 28 12:02:49 2025 +0100"
  },
  "committer": {
    "name": "Gerd Hoffmann",
    "email": "kraxel@redhat.com",
    "time": "Mon Jun 02 11:20:05 2025 +0200"
  },
  "message": "ahci: Fix hangs due to controller reset\n\nAfter adding AHCI controller reset functionality there are multiple\nreports on AHCI booting regression.\n\nAs per my experiments on various machines, to reset controller\nproperly it is necessary to poll HOST_CTL_RESET bit until it\u0027s\nclear. It is also required to read back HOST_CTL after changing\nHOST_CTL_AHCI_EN bits to ensure the controller has accepted write.\n\nTested on ASMedia ASM1061, Intel H61 native SATA and AMD Phoenix\nnative SATA.\n\nLink: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/RDNRKWBN4N5XQX2TQMM5P4WZ2OOPPNAM/\nLink: https://github.com/FlyGoat/csmwrap/issues/14\nFixes: 8863cbbd15a7 (\"ahci: add controller reset\")\nSigned-off-by: Jiaxun Yang \u003cjiaxun.yang@flygoat.com\u003e\nAcked-by: Paul Menzel \u003cpmenzel@molgen.mpg.de\u003e\nMessage-ID: \u003c20250528-ahci-v2-1-9d7310217ca2@flygoat.com\u003e\nSigned-off-by: Gerd Hoffmann \u003ckraxel@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2285d33d4ae21335e5222ab04608685b5bff3763",
      "old_mode": 33188,
      "old_path": "src/hw/ahci.c",
      "new_id": "7e7a03ddd010d53fa439c8ca49505a2da00241f4",
      "new_mode": 33188,
      "new_path": "src/hw/ahci.c"
    }
  ]
}