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qemu / qemu / ff8f06ee7680fb505079d33caaf8f5ebff0853bc / target-tricore
  1. 97ed5cc tlb: Add "ifetch" argument to cpu_mmu_index() by Benjamin Herrenschmidt · 10 years ago
  2. 1618d2a maint: remove unused include for signal.h by Daniel P. Berrange · 10 years ago
  3. ecc7b3a tcg: Remove tcg_gen_trunc_i64_i32 by Richard Henderson · 10 years ago
  4. 609ad70 tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32 by Richard Henderson · 10 years ago
  5. ea3e984 cpu-exec: Purge all uses of ENV_GET_CPU() by Peter Crosthwaite · 10 years ago
  6. 4bad9e3 cpu: Change cpu_exec_init() arg to cpu, not env by Peter Crosthwaite · 10 years ago
  7. 5a790cc cpu: Add Error argument to cpu_exec_init() by Bharata B Rao · 10 years ago
  8. 5f37fd8 target-tricore: fix depositing bits from PCXI into ICR by Paolo Bonzini · 10 years ago
  9. d49190c disas: Remove uses of CPU env by Peter Crosthwaite · 10 years ago
  10. 07e1548 target-tricore: fix BOL_ST_H_LONGOFF using ld by Bastian Koppelmann · 10 years ago
  11. 9bbd484 target-tricore: fix msub32_q producing the wrong overflow bit by Bastian Koppelmann · 10 years ago
  12. 05b6ca9 target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result by Bastian Koppelmann · 10 years ago
  13. 9371557 target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA by Bastian Koppelmann · 10 years ago
  14. 0e045f4 target-tricore: add FRET instructions of the v1.6 ISA by Bastian Koppelmann · 10 years ago
  15. 9e14a7b target-tricore: add FCALL instructions of the v1.6 ISA by Bastian Koppelmann · 10 years ago
  16. bc3551c target-tricore: add SYS_RESTORE instruction of the v1.6 ISA by Bastian Koppelmann · 10 years ago
  17. e5c96c8 target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA by Bastian Koppelmann · 10 years ago
  18. ddd8ceb target-tricore: add SWAPMSK instructions of the v1.6.1 ISA by Bastian Koppelmann · 10 years ago
  19. 62872eb target-tricore: add CMPSWP instructions of the v1.6.1 ISA by Bastian Koppelmann · 10 years ago
  20. fcecf12 target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA by Bastian Koppelmann · 10 years ago
  21. 6d2afc8 target-tricore: introduce ISA v1.6.1 feature by Bastian Koppelmann · 10 years ago
  22. fd5ecf3 target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3 by Bastian Koppelmann · 10 years ago
  23. 3446a11 target-tricore: fix rfe not restoring the PC by Bastian Koppelmann · 10 years ago
  24. bc72f8a target-tricore: fix rslcx restoring the upper context instead of the lower by Bastian Koppelmann · 10 years ago
  25. 4959d6b target-tricore: fix BO_OFF10_SEXT calculating the wrong offset by Bastian Koppelmann · 10 years ago
  26. 7bd0eae target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4 by Bastian Koppelmann · 10 years ago
  27. 250ef8c target-tricore: Fix LOOP using wrong register for compare by Bastian Koppelmann · 10 years ago
  28. fee068e tcg: Delete unused cpu_pc_from_tb() by Peter Crosthwaite · 10 years ago
  29. 7b4b0b5 target-tricore: Fix check which was always false by Stefan Weil · 10 years ago
  30. f1fdaf5 target-tricore: fix CACHEA/I_POSTINC/PREINC using data register.. by Bastian Koppelmann · 10 years ago
  31. f69c24e target-tricore: properly fix dvinit_b/h_13 by Bastian Koppelmann · 10 years ago
  32. 00e1754 target-tricore: fix RRPW_DEXTR using wrong reg by Bastian Koppelmann · 10 years ago
  33. 2b9d09b target-tricore: fix DVINIT_HU/BU calculating overflow before result by Bastian Koppelmann · 10 years ago
  34. 30a0d72 target-tricore: Fix two helper functions (clang warnings) by Stefan Weil · 10 years ago
  35. de7ad4c Fix typos in comments by Viswesh · 10 years ago
  36. b724b01 target-tricore: Add instructions of SYS opcode format by Bastian Koppelmann · 10 years ago
  37. eb989d2 target-tricore: Add instructions of RRRW opcode format by Bastian Koppelmann · 10 years ago
  38. 4d108fe target-tricore: Add instructions of RRRR opcode format by Bastian Koppelmann · 10 years ago
  39. 068fac7 target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode by Bastian Koppelmann · 10 years ago
  40. 62e47b2 target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as first opcode by Bastian Koppelmann · 10 years ago
  41. f4aef47 target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as first opcode by Bastian Koppelmann · 10 years ago
  42. 42a268c tcg: Change translator-side labels to a pointer by Richard Henderson · 10 years ago
  43. 2994fd9 cpu: Make cpu_init() return QOM CPUState object by Eduardo Habkost · 10 years ago
  44. bebe80f target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode by Bastian Koppelmann · 10 years ago
  45. b00aa8e target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode by Bastian Koppelmann · 10 years ago
  46. 2e430e1 target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode by Bastian Koppelmann · 10 years ago
  47. 2984cfb target-tricore: Add instructions of RRR2 opcode format by Bastian Koppelmann · 10 years ago
  48. 3debbb5 target-tricore: fix msub32_suov return wrong results by Bastian Koppelmann · 10 years ago
  49. f0cab01 target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper by Bastian Koppelmann · 10 years ago
  50. fe700ad tcg: Introduce tcg_op_buf_count and tcg_op_buf_full by Richard Henderson · 11 years ago
  51. 0a7df5d tcg: Move emit of INDEX_op_end into gen_tb_end by Richard Henderson · 11 years ago
  52. 0953225 target-tricore: Add instructions of RRR opcode format by Bastian Koppelmann · 10 years ago
  53. 8fb9d0e target-tricore: Add instructions of RRPW opcode format by Bastian Koppelmann · 10 years ago
  54. 12f323e target-tricore: Add instructions of RR2 opcode format by Bastian Koppelmann · 10 years ago
  55. f1cc6ea target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode by Bastian Koppelmann · 10 years ago
  56. 85d604a target-tricore: split up suov32 into suov32_pos and suov32_neg by Bastian Koppelmann · 10 years ago
  57. 40a1f64 target-tricore: Fix bugs found by coverity by Bastian Koppelmann · 10 years ago
  58. 811ea60 target-tricore: calculate av bits before saturation by Bastian Koppelmann · 10 years ago
  59. 5f30046 target-tricore: Several translator and cpu model fixes by Bastian Koppelmann · 10 years ago
  60. 452e3d4 target-tricore: Add missing ULL suffix on 64 bit constant by Peter Maydell · 10 years ago
  61. 3709741 target-tricore: Fix new typos by Stefan Weil · 10 years ago
  62. a4ba200 Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging by Peter Maydell · 10 years ago
  63. cd42d5b gen-icount: check cflags instead of use_icount global by Paolo Bonzini · 10 years ago
  64. 9655b93 target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode by Bastian Koppelmann · 10 years ago
  65. 436d63f target-tricore: Fix MFCR/MTCR insn and B format offset. by Bastian Koppelmann · 10 years ago
  66. b5fd8fa target-tricore: Add missing 1.6 insn of BOL opcode format by Bastian Koppelmann · 10 years ago
  67. e2bed10 target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode by Bastian Koppelmann · 10 years ago
  68. f2f1585 target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode by Bastian Koppelmann · 10 years ago
  69. 0b79a78 target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode by Bastian Koppelmann · 10 years ago
  70. d5de783 target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode by Bastian Koppelmann · 10 years ago
  71. e4e3917 target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 by Bastian Koppelmann · 10 years ago
  72. 7f13420 target-tricore: Fix mask handling JNZ.T being 7 bit long by Bastian Koppelmann · 10 years ago
  73. 45820fc target-tricore: pretty-print register dump and show more status registers by Alex Zuepke · 10 years ago
  74. 4b5b443 target-tricore: add missing 64-bit MOV in RLC format by Alex Zuepke · 10 years ago
  75. af715d9 target-tricore: typo in BOL format by Alex Zuepke · 10 years ago
  76. 781b717 target-tricore: fix offset masking in BOL format by Alex Zuepke · 10 years ago
  77. 328f1f0 target-tricore: Add instructions of RCR opcode format by Bastian Koppelmann · 10 years ago
  78. 2b2f7d9 target-tricore: Add instructions of RLC opcode format by Bastian Koppelmann · 10 years ago
  79. ed51626 target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format by Bastian Koppelmann · 10 years ago
  80. 47e0443 target-tricore: Make TRICORE_FEATURES implying others. by Bastian Koppelmann · 10 years ago
  81. 0974257 target-tricore: Add instructions of RC opcode format by Bastian Koppelmann · 10 years ago
  82. a68e0d5 target-tricore: Add instructions of BRR opcode format by Bastian Koppelmann · 10 years ago
  83. 83c1bb1 target-tricore: Add instructions of BRN opcode format by Bastian Koppelmann · 10 years ago
  84. fc2ef4a target-tricore: Add instructions of BRC opcode format by Bastian Koppelmann · 10 years ago
  85. 3fb763c target-tricore: Add instructions of BOL opcode format by Bastian Koppelmann · 10 years ago
  86. 3a16ecb target-tricore: Add instructions of BO opcode format by Bastian Koppelmann · 11 years ago
  87. b74f2b5 target-tricore: Add instructions of BIT opcode format by Bastian Koppelmann · 11 years ago
  88. f718b0b target-tricore: Add instructions of B opcode format by Bastian Koppelmann · 11 years ago
  89. 59543d4 target-tricore: Add instructions of ABS, ABSB opcode format by Bastian Koppelmann · 11 years ago
  90. 030c58d target-tricore: Cleanup and Bugfixes by Bastian Koppelmann · 11 years ago
  91. dfdb483 target-tricore: Remove the dummy interrupt boilerplate by Richard Henderson · 11 years ago
  92. 44ea343 target-tricore: Add instructions of SR opcode format by Bastian Koppelmann · 11 years ago
  93. 5a7634a target-tricore: Add instructions of SLR, SSRO and SRO opcode format by Bastian Koppelmann · 11 years ago
  94. 5de9351 target-tricore: Add instructions of SC opcode format by Bastian Koppelmann · 11 years ago
  95. a47b50d target-tricore: Add instructions of SBR opcode format by Bastian Koppelmann · 11 years ago
  96. 70b0226 target-tricore: Add instructions of SBC and SBRN opcode format by Bastian Koppelmann · 11 years ago
  97. 9a31922 target-tricore: Add instructions of SB opcode format by Bastian Koppelmann · 11 years ago
  98. d279821 target-tricore: Add instructions of SRRS and SLRO opcode format by Bastian Koppelmann · 11 years ago
  99. 46aa848 target-tricore: Add instructions of SSR opcode format by Bastian Koppelmann · 11 years ago
  100. 2692802 target-tricore: Add instructions of SRR opcode format by Bastian Koppelmann · 11 years ago