1. 45b1f81 hw/intc: Constify VMState by Richard Henderson · 12 months ago
  2. b77af26 accel/tcg: Replace CPUState.env_ptr with cpu_env() by Richard Henderson · 1 year, 3 months ago
  3. 9382a9e hw/intc: Make rtc variable names consistent by Jason Chien · 1 year, 5 months ago
  4. e0922b7 hw/intc: Fix upper/lower mtime write calculation by Jason Chien · 1 year, 5 months ago
  5. 64452a0 hw: intc: Use cpu_by_arch_id to fetch CPU state by Mayuresh Chitale · 1 year, 10 months ago
  6. 7cbcc53 hw/intc: Move mtimer/mtimecmp to aclint by Atish Patra · 2 years, 4 months ago
  7. 9323e79 Fix 'writeable' typos by Peter Maydell · 2 years, 6 months ago
  8. 7704672 hw/intc: Pass correct hartid while updating mtimecmp by Atish Patra · 2 years, 7 months ago
  9. 8124f81 hw/intc: riscv_aclint: Add reset function of ACLINT devices by Jim Shu · 2 years, 8 months ago
  10. e2f01f3 hw/intc: Make RISC-V ACLINT mtime MMIO register writable by Frank Chang · 2 years, 8 months ago
  11. d42df0e hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT by Frank Chang · 2 years, 8 months ago
  12. 231a90c hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT by Frank Chang · 2 years, 8 months ago
  13. b21e238 Use g_new() & friends where that makes obvious sense by Markus Armbruster · 2 years, 9 months ago
  14. b8fb878 hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT by Anup Patel · 3 years, 4 months ago
  15. cc63a18 hw/intc: Rename sifive_clint sources to riscv_aclint sources by Anup Patel · 3 years, 4 months ago[Renamed (99%) from hw/intc/sifive_clint.c]
  16. a714b8a hw/intc: sifive_clint: Use RISC-V CPU GPIO lines by Alistair Francis · 3 years, 4 months ago
  17. 4dc06bb hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp() by David Hoppenbrouwers · 3 years, 4 months ago
  18. 406fafd hw/riscv: Move sifive_clint model to hw/intc by Bin Meng · 4 years, 3 months ago[Renamed (99%) from hw/riscv/sifive_clint.c]
  19. a47ef6e hw/riscv: clint: Avoid using hard-coded timebase frequency by Bin Meng · 4 years, 4 months ago
  20. 3bf03f0 hw/riscv: Allow creating multiple instances of CLINT by Anup Patel · 4 years, 7 months ago
  21. 70b78d4 hw/riscv: Allow 64 bit access to SiFive CLINT by Alistair Francis · 4 years, 6 months ago
  22. 3c6ef47 sysbus: Convert to sysbus_realize() etc. with Coccinelle by Markus Armbruster · 4 years, 6 months ago
  23. 3e80f69 qdev: Convert uses of qdev_create() with Coccinelle by Markus Armbruster · 4 years, 6 months ago
  24. 5f3616c hw/riscv: Provide rdtime callback for TCG in CLINT emulation by Anup Patel · 4 years, 11 months ago
  25. 4f67d30 qdev: set properties with device_class_set_props() by Marc-André Lureau · 5 years ago
  26. a27bd6c Include hw/qdev-properties.h less by Markus Armbruster · 5 years ago
  27. 0b8fa32 Include qemu/module.h where needed, drop it from qemu-common.h by Markus Armbruster · 6 years ago
  28. ef9e41d RISC-V: Fix CLINT timecmp low 32-bit writes by Michael Clark · 6 years ago
  29. 85ba724 RISC-V: Allow setting and clearing multiple irqs by Michael Clark · 7 years ago
  30. 2a8756e RISC-V: Replace hardcoded constants with enum values by Michael Clark · 7 years ago
  31. 1c77c41 SiFive RISC-V CLINT Block by Michael Clark · 7 years ago