1. e5c96c8 target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA by Bastian Koppelmann · 10 years ago
  2. ddd8ceb target-tricore: add SWAPMSK instructions of the v1.6.1 ISA by Bastian Koppelmann · 10 years ago
  3. 62872eb target-tricore: add CMPSWP instructions of the v1.6.1 ISA by Bastian Koppelmann · 10 years ago
  4. fcecf12 target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA by Bastian Koppelmann · 10 years ago
  5. 7bd0eae target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4 by Bastian Koppelmann · 10 years ago
  6. 250ef8c target-tricore: Fix LOOP using wrong register for compare by Bastian Koppelmann · 10 years ago
  7. f1fdaf5 target-tricore: fix CACHEA/I_POSTINC/PREINC using data register.. by Bastian Koppelmann · 10 years ago
  8. 00e1754 target-tricore: fix RRPW_DEXTR using wrong reg by Bastian Koppelmann · 10 years ago
  9. 2b9d09b target-tricore: fix DVINIT_HU/BU calculating overflow before result by Bastian Koppelmann · 10 years ago
  10. de7ad4c Fix typos in comments by Viswesh · 10 years ago
  11. b724b01 target-tricore: Add instructions of SYS opcode format by Bastian Koppelmann · 10 years ago
  12. eb989d2 target-tricore: Add instructions of RRRW opcode format by Bastian Koppelmann · 10 years ago
  13. 4d108fe target-tricore: Add instructions of RRRR opcode format by Bastian Koppelmann · 10 years ago
  14. 068fac7 target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode by Bastian Koppelmann · 10 years ago
  15. 62e47b2 target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as first opcode by Bastian Koppelmann · 10 years ago
  16. f4aef47 target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as first opcode by Bastian Koppelmann · 10 years ago
  17. 42a268c tcg: Change translator-side labels to a pointer by Richard Henderson · 10 years ago
  18. bebe80f target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode by Bastian Koppelmann · 10 years ago
  19. b00aa8e target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode by Bastian Koppelmann · 10 years ago
  20. 2e430e1 target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode by Bastian Koppelmann · 10 years ago
  21. 2984cfb target-tricore: Add instructions of RRR2 opcode format by Bastian Koppelmann · 10 years ago
  22. f0cab01 target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper by Bastian Koppelmann · 10 years ago
  23. fe700ad tcg: Introduce tcg_op_buf_count and tcg_op_buf_full by Richard Henderson · 11 years ago
  24. 0a7df5d tcg: Move emit of INDEX_op_end into gen_tb_end by Richard Henderson · 11 years ago
  25. 0953225 target-tricore: Add instructions of RRR opcode format by Bastian Koppelmann · 10 years ago
  26. 8fb9d0e target-tricore: Add instructions of RRPW opcode format by Bastian Koppelmann · 10 years ago
  27. 12f323e target-tricore: Add instructions of RR2 opcode format by Bastian Koppelmann · 10 years ago
  28. f1cc6ea target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode by Bastian Koppelmann · 10 years ago
  29. 40a1f64 target-tricore: Fix bugs found by coverity by Bastian Koppelmann · 10 years ago
  30. 5f30046 target-tricore: Several translator and cpu model fixes by Bastian Koppelmann · 10 years ago
  31. 3709741 target-tricore: Fix new typos by Stefan Weil · 10 years ago
  32. a4ba200 Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging by Peter Maydell · 10 years ago
  33. cd42d5b gen-icount: check cflags instead of use_icount global by Paolo Bonzini · 10 years ago
  34. 9655b93 target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode by Bastian Koppelmann · 10 years ago
  35. 436d63f target-tricore: Fix MFCR/MTCR insn and B format offset. by Bastian Koppelmann · 10 years ago
  36. b5fd8fa target-tricore: Add missing 1.6 insn of BOL opcode format by Bastian Koppelmann · 10 years ago
  37. e2bed10 target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode by Bastian Koppelmann · 10 years ago
  38. f2f1585 target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode by Bastian Koppelmann · 10 years ago
  39. 0b79a78 target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode by Bastian Koppelmann · 10 years ago
  40. d5de783 target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode by Bastian Koppelmann · 10 years ago
  41. 7f13420 target-tricore: Fix mask handling JNZ.T being 7 bit long by Bastian Koppelmann · 10 years ago
  42. 45820fc target-tricore: pretty-print register dump and show more status registers by Alex Zuepke · 10 years ago
  43. 4b5b443 target-tricore: add missing 64-bit MOV in RLC format by Alex Zuepke · 10 years ago
  44. af715d9 target-tricore: typo in BOL format by Alex Zuepke · 10 years ago
  45. 328f1f0 target-tricore: Add instructions of RCR opcode format by Bastian Koppelmann · 10 years ago
  46. 2b2f7d9 target-tricore: Add instructions of RLC opcode format by Bastian Koppelmann · 10 years ago
  47. ed51626 target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format by Bastian Koppelmann · 10 years ago
  48. 47e0443 target-tricore: Make TRICORE_FEATURES implying others. by Bastian Koppelmann · 10 years ago
  49. 0974257 target-tricore: Add instructions of RC opcode format by Bastian Koppelmann · 10 years ago
  50. a68e0d5 target-tricore: Add instructions of BRR opcode format by Bastian Koppelmann · 10 years ago
  51. 83c1bb1 target-tricore: Add instructions of BRN opcode format by Bastian Koppelmann · 10 years ago
  52. fc2ef4a target-tricore: Add instructions of BRC opcode format by Bastian Koppelmann · 10 years ago
  53. 3fb763c target-tricore: Add instructions of BOL opcode format by Bastian Koppelmann · 10 years ago
  54. 3a16ecb target-tricore: Add instructions of BO opcode format by Bastian Koppelmann · 10 years ago
  55. b74f2b5 target-tricore: Add instructions of BIT opcode format by Bastian Koppelmann · 10 years ago
  56. f718b0b target-tricore: Add instructions of B opcode format by Bastian Koppelmann · 10 years ago
  57. 59543d4 target-tricore: Add instructions of ABS, ABSB opcode format by Bastian Koppelmann · 10 years ago
  58. 44ea343 target-tricore: Add instructions of SR opcode format by Bastian Koppelmann · 10 years ago
  59. 5a7634a target-tricore: Add instructions of SLR, SSRO and SRO opcode format by Bastian Koppelmann · 10 years ago
  60. 5de9351 target-tricore: Add instructions of SC opcode format by Bastian Koppelmann · 10 years ago
  61. a47b50d target-tricore: Add instructions of SBR opcode format by Bastian Koppelmann · 10 years ago
  62. 70b0226 target-tricore: Add instructions of SBC and SBRN opcode format by Bastian Koppelmann · 10 years ago
  63. 9a31922 target-tricore: Add instructions of SB opcode format by Bastian Koppelmann · 10 years ago
  64. d279821 target-tricore: Add instructions of SRRS and SLRO opcode format by Bastian Koppelmann · 10 years ago
  65. 46aa848 target-tricore: Add instructions of SSR opcode format by Bastian Koppelmann · 10 years ago
  66. 2692802 target-tricore: Add instructions of SRR opcode format by Bastian Koppelmann · 10 years ago
  67. 0707ec1 target-tricore: Add instructions of SRC opcode format by Bastian Koppelmann · 10 years ago
  68. 7c87d07 target-tricore: Add masks and opcodes for decoding by Bastian Koppelmann · 10 years ago
  69. 0aaeb11 target-tricore: Add initialization for translation and activate target by Bastian Koppelmann · 10 years ago
  70. 48e06fe target-tricore: Add target stubs and qom-cpu by Bastian Koppelmann · 10 years ago