1. f2ab172 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists by Bastian Koppelmann · 6 years ago
  2. 7a50d3e target/riscv: Move gen_arith_imm() decoding into trans_* functions by Bastian Koppelmann · 6 years ago
  3. 4ba79c4 target/riscv: Convert RV priv insns to decodetree by Bastian Koppelmann · 6 years ago
  4. 97f8b49 target/riscv: Convert RV32D insns to decodetree by Bastian Koppelmann · 6 years ago
  5. 6f0e74f target/riscv: Convert RV32F insns to decodetree by Bastian Koppelmann · 6 years ago
  6. 3b77c28 target/riscv: Convert RV32A insns to decodetree by Bastian Koppelmann · 6 years ago
  7. d2e2c1e target/riscv: Convert RVXM insns to decodetree by Bastian Koppelmann · 6 years ago
  8. 771fbe1 target/riscv: Convert RVXI csr insns to decodetree by Bastian Koppelmann · 6 years ago
  9. 0c865e8 target/riscv: Convert RVXI fence insns to decodetree by Bastian Koppelmann · 6 years ago
  10. b73a987 target/riscv: Convert RVXI arithmetic insns to decodetree by Bastian Koppelmann · 6 years ago
  11. c1000d4 target/riscv: Convert RV32I load/store insns to decodetree by Bastian Koppelmann · 6 years ago
  12. 3cca75a target/riscv: Convert RVXI branch insns to decodetree by Bastian Koppelmann · 6 years ago
  13. 2a53cff target/riscv: Activate decodetree and implemnt LUI & AUIPC by Bastian Koppelmann · 6 years ago