- c2a46a9 target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree by Peter Maydell · 6 years ago
- e3bb599 target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree by Peter Maydell · 6 years ago
- f65988a target/arm: Convert VMINNM, VMAXNM to decodetree by Peter Maydell · 6 years ago
- b3ff4b8 target/arm: Convert the VSEL instructions to decodetree by Peter Maydell · 6 years ago
- 06db819 target/arm: Factor out VFP access checking code by Peter Maydell · 6 years ago
- 78e138b target/arm: Add stubs for AArch32 VFP decodetree by Peter Maydell · 6 years ago
- 3a7a2b4 target/arm: Use tcg_gen_gvec_bitsel by Richard Henderson · 6 years ago
- 2fc0cc0 target/arm: Use env_cpu, env_archcpu by Richard Henderson · 6 years ago
- f1672e6 semihosting: move semihosting configuration into its own directory by Alex Bennée · 6 years ago
- 2f143d3 target/arm: Fix vector operation segfault by Alistair Francis · 6 years ago
- 4e027a7 target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs by Richard Henderson · 6 years ago
- ff1f11f tcg: Add support for integer absolute value by Richard Henderson · 6 years ago
- 53229a7 tcg: Specify optional vector requirements with a list by Richard Henderson · 6 years ago
- 956fe14 target/arm: Implement VLLDM for v7M CPUs with an FPU by Peter Maydell · 6 years ago
- 019076b target/arm: Implement VLSTM for v7M CPUs with an FPU by Peter Maydell · 6 years ago
- e33cf0f target/arm: Implement M-profile lazy FP state preservation by Peter Maydell · 6 years ago
- 6000531 target/arm: Activate M-profile floating point context when FPCCR.ASPEN is set by Peter Maydell · 6 years ago
- 6d60c67 target/arm: Set FPCCR.S when executing M-profile floating point insns by Peter Maydell · 6 years ago
- ea7ac69 target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags by Peter Maydell · 6 years ago
- 8859ba3 target/arm: Decode FP instructions for M profile by Peter Maydell · 6 years ago
- d87513c target/arm: Honour M-profile FP enable bits by Peter Maydell · 6 years ago
- ef9aae2 target/arm: Disable most VFP sysregs for M-profile by Peter Maydell · 6 years ago
- 8b86d6d tcg: Hoist max_insns computation to tb_gen_code by Richard Henderson · 6 years ago
- 90c84c5 qom/cpu: Simplify how CPUClass:cpu_dump_state() prints by Markus Armbruster · 6 years ago
- 22ac3c4 target/arm: Add set/clear_pstate_bits, share gen_ss_advance by Richard Henderson · 6 years ago
- 9888bd1 target/arm: Implement ARMv8.0-SB by Richard Henderson · 6 years ago
- 9d090d1 target/arm: Fix PC test for LDM (exception return) by Richard Henderson · 6 years ago
- 8773231 target/arm: Implement VFMAL and VFMSL for aarch32 by Richard Henderson · 6 years ago
- c0c760a target/arm: Gate "miscellaneous FP" insns by ID register field by Peter Maydell · 6 years ago
- 602f6e4 target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions by Peter Maydell · 6 years ago
- 6c1f6f2 target/arm: Implement ARMv8.3-JSConv by Richard Henderson · 6 years ago
- e80941b target/arm: Rearrange Floating-point data-processing (2 regs) by Richard Henderson · 6 years ago
- 89e68b5 target/arm: Use vector operations for saturation by Richard Henderson · 6 years ago
- ec527e4 target/arm: Fix arm_cpu_dump_state vs FPSCR by Richard Henderson · 6 years ago
- 9ecd3c5 target/arm: Use tcg integer min/max primitives for neon by Richard Henderson · 6 years ago
- 6f27822 target/arm: Use vector minmax expanders for aarch32 by Richard Henderson · 6 years ago
- 2900847 target/arm: Rely on optimization within tcg_gen_gvec_or by Richard Henderson · 6 years ago
- 96c5529 target/arm: Emit barriers for A32/T32 load-acquire/store-release insns by Peter Maydell · 6 years ago
- aad821a target/arm: Convert ARM_TBFLAG_* to FIELDs by Richard Henderson · 6 years ago
- 2d6ac92 target/arm: Reorg NEON VLD/VST single element to one lane by Richard Henderson · 6 years ago
- e23f12b target/arm: Promote consecutive memory ops for aa32 by Richard Henderson · 6 years ago
- ac55d00 target/arm: Reorg NEON VLD/VST all elements by Richard Henderson · 6 years ago
- 7377c2c target/arm: Use gvec for NEON VLD all lanes by Richard Henderson · 6 years ago
- ea580fa target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE by Richard Henderson · 6 years ago
- 4a7832b target/arm: Use gvec for NEON_3R_VML by Richard Henderson · 6 years ago
- f3cd821 target/arm: Use gvec for VSRI, VSLI by Richard Henderson · 6 years ago
- 41f6c11 target/arm: Use gvec for VSRA by Richard Henderson · 6 years ago
- 1dc8425 target/arm: Use gvec for VSHR, VSHL by Richard Henderson · 6 years ago
- 8208318 target/arm: Use gvec for NEON_3R_VMUL by Richard Henderson · 6 years ago
- 4bf940b target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG by Richard Henderson · 6 years ago
- e4717ae target/arm: Use gvec for NEON_3R_VADD_VSUB insns by Richard Henderson · 6 years ago
- eabcd6f target/arm: Use gvec for NEON_3R_LOGIC insns by Richard Henderson · 6 years ago
- 246fa4a target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate) by Richard Henderson · 6 years ago
- 32f91fb target/arm: Use gvec for NEON VDUP by Richard Henderson · 6 years ago
- 308e563 target/arm: Mark some arrays const by Richard Henderson · 6 years ago
- 7108e25 target/arm: Don't call tcg_clear_temp_count by Richard Henderson · 6 years ago
- 4be42f4 target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode by Peter Maydell · 6 years ago
- 81e3728 target/arm: Improve debug logging of AArch32 exception return by Peter Maydell · 6 years ago
- 5763190 target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test by Richard Henderson · 6 years ago
- 09cbd50 target/arm: Convert jazelle from feature bit to isar1 test by Richard Henderson · 6 years ago
- 7e0cf8b target/arm: Convert division from feature bits to isar0 tests by Richard Henderson · 6 years ago
- 962fcbf target/arm: Convert v8 extensions from feature bits to isar tests by Richard Henderson · 6 years ago
- 8a954fa target/arm: Add v8M stack checks for VLDM/VSTM by Peter Maydell · 6 years ago
- aa369e5 target/arm: Add v8M stack checks for Thumb push/pop by Peter Maydell · 6 years ago
- 0bc003b target/arm: Add v8M stack checks for T32 load/store single by Peter Maydell · 6 years ago
- 7c0ed88 target/arm: Add v8M stack checks for Thumb2 LDM/STM by Peter Maydell · 6 years ago
- 910d769 target/arm: Add v8M stack checks for LDRD/STRD (imm) by Peter Maydell · 6 years ago
- a2d12f0 target/arm: Add some comments in Thumb decode by Peter Maydell · 6 years ago
- 5520318 target/arm: Add v8M stack checks on ADD/SUB/MOV of SP by Peter Maydell · 6 years ago
- 4730fb8 target/arm: Define new TBFLAG for v8M stack checking by Peter Maydell · 6 years ago
- d00584b target/arm: Untabify translate.c by Peter Maydell · 7 years ago
- 55c544e target/arm: Implement AArch32 ERET instruction by Peter Maydell · 7 years ago
- aec4dd0 target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked) by Peter Maydell · 7 years ago
- c2d9644 target/arm: Fix crash on conditional instruction in an IT block by Roman Kapl · 7 years ago
- 26c470a target/arm: Implement ARMv8.2-DotProd by Richard Henderson · 7 years ago
- 2cc9991 target/arm: Pass index to AdvSIMD FCMLA (indexed) by Richard Henderson · 7 years ago
- 2aeba0d target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline by Julia Suvorova · 7 years ago
- 8297cb1 target/arm: Minor cleanup for ARMv6-M 32-bit instructions by Julia Suvorova · 7 years ago
- 1412010 target/arm: Allow ARMv6-M Thumb2 instructions by Julia Suvorova · 7 years ago
- 07ea28b tcg: Pass tb and index to tcg_gen_exit_tb separately by Richard Henderson · 7 years ago
- 486624f target/arm: convert conversion helpers to fpst/ahp_flag by Alex Bennée · 7 years ago
- b542683 translator: merge max_insns into DisasContextBase by Emilio G. Cota · 7 years ago
- bfe7ad5 target/arm: avoid integer overflow in next_page PC check by Emilio G. Cota · 7 years ago
- b1e5336 target/arm: Implement v8M VLLDM and VLSTM by Peter Maydell · 7 years ago
- e69ad9d target/arm: Allow EL change hooks to do IO by Aaron Lindsay · 7 years ago
- c4869ca target-arm: Check undefined opcodes for SWP in A32 decoder by Onur Sahin · 7 years ago
- c900a2e target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK by Peter Maydell · 7 years ago
- 0052087 target/arm: Decode t32 simd 3reg and 2reg_scalar extension by Richard Henderson · 7 years ago
- 638808f target/arm: Decode aa32 armv8.3 2-reg-index by Richard Henderson · 7 years ago
- 8b7209f target/arm: Decode aa32 armv8.3 3-same by Richard Henderson · 7 years ago
- 61adacc target/arm: Decode aa32 armv8.1 two reg and a scalar by Richard Henderson · 7 years ago
- 36a7193 target/arm: Decode aa32 armv8.1 three same by Richard Henderson · 7 years ago
- 9b04991 target/arm/helper: pass explicit fpst to set_rmode by Alex Bennée · 7 years ago
- 384c6c0 target/arm/translate.c: Fix missing 'break' for TT insns by Peter Maydell · 7 years ago
- c39c2b9 target/arm: Expand vector registers for SVE by Richard Henderson · 7 years ago
- 9a2b525 target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers by Richard Henderson · 7 years ago
- 3f68b8a target/arm: Change the type of vfp.regs by Richard Henderson · 7 years ago
- e7c06c4 target/arm: Use pointers in neon tbl helper by Richard Henderson · 7 years ago
- b13708b target/arm: Use pointers in neon zip/uzp helpers by Richard Henderson · 7 years ago
- 1a66ac6 target/arm: Use pointers in crypto helpers by Richard Henderson · 7 years ago