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qemu / qemu / ab1339b9b40752d076ae9784ed07f14194f130bd / target-arm
  1. 1273d9c target-arm: Drop unused DECODE_CPREG_CRN macro by Peter Maydell · 12 years ago
  2. d593c48 target-arm: use deposit instead of hardcoded version by Aurelien Jarno · 12 years ago
  3. 00e3ab2 target-arm: mark a few integer helpers const and pure by Aurelien Jarno · 12 years ago
  4. 365af80 target-arm: convert sar, shl and shr helpers to TCG by Aurelien Jarno · 12 years ago
  5. 72485ec target-arm: convert add_cc and sub_cc helpers to TCG by Aurelien Jarno · 12 years ago
  6. 66c374d target-arm: use globals for CC flags by Aurelien Jarno · 12 years ago
  7. f2617cf target-arm: Reinstate display of VFP registers in cpu_dump_state by Peter Maydell · 12 years ago
  8. fdefe51 Emit debug_insn for CPU_LOG_TB_OP_OPT as well. by Richard Henderson · 12 years ago
  9. d31dd73 target-arm: final conversion to AREG0 free mode by Blue Swirl · 12 years ago
  10. 9ef3927 target-arm: convert remaining helpers by Blue Swirl · 12 years ago
  11. 1ce94f8 target-arm: convert void helpers by Blue Swirl · 12 years ago
  12. 599d64f target-arm: Fix potential buffer overflow by Stefan Weil · 12 years ago
  13. 396bef4 arm-semi: don't leak 1KB user string lock buffer upon TARGET_SYS_OPEN by Jim Meyering · 13 years ago
  14. b90372a target-arm: Fix typos in comments by Peter Maydell · 13 years ago
  15. 6562674 arm: translate: comment typo - s/middel/middle/ by Peter A. G. Crosthwaite · 13 years ago
  16. 3dde962 target-arm: Add support for long format translation table walks by Peter Maydell · 13 years ago
  17. e42c4db target-arm: Implement TTBCR changes for LPAE by Peter Maydell · 13 years ago
  18. 702a935 target-arm: Implement long-descriptor PAR format by Peter Maydell · 13 years ago
  19. 77a71dd target-arm: Use target_phys_addr_t in get_phys_addr() by Peter Maydell · 13 years ago
  20. 891a2fe target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE by Peter Maydell · 13 years ago
  21. f9fc619 target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE by Peter Maydell · 13 years ago
  22. 7ac681c target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers by Peter Maydell · 13 years ago
  23. 918f5dc target-arm: Extend feature flags to 64 bits by Peter Maydell · 13 years ago
  24. de9b05b target-arm: Implement privileged-execute-never (PXN) by Peter Maydell · 13 years ago
  25. 3cc0cd6 ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits by Peter Maydell · 13 years ago
  26. ed33685 target-arm: Fix TCG temp handling in 64 bit cp writes by Peter Maydell · 13 years ago
  27. 091fd17 target-arm: Fix some copy-and-paste errors in cp register names by Peter Maydell · 13 years ago
  28. 81a60ad target-arm: Fix typo that meant TTBR1 accesses went to TTBR0 by Peter Maydell · 13 years ago
  29. 2bee510 target-arm: Fix CP15 based WFI by Paul Brook · 13 years ago
  30. b2d06f9 target-arm: Remove ARM_CPUID_* macros by Peter Maydell · 13 years ago
  31. 4a9a539 target-arm: Remove remaining old cp15 infrastructure by Peter Maydell · 13 years ago
  32. 30b05bb target-arm: Move block cache ops to new cp15 framework by Peter Maydell · 13 years ago
  33. b22af02 target-arm: Remove c0_cachetype CPUARMState field by Peter Maydell · 13 years ago
  34. 7884849 target-arm: Convert final ID registers by Peter Maydell · 13 years ago
  35. 81bdde9 target-arm: Convert MPIDR by Peter Maydell · 13 years ago
  36. 776d4e5 target-arm: Convert cp15 cache ID registers by Peter Maydell · 13 years ago
  37. 8515a09 target-arm: Convert cp15 crn=0 crm={1,2} feature registers by Peter Maydell · 13 years ago
  38. 2771db2 target-arm: Convert cp15 crn=1 registers by Peter Maydell · 13 years ago
  39. 34f9052 target-arm: Convert cp15 crn=9 registers by Peter Maydell · 13 years ago
  40. 06d76f3 target-arm: Convert cp15 crn=6 registers by Peter Maydell · 13 years ago
  41. c480421 target-arm: convert cp15 crn=7 registers by Peter Maydell · 13 years ago
  42. 4a50160 target-arm: Convert cp15 VA-PA translation registers by Peter Maydell · 13 years ago
  43. d929823 target-arm: Convert cp15 MMU TLB control by Peter Maydell · 13 years ago
  44. 1047b9d target-arm: Convert cp15 crn=15 registers by Peter Maydell · 13 years ago
  45. 4fdd17d target-arm: Convert cp15 crn=10 registers by Peter Maydell · 13 years ago
  46. 08de207 target-arm: Convert cp15 crn=13 registers by Peter Maydell · 13 years ago
  47. ecce5c3 target-arm: Convert cp15 crn=2 registers by Peter Maydell · 13 years ago
  48. 18032be target-arm: Convert MMU fault status cp15 registers by Peter Maydell · 13 years ago
  49. c983fe6 target-arm: Convert cp15 c3 register by Peter Maydell · 13 years ago
  50. 6cc7a3a target-arm: Convert generic timer cp15 regs by Peter Maydell · 13 years ago
  51. 200ac0e target-arm: Convert performance monitor registers by Peter Maydell · 13 years ago
  52. 4d31c59 target-arm: Convert TLS registers by Peter Maydell · 13 years ago
  53. 7d57f40 target-arm: Convert WFI/barriers special cases to cp_reginfo by Peter Maydell · 13 years ago
  54. c326b97 target-arm: Convert TEECR, TEEHBR to new scheme by Peter Maydell · 13 years ago
  55. e9aa6c2 target-arm: Convert debug registers to cp_reginfo by Peter Maydell · 13 years ago
  56. 2ceb98c target-arm: Add register_cp_regs_for_features() by Peter Maydell · 13 years ago
  57. e8070a2 target-arm: Remove old cpu_arm_set_cp_io infrastructure by Peter Maydell · 13 years ago
  58. 4b6a83f target-arm: initial coprocessor register framework by Peter Maydell · 13 years ago
  59. 200bf59 target-arm: Fix 11MPCore cache type register value by Peter Maydell · 13 years ago
  60. fbe37ef build: move other target-*/ objects to nested Makefile.objs by Paolo Bonzini · 13 years ago
  61. 9cdc8df build: move libobj-y variable to nested Makefile.objs by Paolo Bonzini · 13 years ago
  62. 5e8861a build: move obj-TARGET-y variables to nested Makefile.objs by Paolo Bonzini · 13 years ago
  63. b7e516c Kill off cpu_state_reset() by Andreas Färber · 13 years ago
  64. df90dad target-arm: Use cpu_reset() in cpu_arm_init() by Andreas Färber · 13 years ago
  65. ad37ad5 target-arm/cpu.h: Make cpu_init("nonexistent cpu") return NULL by Peter Maydell · 13 years ago
  66. 7e598de target-arm: When setting FPSCR.QC, don't clear other FPSCR bits by Matt Craighead · 13 years ago
  67. 10962fd target-arm: Make SETEND respect bswap_code (BE8) setting by Peter Maydell · 13 years ago
  68. c5fad12 target-arm: Move A9 config_base_address reset value to ARMCPU by Peter Maydell · 13 years ago
  69. 778c3a0 target-arm: Change cpu_arm_init() return type to ARMCPU by Andreas Färber · 13 years ago
  70. 3c30dd5 target-arm: Move reset handling to arm_cpu_reset by Peter Maydell · 13 years ago
  71. caa1d07 target-arm: Drop cpu_reset_model_id() by Peter Maydell · 13 years ago
  72. 85df378 target-arm: Move cache ID register setup to cpu specific init fns by Peter Maydell · 13 years ago
  73. 8092d2f target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset by Peter Maydell · 13 years ago
  74. 2e4d7e3 target-arm: Move feature register setup to per-CPU init fns by Peter Maydell · 13 years ago
  75. 0cc892f target-arm: Move iWMMXT wCID reset to cpu_state_reset by Peter Maydell · 13 years ago
  76. 4e851c3 target-arm: Drop JTAG_ID documentation by Peter Maydell · 13 years ago
  77. 0ca7e01 target-arm: Move SCTLR reset value setup to per cpu init fns by Peter Maydell · 13 years ago
  78. 64e1671 target-arm: Move CTR setup to per cpu init fns by Peter Maydell · 13 years ago
  79. bd35c35 target-arm: Move MVFR* setup to per cpu init fns by Peter Maydell · 13 years ago
  80. 325b3ce target-arm: Move FPSID config to cpu init fns by Peter Maydell · 13 years ago
  81. 581be09 target-arm: Move feature bit settings to CPU init fns by Peter Maydell · 13 years ago
  82. 777dc78 target-arm: Add QOM subclasses for each ARM cpu implementation by Peter Maydell · 13 years ago
  83. ce854d7 target-arm: remind to keep arm features in sync with linux-user/elfload.c by Benoit Canet · 13 years ago
  84. 2050396 Use uintptr_t for various op related functions by Blue Swirl · 13 years ago
  85. d8fd295 Userspace ARM BE8 support by Paul Brook · 13 years ago
  86. 06ed5d6 ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers. by Andrew Towers · 13 years ago
  87. dec9c2d target-arm: Minimalistic CPU QOM'ification by Andreas Färber · 13 years ago
  88. 0bcd08b target-arm: Drop cpu_arm_close() by Andreas Färber · 13 years ago
  89. d9e028c target-arm: Decode SETEND correctly in Thumb by Peter Maydell · 13 years ago
  90. c98d174 target-arm: Clear IT bits when taking exceptions in v7M by Peter Maydell · 13 years ago
  91. 4de4779 target-arm: Fix typo in ARM946 cp15 c5 handling by Peter Maydell · 13 years ago
  92. 9349b4f Rename CPUState -> CPUArchState by Andreas Färber · 13 years ago
  93. 0ecb72a target-arm: Don't overuse CPUState by Andreas Färber · 13 years ago
  94. 1bba0dc Rename cpu_reset() to cpu_state_reset() by Andreas Färber · 13 years ago
  95. 853bfcc target-arm: Clean includes by Stefan Weil · 13 years ago
  96. a84fac1 target-arm/helper.c: tb_flush() on CPU reset by Peter Maydell · 13 years ago
  97. 2d2624a target-arm/helper.c: Correct FPSID value for Cortex-A9 by Peter Maydell · 13 years ago
  98. 0b03bdf Add Cortex-A15 CPU definition by Peter Maydell · 13 years ago
  99. 0383ac0 Add dummy implementation of generic timer cp15 registers by Peter Maydell · 13 years ago
  100. 5fe9101 arm: store the config_base_register during cpu_reset by Mark Langsdorf · 13 years ago