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qemu / qemu / a6fd08eb625ae3c6a878f527270a9d384d1b04d2 / target-sh4 / translate.c
  1. 72cf2d4 Fix sys-queue.h conflict for good by Blue Swirl · 16 years ago
  2. 8167ee8 Update to a hopefully more future proof FSF address by Blue Swirl · 16 years ago
  3. 5561650 Include assert.h from qemu-common.h by Paul Brook · 16 years ago
  4. 0bf46a4 qemu: introduce qemu_init_vcpu (Marcelo Tosatti) by aliguori · 16 years ago
  5. 1b530a6 Add new command line option -singlestep for tcg single stepping. by aurel32 · 16 years ago
  6. 852d481 SH: Improve movca.l/ocbi emulation. by edgar_igl · 16 years ago
  7. 66c7c80 SH: Implement MOVCO.L and MOVLI.L by aurel32 · 16 years ago
  8. c2432a4 SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support by aurel32 · 16 years ago
  9. 0d0266a targets: remove error handling from qemu_malloc() callers (Avi Kivity) by aliguori · 16 years ago
  10. eca1bdf Log reset events (Jan Kiszka) by aliguori · 16 years ago
  11. 8fec2b8 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost) by aliguori · 16 years ago
  12. 93fcfe3 Convert references to logfile/loglevel to use qemu_log*() macros by aliguori · 16 years ago
  13. 5b7141a sh4: Add FMAC instruction support by aurel32 · 16 years ago
  14. fad6cb1 Update FSF address in GPL/LGPL boilerplate by aurel32 · 16 years ago
  15. df9247b tcg_temp_local_new should take no parameter by aurel32 · 16 years ago
  16. b1503cd Use the ARRAY_SIZE() macro where appropriate. by malc · 16 years ago
  17. 56cd2b9 target-sh4: make the initial value of SR easier to read by aurel32 · 16 years ago
  18. f3ff7fa target-sh4: don't disable FPU instructions in user mode by aurel32 · 16 years ago
  19. bacc637 target-sh4: disable debug code by aurel32 · 16 years ago
  20. 71968fa target-sh4: add prefi, icbi, synco by aurel32 · 16 years ago
  21. a9c43f8 target-sh4: add SH7785 as CPU option by aurel32 · 16 years ago
  22. f619837 target-sh4: check FD bit for FP instructions by aurel32 · 16 years ago
  23. b79e175 SH4: kill a few warnings by aurel32 · 16 years ago
  24. d8299bc SH4: Implement FD bit by aurel32 · 16 years ago
  25. c0ce998 Use sys-queue.h for break/watchpoint managment (Jan Kiszka) by aliguori · 16 years ago
  26. 11bb09f target-sh4: fix 64-bit fmov to/from memory by aurel32 · 16 years ago
  27. 12d9613 target-sh4: fix fldi0/fldi1 by aurel32 · 16 years ago
  28. 66ba317 target-sh4: map FP registers as TCG variables by aurel32 · 16 years ago
  29. a1d1bb3 Refactor and enhance break/watchpoint API (Jan Kiszka) by aliguori · 16 years ago
  30. a7812ae TCG variable type checking. by pbrook · 16 years ago
  31. b1d8e52 Fix undeclared symbol warnings from sparse by blueswir1 · 16 years ago
  32. 7526aa2 SH4: Implement MOVUA.L by aurel32 · 16 years ago
  33. bdbf22e SH4: fix single-stepping by aurel32 · 16 years ago
  34. c69e326 SH4: Fix swap.b by aurel32 · 16 years ago
  35. 1ed1a78 Silence some warnings about no value returned from non-void function by blueswir1 · 16 years ago
  36. 36aa55d Add concat_i32_i64 op. by pbrook · 17 years ago
  37. b55266b Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings by blueswir1 · 17 years ago
  38. fe25591 SH4: Privilege check for instructions by aurel32 · 17 years ago
  39. 7478757 sh4: doesn't set the cpu_model_str by aurel32 · 17 years ago
  40. f24f381 SH4: sleep instruction bug fix by aurel32 · 17 years ago
  41. 0fd3ca3 sh4: CPU versioning. by aurel32 · 17 years ago
  42. 86e0abc SH4: fix a regression introduced in r5122 by aurel32 · 17 years ago
  43. 17b086f SH4: Remove dyngen leftovers by aurel32 · 17 years ago
  44. 7fdf924 SH4: final conversion to TCG by aurel32 · 17 years ago
  45. cc4ba6a SH4: convert floating-point ops to TCG by aurel32 · 17 years ago
  46. c55497e SH4: Remove most uses of cpu_T[0] and cpu_T[1] by aurel32 · 17 years ago
  47. 7efbe24 SH4: TCG optimisations by aurel32 · 17 years ago
  48. 69d6275 SH4: Convert remaining non-fp ops to TCG by aurel32 · 17 years ago
  49. c047da1 SH4: Convert shift functions to TCG by aurel32 · 17 years ago
  50. 390af82 SH4: convert control/status register load/store to TCG by aurel32 · 17 years ago
  51. fa4da10 SH4: Convert memory loads/stores to TCG by aurel32 · 17 years ago
  52. 6f06939 SH4: convert some more arithmetics ops to TCG by aurel32 · 17 years ago
  53. e6afc2f SH4: convert a few helpers to TCG by aurel32 · 17 years ago
  54. 1000822 SH4: convert branch/jump instructions to TCG by aurel32 · 17 years ago
  55. a462561 SH4: convert simple compare instructions to TCG by aurel32 · 17 years ago
  56. 3a8a44c SH4: convert a few control or system register functions to TCG by aurel32 · 17 years ago
  57. 829337a SH4: Fix bugs introduce in r5099 by aurel32 · 17 years ago
  58. 5aa3b1e SH4: fix xtrct Rm,Rn (broken in r5103) by aurel32 · 17 years ago
  59. 559dd74 SH4: convert logic and arithmetic ops to TCG by aurel32 · 17 years ago
  60. 1e8864f SH4: use TCG variables for gregs by aurel32 · 17 years ago
  61. 3bf73a4 SH4: use uint32_t/i32 based types/ops by aurel32 · 17 years ago
  62. 8f99cc6 SH4: Convert register moves to TCG by aurel32 · 17 years ago
  63. a73d39b SH4: Convert dyngen registers moves to TCG by aurel32 · 17 years ago
  64. ccc9cc5 SH4: Convert immediate loads to TCG by aurel32 · 17 years ago
  65. 988d7ea SH4: add support for TCG helpers by aurel32 · 17 years ago
  66. 6858571 SH4: Init TCG variables by aurel32 · 17 years ago
  67. 825c69c sh4: fix tas.b @Rn instruction by aurel32 · 17 years ago
  68. 7da76bc [sh4] code translation bug fix by aurel32 · 17 years ago
  69. 274a9e7 [sh4] delay slot bug fix by aurel32 · 17 years ago
  70. 833ed38 [sh4] sleep instruction by aurel32 · 17 years ago
  71. a5f1b96 Fix warnings that would be generated by gcc -Wstrict-prototypes by blueswir1 · 17 years ago
  72. 2cfc5f1 Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues. by ths · 17 years ago
  73. b2437bf Add missing static qualifiers. by pbrook · 17 years ago
  74. 2e70f6e Add instruction counter. by pbrook · 17 years ago
  75. ea2b542 SH4 MMU improvements by aurel32 · 17 years ago
  76. d2856f1 Factorize code in translate.c by aurel32 · 17 years ago
  77. ca10f86 Remove osdep.c/qemu-img code duplication by aurel32 · 17 years ago
  78. 24988dc SH4, fix several instructions by aurel32 · 17 years ago
  79. 57fec1f use the TCG code generator by bellard · 17 years ago
  80. 823029f SH4 delay slot code update, by Magnus Damm. by ths · 17 years ago
  81. b0b3de8 fixed FPU rounding init by bellard · 17 years ago
  82. aaed909 added cpu_model parameter to cpu_init() by bellard · 17 years ago
  83. c5e814b Fix rte opcode, by Magnus Damm. by ths · 18 years ago
  84. 5fafdf2 find -type f | xargs sed -i 's/[\t ]$//g' # on most files by ths · 18 years ago
  85. ce62e5b Fix tb->size mishandling, by Daniel Jacobowitz. by ths · 18 years ago
  86. 8c2cc7c SH4 mov.b fix, by Vince Weaver. by ths · 18 years ago
  87. 022a22c Ignore PR flag in FPSCR when performing fmov, by Magnus Damm. by ths · 18 years ago
  88. e67888a Document FPSCR usage, by Magnus Damm. by ths · 18 years ago
  89. e3d8a98 Use DREG() instead of XREG() wherever possible, by Magnus Damm. by ths · 18 years ago
  90. ea6cf6b Emulate more fpu opcodes, by Magnus Damm. by ths · 18 years ago
  91. 4c909d1 Set FD bit in SR to emulate kernel behaviour, by Magnus Damm. by ths · 18 years ago
  92. f09111e Fix XHACK() macro and use FREG if possible, by Magnus Damm. by ths · 18 years ago
  93. 8bf5a80 Fix opcode for sts.l fpul/cpscr, by Magnus Damm. by ths · 18 years ago
  94. 820e00f Define gen_intermediate_code_internal as "static inline". by ths · 18 years ago
  95. 9c2a9ea SH bugfixes. by pbrook · 19 years ago
  96. 397e923 Remove debug output. by pbrook · 19 years ago
  97. 355fb23 SH usermode fault handling. by pbrook · 19 years ago
  98. 9854bc4 SH4 rts fix. by pbrook · 19 years ago
  99. eda9b09 sh4 fmov et al instructions (amatus) by bellard · 19 years ago
  100. fdf9b3e sh4 target (Samuel Tardieu) by bellard · 19 years ago