Sign in
qemu
/
qemu
/
a6130237b85e15463592484155aa905a9b39cc6c
/
target-tricore
4910e6e
target-*: dfilter support for in_asm
by Richard Henderson
· 9 years ago
63c9155
cpu: move exec-all.h inclusion out of cpu.h
by Paolo Bonzini
· 9 years ago
fc111b1
target-tricore: make cpu-qom.h not target specific
by Paolo Bonzini
· 9 years ago
cb8d4c8
Fix some typos found by codespell
by Stefan Weil
· 9 years ago
90aa39a
tcg: Allow goto_tb to any target PC in user mode
by Sergey Fedorov
· 9 years ago
89fee74
tb: consistently use uint32_t for tb->flags
by Emilio G. Cota
· 9 years ago
84a5a80
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
by Peter Maydell
· 9 years ago
0d4c3b8
target-tricore: Add ftoi and itof instructions
by Bastian Koppelmann
· 9 years ago
743cd09
target-tricore: Add cmp.f instruction
by Bastian Koppelmann
· 9 years ago
446ee5b
target-tricore: Add div.f instruction
by Bastian Koppelmann
· 9 years ago
daab3f7
target-tricore: Add mul.f instruction
by Bastian Koppelmann
· 9 years ago
baf410d
target-tricore: add add.f/sub.f instructions
by Bastian Koppelmann
· 9 years ago
c433a17
target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide
by Bastian Koppelmann
· 9 years ago
996a729
target-tricore: Add FPU infrastructure
by Bastian Koppelmann
· 9 years ago
1bd3e2f
target-tricore: Fix psw_read() clearing too many bits
by Bastian Koppelmann
· 9 years ago
9029710
target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit
by Bastian Koppelmann
· 9 years ago
1f75cba
target-tricore: add missing break in insn decode switch stmt
by Bastian Koppelmann
· 9 years ago
da34e65
include/qemu/osdep.h: Don't include qapi/error.h
by Markus Armbruster
· 9 years ago
1bcea73
tcg: Add type for vCPU pointers
by Lluís Vilanova
· 9 years ago
828066c
target-tricore: add opd trap generation
by Bastian Koppelmann
· 9 years ago
f678f67
target-tricore: add illegal opcode trap generation
by Bastian Koppelmann
· 9 years ago
3292b44
target-tricore: add context managment trap generation
by Bastian Koppelmann
· 9 years ago
518d7fd
target-tricore: Add trap handling & SOVF/OVF traps
by Bastian Koppelmann
· 9 years ago
5dc1fba
target-tricore: Fix wrong precedences on psw_write
by Bastian Koppelmann
· 9 years ago
7237335
target-tricore: fix save_context_upper using env->PSW
by Bastian Koppelmann
· 9 years ago
30456d5
all: Clean up includes
by Peter Maydell
· 9 years ago
e1ccc05
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr
by Richard Henderson
· 11 years ago
508127e
log: do not unnecessarily include qom/cpu.h
by Paolo Bonzini
· 9 years ago
61d9f32
tricore: Clean up includes
by Peter Maydell
· 9 years ago
b81b971
tricore: avoid "naked" qemu_log
by Paolo Bonzini
· 9 years ago
4c315c2
qdev: Protect device-list-properties against broken devices
by Markus Armbruster
· 9 years ago
4e5e121
tcg: Remove gen_intermediate_code_pc
by Richard Henderson
· 9 years ago
bad729e
tcg: Pass data argument to restore_state_to_opc
by Richard Henderson
· 9 years ago
190ce7f
tcg: Add TCG_MAX_INSNS
by Richard Henderson
· 9 years ago
959082f
target-*: Increment num_insns immediately after tcg_gen_insn_start
by Richard Henderson
· 9 years ago
667b8e2
target-*: Unconditionally emit tcg_gen_insn_start
by Richard Henderson
· 9 years ago
7183128
tricore: Remove ELF_MACHINE from cpu.h
by Peter Crosthwaite
· 10 years ago
97ed5cc
tlb: Add "ifetch" argument to cpu_mmu_index()
by Benjamin Herrenschmidt
· 9 years ago
1618d2a
maint: remove unused include for signal.h
by Daniel P. Berrange
· 9 years ago
ecc7b3a
tcg: Remove tcg_gen_trunc_i64_i32
by Richard Henderson
· 9 years ago
609ad70
tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32
by Richard Henderson
· 9 years ago
ea3e984
cpu-exec: Purge all uses of ENV_GET_CPU()
by Peter Crosthwaite
· 10 years ago
4bad9e3
cpu: Change cpu_exec_init() arg to cpu, not env
by Peter Crosthwaite
· 9 years ago
5a790cc
cpu: Add Error argument to cpu_exec_init()
by Bharata B Rao
· 9 years ago
5f37fd8
target-tricore: fix depositing bits from PCXI into ICR
by Paolo Bonzini
· 9 years ago
d49190c
disas: Remove uses of CPU env
by Peter Crosthwaite
· 10 years ago
07e1548
target-tricore: fix BOL_ST_H_LONGOFF using ld
by Bastian Koppelmann
· 10 years ago
9bbd484
target-tricore: fix msub32_q producing the wrong overflow bit
by Bastian Koppelmann
· 10 years ago
05b6ca9
target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result
by Bastian Koppelmann
· 10 years ago
9371557
target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
by Bastian Koppelmann
· 10 years ago
0e045f4
target-tricore: add FRET instructions of the v1.6 ISA
by Bastian Koppelmann
· 10 years ago
9e14a7b
target-tricore: add FCALL instructions of the v1.6 ISA
by Bastian Koppelmann
· 10 years ago
bc3551c
target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
by Bastian Koppelmann
· 10 years ago
e5c96c8
target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
by Bastian Koppelmann
· 10 years ago
ddd8ceb
target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
by Bastian Koppelmann
· 10 years ago
62872eb
target-tricore: add CMPSWP instructions of the v1.6.1 ISA
by Bastian Koppelmann
· 10 years ago
fcecf12
target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
by Bastian Koppelmann
· 10 years ago
6d2afc8
target-tricore: introduce ISA v1.6.1 feature
by Bastian Koppelmann
· 10 years ago
fd5ecf3
target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3
by Bastian Koppelmann
· 10 years ago
3446a11
target-tricore: fix rfe not restoring the PC
by Bastian Koppelmann
· 10 years ago
bc72f8a
target-tricore: fix rslcx restoring the upper context instead of the lower
by Bastian Koppelmann
· 10 years ago
4959d6b
target-tricore: fix BO_OFF10_SEXT calculating the wrong offset
by Bastian Koppelmann
· 10 years ago
7bd0eae
target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4
by Bastian Koppelmann
· 10 years ago
250ef8c
target-tricore: Fix LOOP using wrong register for compare
by Bastian Koppelmann
· 10 years ago
fee068e
tcg: Delete unused cpu_pc_from_tb()
by Peter Crosthwaite
· 10 years ago
7b4b0b5
target-tricore: Fix check which was always false
by Stefan Weil
· 10 years ago
f1fdaf5
target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..
by Bastian Koppelmann
· 10 years ago
f69c24e
target-tricore: properly fix dvinit_b/h_13
by Bastian Koppelmann
· 10 years ago
00e1754
target-tricore: fix RRPW_DEXTR using wrong reg
by Bastian Koppelmann
· 10 years ago
2b9d09b
target-tricore: fix DVINIT_HU/BU calculating overflow before result
by Bastian Koppelmann
· 10 years ago
30a0d72
target-tricore: Fix two helper functions (clang warnings)
by Stefan Weil
· 10 years ago
de7ad4c
Fix typos in comments
by Viswesh
· 10 years ago
b724b01
target-tricore: Add instructions of SYS opcode format
by Bastian Koppelmann
· 10 years ago
eb989d2
target-tricore: Add instructions of RRRW opcode format
by Bastian Koppelmann
· 10 years ago
4d108fe
target-tricore: Add instructions of RRRR opcode format
by Bastian Koppelmann
· 10 years ago
068fac7
target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode
by Bastian Koppelmann
· 10 years ago
62e47b2
target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as first opcode
by Bastian Koppelmann
· 10 years ago
f4aef47
target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as first opcode
by Bastian Koppelmann
· 10 years ago
42a268c
tcg: Change translator-side labels to a pointer
by Richard Henderson
· 10 years ago
2994fd9
cpu: Make cpu_init() return QOM CPUState object
by Eduardo Habkost
· 10 years ago
bebe80f
target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode
by Bastian Koppelmann
· 10 years ago
b00aa8e
target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode
by Bastian Koppelmann
· 10 years ago
2e430e1
target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode
by Bastian Koppelmann
· 10 years ago
2984cfb
target-tricore: Add instructions of RRR2 opcode format
by Bastian Koppelmann
· 10 years ago
3debbb5
target-tricore: fix msub32_suov return wrong results
by Bastian Koppelmann
· 10 years ago
f0cab01
target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper
by Bastian Koppelmann
· 10 years ago
fe700ad
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
by Richard Henderson
· 11 years ago
0a7df5d
tcg: Move emit of INDEX_op_end into gen_tb_end
by Richard Henderson
· 11 years ago
0953225
target-tricore: Add instructions of RRR opcode format
by Bastian Koppelmann
· 10 years ago
8fb9d0e
target-tricore: Add instructions of RRPW opcode format
by Bastian Koppelmann
· 10 years ago
12f323e
target-tricore: Add instructions of RR2 opcode format
by Bastian Koppelmann
· 10 years ago
f1cc6ea
target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode
by Bastian Koppelmann
· 10 years ago
85d604a
target-tricore: split up suov32 into suov32_pos and suov32_neg
by Bastian Koppelmann
· 10 years ago
40a1f64
target-tricore: Fix bugs found by coverity
by Bastian Koppelmann
· 10 years ago
811ea60
target-tricore: calculate av bits before saturation
by Bastian Koppelmann
· 10 years ago
5f30046
target-tricore: Several translator and cpu model fixes
by Bastian Koppelmann
· 10 years ago
452e3d4
target-tricore: Add missing ULL suffix on 64 bit constant
by Peter Maydell
· 10 years ago
3709741
target-tricore: Fix new typos
by Stefan Weil
· 10 years ago
a4ba200
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
by Peter Maydell
· 10 years ago
cd42d5b
gen-icount: check cflags instead of use_icount global
by Paolo Bonzini
· 10 years ago
Next »