Google Git
Sign in
qemu / qemu / 8dc007d3d9f79d0c60c750055a79ce8b21bfb494 / target / riscv / insn16.decode
  1. 4cc16b3 target/riscv: Add checks for several RVC reserved operands by Richard Henderson · 6 years ago
  2. 0e68e24 target/riscv: Split RVC32 and RVC64 insns into separate files by Richard Henderson · 6 years ago
  3. c2cfb97 target/riscv: Use pattern groups in insn16.decode by Richard Henderson · 6 years ago
  4. 6cafec9 target/riscv: Merge argument decode for RVC shifti by Richard Henderson · 6 years ago
  5. e1d455d target/riscv: Merge argument sets for insn32 and insn16 by Richard Henderson · 6 years ago
  6. 97b0be8 target/riscv: Convert quadrant 2 of RVXC insns to decodetree by Bastian Koppelmann · 6 years ago
  7. 07b001c target/riscv: Convert quadrant 1 of RVXC insns to decodetree by Bastian Koppelmann · 6 years ago
  8. e98d914 target/riscv: Convert quadrant 0 of RVXC insns to decodetree by Bastian Koppelmann · 6 years ago