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qemu / qemu / 8979c945c1a7ffd20edbd5da2513c04baccfd7de / target-i386 / ops_sse_header.h
  1. d640045 target-i386: add AES-NI instructions by Aurelien Jarno · 12 years ago
  2. e71827b target-i386: add pclmulqdq instruction by Aurelien Jarno · 12 years ago
  3. d3eb5ea x86: avoid AREG0 for FPU helpers by Blue Swirl · 13 years ago
  4. 2bece2c tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts. by Richard Henderson · 15 years ago
  5. d9f4bb2 target-i386: add SSE4a instruction support by Andre Przywara · 15 years ago
  6. 8167ee8 Update to a hopefully more future proof FSF address by Blue Swirl · 16 years ago
  7. fad6cb1 Update FSF address in GPL/LGPL boilerplate by aurel32 · 16 years ago
  8. a7812ae TCG variable type checking. by pbrook · 16 years ago
  9. 222a333 Implement SSE4.1, SSE4.2 (x86). by balrog · 16 years ago
  10. 4242b1b Implement x86 SSSE3 instructions. by balrog · 16 years ago
  11. 437a88a proper helper definition registering (all targets must do that) by bellard · 17 years ago
  12. b8b6a50 converted more helpers to TCG - fixed some SVM issues by bellard · 17 years ago
  13. 5af4518 converted SSE/MMX ops to TCG by bellard · 17 years ago