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qemu / qemu / 887ce500ef0046d35e613e40f7beb647a797b3e7 / target / riscv
  1. b36e239 target: Use ArchCPU as interface to target CPU by Philippe Mathieu-Daudé · 3 years, 1 month ago
  2. 9295b1a target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro by Philippe Mathieu-Daudé · 3 years, 1 month ago
  3. 1ea4a06 target: Use CPUArchState as interface to target-specific CPU state by Philippe Mathieu-Daudé · 3 years, 1 month ago
  4. 3cb1a41 target: Include missing 'cpu.h' by Philippe Mathieu-Daudé · 3 years, 1 month ago
  5. 03ff4f8 misc: Add missing "sysemu/cpu-timers.h" include by Philippe Mathieu-Daudé · 3 years, 1 month ago
  6. 6b1acce target/riscv: expose zfinx, zdinx, zhinx{min} properties by Weiwei Li · 3 years, 1 month ago
  7. a2464a4 target/riscv: add support for zhinx/zhinxmin by Weiwei Li · 3 years, 1 month ago
  8. 026e73f target/riscv: add support for zdinx by Weiwei Li · 3 years, 1 month ago
  9. e1a29bb target/riscv: add support for zfinx by Weiwei Li · 3 years, 1 month ago
  10. c163b3b target/riscv: hardwire mstatus.FS to zero when enable zfinx by Weiwei Li · 3 years, 1 month ago
  11. 89ffdce target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} by Weiwei Li · 3 years, 1 month ago
  12. 90f9e35 target/riscv: fix inverted checks for ext_zb[abcs] by Philipp Tomsich · 3 years, 1 month ago
  13. b8012ec target: Add missing "qemu/timer.h" include by Philippe Mathieu-Daudé · 3 years, 1 month ago
  14. bbce8ba target/riscv: add support for svpbmt extension by Weiwei Li · 3 years, 1 month ago
  15. c5d77dd target/riscv: add support for svinval extension by Weiwei Li · 3 years, 1 month ago
  16. 2bacb22 target/riscv: add support for svnapot extension by Weiwei Li · 3 years, 1 month ago
  17. b6ecc63 target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE by Weiwei Li · 3 years, 1 month ago
  18. 05e6ca5 target/riscv: Ignore reserved bits in PTE for RV64 by Guo Ren · 3 years, 1 month ago
  19. 91870b5 target/riscv: Allow users to force enable AIA CSRs in HART by Anup Patel · 3 years, 1 month ago
  20. ac4b030 target/riscv: Implement AIA IMSIC interface CSRs by Anup Patel · 3 years, 1 month ago
  21. d1ceff4 target/riscv: Implement AIA xiselect and xireg CSRs by Anup Patel · 3 years, 1 month ago
  22. c7de92b target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs by Anup Patel · 3 years, 1 month ago
  23. d0237b4 target/riscv: Implement AIA interrupt filtering CSRs by Anup Patel · 3 years, 1 month ago
  24. 2b60239 target/riscv: Implement AIA hvictl and hviprioX CSRs by Anup Patel · 3 years, 1 month ago
  25. d028ac7 target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 by Anup Patel · 3 years, 1 month ago
  26. 43dc93a target/riscv: Implement AIA local interrupt priorities by Anup Patel · 3 years, 1 month ago
  27. 69077dd target/riscv: Allow AIA device emulation to set ireg rmw callback by Anup Patel · 3 years, 1 month ago
  28. aa7508b target/riscv: Add defines for AIA CSRs by Anup Patel · 3 years, 1 month ago
  29. 32b0ada target/riscv: Add AIA cpu feature by Anup Patel · 3 years, 1 month ago
  30. f87adf2 target/riscv: Allow setting CPU feature from machine/device emulation by Anup Patel · 3 years, 1 month ago
  31. 02d9565 target/riscv: Improve delivery of guest external interrupts by Anup Patel · 3 years, 1 month ago
  32. cd032fe target/riscv: Implement hgeie and hgeip CSRs by Anup Patel · 3 years, 1 month ago
  33. 881df35 target/riscv: Implement SGEIP bit in hip and hie CSRs by Anup Patel · 3 years, 1 month ago
  34. dceecac target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode by Anup Patel · 3 years, 1 month ago
  35. ac6bcf4 target/riscv: Fix vill field write in vtype by LIU Zhiwei · 3 years, 1 month ago
  36. 0d429bd target/riscv: Add XVentanaCondOps custom extension by Philipp Tomsich · 3 years, 1 month ago
  37. 5e199b6 target/riscv: iterate over a table of decoders by Philipp Tomsich · 3 years, 1 month ago
  38. f2a32be target/riscv: access cfg structure through DisasContext by Philipp Tomsich · 3 years, 1 month ago
  39. 79bf3b5 target/riscv: access configuration through cfg_ptr in DisasContext by Philipp Tomsich · 3 years, 1 month ago
  40. 3b91323 target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr by Philipp Tomsich · 3 years, 1 month ago
  41. 466292b target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' by Philipp Tomsich · 3 years, 1 month ago
  42. 6c3a924 target/riscv: correct "code should not be reached" for x-rv128 by Frédéric Pétrot · 3 years, 1 month ago
  43. f297245 target/riscv: Relax UXL field for debugging by LIU Zhiwei · 3 years, 2 months ago
  44. f310df5 target/riscv: Enable uxl field write by LIU Zhiwei · 3 years, 2 months ago
  45. 5a2ae23 target/riscv: Set default XLEN for hypervisor by LIU Zhiwei · 3 years, 2 months ago
  46. d8c40c2 target/riscv: Adjust scalar reg in vector with XLEN by LIU Zhiwei · 3 years, 2 months ago
  47. d6b9d93 target/riscv: Adjust vector address with mask by LIU Zhiwei · 3 years, 2 months ago
  48. 01d0952 target/riscv: Fix check range for first fault only by LIU Zhiwei · 3 years, 2 months ago
  49. eef11ce target/riscv: Remove VILL field in VTYPE by LIU Zhiwei · 3 years, 2 months ago
  50. 31961cf target/riscv: Adjust vsetvl according to XLEN by LIU Zhiwei · 3 years, 2 months ago
  51. d96a271 target/riscv: Split out the vill from vtype by LIU Zhiwei · 3 years, 2 months ago
  52. 4208dc7 target/riscv: Split pm_enabled into mask and base by LIU Zhiwei · 3 years, 2 months ago
  53. 4302bef target/riscv: Calculate address according to XLEN by LIU Zhiwei · 3 years, 2 months ago
  54. 0cff460 target/riscv: Alloc tcg global for cur_pm[mask|base] by LIU Zhiwei · 3 years, 2 months ago
  55. 40bfa5f target/riscv: Create current pm fields in env by LIU Zhiwei · 3 years, 2 months ago
  56. 83b519b target/riscv: Adjust csr write mask with XLEN by LIU Zhiwei · 3 years, 2 months ago
  57. 47bdec8 target/riscv: Relax debug check for pm write by LIU Zhiwei · 3 years, 2 months ago
  58. 1191be0 target/riscv: Use gdb xml according to max mxlen by LIU Zhiwei · 3 years, 2 months ago
  59. bf9e776 target/riscv: Extend pc for runtime pc write by LIU Zhiwei · 3 years, 2 months ago
  60. 8c796f1 target/riscv: Ignore the pc bits above XLEN by LIU Zhiwei · 3 years, 2 months ago
  61. 440544e target/riscv: Create xl field in env by LIU Zhiwei · 3 years, 2 months ago
  62. 40f0c20 target/riscv: Sign extend pc for different XLEN by LIU Zhiwei · 3 years, 2 months ago
  63. a14db52 target/riscv: Sign extend link reg for jal and jalr by LIU Zhiwei · 3 years, 2 months ago
  64. b655dc7 target/riscv: Don't save pc when exception return by LIU Zhiwei · 3 years, 2 months ago
  65. 79f26b3 target/riscv: Adjust pmpcfg access with mxl by LIU Zhiwei · 3 years, 2 months ago
  66. 2fc1b44 target/riscv: rvv-1.0: Allow Zve32f extension to be turned on by Frank Chang · 3 years, 2 months ago
  67. 6db0232 target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns by Frank Chang · 3 years, 2 months ago
  68. f4dcf51 target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns by Frank Chang · 3 years, 2 months ago
  69. 8527b5d target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns by Frank Chang · 3 years, 2 months ago
  70. abe2d74 target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns by Frank Chang · 3 years, 2 months ago
  71. da61f12 target/riscv: rvv-1.0: Add Zve32f support for configuration insns by Frank Chang · 3 years, 2 months ago
  72. 32e579b target/riscv: rvv-1.0: Add Zve32f extension into RISC-V by Frank Chang · 3 years, 2 months ago
  73. bfefe40 target/riscv: rvv-1.0: Allow Zve64f extension to be turned on by Frank Chang · 3 years, 2 months ago
  74. 68fa389 target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns by Frank Chang · 3 years, 2 months ago
  75. 235d116 target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns by Frank Chang · 3 years, 2 months ago
  76. 193fb5c target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns by Frank Chang · 3 years, 2 months ago
  77. 40d78c8 target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns by Frank Chang · 3 years, 2 months ago
  78. 13dbc82 target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns by Frank Chang · 3 years, 2 months ago
  79. aaae699 target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns by Frank Chang · 3 years, 2 months ago
  80. 4941040 target/riscv: rvv-1.0: Add Zve64f support for load and store insns by Frank Chang · 3 years, 2 months ago
  81. c7a26fb target/riscv: rvv-1.0: Add Zve64f support for configuration insns by Frank Chang · 3 years, 2 months ago
  82. b4a99d4 target/riscv: rvv-1.0: Add Zve64f extension into RISC-V by Frank Chang · 3 years, 2 months ago
  83. 1eb9a5d target/riscv: Support virtual time context synchronization by Yifei Jiang · 3 years, 2 months ago
  84. 9ad3e01 target/riscv: Implement virtual time adjusting with vm state changing by Yifei Jiang · 3 years, 2 months ago
  85. 27abe66 target/riscv: Add kvm_riscv_get/put_regs_timer by Yifei Jiang · 3 years, 2 months ago
  86. 10f1ca2 target/riscv: Add host cpu type by Yifei Jiang · 3 years, 2 months ago
  87. 4eb4712 target/riscv: Handle KVM_EXIT_RISCV_SBI exit by Yifei Jiang · 3 years, 2 months ago
  88. 2b650fb target/riscv: Support setting external interrupt by KVM by Yifei Jiang · 3 years, 2 months ago
  89. ad40be2 target/riscv: Support start kernel directly by KVM by Yifei Jiang · 3 years, 2 months ago
  90. 9997cc1 target/riscv: Implement kvm_arch_put_registers by Yifei Jiang · 3 years, 2 months ago
  91. 937f0b4 target/riscv: Implement kvm_arch_get_registers by Yifei Jiang · 3 years, 2 months ago
  92. 0a312b8 target/riscv: Implement function kvm_arch_init_vcpu by Yifei Jiang · 3 years, 2 months ago
  93. 91654e6 target/riscv: Add target/riscv/kvm.c to place the public kvm interface by Yifei Jiang · 3 years, 2 months ago
  94. 48eaeb5 target/riscv: Implement the stval/mtval illegal instruction by Alistair Francis · 3 years, 3 months ago
  95. 86d0c45 target/riscv: Fixup setting GVA by Alistair Francis · 3 years, 3 months ago
  96. ea7b5d5 target/riscv: Set the opcode in DisasContext by Alistair Francis · 3 years, 3 months ago
  97. 457c360 target/riscv: actual functions to realize crs 128-bit insns by Frédéric Pétrot · 3 years, 2 months ago
  98. 7934fde target/riscv: modification of the trans_csrxx for 128-bit support by Frédéric Pétrot · 3 years, 2 months ago
  99. 961738f target/riscv: helper functions to wrap calls to 128-bit csr insns by Frédéric Pétrot · 3 years, 2 months ago
  100. 2c64ab6 target/riscv: adding high part of some csrs by Frédéric Pétrot · 3 years, 2 months ago