1. 7ea47fe target-arm: Implement ARMv8 single-step handling for A64 code by Peter Maydell · 11 years ago
  2. cc9c1ed target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb by Peter Maydell · 11 years ago
  3. 229a138 target-arm: Fix return address for A64 BRK instructions by Peter Maydell · 11 years ago
  4. a7e30d8 trace: [tcg] Include TCG-tracing header on all targets by Lluís Vilanova · 11 years ago
  5. 4063452 target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv() by Peter Maydell · 11 years ago
  6. 220ad4c target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int() by Peter Maydell · 11 years ago
  7. f6fe04d target-arm: A64: Implement two-register SHA instructions by Peter Maydell · 11 years ago
  8. be56f04 target-arm: A64: Implement 3-register SHA instructions by Peter Maydell · 11 years ago
  9. 5acc765 target-arm: A64: Implement AES instructions by Peter Maydell · 11 years ago
  10. 130f2e7 target-arm: A64: Implement CRC instructions by Peter Maydell · 11 years ago
  11. 411bdc7 target-arm: A64: Use PMULL feature bit for PMULL by Peter Maydell · 11 years ago
  12. 1d85476 target-arm: move arm_*_code to a separate file by Paolo Bonzini · 11 years ago
  13. 2ef6175 tcg: Invert the inclusion of helper.h by Richard Henderson · 11 years ago
  14. 14c521d target-arm: A64: Trap ERET from EL0 at translation time by Edgar E. Iglesias · 11 years ago
  15. 9d4c4e8 target-arm: Move get_mem_index to translate.h by Edgar E. Iglesias · 11 years ago
  16. 1b505f9 target-arm: A64: Handle blr lr by Edgar E. Iglesias · 11 years ago
  17. 252ec40 target-arm: implement WFE/YIELD as a yield for AArch64 by Rob Herring · 11 years ago
  18. e44a90c target-arm: A64: fix unallocated test of scalar SQXTUN by Alex Bennée · 11 years ago
  19. 52e60cd target-arm: Implement AArch64 EL1 exception handling by Rob Herring · 11 years ago
  20. aca3f40 target-arm: A64: Implement DC ZVA by Peter Maydell · 11 years ago
  21. 90e4963 target-arm: A64: Add assertion that FP access was checked by Peter Maydell · 11 years ago
  22. 8c6afa6 target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set by Peter Maydell · 11 years ago
  23. d4a2dc6 target-arm: Add support for generating exceptions with syndrome information by Peter Maydell · 11 years ago
  24. 8bcbf37 target-arm: Provide correct syndrome information for cpreg access traps by Peter Maydell · 11 years ago
  25. ccd3808 target-arm: Split out private-to-target functions into internals.h by Peter Maydell · 11 years ago
  26. d108609 target-arm: Fix A64 Neon MLS by Peter Maydell · 11 years ago
  27. 09e0373 target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD) by Alex Bennée · 11 years ago
  28. 0a79bc8 target-arm: A64: Add saturating int ops (SQNEG/SQABS) by Alex Bennée · 11 years ago
  29. c2fb418 target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate) by Alex Bennée · 11 years ago
  30. 5553955 target-arm: A64: Implement FCVTXN by Peter Maydell · 11 years ago
  31. 5201c13 target-arm: A64: Implement scalar saturating narrow ops by Alex Bennée · 11 years ago
  32. 8b092ca target-arm: A64: Move handle_2misc_narrow function by Alex Bennée · 11 years ago
  33. b6d4443 target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE by Alex Bennée · 11 years ago
  34. 2ed3ea1 target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories by Peter Maydell · 11 years ago
  35. a847f32 target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL by Peter Maydell · 11 years ago
  36. 03df01e target-arm: A64: Implement FRINT* by Peter Maydell · 11 years ago
  37. 37a706a target-arm: A64: Implement SRI by Peter Maydell · 11 years ago
  38. 8f0c675 target-arm: A64: Add FRECPX (reciprocal exponent) by Alex Bennée · 11 years ago
  39. a566da1 target-arm: A64: List unsupported shift-imm opcodes by Peter Maydell · 11 years ago
  40. 931c8cc target-arm: A64: Implement FCVTL by Peter Maydell · 11 years ago
  41. 261a5b4 target-arm: A64: Implement FCVTN by Peter Maydell · 11 years ago
  42. 04c7c6c target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions by Peter Maydell · 11 years ago
  43. 73a81d1 target-arm: A64: Implement SHLL, SHLL2 by Peter Maydell · 11 years ago
  44. 6781fa1 target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP by Peter Maydell · 11 years ago
  45. c1b876b target-arm: A64: Saturating and narrowing shift ops by Alex Bennée · 11 years ago
  46. b05c306 target-arm: A64: Add remaining CLS/Z vector ops by Alex Bennée · 11 years ago
  47. f612537 target-arm: A64: Add FSQRT to C3.6.17 (two misc) by Alex Bennée · 11 years ago
  48. 10113b6 target-arm: A64: Add last AdvSIMD Integer to FP ops by Alex Bennée · 11 years ago
  49. cf4ab1a target-arm: A64: Fix bug in add_sub_ext handling of rn by Alex Bennée · 11 years ago
  50. a984e42 target-arm: A64: Implement PMULL instruction by Peter Maydell · 11 years ago
  51. f0c3c50 cpu: Move breakpoints field from CPU_COMMON to CPUState by Andreas Färber · 11 years ago
  52. 0624976 target-arm: Fix intptr_t vs tcg_target_long by Richard Henderson · 11 years ago
  53. 9cfa0b4 target-arm: A64: Implement MSR (immediate) instructions by Peter Maydell · 11 years ago
  54. 1ed69e8 target-arm: A64: Implement WFI by Peter Maydell · 11 years ago
  55. d9ea7d2 target-arm: Get MMU index information correct for A64 code by Peter Maydell · 11 years ago
  56. 0eef9d9 target-arm: Implement AArch64 CurrentEL sysreg by Peter Maydell · 11 years ago
  57. 60510ae target-arm: A64: Implement unprivileged load/store by Peter Maydell · 11 years ago
  58. e4b998d target-arm: A64: Implement narrowing three-reg-diff operations by Peter Maydell · 11 years ago
  59. dfc15c7 target-arm: A64: Implement the wide 3-reg-different operations by Peter Maydell · 11 years ago
  60. 70d7f98 target-arm: A64: Add most remaining three-reg-diff widening ops by Peter Maydell · 11 years ago
  61. 13caf1f target-arm: A64: Add opcode comments to disas_simd_three_reg_diff by Peter Maydell · 11 years ago
  62. d324b36 target-arm: A64: Implement store-exclusive for system mode by Peter Maydell · 11 years ago
  63. ea4571e target-arm: Remove unnecessary code now read/write fns can't fail by Peter Maydell · 11 years ago
  64. f59df3f target-arm: Split cpreg access checks out from read/write functions by Peter Maydell · 11 years ago
  65. 626187d target-arm: Log bad system register accesses with LOG_UNIMP by Peter Maydell · 11 years ago
  66. 057d5f6 target-arm: A64: Implement remaining 3-same instructions by Peter Maydell · 11 years ago
  67. bc242f9 target-arm: A64: Implement floating point pairwise insns by Alex Bennée · 11 years ago
  68. 8908f4d target-arm: A64: Implement SIMD FP compare and set insns by Alex Bennée · 11 years ago
  69. b033cd3 target-arm: A64: Implement scalar three different instructions by Peter Maydell · 11 years ago
  70. 9f82e0f target-arm: A64: Implement SIMD scalar indexed instructions by Peter Maydell · 11 years ago
  71. c44ad1f target-arm: A64: Implement long vector x indexed insns by Peter Maydell · 11 years ago
  72. f5e51e7 target-arm: A64: Implement plain vector SIMD indexed element insns by Peter Maydell · 11 years ago
  73. 999b53e disas: Implement disassembly output for A64 by Claudio Fontana · 11 years ago
  74. f93d013 target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group by Peter Maydell · 11 years ago
  75. 39d8211 target-arm: A64: Add 2-reg-misc REV* instructions by Alex Bennée · 11 years ago
  76. d980fd5 target-arm: A64: Add narrowing 2-reg-misc instructions by Peter Maydell · 11 years ago
  77. 86cbc41 target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT by Peter Maydell · 11 years ago
  78. 94b6c91 target-arm: A64: Implement 2-register misc compares, ABS, NEG by Peter Maydell · 11 years ago
  79. 45aecc6 target-arm: A64: Add skeleton decode for SIMD 2-reg misc group by Peter Maydell · 11 years ago
  80. effa8e0 target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc by Peter Maydell · 11 years ago
  81. c0b2b5f target-arm: A64: Implement remaining integer scalar-3-same insns by Peter Maydell · 11 years ago
  82. 3720a7e target-arm: A64: Implement scalar pairwise ops by Peter Maydell · 11 years ago
  83. 0173a00 target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD by Peter Maydell · 11 years ago
  84. 8b12a0c target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns by Peter Maydell · 11 years ago
  85. 6d9571f target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns by Peter Maydell · 11 years ago
  86. 4d1cef8 target-arm: A64: Add SIMD shift by immediate by Alex Bennée · 11 years ago
  87. 845ea09 target-arm: A64: Add simple SIMD 3-same floating point ops by Peter Maydell · 11 years ago
  88. 1f8a73a target-arm: A64: Add integer ops from SIMD 3-same group by Peter Maydell · 11 years ago
  89. 956d272 target-arm: A64: Add logic ops from SIMD 3 same group by Peter Maydell · 11 years ago
  90. e1cea11 target-arm: A64: Add top level decode for SIMD 3-same group by Peter Maydell · 11 years ago
  91. b305dba target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops by Peter Maydell · 11 years ago
  92. 0ae3932 target-arm: A64: Add SIMD three-different ABDL instructions by Peter Maydell · 11 years ago
  93. a08582f target-arm: A64: Add SIMD three-different multiply accumulate insns by Peter Maydell · 11 years ago
  94. 9972da6 target-arm: Move arm_rmode_to_sf to a shared location. by Will Newton · 11 years ago
  95. 360a6f2 target-arm: A64: Add SIMD scalar copy instructions by Peter Maydell · 11 years ago
  96. f3f8c4f target-arm: A64: Add SIMD modified immediate group by Alex Bennée · 11 years ago
  97. 67bb938 target-arm: A64: Add SIMD copy operations by Alex Bennée · 11 years ago
  98. 4a0ff1c target-arm: A64: Add SIMD across-lanes instructions by Michael Matz · 11 years ago
  99. 5fa5469 target-arm: A64: Add SIMD ZIP/UZP/TRN by Michael Matz · 11 years ago
  100. 7c51048 target-arm: A64: Add SIMD TBL/TBLX by Michael Matz · 11 years ago