1. 7496f52 cpu_single_env init by bellard · 21 years ago
  2. 63b7e03 boot to top of 4GB space by bellard · 21 years ago
  3. ffddfee added cpu_reset() by bellard · 21 years ago
  4. eba2af6 buffer overflow fix by bellard · 21 years ago
  5. 28c3ee3 cr0.ET fix (Win95 boot fix) by bellard · 21 years ago
  6. eeab3a5 dump A20 state by bellard · 21 years ago
  7. 67b915a win32 port (initial patch by kazu) by bellard · 21 years ago
  8. 73bdea1 2.6 kernel compile fix by bellard · 21 years ago
  9. 9588b95 CR0.MP/EM/TS support - native fpu support in code copy mode by bellard · 21 years ago
  10. 0e4b179 experimental code copy support - fixed A20 emulation by bellard · 21 years ago
  11. 34f715e fixed WP semantics by bellard · 21 years ago
  12. 1ac157d more precise TLB invalidation - init cleanup by bellard · 21 years ago
  13. 10f0e41 combine PDE and PTE protections as in intel specs - added cpu_get_phys_page_debug() by bellard · 21 years ago
  14. 777aca2 fixed dirty bit support for 4M pages (L4 Pistachio fix) by bellard · 21 years ago
  15. c8135d9 fixed subtle bug: in some cases PG_DIRTY was not set correctly by bellard · 21 years ago
  16. 436d8b8 correct value for ADDSEG is real mode (fixes GRUB boot) - update static protected mode state - use generic tlb_set_page() by bellard · 21 years ago
  17. b7f0f46 debug fixes - use more generic TLB mappings by bellard · 21 years ago
  18. 5e809a8 dump irq inhibit flag as it is a part of the cpu state by bellard · 21 years ago
  19. 6bb7057 a20 fix by bellard · 21 years ago
  20. afa05eb always completely redefine the TLB in case of MMU fault by bellard · 21 years ago
  21. 246d897 dump more registers by bellard · 21 years ago
  22. 461c047 a20 support by bellard · 21 years ago
  23. 61382a5 full softmmu support by bellard · 21 years ago
  24. 2c0262a new directory structure by bellard · 21 years ago