- 0eaef5a Less hardcoding of TARGET_USER_ONLY. by ths · 17 years ago
- b6d96be Use temporary registers for the MIPS FPU emulation. by ths · 17 years ago
- 9656f32 Move interrupt_request and user_mode_only to common cpu state. by pbrook · 17 years ago
- b3c7724 Move CPU save/load registration to common code. by pbrook · 17 years ago
- 2e70f6e Add instruction counter. by pbrook · 17 years ago
- b5dc773 More efficient target register / TC accesses. by ths · 17 years ago
- 1a3fd9c Remove remaining uses of T0 in the MIPS target. by ths · 17 years ago
- e1bf387 T1 is now dead. by ths · 17 years ago
- 764dfc3 Move FP TNs to cpu env. by ths · 17 years ago
- f8ed707 Fix typo. by pbrook · 17 years ago
- 6e68e07 Move clone() register setup to target specific code. Handle fork-like clone. by pbrook · 17 years ago
- 9133e39 Push common interrupt variables to cpu-defs.h (Glauber Costa) by bellard · 17 years ago
- ce5232c moved halted field to CPU_COMMON by bellard · 17 years ago
- 893f986 Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford. by ths · 17 years ago
- 958fb4a Use TCG for MIPS GPR moves. by ths · 17 years ago
- 3945462 Simplify mips branch handling. Retire T2 from use. Use TCG for branches. by ths · 17 years ago
- d0dc7dc Make MIPS MT implementation more cache friendly. by ths · 17 years ago
- b8aa459 MIPS COP1X (and related) instructions, by Richard Sandiford. by ths · 17 years ago
- 14e51cc De-cruft exception definitions, and implement nicer debug output. by ths · 17 years ago
- 6d35524 Improved PABITS handling, and config register fixes. by ths · 17 years ago
- aaed909 added cpu_model parameter to cpu_init() by bellard · 17 years ago
- 7df526e Move kernel loader parameters from the cpu state to being board specific. by ths · 17 years ago
- 623a930 Implement missing MIPS supervisor mode bits. by ths · 17 years ago
- 647de6c Handle IBE on MIPS properly. by ths · 17 years ago
- 6ebbf39 Replace is_user variable with mmu_idx in softmmu core, by j_mayer · 17 years ago
- c732abe Unify '-cpu ?' option. by j_mayer · 17 years ago
- 198a74d Move get_sp_from_cpustate from cpu.h to target_signal.h. by ths · 17 years ago
- a04e134 linux-user sigaltstack() syscall, by Thayne Harbaugh. by ths · 17 years ago
- 387a8fe Optimise instructions accessing CP0, by Aurelien Jarno. by ths · 17 years ago
- e189e74 Per-CPU instruction decoding implementation, by Aurelien Jarno. by ths · 17 years ago
- ead9360 Partial support for 34K multithreading, not functional yet. by ths · 18 years ago
- e034e2c Handle MIPS64 SEGBITS value correctly. by ths · 18 years ago
- 9467d44 Move target-specific defines to the target directories. by ths · 18 years ago
- 33ac7f1 Don't kill the registered irqs on reset. by ths · 18 years ago
- 51b2772 Fix CPU (re-)selection on reset. by ths · 18 years ago
- 78749ba Fix usermode check, thanks Aurelien Jarno. by ths · 18 years ago
- 5e75551 Don't check the FPU state for each FPU instruction, use hflags to by ths · 18 years ago
- 6e47312 Handle PX/UX status flags correctly, by Aurelien Jarno. by ths · 18 years ago
- fd88b6a The 24k wants more watch and srsmap registers. by ths · 18 years ago
- fd4a04e - Move FPU exception handling into helper functions, since they are big. by ths · 18 years ago
- 388bb21 MIPS linux-user update. by ths · 18 years ago
- 29929e3 MIPS TLB style selection at runtime, by Herve Poussineau. by ths · 18 years ago
- 5a5012e MIPS 64-bit FPU support, plus some collateral bugfixes in the by ths · 18 years ago
- fcb4a41 Choose number of TLBs at runtime, by Herve Poussineau. by ths · 18 years ago
- d537cf6 Unify IRQ handling. by pbrook · 18 years ago
- f7cfb2a 64bit MIPS FPUs have 32 registers. by ths · 18 years ago
- 36bb244 Fix typo, suggested by Ben Taylor. by ths · 18 years ago
- 24c7b0e Sanitize mips exception handling. by ths · 18 years ago
- e397ee3 Fix enough FPU/R2 support to get 24Kf going. by ths · 18 years ago
- 33d68b5 MIPS -cpu selection support, by Herve Poussineau. by ths · 18 years ago
- 6f5b89a MIPS Userland TLS register emulation, by Daniel Jacobowitz. by ths · 18 years ago
- 36d2395 MIPS FPU dynamic activation, part 1, by Herve Poussineau. by ths · 18 years ago
- 3594c77 Replace TLSZ with TARGET_FMT_lx. by ths · 18 years ago
- b29a034 EBase is limited to KSEG0/KSEG1 even on 64bit CPUs. by ths · 18 years ago
- 4de9b24 Reworking MIPS interrupt handling, by Aurelien Jarno. by ths · 18 years ago
- 9c2149c Implementing dmfc/dmtc. by ths · 18 years ago
- 3b1c8be Fix PageMask handling, second part. by ths · 18 years ago
- 9042c0e Check ELF binaries for machine type and endianness. by ths · 18 years ago
- 5dc4b74 Scrap SIGN_EXTEND32. by ths · 18 years ago
- c570fd1 Preliminiary MIPS64 support, disabled by default due to performance impact. by ths · 18 years ago
- 7a387ff Add MIPS32R2 instructions, and generally straighten out the instruction by ths · 18 years ago
- 6ae8177 Halt/reboot support for Linux, by Daniel Jacobowitz. This is a band-aid by ths · 18 years ago
- 814b9a4 MIPS TLB performance improvements, by Daniel Jacobowitz. by ths · 18 years ago
- fdbb469 Solaris/SPARC host port (Ben Taylor) by bellard · 19 years ago
- 43057ab use constants for TLB handling (Thiemo Seufer) by bellard · 19 years ago
- c5d6edc mips config fixes (initial patch by Stefan Weil) by bellard · 19 years ago
- 6ea83fe MIPS FPU support (Marius Goeger) by bellard · 19 years ago
- 56b1940 Rename MIPS_HFLAG(S)_TMASK (Thiemo Seufer). by pbrook · 19 years ago
- 98c1b82 e bitfields in mips TLB structures (Thiemo Seufer). by pbrook · 19 years ago
- 4ad40f3 MIPS fixes (Daniel Jacobowitz) by bellard · 19 years ago
- a316d33 added CPU_COMMON and CPUState.tb_jmp_cache[] by bellard · 19 years ago
- e37e863 correct split between helper.c and op_helper.c - cosmetics by bellard · 20 years ago
- 6af0bf9 MIPS target (Jocelyn Mayer) by bellard · 20 years ago
