- 1ffc346 Be more economical with local temporaries. by ths · 17 years ago
- aaa9128 Convert some MIPS load/store instructions to TCG. by ths · 17 years ago
- 958fb4a Use TCG for MIPS GPR moves. by ths · 17 years ago
- b7ef7bf Fix MIPS64 branches. Funny how this survived testing. by ths · 17 years ago
- 4586f9e Really really revert commit r4343 by aurel32 · 17 years ago
- e34d2d6 Really revert commit r4343 by aurel32 · 17 years ago
- d478990 Don't stop translation for mtc0 compare by aurel32 · 17 years ago
- 3945462 Simplify mips branch handling. Retire T2 from use. Use TCG for branches. by ths · 17 years ago
- d2856f1 Factorize code in translate.c by aurel32 · 17 years ago
- ca10f86 Remove osdep.c/qemu-img code duplication by aurel32 · 17 years ago
- d0dc7dc Make MIPS MT implementation more cache friendly. by ths · 17 years ago
- 57fec1f use the TCG code generator by bellard · 17 years ago
- b8aa459 MIPS COP1X (and related) instructions, by Richard Sandiford. by ths · 17 years ago
- e9c71dd Support for VR5432, and some of its special instructions. Original patch by ths · 17 years ago
- b352fa4 Update debug code to match new accumulator register layout. by ths · 17 years ago
- 01ba981 Handle cpu_model in copy_cpu(), by Kirill A. Shutemov. by ths · 17 years ago
- ae2dbf7 Micro-optimize back-to-back store-load sequences. by ths · 17 years ago
- 185f076 Optimize the conventional move operation. by ths · 17 years ago
- c6d6dd7 Fix MIPS64 R2 instructions. by ths · 17 years ago
- aaed909 added cpu_model parameter to cpu_init() by bellard · 17 years ago
- d26bc21 Clean out the N32 macros from target-mips, and introduce MIPS ABI specific by ths · 17 years ago
- 855cea8 Formatting fix. by ths · 17 years ago
- 623a930 Implement missing MIPS supervisor mode bits. by ths · 17 years ago
- 9f77c1c Remove bogus instruction decode. by ths · 17 years ago
- 7385ac0 Use the standard ASE check for MIPS-3D and MT. by ths · 17 years ago
- d8a5950 Switch bc1any* instructions off if no MIPS-3D is implemented. by ths · 17 years ago
- aa34373 Use always_inline in the MIPS support where applicable. by ths · 17 years ago
- 4e9f853 Fix [ls][wd][lr] instructions, by Aurelien Jarno. by ths · 17 years ago
- 540635b Code provision for n32/n64 mips userland emulation. Not functional yet. by ths · 17 years ago
- fe25323 Wrap a few often used tests with unlikely(), by Aurelien Jarno. by ths · 17 years ago
- 387a8fe Optimise instructions accessing CP0, by Aurelien Jarno. by ths · 17 years ago
- e189e74 Per-CPU instruction decoding implementation, by Aurelien Jarno. by ths · 17 years ago
- c068688 Extend TB flags to 64 bits (Alexander Graf). by j_mayer · 17 years ago
- 3b46e62 find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex. by ths · 17 years ago
- 5fafdf2 find -type f | xargs sed -i 's/[\t ]$//g' # on most files by ths · 17 years ago
- ce62e5b Fix tb->size mishandling, by Daniel Jacobowitz. by ths · 17 years ago
- ead9360 Partial support for 34K multithreading, not functional yet. by ths · 17 years ago
- 3ddf0b5 Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno. by ths · 18 years ago
- 8dfdb87 Implement recip1/recip2/rsqrt1/rsqrt2. by ths · 18 years ago
- 3a95e3a Check for R2 instructions, and throw RI if we don't emulate R2. by ths · 18 years ago
- 8487327 Make sure hflags are updated for CP0_Status changes. by ths · 18 years ago
- 278d070 Simplify code. by ths · 18 years ago
- 5e75551 Don't check the FPU state for each FPU instruction, use hflags to by ths · 18 years ago
- 6e47312 Handle PX/UX status flags correctly, by Aurelien Jarno. by ths · 18 years ago
- 9b9e439 MIPS64 addressing fixes, by Aurelien Jarno. by ths · 18 years ago
- fd88b6a The 24k wants more watch and srsmap registers. by ths · 18 years ago
- df1561e The previous patch to make breakpoints work was a performance by ths · 18 years ago
- 3a5b360 Catch more MIPS FPU cornercases, fix addr.ps and mulr.ps instructions. by ths · 18 years ago
- 93b12cc Fix indexed FP load/store instructions. by ths · 18 years ago
- 57fa1fb More MIPS 64-bit FPU support. by ths · 18 years ago
- f469b9d Fix slti/sltiu for MIPS64, by Aurelien Jarno. by ths · 18 years ago
- 5d46d55 Fix ldl/ldr implementation, by Aurelien Jarno. by ths · 18 years ago
- fd4a04e - Move FPU exception handling into helper functions, since they are big. by ths · 18 years ago
- 34ae7b5 Work around the lack of proper handling for self-modifying code. by ths · 18 years ago
- f1b0aa5 Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno. by ths · 18 years ago
- 703eaf3 Don't decode CP0 XContext on 32bit MIPS. by ths · 18 years ago
- 29929e3 MIPS TLB style selection at runtime, by Herve Poussineau. by ths · 18 years ago
- 5a1e8ff Implemented cabs FP instructions, and improve exception handling for by ths · 18 years ago
- 287c4b8 Another bit of nicer debug output. by ths · 18 years ago
- fbcc682 Implement FP madd/msub, wire up bc1any[24][ft]. by ths · 18 years ago
- 923617a Improved debug output for the MIPS opcode decoder. by ths · 18 years ago
- beebb57 Fix for the scd instruction, by Aurelien Jarno. by ths · 18 years ago
- a6763a5 Fix MIPS64 address computation specialcase, by Aurelien Jarno. by ths · 18 years ago
- 5a5012e MIPS 64-bit FPU support, plus some collateral bugfixes in the by ths · 18 years ago
- d692930 Next attempt to get the lui sign extension right. by ths · 18 years ago
- 7bc4506 Fix lui sign extension. by ths · 18 years ago
- fcb4a41 Choose number of TLBs at runtime, by Herve Poussineau. by ths · 18 years ago
- 9898128 Simplify branch likely handling. by ths · 18 years ago
- 171b31e Don't use T2 for INS, it conflicts with branch delay slot handling. by ths · 18 years ago
- a85427b Small code generation optimization. by ths · 18 years ago
- 16c00cb Restart interrupts after an exception. by ths · 18 years ago
- 2f64454 Make SYNCI_Step and CCRes CPU-specific. by ths · 18 years ago
- b48cfdf Throw RI for invalid MFMC0-class instructions. Introduce optional by ths · 18 years ago
- 2423f66 Code formatting fix. by ths · 18 years ago
- 534ce69 More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may by ths · 18 years ago
- c090a8f Fix CP0_IntCtl handling. by ths · 18 years ago
- 4e7a4a4 Mark watchpoint features as unimplemented. by ths · 18 years ago
- 62c5609 Catch unaligned sc/scd. by ths · 18 years ago
- 97428a4 Fix exception handling cornercase for rdhwr. by ths · 18 years ago
- dac9321 Remove bogus mtc0 handling. by ths · 18 years ago
- e0c84da Implement prefx. by ths · 18 years ago
- cbeb085 Set proper BadVAddress value for unaligned instruction fetch. by ths · 18 years ago
- e04bcc6 Actually skip over delay slot for a non-taken branch likely. by ths · 18 years ago
- f41c52f Save state for all CP0 instructions, they may throw a CPU exception. by ths · 18 years ago
- c53f4a6 fix branch delay slot cornercases. by ths · 18 years ago
- 5a63bcb Fix rotr immediate ops, mask shift/rotate arguments to their allowed size. by ths · 18 years ago
- 1579a72 Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise by ths · 18 years ago
- 876d4b0 Fix code formatting. by ths · 18 years ago
- 3812154 MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers by ths · 18 years ago
- 60aa19a Actually enable 64bit configuration. by ths · 18 years ago
- 24c7b0e Sanitize mips exception handling. by ths · 18 years ago
- e397ee3 Fix enough FPU/R2 support to get 24Kf going. by ths · 18 years ago
- 3953d78 Move mips CPU specific initialization to translate_init.c. by ths · 18 years ago
- 3ad4bb2 Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil. by ths · 18 years ago
- 820e00f Define gen_intermediate_code_internal as "static inline". by ths · 18 years ago
- 33d68b5 MIPS -cpu selection support, by Herve Poussineau. by ths · 18 years ago
- 6f5b89a MIPS Userland TLS register emulation, by Daniel Jacobowitz. by ths · 18 years ago
- 36d2395 MIPS FPU dynamic activation, part 1, by Herve Poussineau. by ths · 18 years ago
- 00a709c Fix mips FPU emulation, 32 bit data types are allowed to use odd registers. by ths · 18 years ago
- 3594c77 Replace TLSZ with TARGET_FMT_lx. by ths · 18 years ago