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qemu / qemu / 77f193daa80a097a892c5c86e6038de9ffe59938 / target-mips / translate.c
  1. 1ffc346 Be more economical with local temporaries. by ths · 17 years ago
  2. aaa9128 Convert some MIPS load/store instructions to TCG. by ths · 17 years ago
  3. 958fb4a Use TCG for MIPS GPR moves. by ths · 17 years ago
  4. b7ef7bf Fix MIPS64 branches. Funny how this survived testing. by ths · 17 years ago
  5. 4586f9e Really really revert commit r4343 by aurel32 · 17 years ago
  6. e34d2d6 Really revert commit r4343 by aurel32 · 17 years ago
  7. d478990 Don't stop translation for mtc0 compare by aurel32 · 17 years ago
  8. 3945462 Simplify mips branch handling. Retire T2 from use. Use TCG for branches. by ths · 17 years ago
  9. d2856f1 Factorize code in translate.c by aurel32 · 17 years ago
  10. ca10f86 Remove osdep.c/qemu-img code duplication by aurel32 · 17 years ago
  11. d0dc7dc Make MIPS MT implementation more cache friendly. by ths · 17 years ago
  12. 57fec1f use the TCG code generator by bellard · 17 years ago
  13. b8aa459 MIPS COP1X (and related) instructions, by Richard Sandiford. by ths · 17 years ago
  14. e9c71dd Support for VR5432, and some of its special instructions. Original patch by ths · 17 years ago
  15. b352fa4 Update debug code to match new accumulator register layout. by ths · 17 years ago
  16. 01ba981 Handle cpu_model in copy_cpu(), by Kirill A. Shutemov. by ths · 17 years ago
  17. ae2dbf7 Micro-optimize back-to-back store-load sequences. by ths · 17 years ago
  18. 185f076 Optimize the conventional move operation. by ths · 17 years ago
  19. c6d6dd7 Fix MIPS64 R2 instructions. by ths · 17 years ago
  20. aaed909 added cpu_model parameter to cpu_init() by bellard · 17 years ago
  21. d26bc21 Clean out the N32 macros from target-mips, and introduce MIPS ABI specific by ths · 17 years ago
  22. 855cea8 Formatting fix. by ths · 17 years ago
  23. 623a930 Implement missing MIPS supervisor mode bits. by ths · 17 years ago
  24. 9f77c1c Remove bogus instruction decode. by ths · 17 years ago
  25. 7385ac0 Use the standard ASE check for MIPS-3D and MT. by ths · 17 years ago
  26. d8a5950 Switch bc1any* instructions off if no MIPS-3D is implemented. by ths · 17 years ago
  27. aa34373 Use always_inline in the MIPS support where applicable. by ths · 17 years ago
  28. 4e9f853 Fix [ls][wd][lr] instructions, by Aurelien Jarno. by ths · 17 years ago
  29. 540635b Code provision for n32/n64 mips userland emulation. Not functional yet. by ths · 17 years ago
  30. fe25323 Wrap a few often used tests with unlikely(), by Aurelien Jarno. by ths · 17 years ago
  31. 387a8fe Optimise instructions accessing CP0, by Aurelien Jarno. by ths · 17 years ago
  32. e189e74 Per-CPU instruction decoding implementation, by Aurelien Jarno. by ths · 17 years ago
  33. c068688 Extend TB flags to 64 bits (Alexander Graf). by j_mayer · 17 years ago
  34. 3b46e62 find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex. by ths · 17 years ago
  35. 5fafdf2 find -type f | xargs sed -i 's/[\t ]$//g' # on most files by ths · 17 years ago
  36. ce62e5b Fix tb->size mishandling, by Daniel Jacobowitz. by ths · 17 years ago
  37. ead9360 Partial support for 34K multithreading, not functional yet. by ths · 17 years ago
  38. 3ddf0b5 Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno. by ths · 18 years ago
  39. 8dfdb87 Implement recip1/recip2/rsqrt1/rsqrt2. by ths · 18 years ago
  40. 3a95e3a Check for R2 instructions, and throw RI if we don't emulate R2. by ths · 18 years ago
  41. 8487327 Make sure hflags are updated for CP0_Status changes. by ths · 18 years ago
  42. 278d070 Simplify code. by ths · 18 years ago
  43. 5e75551 Don't check the FPU state for each FPU instruction, use hflags to by ths · 18 years ago
  44. 6e47312 Handle PX/UX status flags correctly, by Aurelien Jarno. by ths · 18 years ago
  45. 9b9e439 MIPS64 addressing fixes, by Aurelien Jarno. by ths · 18 years ago
  46. fd88b6a The 24k wants more watch and srsmap registers. by ths · 18 years ago
  47. df1561e The previous patch to make breakpoints work was a performance by ths · 18 years ago
  48. 3a5b360 Catch more MIPS FPU cornercases, fix addr.ps and mulr.ps instructions. by ths · 18 years ago
  49. 93b12cc Fix indexed FP load/store instructions. by ths · 18 years ago
  50. 57fa1fb More MIPS 64-bit FPU support. by ths · 18 years ago
  51. f469b9d Fix slti/sltiu for MIPS64, by Aurelien Jarno. by ths · 18 years ago
  52. 5d46d55 Fix ldl/ldr implementation, by Aurelien Jarno. by ths · 18 years ago
  53. fd4a04e - Move FPU exception handling into helper functions, since they are big. by ths · 18 years ago
  54. 34ae7b5 Work around the lack of proper handling for self-modifying code. by ths · 18 years ago
  55. f1b0aa5 Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno. by ths · 18 years ago
  56. 703eaf3 Don't decode CP0 XContext on 32bit MIPS. by ths · 18 years ago
  57. 29929e3 MIPS TLB style selection at runtime, by Herve Poussineau. by ths · 18 years ago
  58. 5a1e8ff Implemented cabs FP instructions, and improve exception handling for by ths · 18 years ago
  59. 287c4b8 Another bit of nicer debug output. by ths · 18 years ago
  60. fbcc682 Implement FP madd/msub, wire up bc1any[24][ft]. by ths · 18 years ago
  61. 923617a Improved debug output for the MIPS opcode decoder. by ths · 18 years ago
  62. beebb57 Fix for the scd instruction, by Aurelien Jarno. by ths · 18 years ago
  63. a6763a5 Fix MIPS64 address computation specialcase, by Aurelien Jarno. by ths · 18 years ago
  64. 5a5012e MIPS 64-bit FPU support, plus some collateral bugfixes in the by ths · 18 years ago
  65. d692930 Next attempt to get the lui sign extension right. by ths · 18 years ago
  66. 7bc4506 Fix lui sign extension. by ths · 18 years ago
  67. fcb4a41 Choose number of TLBs at runtime, by Herve Poussineau. by ths · 18 years ago
  68. 9898128 Simplify branch likely handling. by ths · 18 years ago
  69. 171b31e Don't use T2 for INS, it conflicts with branch delay slot handling. by ths · 18 years ago
  70. a85427b Small code generation optimization. by ths · 18 years ago
  71. 16c00cb Restart interrupts after an exception. by ths · 18 years ago
  72. 2f64454 Make SYNCI_Step and CCRes CPU-specific. by ths · 18 years ago
  73. b48cfdf Throw RI for invalid MFMC0-class instructions. Introduce optional by ths · 18 years ago
  74. 2423f66 Code formatting fix. by ths · 18 years ago
  75. 534ce69 More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may by ths · 18 years ago
  76. c090a8f Fix CP0_IntCtl handling. by ths · 18 years ago
  77. 4e7a4a4 Mark watchpoint features as unimplemented. by ths · 18 years ago
  78. 62c5609 Catch unaligned sc/scd. by ths · 18 years ago
  79. 97428a4 Fix exception handling cornercase for rdhwr. by ths · 18 years ago
  80. dac9321 Remove bogus mtc0 handling. by ths · 18 years ago
  81. e0c84da Implement prefx. by ths · 18 years ago
  82. cbeb085 Set proper BadVAddress value for unaligned instruction fetch. by ths · 18 years ago
  83. e04bcc6 Actually skip over delay slot for a non-taken branch likely. by ths · 18 years ago
  84. f41c52f Save state for all CP0 instructions, they may throw a CPU exception. by ths · 18 years ago
  85. c53f4a6 fix branch delay slot cornercases. by ths · 18 years ago
  86. 5a63bcb Fix rotr immediate ops, mask shift/rotate arguments to their allowed size. by ths · 18 years ago
  87. 1579a72 Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise by ths · 18 years ago
  88. 876d4b0 Fix code formatting. by ths · 18 years ago
  89. 3812154 MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers by ths · 18 years ago
  90. 60aa19a Actually enable 64bit configuration. by ths · 18 years ago
  91. 24c7b0e Sanitize mips exception handling. by ths · 18 years ago
  92. e397ee3 Fix enough FPU/R2 support to get 24Kf going. by ths · 18 years ago
  93. 3953d78 Move mips CPU specific initialization to translate_init.c. by ths · 18 years ago
  94. 3ad4bb2 Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil. by ths · 18 years ago
  95. 820e00f Define gen_intermediate_code_internal as "static inline". by ths · 18 years ago
  96. 33d68b5 MIPS -cpu selection support, by Herve Poussineau. by ths · 18 years ago
  97. 6f5b89a MIPS Userland TLS register emulation, by Daniel Jacobowitz. by ths · 18 years ago
  98. 36d2395 MIPS FPU dynamic activation, part 1, by Herve Poussineau. by ths · 18 years ago
  99. 00a709c Fix mips FPU emulation, 32 bit data types are allowed to use odd registers. by ths · 18 years ago
  100. 3594c77 Replace TLSZ with TARGET_FMT_lx. by ths · 18 years ago