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qemu / qemu / 6e7cd94462d65405037c993fc4401d6fceed6660 / target-arm / helper-a64.c
  1. b21ab1f target-arm: A64: Print ELR when taking exceptions by Soren Brinkmann · 10 years ago
  2. 012a906 target-arm: Update interrupt handling to use target EL by Greg Bellows · 10 years ago
  3. 7847f9e target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc) by Peter Maydell · 10 years ago
  4. ce02049 target-arm: Add 32/64-bit register sync by Greg Bellows · 10 years ago
  5. a8eb6e1 target-arm: Squash input denormals in FRECPS and FRSQRTS by Peter Maydell · 10 years ago
  6. dabf005 Fix FMULX not squashing denormalized inputs when FZ is set. by Xiangyu Hu · 10 years ago
  7. dcbff19 target-arm: rename arm_current_pl to arm_current_el by Greg Bellows · 10 years ago
  8. 9812860 target-arm: add emulation of PSCI calls for system emulation by Rob Herring · 10 years ago
  9. 0adf7d3 target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes by Rob Herring · 10 years ago
  10. 136e67e target-arm: Add support for VIRQ and VFIQ by Edgar E. Iglesias · 11 years ago
  11. e0d6e6a target-arm: A64: Emulate the SMC insn by Edgar E. Iglesias · 11 years ago
  12. 607d98b target-arm: Add a Hypervisor Trap exception type by Edgar E. Iglesias · 11 years ago
  13. 35979d7 target-arm: A64: Emulate the HVC insn by Edgar E. Iglesias · 11 years ago
  14. 2dd081a target-arm: A64: Correct updates to FAR and ESR on exceptions by Edgar E. Iglesias · 11 years ago
  15. 9e729b5 target-arm: A64: Refactor aarch64_cpu_do_interrupt by Edgar E. Iglesias · 11 years ago
  16. 2f0180c target-arm: Make far_el1 an array by Edgar E. Iglesias · 11 years ago
  17. f151b12 target-arm: A64: Respect SPSEL when taking exceptions by Edgar E. Iglesias · 11 years ago
  18. 130f2e7 target-arm: A64: Implement CRC instructions by Peter Maydell · 11 years ago
  19. 4e624ed target-arm: add support for v8 VMULL.P64 instruction by Peter Maydell · 11 years ago
  20. 2ef6175 tcg: Invert the inclusion of helper.h by Richard Henderson · 11 years ago
  21. 2a923c4 target-arm: A64: Introduce aarch64_banked_spsr_index() by Edgar E. Iglesias · 11 years ago
  22. 68fdb6c target-arm: c12_vbar -> vbar_el[] by Edgar E. Iglesias · 11 years ago
  23. d81c519 target-arm: Make esr_el1 an array by Edgar E. Iglesias · 11 years ago
  24. 6947f05 target-arm: Make elr_el1 an array by Edgar E. Iglesias · 11 years ago
  25. 52e60cd target-arm: Implement AArch64 EL1 exception handling by Rob Herring · 11 years ago
  26. 5553955 target-arm: A64: Implement FCVTXN by Peter Maydell · 11 years ago
  27. 8f0c675 target-arm: A64: Add FRECPX (reciprocal exponent) by Alex Bennée · 11 years ago
  28. 6781fa1 target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP by Peter Maydell · 11 years ago
  29. b05c306 target-arm: A64: Add remaining CLS/Z vector ops by Alex Bennée · 11 years ago
  30. a984e42 target-arm: A64: Implement PMULL instruction by Peter Maydell · 11 years ago
  31. 057d5f6 target-arm: A64: Implement remaining 3-same instructions by Peter Maydell · 11 years ago
  32. 8908f4d target-arm: A64: Implement SIMD FP compare and set insns by Alex Bennée · 11 years ago
  33. f5e51e7 target-arm: A64: Implement plain vector SIMD indexed element insns by Peter Maydell · 11 years ago
  34. 7c51048 target-arm: A64: Add SIMD TBL/TBLX by Michael Matz · 11 years ago
  35. da7dafe target-arm: A64: Add support for floating point compare by Claudio Fontana · 11 years ago
  36. e80c502 target-arm: A64: add support for 1-src CLS insn by Claudio Fontana · 11 years ago
  37. 82e14b0 target-arm: A64: add support for 1-src RBIT insn by Alexander Graf · 11 years ago
  38. 680ead2 target-arm: A64: add support for 1-src data processing and CLZ by Claudio Fontana · 11 years ago
  39. 8220e91 target-arm: A64: add support for 2-src data processing and DIV by Alexander Graf · 11 years ago
  40. d3e35a1 target-arm: A64: add stubs for a64 specific helpers by Alexander Graf · 11 years ago