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qemu / qemu / 69e87b32680a41d9761191443587c595b6f5fc3f / target-arm / cpu64.c
  1. da34e65 include/qemu/osdep.h: Don't include qapi/error.h by Markus Armbruster · 9 years ago
  2. 4054bfa target-arm: Add the pmceid0 and pmceid1 registers by Alistair Francis · 9 years ago
  3. 3ad901b target-arm: Enable EL3 for Cortex-A53 and Cortex-A57 by Peter Maydell · 9 years ago
  4. b3820e6 gdb: provide the name of the architecture in the target.xml by David Hildenbrand · 9 years ago
  5. 966f758 target-arm: Use a single entry point for AArch64 and AArch32 exceptions by Peter Maydell · 9 years ago
  6. 74c21bd target-arm: Clean up includes by Peter Maydell · 9 years ago
  7. 13b72b2 target-arm: Fix REVIDR reset value by Sergey Fedorov · 10 years ago
  8. 7525465 target-arm/kvm64: Add cortex-a53 cpu support by Shannon Zhao · 10 years ago
  9. e353102 target-arm: cpu64: Add support for Cortex-A53 by Peter Crosthwaite · 10 years ago
  10. ee80426 target-arm: cpu64: generalise name of A57 regs by Peter Crosthwaite · 10 years ago
  11. 0458b7b target-arm: Add missing compatible property to A57 by Ryota Ozaki · 10 years ago
  12. fb8d6c2 target-arm: Add CPU property to disable AArch64 by Greg Bellows · 10 years ago
  13. 0e7b176 target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" by Peter Maydell · 10 years ago
  14. 0adf7d3 target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes by Rob Herring · 10 years ago
  15. e892571 target-arm: Use cpu_exec_interrupt qom hook by Richard Henderson · 10 years ago
  16. c379621 target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values by Peter Maydell · 11 years ago
  17. 48eb3ae target-arm: Adjust debug ID registers per-CPU by Peter Maydell · 11 years ago
  18. da5141f target-arm: VFPv4 implies half-precision extension by Peter Maydell · 11 years ago
  19. 25f748e target-arm: Clean up handling of ARMv8 optional feature bits by Peter Maydell · 11 years ago
  20. fb8ad9f target-arm: Remove unnecessary setting of feature bits by Peter Maydell · 11 years ago
  21. bf01601 target-arm/cpu64.c: Actually register Cortex-A57 impdef registers by Peter Maydell · 11 years ago
  22. 1773111 target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 by Peter Maydell · 11 years ago
  23. 7633378 target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc by Peter Maydell · 11 years ago
  24. f318cec target-arm: Implement CBAR for Cortex-A57 by Peter Maydell · 11 years ago
  25. 377a44e target-arm: Implement Cortex-A57 implementation-defined system registers by Peter Maydell · 11 years ago
  26. 85acfa9 target-arm: Remove THUMB2EE feature from AArch64 'any' CPU by Peter Maydell · 11 years ago
  27. cb1fa94 target-arm: Add Cortex-A57 processor by Peter Maydell · 11 years ago
  28. 52e60cd target-arm: Implement AArch64 EL1 exception handling by Rob Herring · 11 years ago
  29. aca3f40 target-arm: A64: Implement DC ZVA by Peter Maydell · 11 years ago
  30. 7da845b target-arm: A64: Make cache ID registers visible to AArch64 by Peter Maydell · 11 years ago
  31. 83e6813 target-arm: Switch ARMCPUInfo arrays to use terminator entries by Peter Maydell · 11 years ago
  32. 7b1aa02 target-arm: fix build with gcc 4.8.2 by Michael S. Tsirkin · 11 years ago
  33. 5ce4f35 target-arm: A64: add set_pc cpu method by Alexander Graf · 11 years ago
  34. 96c0421 target-arm: Add AArch64 gdbstub support by Alexander Graf · 11 years ago
  35. 14ade10 target-arm: Add AArch64 translation stub by Alexander Graf · 11 years ago
  36. d14d42f target-arm: Add new AArch64CPUInfo base class and subclasses by Peter Maydell · 11 years ago