1. b7e516c Kill off cpu_state_reset() by Andreas Färber · 13 years ago
  2. 30bf942 target-mips: Let cpu_mips_init() return MIPSCPU by Andreas Färber · 13 years ago
  3. bed38e4 target-mips: Remove commented-out function declaration by Andreas Färber · 13 years ago
  4. 61d25e1 Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpu by Blue Swirl · 13 years ago
  5. 0f71a70 target-mips: QOM'ify CPU by Andreas Färber · 13 years ago
  6. dda3c2e target-mips: Move definition of uint_fast{8, 16}_t to osdep.h by Andreas Färber · 13 years ago
  7. 5cbdb3a Replace Qemu by QEMU in comments by Stefan Weil · 13 years ago
  8. 9349b4f Rename CPUState -> CPUArchState by Andreas Färber · 13 years ago
  9. 7db13fa target-mips: Don't overuse CPUState by Andreas Färber · 13 years ago
  10. 4abf79a fix spelling in target sub directory by Dong Xu Wang · 13 years ago
  11. 344eecf mips: Support the MT TCStatus IXMT irq disable flag by Edgar E. Iglesias · 14 years ago
  12. f249412 mips: Add MT halting and waking of VPEs by Edgar E. Iglesias · 14 years ago
  13. 97b348e Remove unused is_softmmu parameter from cpu_handle_mmu_fault by Blue Swirl · 14 years ago
  14. 3e45717 exec.h cleanup by Blue Swirl · 14 years ago
  15. b14ef7c Fix unassigned memory access handling by Blue Swirl · 14 years ago
  16. f081c76 Move cpu_has_work and cpu_pc_from_tb to cpu.h by Blue Swirl · 14 years ago
  17. 4ff9786 Fix trivial "endianness bugs" by Stefan Weil · 14 years ago
  18. 4cdc1cd target-mips: fix host CPU consumption when guest is idle by Aurelien Jarno · 14 years ago
  19. 9a78eea target-xxx: Use fprintf_function (format checking) by Stefan Weil · 14 years ago
  20. 138afb0 mips: Add support for VInt and VEIC irq modes by Edgar E. Iglesias · 15 years ago
  21. 5dc5d9f mips: more fixes to the MIPS interrupt glue logic by Aurelien Jarno · 15 years ago
  22. 3638831 mips: Correct MIPS interrupt glue logic for icount by Edgar E. Iglesias · 15 years ago
  23. a88790a remove exec-all.h inclusion from cpu.h by Paolo Bonzini · 15 years ago
  24. 10eb0cc move cpu_pc_from_tb to target-*/exec.h by Paolo Bonzini · 15 years ago
  25. bbfa8f7 target-mips: add microMIPS exception handler support by Nathan Froyd · 15 years ago
  26. 3c7b48b Target specific usermode cleanup by Paul Brook · 15 years ago
  27. c36bbb2 target-mips: don't call cpu_loop_exit() from helper.c by Aurelien Jarno · 15 years ago
  28. 79ef2c4 target-mips: add new HFLAGs for JALX and 16/32-bit delay slots by Nathan Froyd · 15 years ago
  29. 25b91e3 target-mips: add a function to do virtual -> physical translations by Aurelien Jarno · 15 years ago
  30. 60c9af0 target-mips: fix physical address type in MMU functions by Aurelien Jarno · 15 years ago
  31. 2a6e32d target-mips: make CP0_LLAddr register CPU dependent by Aurelien Jarno · 15 years ago
  32. 5499b6f target-mips: rename CP0_LLAddr into lladdr by Aurelien Jarno · 15 years ago
  33. 51cc2e7 mips: fix cpu_reset memory leak by Blue Swirl · 15 years ago
  34. c227f09 Revert "Get rid of _t suffix" by Anthony Liguori · 15 years ago
  35. 99a0949 Get rid of _t suffix by malc · 15 years ago
  36. 0b5c1ce cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal by Nathan Froyd · 16 years ago
  37. e2542fe rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN by Juan Quintela · 16 years ago
  38. dfe5fff change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION} by Juan Quintela · 16 years ago
  39. 590bc60 MIPS atomic instructions by Paul Brook · 16 years ago
  40. ff867dd MIPS usermode TLS register by Paul Brook · 16 years ago
  41. 1ba74fb target-mips: optimize gen_compute_branch() by aurel32 · 16 years ago
  42. c01fccd target-mips: rename helpers from do_ to helper_ by aurel32 · 16 years ago
  43. c276471 The _exit syscall is used for both thread termination in NPTL applications, by pbrook · 16 years ago
  44. f9480ff Fix remaining compiler warnings for mips targets. by ths · 16 years ago
  45. 6b91754 Refactor translation block CPU state handling (Jan Kiszka) by aliguori · 16 years ago
  46. 622ed36 Convert CPU_PC_FROM_TB to static inline (Jan Kiszka) by aliguori · 16 years ago
  47. 2623c1e target-mips: optimize gen_op_addr_add() (2/2) by aurel32 · 16 years ago
  48. e18231a Show size for unassigned accesses (Robert Reif) by blueswir1 · 16 years ago
  49. f01be15 Move the active FPU registers into env again, and use more TCG registers by ths · 16 years ago
  50. 0eaef5a Less hardcoding of TARGET_USER_ONLY. by ths · 17 years ago
  51. b6d96be Use temporary registers for the MIPS FPU emulation. by ths · 17 years ago
  52. 9656f32 Move interrupt_request and user_mode_only to common cpu state. by pbrook · 17 years ago
  53. b3c7724 Move CPU save/load registration to common code. by pbrook · 17 years ago
  54. 2e70f6e Add instruction counter. by pbrook · 17 years ago
  55. b5dc773 More efficient target register / TC accesses. by ths · 17 years ago
  56. 1a3fd9c Remove remaining uses of T0 in the MIPS target. by ths · 17 years ago
  57. e1bf387 T1 is now dead. by ths · 17 years ago
  58. 764dfc3 Move FP TNs to cpu env. by ths · 17 years ago
  59. f8ed707 Fix typo. by pbrook · 17 years ago
  60. 6e68e07 Move clone() register setup to target specific code. Handle fork-like clone. by pbrook · 17 years ago
  61. 9133e39 Push common interrupt variables to cpu-defs.h (Glauber Costa) by bellard · 17 years ago
  62. ce5232c moved halted field to CPU_COMMON by bellard · 17 years ago
  63. 893f986 Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford. by ths · 17 years ago
  64. 958fb4a Use TCG for MIPS GPR moves. by ths · 17 years ago
  65. 3945462 Simplify mips branch handling. Retire T2 from use. Use TCG for branches. by ths · 17 years ago
  66. d0dc7dc Make MIPS MT implementation more cache friendly. by ths · 17 years ago
  67. b8aa459 MIPS COP1X (and related) instructions, by Richard Sandiford. by ths · 17 years ago
  68. 14e51cc De-cruft exception definitions, and implement nicer debug output. by ths · 17 years ago
  69. 6d35524 Improved PABITS handling, and config register fixes. by ths · 17 years ago
  70. aaed909 added cpu_model parameter to cpu_init() by bellard · 17 years ago
  71. 7df526e Move kernel loader parameters from the cpu state to being board specific. by ths · 17 years ago
  72. 623a930 Implement missing MIPS supervisor mode bits. by ths · 17 years ago
  73. 647de6c Handle IBE on MIPS properly. by ths · 17 years ago
  74. 6ebbf39 Replace is_user variable with mmu_idx in softmmu core, by j_mayer · 17 years ago
  75. c732abe Unify '-cpu ?' option. by j_mayer · 17 years ago
  76. 198a74d Move get_sp_from_cpustate from cpu.h to target_signal.h. by ths · 17 years ago
  77. a04e134 linux-user sigaltstack() syscall, by Thayne Harbaugh. by ths · 17 years ago
  78. 387a8fe Optimise instructions accessing CP0, by Aurelien Jarno. by ths · 17 years ago
  79. e189e74 Per-CPU instruction decoding implementation, by Aurelien Jarno. by ths · 17 years ago
  80. ead9360 Partial support for 34K multithreading, not functional yet. by ths · 17 years ago
  81. e034e2c Handle MIPS64 SEGBITS value correctly. by ths · 18 years ago
  82. 9467d44 Move target-specific defines to the target directories. by ths · 18 years ago
  83. 33ac7f1 Don't kill the registered irqs on reset. by ths · 18 years ago
  84. 51b2772 Fix CPU (re-)selection on reset. by ths · 18 years ago
  85. 78749ba Fix usermode check, thanks Aurelien Jarno. by ths · 18 years ago
  86. 5e75551 Don't check the FPU state for each FPU instruction, use hflags to by ths · 18 years ago
  87. 6e47312 Handle PX/UX status flags correctly, by Aurelien Jarno. by ths · 18 years ago
  88. fd88b6a The 24k wants more watch and srsmap registers. by ths · 18 years ago
  89. fd4a04e - Move FPU exception handling into helper functions, since they are big. by ths · 18 years ago
  90. 388bb21 MIPS linux-user update. by ths · 18 years ago
  91. 29929e3 MIPS TLB style selection at runtime, by Herve Poussineau. by ths · 18 years ago
  92. 5a5012e MIPS 64-bit FPU support, plus some collateral bugfixes in the by ths · 18 years ago
  93. fcb4a41 Choose number of TLBs at runtime, by Herve Poussineau. by ths · 18 years ago
  94. d537cf6 Unify IRQ handling. by pbrook · 18 years ago
  95. f7cfb2a 64bit MIPS FPUs have 32 registers. by ths · 18 years ago
  96. 36bb244 Fix typo, suggested by Ben Taylor. by ths · 18 years ago
  97. 24c7b0e Sanitize mips exception handling. by ths · 18 years ago
  98. e397ee3 Fix enough FPU/R2 support to get 24Kf going. by ths · 18 years ago
  99. 33d68b5 MIPS -cpu selection support, by Herve Poussineau. by ths · 18 years ago
  100. 6f5b89a MIPS Userland TLS register emulation, by Daniel Jacobowitz. by ths · 18 years ago