- bebe80f target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode by Bastian Koppelmann · 10 years ago
- b00aa8e target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode by Bastian Koppelmann · 10 years ago
- 2e430e1 target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode by Bastian Koppelmann · 10 years ago
- 2984cfb target-tricore: Add instructions of RRR2 opcode format by Bastian Koppelmann · 10 years ago
- 3debbb5 target-tricore: fix msub32_suov return wrong results by Bastian Koppelmann · 10 years ago
- f0cab01 target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper by Bastian Koppelmann · 10 years ago
- fe700ad tcg: Introduce tcg_op_buf_count and tcg_op_buf_full by Richard Henderson · 11 years ago
- 0a7df5d tcg: Move emit of INDEX_op_end into gen_tb_end by Richard Henderson · 11 years ago
- 0953225 target-tricore: Add instructions of RRR opcode format by Bastian Koppelmann · 10 years ago
- 8fb9d0e target-tricore: Add instructions of RRPW opcode format by Bastian Koppelmann · 10 years ago
- 12f323e target-tricore: Add instructions of RR2 opcode format by Bastian Koppelmann · 10 years ago
- f1cc6ea target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode by Bastian Koppelmann · 10 years ago
- 85d604a target-tricore: split up suov32 into suov32_pos and suov32_neg by Bastian Koppelmann · 10 years ago
- 40a1f64 target-tricore: Fix bugs found by coverity by Bastian Koppelmann · 10 years ago
- 811ea60 target-tricore: calculate av bits before saturation by Bastian Koppelmann · 10 years ago
- 5f30046 target-tricore: Several translator and cpu model fixes by Bastian Koppelmann · 10 years ago
- 452e3d4 target-tricore: Add missing ULL suffix on 64 bit constant by Peter Maydell · 10 years ago
- 3709741 target-tricore: Fix new typos by Stefan Weil · 10 years ago
- a4ba200 Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging by Peter Maydell · 10 years ago
- cd42d5b gen-icount: check cflags instead of use_icount global by Paolo Bonzini · 10 years ago
- 9655b93 target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode by Bastian Koppelmann · 10 years ago
- 436d63f target-tricore: Fix MFCR/MTCR insn and B format offset. by Bastian Koppelmann · 10 years ago
- b5fd8fa target-tricore: Add missing 1.6 insn of BOL opcode format by Bastian Koppelmann · 10 years ago
- e2bed10 target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode by Bastian Koppelmann · 10 years ago
- f2f1585 target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode by Bastian Koppelmann · 10 years ago
- 0b79a78 target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode by Bastian Koppelmann · 10 years ago
- d5de783 target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode by Bastian Koppelmann · 10 years ago
- e4e3917 target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 by Bastian Koppelmann · 10 years ago
- 7f13420 target-tricore: Fix mask handling JNZ.T being 7 bit long by Bastian Koppelmann · 10 years ago
- 45820fc target-tricore: pretty-print register dump and show more status registers by Alex Zuepke · 10 years ago
- 4b5b443 target-tricore: add missing 64-bit MOV in RLC format by Alex Zuepke · 10 years ago
- af715d9 target-tricore: typo in BOL format by Alex Zuepke · 10 years ago
- 781b717 target-tricore: fix offset masking in BOL format by Alex Zuepke · 10 years ago
- 328f1f0 target-tricore: Add instructions of RCR opcode format by Bastian Koppelmann · 10 years ago
- 2b2f7d9 target-tricore: Add instructions of RLC opcode format by Bastian Koppelmann · 10 years ago
- ed51626 target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format by Bastian Koppelmann · 10 years ago
- 47e0443 target-tricore: Make TRICORE_FEATURES implying others. by Bastian Koppelmann · 10 years ago
- 0974257 target-tricore: Add instructions of RC opcode format by Bastian Koppelmann · 10 years ago
- a68e0d5 target-tricore: Add instructions of BRR opcode format by Bastian Koppelmann · 10 years ago
- 83c1bb1 target-tricore: Add instructions of BRN opcode format by Bastian Koppelmann · 10 years ago
- fc2ef4a target-tricore: Add instructions of BRC opcode format by Bastian Koppelmann · 10 years ago
- 3fb763c target-tricore: Add instructions of BOL opcode format by Bastian Koppelmann · 10 years ago
- 3a16ecb target-tricore: Add instructions of BO opcode format by Bastian Koppelmann · 10 years ago
- b74f2b5 target-tricore: Add instructions of BIT opcode format by Bastian Koppelmann · 10 years ago
- f718b0b target-tricore: Add instructions of B opcode format by Bastian Koppelmann · 10 years ago
- 59543d4 target-tricore: Add instructions of ABS, ABSB opcode format by Bastian Koppelmann · 10 years ago
- 030c58d target-tricore: Cleanup and Bugfixes by Bastian Koppelmann · 10 years ago
- dfdb483 target-tricore: Remove the dummy interrupt boilerplate by Richard Henderson · 10 years ago
- 44ea343 target-tricore: Add instructions of SR opcode format by Bastian Koppelmann · 11 years ago
- 5a7634a target-tricore: Add instructions of SLR, SSRO and SRO opcode format by Bastian Koppelmann · 11 years ago
- 5de9351 target-tricore: Add instructions of SC opcode format by Bastian Koppelmann · 11 years ago
- a47b50d target-tricore: Add instructions of SBR opcode format by Bastian Koppelmann · 11 years ago
- 70b0226 target-tricore: Add instructions of SBC and SBRN opcode format by Bastian Koppelmann · 11 years ago
- 9a31922 target-tricore: Add instructions of SB opcode format by Bastian Koppelmann · 11 years ago
- d279821 target-tricore: Add instructions of SRRS and SLRO opcode format by Bastian Koppelmann · 11 years ago
- 46aa848 target-tricore: Add instructions of SSR opcode format by Bastian Koppelmann · 11 years ago
- 2692802 target-tricore: Add instructions of SRR opcode format by Bastian Koppelmann · 11 years ago
- 0707ec1 target-tricore: Add instructions of SRC opcode format by Bastian Koppelmann · 11 years ago
- 7c87d07 target-tricore: Add masks and opcodes for decoding by Bastian Koppelmann · 11 years ago
- 0aaeb11 target-tricore: Add initialization for translation and activate target by Bastian Koppelmann · 11 years ago
- 2d30267 target-tricore: Add softmmu support by Bastian Koppelmann · 11 years ago
- 48e06fe target-tricore: Add target stubs and qom-cpu by Bastian Koppelmann · 11 years ago
