1. b90372a target-arm: Fix typos in comments by Peter Maydell · 12 years ago
  2. 6562674 arm: translate: comment typo - s/middel/middle/ by Peter A. G. Crosthwaite · 12 years ago
  3. 3dde962 target-arm: Add support for long format translation table walks by Peter Maydell · 12 years ago
  4. e42c4db target-arm: Implement TTBCR changes for LPAE by Peter Maydell · 12 years ago
  5. 702a935 target-arm: Implement long-descriptor PAR format by Peter Maydell · 12 years ago
  6. 77a71dd target-arm: Use target_phys_addr_t in get_phys_addr() by Peter Maydell · 12 years ago
  7. 891a2fe target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE by Peter Maydell · 12 years ago
  8. f9fc619 target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE by Peter Maydell · 12 years ago
  9. 7ac681c target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers by Peter Maydell · 12 years ago
  10. 918f5dc target-arm: Extend feature flags to 64 bits by Peter Maydell · 12 years ago
  11. de9b05b target-arm: Implement privileged-execute-never (PXN) by Peter Maydell · 12 years ago
  12. 3cc0cd6 ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits by Peter Maydell · 12 years ago
  13. ed33685 target-arm: Fix TCG temp handling in 64 bit cp writes by Peter Maydell · 12 years ago
  14. 091fd17 target-arm: Fix some copy-and-paste errors in cp register names by Peter Maydell · 12 years ago
  15. 81a60ad target-arm: Fix typo that meant TTBR1 accesses went to TTBR0 by Peter Maydell · 12 years ago
  16. 2bee510 target-arm: Fix CP15 based WFI by Paul Brook · 12 years ago
  17. b2d06f9 target-arm: Remove ARM_CPUID_* macros by Peter Maydell · 13 years ago
  18. 4a9a539 target-arm: Remove remaining old cp15 infrastructure by Peter Maydell · 13 years ago
  19. 30b05bb target-arm: Move block cache ops to new cp15 framework by Peter Maydell · 13 years ago
  20. b22af02 target-arm: Remove c0_cachetype CPUARMState field by Peter Maydell · 13 years ago
  21. 7884849 target-arm: Convert final ID registers by Peter Maydell · 13 years ago
  22. 81bdde9 target-arm: Convert MPIDR by Peter Maydell · 13 years ago
  23. 776d4e5 target-arm: Convert cp15 cache ID registers by Peter Maydell · 13 years ago
  24. 8515a09 target-arm: Convert cp15 crn=0 crm={1,2} feature registers by Peter Maydell · 13 years ago
  25. 2771db2 target-arm: Convert cp15 crn=1 registers by Peter Maydell · 13 years ago
  26. 34f9052 target-arm: Convert cp15 crn=9 registers by Peter Maydell · 13 years ago
  27. 06d76f3 target-arm: Convert cp15 crn=6 registers by Peter Maydell · 13 years ago
  28. c480421 target-arm: convert cp15 crn=7 registers by Peter Maydell · 13 years ago
  29. 4a50160 target-arm: Convert cp15 VA-PA translation registers by Peter Maydell · 13 years ago
  30. d929823 target-arm: Convert cp15 MMU TLB control by Peter Maydell · 13 years ago
  31. 1047b9d target-arm: Convert cp15 crn=15 registers by Peter Maydell · 13 years ago
  32. 4fdd17d target-arm: Convert cp15 crn=10 registers by Peter Maydell · 13 years ago
  33. 08de207 target-arm: Convert cp15 crn=13 registers by Peter Maydell · 13 years ago
  34. ecce5c3 target-arm: Convert cp15 crn=2 registers by Peter Maydell · 13 years ago
  35. 18032be target-arm: Convert MMU fault status cp15 registers by Peter Maydell · 13 years ago
  36. c983fe6 target-arm: Convert cp15 c3 register by Peter Maydell · 13 years ago
  37. 6cc7a3a target-arm: Convert generic timer cp15 regs by Peter Maydell · 13 years ago
  38. 200ac0e target-arm: Convert performance monitor registers by Peter Maydell · 13 years ago
  39. 4d31c59 target-arm: Convert TLS registers by Peter Maydell · 13 years ago
  40. 7d57f40 target-arm: Convert WFI/barriers special cases to cp_reginfo by Peter Maydell · 13 years ago
  41. c326b97 target-arm: Convert TEECR, TEEHBR to new scheme by Peter Maydell · 13 years ago
  42. e9aa6c2 target-arm: Convert debug registers to cp_reginfo by Peter Maydell · 13 years ago
  43. 2ceb98c target-arm: Add register_cp_regs_for_features() by Peter Maydell · 13 years ago
  44. e8070a2 target-arm: Remove old cpu_arm_set_cp_io infrastructure by Peter Maydell · 13 years ago
  45. 4b6a83f target-arm: initial coprocessor register framework by Peter Maydell · 13 years ago
  46. 200bf59 target-arm: Fix 11MPCore cache type register value by Peter Maydell · 13 years ago
  47. fbe37ef build: move other target-*/ objects to nested Makefile.objs by Paolo Bonzini · 13 years ago
  48. 9cdc8df build: move libobj-y variable to nested Makefile.objs by Paolo Bonzini · 13 years ago
  49. 5e8861a build: move obj-TARGET-y variables to nested Makefile.objs by Paolo Bonzini · 13 years ago
  50. b7e516c Kill off cpu_state_reset() by Andreas Färber · 13 years ago
  51. df90dad target-arm: Use cpu_reset() in cpu_arm_init() by Andreas Färber · 13 years ago
  52. ad37ad5 target-arm/cpu.h: Make cpu_init("nonexistent cpu") return NULL by Peter Maydell · 13 years ago
  53. 7e598de target-arm: When setting FPSCR.QC, don't clear other FPSCR bits by Matt Craighead · 13 years ago
  54. 10962fd target-arm: Make SETEND respect bswap_code (BE8) setting by Peter Maydell · 13 years ago
  55. c5fad12 target-arm: Move A9 config_base_address reset value to ARMCPU by Peter Maydell · 13 years ago
  56. 778c3a0 target-arm: Change cpu_arm_init() return type to ARMCPU by Andreas Färber · 13 years ago
  57. 3c30dd5 target-arm: Move reset handling to arm_cpu_reset by Peter Maydell · 13 years ago
  58. caa1d07 target-arm: Drop cpu_reset_model_id() by Peter Maydell · 13 years ago
  59. 85df378 target-arm: Move cache ID register setup to cpu specific init fns by Peter Maydell · 13 years ago
  60. 8092d2f target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset by Peter Maydell · 13 years ago
  61. 2e4d7e3 target-arm: Move feature register setup to per-CPU init fns by Peter Maydell · 13 years ago
  62. 0cc892f target-arm: Move iWMMXT wCID reset to cpu_state_reset by Peter Maydell · 13 years ago
  63. 4e851c3 target-arm: Drop JTAG_ID documentation by Peter Maydell · 13 years ago
  64. 0ca7e01 target-arm: Move SCTLR reset value setup to per cpu init fns by Peter Maydell · 13 years ago
  65. 64e1671 target-arm: Move CTR setup to per cpu init fns by Peter Maydell · 13 years ago
  66. bd35c35 target-arm: Move MVFR* setup to per cpu init fns by Peter Maydell · 13 years ago
  67. 325b3ce target-arm: Move FPSID config to cpu init fns by Peter Maydell · 13 years ago
  68. 581be09 target-arm: Move feature bit settings to CPU init fns by Peter Maydell · 13 years ago
  69. 777dc78 target-arm: Add QOM subclasses for each ARM cpu implementation by Peter Maydell · 13 years ago
  70. ce854d7 target-arm: remind to keep arm features in sync with linux-user/elfload.c by Benoit Canet · 13 years ago
  71. 2050396 Use uintptr_t for various op related functions by Blue Swirl · 13 years ago
  72. d8fd295 Userspace ARM BE8 support by Paul Brook · 13 years ago
  73. 06ed5d6 ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers. by Andrew Towers · 13 years ago
  74. dec9c2d target-arm: Minimalistic CPU QOM'ification by Andreas Färber · 13 years ago
  75. 0bcd08b target-arm: Drop cpu_arm_close() by Andreas Färber · 13 years ago
  76. d9e028c target-arm: Decode SETEND correctly in Thumb by Peter Maydell · 13 years ago
  77. c98d174 target-arm: Clear IT bits when taking exceptions in v7M by Peter Maydell · 13 years ago
  78. 4de4779 target-arm: Fix typo in ARM946 cp15 c5 handling by Peter Maydell · 13 years ago
  79. 9349b4f Rename CPUState -> CPUArchState by Andreas Färber · 13 years ago
  80. 0ecb72a target-arm: Don't overuse CPUState by Andreas Färber · 13 years ago
  81. 1bba0dc Rename cpu_reset() to cpu_state_reset() by Andreas Färber · 13 years ago
  82. 853bfcc target-arm: Clean includes by Stefan Weil · 13 years ago
  83. a84fac1 target-arm/helper.c: tb_flush() on CPU reset by Peter Maydell · 13 years ago
  84. 2d2624a target-arm/helper.c: Correct FPSID value for Cortex-A9 by Peter Maydell · 13 years ago
  85. 0b03bdf Add Cortex-A15 CPU definition by Peter Maydell · 13 years ago
  86. 0383ac0 Add dummy implementation of generic timer cp15 registers by Peter Maydell · 13 years ago
  87. 5fe9101 arm: store the config_base_register during cpu_reset by Mark Langsdorf · 13 years ago
  88. 8583697 target-arm/helper.c: Don't assume softfloat int32 is 32 bits only by Peter Maydell · 13 years ago
  89. dc8714c target-arm: Fix implementation of TLB invalidate operations by Peter Maydell · 13 years ago
  90. 2be2762 arm: Add dummy support for co-processor 15's secure config register by Rob Herring · 13 years ago
  91. d3cb6e2 target-arm: Fix errors in decode of M profile CPS by Peter Maydell · 13 years ago
  92. 7da362d arm: add dummy A9-specific cp15 registers by Mark Langsdorf · 13 years ago
  93. 37064a8 target-arm: Ignore attempts to set invalid modes in CPSR by Peter Maydell · 13 years ago
  94. 1b9e01c target-arm: Don't use cpu_single_env in bank_number() by Peter Maydell · 13 years ago
  95. db8336c target-arm: Infer VFPv3 feature from VFPv4 by Andreas Färber · 13 years ago
  96. 86e72db target-arm: Infer VFP feature from VFPv3 by Andreas Färber · 13 years ago
  97. 908ce98 target-arm: Infer Thumb division feature from M profile by Andreas Färber · 13 years ago
  98. b3faf5f target-arm: Infer Thumb2 feature from ARMv7 by Andreas Färber · 13 years ago
  99. 10e8770 target-arm: Infer AUXCR feature from ARMv6 by Andreas Färber · 13 years ago
  100. bbc5c5f target-arm: Infer ARMv6(K) feature from ARMv7 by Andreas Färber · 13 years ago