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qemu / qemu / 46f296cd3a3ebc3d30e2dbc1da7c4882e3d35ce5 / target-arm
  1. ade0d0c target-arm: dump-guest-memory: add vfp notes for arm by Andrew Jones · 9 years ago
  2. bada8e4 target-arm: dump-guest-memory: add prfpreg notes for aarch64 by Andrew Jones · 9 years ago
  3. da2b914 target-arm: support QMP dump-guest-memory by Andrew Jones · 9 years ago
  4. deb2db9 target-arm: Use the right MMU index in arm_regime_using_lpae_format by Alvise Rigo · 9 years ago
  5. 9af9e0f error: Strip trailing '\n' from error string arguments (again) by Markus Armbruster · 9 years ago
  6. 15eafc2 kvm: x86: add support for KVM_CAP_SPLIT_IRQCHIP by Paolo Bonzini · 9 years ago
  7. 34c45d5 target-arm: kvm - re-inject guest debug exceptions by Alex Bennée · 9 years ago
  8. e4482ab target-arm: kvm - add support for HW assisted debug by Alex Bennée · 9 years ago
  9. 26ae593 target-arm: kvm - support for single step by Alex Bennée · 9 years ago
  10. 2ecb202 target-arm: kvm - implement software breakpoints by Alex Bennée · 9 years ago
  11. 29eb3d9 target-arm: kvm64 - introduce kvm_arm_init_debug() by Alex Bennée · 9 years ago
  12. 7999a5c target-arm: Fix and improve AA32 singlestep translation completion code by Sergey Fedorov · 9 years ago
  13. 3090147 target-arm: raise exception on misaligned LDREX operands by Andrew Baumann · 9 years ago
  14. e14f0eb target-arm/translate-a64.c: Correct unallocated checks for ldst_excl by Peter Maydell · 9 years ago
  15. 6109769 target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8 by Peter Maydell · 9 years ago
  16. ce8a1b5 target-arm: Update condexec before arch BP check in AA32 translation by Sergey Fedorov · 9 years ago
  17. 43bfa4a target-arm: Update condexec before CP access check in AA32 translation by Sergey Fedorov · 9 years ago
  18. ed6c644 target-arm: Update PC before calling gen_helper_check_breakpoints() by Sergey Fedorov · 9 years ago
  19. 577bf80 target-arm: Clean up DISAS_UPDATE usage in AArch32 translation code by Sergey Fedorov · 9 years ago
  20. 5c629f4 target-arm: Fix gdb singlestep handling in arm_debug_excp_handler() by Sergey Fedorov · 9 years ago
  21. 06e5cf7 target-arm: Report S/NS status in the CPU debug logs by Peter Maydell · 9 years ago
  22. 08b8e0f target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32 by Peter Maydell · 9 years ago
  23. 99a99c1 target-arm: Add and use symbolic names for register banks by Soren Brinkmann · 9 years ago
  24. 522a0d4 target-*: Advance pc after recognizing a breakpoint by Richard Henderson · 9 years ago
  25. 9b53926 target-arm: Add support for S1 + S2 MMU translations by Edgar E. Iglesias · 9 years ago
  26. d759a45 target-arm: Route S2 MMU faults to EL2 by Edgar E. Iglesias · 9 years ago
  27. a614e69 target-arm: Add S2 translation to 32bit S1 PTWs by Edgar E. Iglesias · 9 years ago
  28. 3778597 target-arm: Add S2 translation to 64bit S1 PTWs by Edgar E. Iglesias · 9 years ago
  29. e14b5a2 target-arm: Add ARMMMUFaultInfo by Edgar E. Iglesias · 9 years ago
  30. af51f56 target-arm: Avoid inline for get_phys_addr by Edgar E. Iglesias · 9 years ago
  31. 6ab1a5e target-arm: Add support for S2 page-table protection bits by Edgar E. Iglesias · 9 years ago
  32. 1853d5a target-arm: Add computation of starting level for S2 PTW by Edgar E. Iglesias · 9 years ago
  33. 973a543 target-arm: lpae: Rename granule_sz to stride by Edgar E. Iglesias · 9 years ago
  34. 4ca6a05 target-arm: lpae: Replace tsz with computed inputsize by Edgar E. Iglesias · 9 years ago
  35. 4ee3809 target-arm: Add support for AArch32 S2 negative t0sz by Edgar E. Iglesias · 9 years ago
  36. 1f4c8c1 target-arm: lpae: Move declaration of t0sz and t1sz by Edgar E. Iglesias · 9 years ago
  37. 5c31a10 target-arm: lpae: Make t0sz and t1sz signed integers by Edgar E. Iglesias · 9 years ago
  38. 59e0553 target-arm: Add HPFAR_EL2 by Edgar E. Iglesias · 9 years ago
  39. b876452 target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ) by Soren Brinkmann · 9 years ago
  40. 541ebcd target-arm/translate.c: Handle non-executable page-straddling Thumb insns by Peter Maydell · 9 years ago
  41. 7cd6de3 target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked() by Peter Maydell · 9 years ago
  42. 526d580 Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging by Peter Maydell · 9 years ago
  43. dc9f06c kvm: Pass PCI device pointer to MSI routing functions by Pavel Fedin · 9 years ago
  44. 5d98bf8 target-arm: Fix CPU breakpoint handling by Sergey Fedorov · 9 years ago
  45. e63a2d4 target-arm: Fix GDB breakpoint handling by Sergey Fedorov · 9 years ago
  46. 81669b8 target-arm: implement arm_debug_target_el() by Sergey Fedorov · 10 years ago
  47. 14cc7b5 target-arm: Add MDCR_EL2 by Sergey Fedorov · 9 years ago
  48. 1424ca8 target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs by Davorin Mista · 9 years ago
  49. 2cde031 target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL by Sergey Sorokin · 9 years ago
  50. 6df99de target-arm: Break the TB after ISB to execute self-modified code correctly by Sergey Sorokin · 9 years ago
  51. 82c39f6 target-arm: Add missing 'static' attribute by Stefan Weil · 9 years ago
  52. 4c315c2 qdev: Protect device-list-properties against broken devices by Markus Armbruster · 10 years ago
  53. 4e5e121 tcg: Remove gen_intermediate_code_pc by Richard Henderson · 10 years ago
  54. bad729e tcg: Pass data argument to restore_state_to_opc by Richard Henderson · 10 years ago
  55. 190ce7f tcg: Add TCG_MAX_INSNS by Richard Henderson · 10 years ago
  56. dc03246 target-*: Drop cpu_gen_code define by Richard Henderson · 10 years ago
  57. 52e971d target-arm: Add condexec state to insn_start by Richard Henderson · 10 years ago
  58. b933066 target-*: Introduce and use cpu_breakpoint_test by Richard Henderson · 10 years ago
  59. 959082f target-*: Increment num_insns immediately after tcg_gen_insn_start by Richard Henderson · 10 years ago
  60. 667b8e2 target-*: Unconditionally emit tcg_gen_insn_start by Richard Henderson · 10 years ago
  61. 765b842 tcg: Rename debug_insn_start to insn_start by Richard Henderson · 10 years ago
  62. 9e07142 Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging by Peter Maydell · 10 years ago
  63. 352c98e arm: clarify the use of muldiv64() by Laurent Vivier · 10 years ago
  64. b597c3f arm: Remove ELF_MACHINE from cpu.h by Peter Crosthwaite · 10 years ago
  65. a7bf303 hw/intc: Initial implementation of vGICv3 by Pavel Fedin · 10 years ago
  66. 34e85cd arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create() by Pavel Fedin · 10 years ago
  67. 42fedbc target-arm: Use new revbit functions by Richard Henderson · 10 years ago
  68. f0d574d target-arm: Add VMPIDR_EL2 by Edgar E. Iglesias · 10 years ago
  69. 06a7e64 target-arm: Break out mpidr_read_val() by Edgar E. Iglesias · 10 years ago
  70. 731de9e target-arm: Add VPIDR_EL2 by Edgar E. Iglesias · 10 years ago
  71. 0c5fbf3 target-arm: Suppress EPD for S2, EL2 and EL3 translations by Edgar E. Iglesias · 10 years ago
  72. 1edee47 target-arm: Suppress TBI for S2 translations by Edgar E. Iglesias · 10 years ago
  73. b698e9c target-arm: Add VTTBR_EL2 by Edgar E. Iglesias · 10 years ago
  74. 68e9c2f target-arm: Add VTCR_EL2 by Edgar E. Iglesias · 10 years ago
  75. 7cb36e1 target-arm: Use tcg_gen_extrh_i64_i32 by Richard Henderson · 10 years ago
  76. 8fb0ad8 target-arm: Recognize ROR by Richard Henderson · 10 years ago
  77. d3a77b4 target-arm: Eliminate unnecessary zero-extend in disas_bitfield by Richard Henderson · 10 years ago
  78. 9924e85 target-arm: Recognize UXTB, UXTH, LSR, LSL by Richard Henderson · 10 years ago
  79. ef60151 target-arm: Recognize SXTB, SXTH, SXTW, ASR by Richard Henderson · 10 years ago
  80. 6e06102 target-arm: Implement fcsel with movcond by Richard Henderson · 10 years ago
  81. 7dd03d7 target-arm: Implement ccmp branchless by Richard Henderson · 10 years ago
  82. 259cb68 target-arm: Use setcond and movcond for csel by Richard Henderson · 10 years ago
  83. 9305eac target-arm: Handle always condition codes within arm_test_cc by Richard Henderson · 10 years ago
  84. 6c2c63d target-arm: Introduce DisasCompare by Richard Henderson · 10 years ago
  85. 78bcaa3 target-arm: Share all common TCG temporaries by Richard Henderson · 10 years ago
  86. 97ed5cc tlb: Add "ifetch" argument to cpu_mmu_index() by Benjamin Herrenschmidt · 10 years ago
  87. 67cc32e typofixes - v4 by Veres Lajos · 10 years ago
  88. b6af097 maint: remove / fix many doubled words by Daniel P. Berrange · 10 years ago
  89. c96fc9b target-arm: Add AArch64 access to PAR_EL1 by Edgar E. Iglesias · 10 years ago
  90. 7a379c7 target-arm: Correct opc1 for AT_S12Exx by Edgar E. Iglesias · 10 years ago
  91. dbc29a8 target-arm: Log the target EL when taking exceptions by Edgar E. Iglesias · 10 years ago
  92. cef9ee7 target-arm: Fix default_exception_el() function for the case when EL3 is not supported by Sergey Sorokin · 10 years ago
  93. 0f4a9e4 target-arm: Refactor CPU affinity handling by Pavel Fedin · 10 years ago
  94. 7718425 target-arm: Fix arm_excp_unmasked() function by Sergey Sorokin · 10 years ago
  95. 3a9148d target-arm: Fix AArch32:AArch64 general-purpose register mapping by Sergey Sorokin · 10 years ago
  96. 8f6fd32 arm: Remove hw_error() usages. by Peter Crosthwaite · 10 years ago
  97. f128bf2 arm: cpu: assert() on no-EL2 virt IRQ error condition. by Peter Crosthwaite · 10 years ago
  98. 8012c84 target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction by Peter Maydell · 10 years ago
  99. 7446d35 target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block by Peter Maydell · 10 years ago
  100. e9ebfbf target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call by Peter Maydell · 10 years ago