1. 1190655 hw/core: Constify TCGCPUOps by Richard Henderson · 3 years, 11 months ago
  2. 08928c6 cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps by Philippe Mathieu-Daudé · 3 years, 8 months ago
  3. 8b80bd2 cpu: Introduce SysemuCPUOps structure by Philippe Mathieu-Daudé · 3 years, 8 months ago
  4. 7827168 cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass by Claudio Fontana · 4 years ago
  5. 0545608 cpu: move cc->do_interrupt to tcg_ops by Claudio Fontana · 4 years ago
  6. e124536 cpu: Move tlb_fill to tcg_ops by Eduardo Habkost · 4 years ago
  7. 48c1a3e cpu: Move cpu_exec_* to tcg_ops by Eduardo Habkost · 4 years ago
  8. e9e51b7 cpu: Introduce TCGCpuOperations struct by Eduardo Habkost · 4 years ago
  9. 71b3254 target/openrisc: Move pic_cpu code into CPU object proper by Peter Maydell · 4 years, 1 month ago
  10. 781c67c cpu: Use DeviceClass reset instead of a special CPUClass reset by Peter Maydell · 4 years, 10 months ago
  11. bc9888f cpu: Use cpu_class_set_parent_reset() by Greg Kurz · 5 years ago
  12. 9e3bab0 target/openrisc: Update cpu "any" to v1.3 by Richard Henderson · 5 years ago
  13. a465772 target/openrisc: Implement move to/from FPCSR by Richard Henderson · 5 years ago
  14. 62f2b03 target/openrisc: Add support for ORFPX64A32 by Richard Henderson · 6 years ago
  15. fe636d3 target/openrisc: Check CPUCFG_OF32S for float insns by Richard Henderson · 5 years ago
  16. 8bebf7d target/openrisc: Add VR2 and AVR special processor registers by Richard Henderson · 5 years ago
  17. c7efab4 target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init by Richard Henderson · 5 years ago
  18. a8d2532 Include qemu-common.h exactly where needed by Markus Armbruster · 6 years ago
  19. 7506ed9 cpu: Introduce cpu_set_cpustate_pointers by Richard Henderson · 6 years ago
  20. 35e911a target/openrisc: Convert to CPUClass::tlb_fill by Richard Henderson · 6 years ago
  21. 0442428 target: Simplify how the TARGET_cpu_list() print by Markus Armbruster · 6 years ago
  22. 779fc6a target/openrisc: Fix LGPL version number by Thomas Huth · 6 years ago
  23. e8f2904 linux-user: Implement signals for openrisc by Richard Henderson · 7 years ago
  24. 1cc9e5d target/openrisc: Increase the TLB size by Richard Henderson · 7 years ago
  25. 23d45eb target/openrisc: Remove indirect function calls for mmu by Richard Henderson · 7 years ago
  26. d5cabcc target/openrisc: Add print_insn_or1k by Richard Henderson · 7 years ago
  27. 23c11b0 target: Do not include "exec/exec-all.h" if it is not necessary by Philippe Mathieu-Daudé · 7 years ago
  28. bf85388 qdev: use device_class_set_parent_realize/unrealize/reset() by Philippe Mathieu-Daudé · 7 years ago
  29. a677273 openrisc: cleanup cpu type name composition by Igor Mammedov · 7 years ago
  30. 55c3cee qom: Introduce CPUClass.tcg_initialize by Richard Henderson · 7 years ago
  31. 6b4bbd6 openrisc/cputimer: Perparation for Multicore by Stafford Horne · 7 years ago
  32. 8301ea4 qom/cpu: move cpu_model null check to cpu_class_by_name() by Philippe Mathieu-Daudé · 7 years ago
  33. f6f8b26 openrisc: replace cpu_openrisc_init() with cpu_generic_init() by Igor Mammedov · 7 years ago
  34. f4d1414 target/openrisc: Support non-busy idle state using PMR SPR by Stafford Horne · 8 years ago
  35. 48a1b62 target/openrisc: Remove duplicate features property by Stafford Horne · 8 years ago
  36. d89e71e target/openrisc: implement shadow registers by Stafford Horne · 8 years ago
  37. 356a2db target/openrisc: Implement EVBAR register by Tim 'mithro' Ansell · 8 years ago
  38. 930c3d0 target/openrisc: Implement lwa, swa by Richard Henderson · 10 years ago
  39. 1f5c00c qom/cpu: move tlb_flush to cpu_common_reset by Alex Bennée · 8 years ago
  40. fcf5ef2 Move target-* CPU file into a target/ folder by Thomas Huth · 8 years ago[Renamed from target-openrisc/cpu.c]
  41. 82ecffa Open 2.9 development tree by Stefan Hajnoczi · 8 years ago