- fb17018 sparc64: fix umul and smul insns by Igor V. Kovalenko · 15 years ago
- fe987e2 sparc64: fix ldxfsr insn by Igor V. Kovalenko · 15 years ago
- 1295001 sparc64: fix missing address masking v1 by Igor V. Kovalenko · 15 years ago
- 9fd1ae3 sparc64: fix mmu context at trap levels above zero by Igor V. Kovalenko · 15 years ago
- 2aae2b8 sparc64: fix pstate privilege bits by Igor V. Kovalenko · 15 years ago
- 70c4828 target-sparc: Inline some generation of carry for ADDX/SUBX. by Richard Henderson · 15 years ago
- 275ea26 sparc: lazy C flag calculation by Blue Swirl · 15 years ago
- 060718c target-sparc: Fix -singlestep. by Richard Henderson · 15 years ago
- 6ad6135 Fix harmless if statements with empty body, spotted by clang by Blue Swirl · 15 years ago
- 42a8aa8 target-sparc: Free instruction temporaries. by Richard Henderson · 15 years ago
- cca1d52 Sparc: fix PC/NPC during FPU traps by Blue Swirl · 15 years ago
- d7da2a1 Sparc: fix exceptions in delay slot by Blue Swirl · 15 years ago
- 1a7ff92 remove TARGET_* defines from translate-all.c by Paolo Bonzini · 15 years ago
- bc57c11 target-sparc: fix --enable-debug build for 64 bit host by Stefan Weil · 15 years ago
- b551ec0 target-sparc: fix --enable-debug build by Jay Foad · 15 years ago
- 1fae7b7 sparc64: use helper_wrpil to check pending irq on write by Igor V. Kovalenko · 15 years ago
- 01b5d4e sparc64-8bit-asi by Igor V. Kovalenko · 15 years ago
- 72cf2d4 Fix sys-queue.h conflict for good by Blue Swirl · 15 years ago
- c27e275 Sparc32/64: fix jmpl followed by branch by Blue Swirl · 16 years ago
- cfa9051 Fix desynchronization of condition code state when a memory access traps by Blue Swirl · 16 years ago
- 8194f35 Sparc64: replace tsptr with helper routine by Igor Kovalenko · 16 years ago
- 14ed7ad sparc64 flush pending conditional evaluations before exposing cpu state by Igor Kovalenko · 16 years ago
- 8167ee8 Update to a hopefully more future proof FSF address by Blue Swirl · 16 years ago
- 25517f9 Use correct type for SPARC cpu_cc_op by Paul Brook · 16 years ago
- d084469 Convert mulscc by Blue Swirl · 16 years ago
- 6c78ea3 Convert udiv/sdiv by Blue Swirl · 16 years ago
- 3b2d1e9 Convert tagged ops by Blue Swirl · 16 years ago
- 2ca1d92 Convert subx by Blue Swirl · 16 years ago
- d4b0d46 Convert sub by Blue Swirl · 16 years ago
- 38482a7 Convert logical operations and umul/smul by Blue Swirl · 16 years ago
- 789c91e Convert addx by Blue Swirl · 16 years ago
- bdf9f35 Convert add by Blue Swirl · 16 years ago
- 8393617 Use dynamical computation for condition codes by Blue Swirl · 16 years ago
- 719f66a Optimize cmp x, 0 case by Blue Swirl · 16 years ago
- dc1a697 Reindent by Blue Swirl · 16 years ago
- b89e94a Improve instruction name comments for easier searching by Blue Swirl · 16 years ago
- 41d7285 Optimize operations with immediate parameters by Blue Swirl · 16 years ago
- 67526b2 Fix Sparc64 sign extension problems by Blue Swirl · 16 years ago
- 1b530a6 Add new command line option -singlestep for tcg single stepping. by aurel32 · 16 years ago
- d78f399 Delete some unused macros detected with -Wp,-Wunused-macros use by blueswir1 · 16 years ago
- 8fec2b8 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost) by aliguori · 16 years ago
- 93fcfe3 Convert references to logfile/loglevel to use qemu_log*() macros by aliguori · 16 years ago
- fad6cb1 Update FSF address in GPL/LGPL boilerplate by aurel32 · 16 years ago
- c0ce998 Use sys-queue.h for break/watchpoint managment (Jan Kiszka) by aliguori · 16 years ago
- a1d1bb3 Refactor and enhance break/watchpoint API (Jan Kiszka) by aliguori · 16 years ago
- a7812ae TCG variable type checking. by pbrook · 16 years ago
- 2576d83 Use TCG not op by blueswir1 · 16 years ago
- 81b5b81 Use andc, orc, nor and nand by blueswir1 · 16 years ago
- 527067d Fix TCGv size mismatches by blueswir1 · 16 years ago
- b158a78 Implement UA2005 hypervisor traps by blueswir1 · 16 years ago
- 9d92659 Add software and timer interrupt support by blueswir1 · 16 years ago
- ab50801 Use the new concat_tl_i64 op for std and stda by blueswir1 · 16 years ago
- a7ec422 Use the new concat_i32_i64 op for std and stda by blueswir1 · 16 years ago
- 72ccba7 Fix mulscc with high bits set in either src1 or src2 by blueswir1 · 16 years ago
- 5068cbd Write zeros to high bits of y, based on patch by Vince Weaver by blueswir1 · 16 years ago
- d84763b Convert rest of ops using float32 to TCG, remove FT0 and FT1 by blueswir1 · 16 years ago
- c5d04e9 Partially convert float128 conversion ops to TCG by blueswir1 · 16 years ago
- e2ea21b Convert basic 64 bit VIS ops to TCG by blueswir1 · 16 years ago
- 1d01299 Convert basic 32 bit VIS ops to TCG by blueswir1 · 16 years ago
- 714547b Convert basic float32 ops to TCG by blueswir1 · 16 years ago
- 3a3b925 Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG by blueswir1 · 16 years ago
- 510aba2 Fix a typo in fpsub32 by blueswir1 · 16 years ago
- 255e1fc Convert most env fields to TCG registers by blueswir1 · 16 years ago
- 47ad35f Silence gcc warning about constant overflow by blueswir1 · 16 years ago
- b991c38 Fix sign extension problems with smul and umul (Vince Weaver) by blueswir1 · 17 years ago
- 105a1f0 Fix y register loads and stores by blueswir1 · 17 years ago
- ba6a9d8 Fix FCC handling for Sparc64 target, initial patch by Vince Weaver by blueswir1 · 17 years ago
- c93e781 Fix wrwim masking (Luis Pureza) by blueswir1 · 17 years ago
- 5578cea Use initial CPU definition structure for some CPU fields instead of copying by blueswir1 · 17 years ago
- 2ae72bc Correct 32bit carry flag for add instruction (Igor Kovalenko) by blueswir1 · 17 years ago
- 01b1fa6 Fix Sparc64 shifts by blueswir1 · 17 years ago
- 95f9397 Fix offset handling for ASI loads and stores (Vince Weaver) by blueswir1 · 17 years ago
- dd5e630 Fix cmp/subcc/addcc op bugs reported by Vince Weaver by blueswir1 · 17 years ago
- fb79ceb Make UA200x features selectable, add MMU types by blueswir1 · 17 years ago
- db16694 Implement nucleus quad ldda by blueswir1 · 17 years ago
- 2cfc5f1 Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues. by ths · 17 years ago
- 8d7d8c4 wrhpr hstick_cmpr is a store, not a load by blueswir1 · 17 years ago
- 2cade6a Support for address masking by blueswir1 · 17 years ago
- c5f2f66 Flushw can generate exceptions, so save PC & NPC by blueswir1 · 17 years ago
- 71817e4 Really fix cas by blueswir1 · 17 years ago
- 2e70f6e Add instruction counter. by pbrook · 17 years ago
- d987963 Eliminate cpu_T[0] by blueswir1 · 17 years ago
- 3f0436f Eliminate cpu_T[1] by blueswir1 · 17 years ago
- ece43b8 Convert some cpu_dst uses (with loads/stores) to cpu_tmp0 by blueswir1 · 17 years ago
- 5c6a062 Avoid brcond problems, use temps for cpu_src1 & cpu_src2 by blueswir1 · 17 years ago
- 07bf285 Avoid temporary variable use across basic blocks for udivx by blueswir1 · 17 years ago
- 1a14026 Allow NWINDOWS selection (CPU feature with model specific defaults) by blueswir1 · 17 years ago
- e30b467 MicroSparc I didn't have fsmuld op by blueswir1 · 17 years ago
- 2ea815c Free temps by blueswir1 · 17 years ago
- 8d96d20 More TCG type fixes by blueswir1 · 17 years ago
- ef28fd8 Fix cas on i386 by blueswir1 · 17 years ago
- 4f7de37 remove absolete function by bellard · 17 years ago
- a8c768c Nicer debug output by blueswir1 · 17 years ago
- bcb0126 More TCGv type fixes. by pbrook · 17 years ago
- cb63669 Fix ARM conditional branch bug. Add tcg_gen_brcondi. by pbrook · 17 years ago
- 455f900 Fix helper operand type mismatch. by pbrook · 17 years ago
- c9e03d8 Register op helpers by blueswir1 · 17 years ago
- e35298c Generate better code for Sparc32 shifts by blueswir1 · 17 years ago
- 77f193d Wrap long lines by blueswir1 · 17 years ago
- c2bc0e3 Remove someexplicit alignment checks (initial patch by Fabrice Bellard) by blueswir1 · 17 years ago
