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qemu
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2852aafd9d05d97accd7a1d4df8ff25d9ac4cbfc
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target
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openrisc
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translate.c
b9bed1b
target/openrisc: Fix cpu_mmu_index
by Richard Henderson
· 7 years ago
c28fa81
target/openrisc: Form the spr index from tcg
by Richard Henderson
· 7 years ago
01ec3ec
target/openrisc: Exit the TB after l.mtspr
by Richard Henderson
· 7 years ago
2ba6541
target/openrisc: Split out is_user
by Richard Henderson
· 7 years ago
8000ba5
target/openrisc: Link more translation blocks
by Richard Henderson
· 7 years ago
e0a369c
target/openrisc: Fix singlestep_enabled
by Richard Henderson
· 7 years ago
64e46c9
target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
by Richard Henderson
· 7 years ago
c86395c
target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
by Richard Henderson
· 7 years ago
d5cabcc
target/openrisc: Add print_insn_or1k
by Richard Henderson
· 7 years ago
07ea28b
tcg: Pass tb and index to tcg_gen_exit_tb separately
by Richard Henderson
· 7 years ago
c7b6f54
target/openrisc: Merge disas_openrisc_insn
by Richard Henderson
· 7 years ago
6fd204a
target/openrisc: Convert dec_float
by Richard Henderson
· 7 years ago
032de4f
target/openrisc: Convert dec_compi
by Richard Henderson
· 7 years ago
fbb3e29
target/openrisc: Convert dec_comp
by Richard Henderson
· 7 years ago
e720a57
target/openrisc: Convert dec_M
by Richard Henderson
· 7 years ago
e20c259
target/openrisc: Convert dec_logic
by Richard Henderson
· 7 years ago
99d863d
target/openrisc: Convert dec_mac
by Richard Henderson
· 7 years ago
6ad216a
target/openrisc: Convert dec_calc
by Richard Henderson
· 7 years ago
8816f70
target/openrisc: Convert remainder of dec_misc insns
by Richard Henderson
· 7 years ago
d80bff1
target/openrisc: Convert memory insns
by Richard Henderson
· 7 years ago
136e13a
target/openrisc: Convert branch insns
by Richard Henderson
· 7 years ago
7de9729
target/openrisc: Start conversion to decodetree.py
by Richard Henderson
· 7 years ago
4e2d300
target-openrisc: Write back result before FPE exception
by Richard Henderson
· 10 years ago
a4fd3ec
target/openrisc: convert to TranslatorOps
by Emilio G. Cota
· 7 years ago
1ffa4bc
target/openrisc: convert to DisasContextBase
by Emilio G. Cota
· 7 years ago
6e6430a
Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging
by Peter Maydell
· 7 years ago
1d48474
disas: Remove unused flags arguments
by Richard Henderson
· 7 years ago
1c2adb9
tcg: Initialize cpu_env generically
by Richard Henderson
· 7 years ago
b1311c4
tcg: define tcg_init_ctx and make tcg_ctx a pointer
by Emilio G. Cota
· 7 years ago
c5a49c6
tcg: convert tb->cflags reads to tb_cflags(tb)
by Emilio G. Cota
· 7 years ago
77fc6f5
target: [tcg] Use a generic enum for DISAS_ values
by Lluís Vilanova
· 7 years ago
9c489ea
tcg: Pass generic CPUState to gen_intermediate_code()
by Lluís Vilanova
· 7 years ago
d89e71e
target/openrisc: implement shadow registers
by Stafford Horne
· 8 years ago
6597c28
target/openrisc: Optimize for r0 being zero
by Richard Henderson
· 9 years ago
a01deb3
target/openrisc: Tidy handling of delayed branches
by Richard Henderson
· 9 years ago
24c3285
target/openrisc: Tidy ppc/npc implementation
by Richard Henderson
· 9 years ago
a8000cb
target/openrisc: Optimize l.jal to next
by Richard Henderson
· 9 years ago
762e22e
target/openrisc: Fix madd
by Richard Henderson
· 10 years ago
cc5de49
target/openrisc: Implement muld, muldu, macu, msbu
by Richard Henderson
· 10 years ago
6f7332b
target/openrisc: Represent MACHI:MACLO as a single unit
by Richard Henderson
· 10 years ago
24fc5c0
target/openrisc: Implement msync
by Richard Henderson
· 8 years ago
20dc52a
target/openrisc: Enable trap, csync, msync, psync for user mode
by Richard Henderson
· 10 years ago
784696d
target/openrisc: Use movcond where appropriate
by Richard Henderson
· 10 years ago
9745807
target/openrisc: Keep SR_CY and SR_OV in a separate variables
by Richard Henderson
· 10 years ago
84775c4
target/openrisc: Keep SR_F in a separate variable
by Richard Henderson
· 10 years ago
cf2ae44
target/openrisc: Invert the decoding in dec_calc
by Richard Henderson
· 10 years ago
0c53d73
target/openrisc: Put SR[OVE] in TB flags
by Richard Henderson
· 10 years ago
9ecaa27
target/openrisc: Streamline arithmetic and OVE
by Richard Henderson
· 10 years ago
6da544a
target/openrisc: Rationalize immediate extraction
by Richard Henderson
· 8 years ago
111ece5
target/openrisc: Tidy insn dumping
by Richard Henderson
· 10 years ago
930c3d0
target/openrisc: Implement lwa, swa
by Richard Henderson
· 10 years ago
555baef
target-openrisc: Use clz and ctz opcodes
by Richard Henderson
· 8 years ago
fcf5ef2
Move target-* CPU file into a target/ folder
by Thomas Huth
· 8 years ago
[Renamed from target-openrisc/translate.c]
82ecffa
Open 2.9 development tree
by Stefan Hajnoczi
· 8 years ago