1. b9bed1b target/openrisc: Fix cpu_mmu_index by Richard Henderson · 7 years ago
  2. c28fa81 target/openrisc: Form the spr index from tcg by Richard Henderson · 7 years ago
  3. 01ec3ec target/openrisc: Exit the TB after l.mtspr by Richard Henderson · 7 years ago
  4. 2ba6541 target/openrisc: Split out is_user by Richard Henderson · 7 years ago
  5. 8000ba5 target/openrisc: Link more translation blocks by Richard Henderson · 7 years ago
  6. e0a369c target/openrisc: Fix singlestep_enabled by Richard Henderson · 7 years ago
  7. 64e46c9 target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB by Richard Henderson · 7 years ago
  8. c86395c target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP by Richard Henderson · 7 years ago
  9. d5cabcc target/openrisc: Add print_insn_or1k by Richard Henderson · 7 years ago
  10. 07ea28b tcg: Pass tb and index to tcg_gen_exit_tb separately by Richard Henderson · 7 years ago
  11. c7b6f54 target/openrisc: Merge disas_openrisc_insn by Richard Henderson · 7 years ago
  12. 6fd204a target/openrisc: Convert dec_float by Richard Henderson · 7 years ago
  13. 032de4f target/openrisc: Convert dec_compi by Richard Henderson · 7 years ago
  14. fbb3e29 target/openrisc: Convert dec_comp by Richard Henderson · 7 years ago
  15. e720a57 target/openrisc: Convert dec_M by Richard Henderson · 7 years ago
  16. e20c259 target/openrisc: Convert dec_logic by Richard Henderson · 7 years ago
  17. 99d863d target/openrisc: Convert dec_mac by Richard Henderson · 7 years ago
  18. 6ad216a target/openrisc: Convert dec_calc by Richard Henderson · 7 years ago
  19. 8816f70 target/openrisc: Convert remainder of dec_misc insns by Richard Henderson · 7 years ago
  20. d80bff1 target/openrisc: Convert memory insns by Richard Henderson · 7 years ago
  21. 136e13a target/openrisc: Convert branch insns by Richard Henderson · 7 years ago
  22. 7de9729 target/openrisc: Start conversion to decodetree.py by Richard Henderson · 7 years ago
  23. 4e2d300 target-openrisc: Write back result before FPE exception by Richard Henderson · 10 years ago
  24. a4fd3ec target/openrisc: convert to TranslatorOps by Emilio G. Cota · 7 years ago
  25. 1ffa4bc target/openrisc: convert to DisasContextBase by Emilio G. Cota · 7 years ago
  26. 6e6430a Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging by Peter Maydell · 7 years ago
  27. 1d48474 disas: Remove unused flags arguments by Richard Henderson · 7 years ago
  28. 1c2adb9 tcg: Initialize cpu_env generically by Richard Henderson · 7 years ago
  29. b1311c4 tcg: define tcg_init_ctx and make tcg_ctx a pointer by Emilio G. Cota · 7 years ago
  30. c5a49c6 tcg: convert tb->cflags reads to tb_cflags(tb) by Emilio G. Cota · 7 years ago
  31. 77fc6f5 target: [tcg] Use a generic enum for DISAS_ values by Lluís Vilanova · 7 years ago
  32. 9c489ea tcg: Pass generic CPUState to gen_intermediate_code() by Lluís Vilanova · 7 years ago
  33. d89e71e target/openrisc: implement shadow registers by Stafford Horne · 8 years ago
  34. 6597c28 target/openrisc: Optimize for r0 being zero by Richard Henderson · 9 years ago
  35. a01deb3 target/openrisc: Tidy handling of delayed branches by Richard Henderson · 9 years ago
  36. 24c3285 target/openrisc: Tidy ppc/npc implementation by Richard Henderson · 9 years ago
  37. a8000cb target/openrisc: Optimize l.jal to next by Richard Henderson · 9 years ago
  38. 762e22e target/openrisc: Fix madd by Richard Henderson · 10 years ago
  39. cc5de49 target/openrisc: Implement muld, muldu, macu, msbu by Richard Henderson · 10 years ago
  40. 6f7332b target/openrisc: Represent MACHI:MACLO as a single unit by Richard Henderson · 10 years ago
  41. 24fc5c0 target/openrisc: Implement msync by Richard Henderson · 8 years ago
  42. 20dc52a target/openrisc: Enable trap, csync, msync, psync for user mode by Richard Henderson · 10 years ago
  43. 784696d target/openrisc: Use movcond where appropriate by Richard Henderson · 10 years ago
  44. 9745807 target/openrisc: Keep SR_CY and SR_OV in a separate variables by Richard Henderson · 10 years ago
  45. 84775c4 target/openrisc: Keep SR_F in a separate variable by Richard Henderson · 10 years ago
  46. cf2ae44 target/openrisc: Invert the decoding in dec_calc by Richard Henderson · 10 years ago
  47. 0c53d73 target/openrisc: Put SR[OVE] in TB flags by Richard Henderson · 10 years ago
  48. 9ecaa27 target/openrisc: Streamline arithmetic and OVE by Richard Henderson · 10 years ago
  49. 6da544a target/openrisc: Rationalize immediate extraction by Richard Henderson · 8 years ago
  50. 111ece5 target/openrisc: Tidy insn dumping by Richard Henderson · 10 years ago
  51. 930c3d0 target/openrisc: Implement lwa, swa by Richard Henderson · 10 years ago
  52. 555baef target-openrisc: Use clz and ctz opcodes by Richard Henderson · 8 years ago
  53. fcf5ef2 Move target-* CPU file into a target/ folder by Thomas Huth · 8 years ago[Renamed from target-openrisc/translate.c]
  54. 82ecffa Open 2.9 development tree by Stefan Hajnoczi · 8 years ago