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qemu / qemu / 1f8ad88935f5cb5a2968909e392dbeee1a84b931 / target / arm
  1. 37e29a6 target/arm: Avoid an extra temporary for store_exclusive by Richard Henderson · 7 years ago
  2. dddbba9 AArch64: Fix single stepping of ERET instruction by Jaroslaw Pelczar · 7 years ago
  3. 351e527 target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit() by Peter Maydell · 7 years ago
  4. 4d1e7a4 target/arm: Add and use defines for EXCRET constants by Peter Maydell · 7 years ago
  5. 7115cdf target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit() by Peter Maydell · 7 years ago
  6. c615887 target/arm: Get PRECISERR and IBUSERR the right way round by Peter Maydell · 7 years ago
  7. dc3c4c1 target/arm: Clear exclusive monitor on v7M reset, exception entry/exit by Peter Maydell · 7 years ago
  8. 4a16724 target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 by Peter Maydell · 7 years ago
  9. 6dba634 hmp: fix "dump-quest-memory" segfault (arm) by Laurent Vivier · 7 years ago
  10. ef475b5 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907' into staging by Peter Maydell · 7 years ago
  11. c99a55d target/arm: Add Jazelle feature by Portia Stephens · 7 years ago
  12. c79c0a3 target/arm: Implement new do_transaction_failed hook by Peter Maydell · 7 years ago
  13. fb602cb target/arm: Implement BXNS, and banked stack pointers by Peter Maydell · 7 years ago
  14. 61fcd69 target/arm: Move regime_is_secure() to target/arm/internals.h by Peter Maydell · 7 years ago
  15. 334e8da target/arm: Make CFSR register banked for v8M by Peter Maydell · 7 years ago
  16. c51a5cf target/arm: Make MMFAR banked for v8M by Peter Maydell · 7 years ago
  17. 9d40cd8 target/arm: Make CCR register banked for v8M by Peter Maydell · 7 years ago
  18. ecf5e8e target/arm: Make MPU_CTRL register banked for v8M by Peter Maydell · 7 years ago
  19. 1bc04a8 target/arm: Make MPU_RNR register banked for v8M by Peter Maydell · 7 years ago
  20. 62c58ee target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M by Peter Maydell · 7 years ago
  21. 4125e6f target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M by Peter Maydell · 7 years ago
  22. 45db7ba target/arm: Make VTOR register banked for v8M by Peter Maydell · 7 years ago
  23. 8bfc26e target/arm: Make CONTROL register banked for v8M by Peter Maydell · 7 years ago
  24. 42a6686 target/arm: Make FAULTMASK register banked for v8M by Peter Maydell · 7 years ago
  25. 6d80483 target/arm: Make PRIMASK register banked for v8M by Peter Maydell · 7 years ago
  26. acf9494 target/arm: Make BASEPRI register banked for v8M by Peter Maydell · 7 years ago
  27. 66787c7 target/arm: Add MMU indexes for secure v8M by Peter Maydell · 7 years ago
  28. 1d2091b target/arm: Register second AddressSpace for secure v8M CPUs by Peter Maydell · 7 years ago
  29. 1e577cc target/arm: Add state field, feature bit and migration for v8M secure state by Peter Maydell · 7 years ago
  30. 504e3cc target/arm: Implement new PMSAv8 behaviour by Peter Maydell · 7 years ago
  31. 0e1a46b target/arm: Implement ARMv8M's PMSAv8 registers by Peter Maydell · 7 years ago
  32. d0264d8 target/arm: Perform per-insn cross-page check only for Thumb by Richard Henderson · 8 years ago
  33. 722ef0a target/arm: Split out thumb_tr_translate_insn by Richard Henderson · 8 years ago
  34. f770845 target/arm: Move ss check to init_disas_context by Richard Henderson · 8 years ago
  35. dcc3a21 target/arm: [a64] Move page and ss checks to init_disas_context by Richard Henderson · 8 years ago
  36. 2316922 target/arm: [tcg] Port to generic translation framework by Lluís Vilanova · 8 years ago
  37. 58350fa target/arm: [tcg,a64] Port to disas_log by Lluís Vilanova · 8 years ago
  38. 4013f7f target/arm: [tcg] Port to disas_log by Lluís Vilanova · 8 years ago
  39. be40796 target/arm: [tcg,a64] Port to tb_stop by Lluís Vilanova · 8 years ago
  40. 70d3c03 target/arm: [tcg] Port to tb_stop by Lluís Vilanova · 8 years ago
  41. 24299c8 target/arm: [tcg,a64] Port to translate_insn by Lluís Vilanova · 8 years ago
  42. 13189a9 target/arm: [tcg] Port to translate_insn by Lluís Vilanova · 8 years ago
  43. 0cb56b3 target/arm: [tcg,a64] Port to breakpoint_check by Lluís Vilanova · 8 years ago
  44. a68956a target/arm: [tcg,a64] Port to insn_start by Lluís Vilanova · 8 years ago
  45. f62bd89 target/arm: [tcg] Port to insn_start by Lluís Vilanova · 8 years ago
  46. b147685 target/arm: [tcg] Port to tb_start by Lluís Vilanova · 8 years ago
  47. 5c03990 target/arm: [tcg,a64] Port to init_disas_context by Lluís Vilanova · 8 years ago
  48. 1d8a553 target/arm: [tcg] Port to init_disas_context by Lluís Vilanova · 8 years ago
  49. dcba3a8 target/arm: [tcg] Port to DisasContextBase by Lluís Vilanova · 8 years ago
  50. 3805c2e target/arm: Delay check for magic kernel page by Richard Henderson · 8 years ago
  51. 77fc6f5 target: [tcg] Use a generic enum for DISAS_ values by Lluís Vilanova · 8 years ago
  52. a0c231e target/arm: Use DISAS_NORETURN by Richard Henderson · 8 years ago
  53. 3e4d91b target/arm: Fix aa64 ldp register writeback by Richard Henderson · 8 years ago
  54. c528af7 target/arm: Allow deliver_fault() caller to specify EA bit by Peter Maydell · 8 years ago
  55. aac43da target/arm: Factor out fault delivery code by Peter Maydell · 8 years ago
  56. b2bfe9f target/arm/kvm: pmu: improve error handling by Andrew Jones · 8 years ago
  57. b165952 hw/arm/virt: allow pmu instantiation with userspace irqchip by Andrew Jones · 8 years ago
  58. 3f07cb2 target/arm/kvm: pmu: split init and set-irq stages by Andrew Jones · 8 years ago
  59. 07f4873 hw/arm/virt: add pmu interrupt state by Andrew Jones · 8 years ago
  60. 15b3f55 target/arm: Create and use new function arm_v7m_is_handler_mode() by Peter Maydell · 8 years ago
  61. bd70b29 target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed by Peter Maydell · 8 years ago
  62. 5b906f3 target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR by Peter Maydell · 8 years ago
  63. eeade00 target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR by Peter Maydell · 8 years ago
  64. e6ae598 target/arm: Don't store M profile PRIMASK and FAULTMASK in daif by Peter Maydell · 8 years ago
  65. 987ab45 target/arm: Define and use XPSR bit masks by Peter Maydell · 8 years ago
  66. 9d17da4 target/arm: Fix outdated comment about exception exit by Peter Maydell · 8 years ago
  67. 59e4972 target/arm: Remove incorrect comment about MPU_CTRL by Peter Maydell · 8 years ago
  68. ebfe27c target/arm: Tighten up Thumb decode where new v8M insns will be by Peter Maydell · 8 years ago
  69. 3279adb target/arm: Consolidate PMSA handling in get_phys_addr() by Peter Maydell · 8 years ago
  70. 0e28456 target/arm: Don't trap WFI/WFE for M profile by Peter Maydell · 8 years ago
  71. 03ae85f target/arm: Use MMUAccessType enum rather than int by Peter Maydell · 8 years ago
  72. 701e3c7 arm: replace cpu_arm_init() with cpu_generic_init() by Igor Mammedov · 8 years ago
  73. 4a2fdb7 target/arm: Require alignment for load exclusive by Alistair Francis · 8 years ago
  74. 19514cd target/arm: Correct load exclusive pair atomicity by Richard Henderson · 8 years ago
  75. 955fd0a target/arm: Correct exclusive store cmpxchg memop mask by Alistair Francis · 8 years ago
  76. 8908eb1 trace-events: fix code style: print 0x before hex numbers by Vladimir Sementsov-Ogievskiy · 8 years ago
  77. f1a4694 target/arm: Migrate MPU_RNR register state for M profile cores by Peter Maydell · 8 years ago
  78. 69ceea6 target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset by Peter Maydell · 8 years ago
  79. 8531eb4 target/arm: Rename cp15.c6_rgnr to pmsav7.rnr by Peter Maydell · 8 years ago
  80. bf446a1 target/arm: Don't allow guest to make System space executable for M profile by Peter Maydell · 8 years ago
  81. 38aaa60 target/arm: Don't do MPU lookups for addresses in M profile PPB region by Peter Maydell · 8 years ago
  82. 709e440 target/arm: Correct MPU trace handling of write vs execute by Peter Maydell · 8 years ago
  83. 87e0331 docs: fix broken paths to docs/devel/tracing.txt by Philippe Mathieu-Daudé · 8 years ago
  84. e4256c3 target/arm: fix TCG temp leak in aarch64 rev16 by Emilio G. Cota · 8 years ago
  85. 9c489ea tcg: Pass generic CPUState to gen_intermediate_code() by Lluís Vilanova · 8 years ago
  86. 68cedf7 target/arm: optimize aarch32 rev16 by Aurelien Jarno · 8 years ago
  87. abb1066 target/arm: Optimize aarch64 rev16 by Richard Henderson · 8 years ago
  88. b29fd33 target/arm: use DISAS_EXIT for eret handling by Alex Bennée · 8 years ago
  89. 0b609cc target/arm: use gen_goto_tb for ISB handling by Alex Bennée · 8 years ago
  90. 4cae8f5 target/arm/translate: ensure gen_goto_tb sets exit flags by Alex Bennée · 8 years ago
  91. abd1fb0 target/arm/translate.h: expand comment on DISAS_EXIT by Alex Bennée · 8 years ago
  92. e8d52302 target/arm/translate: make DISAS_UPDATE match declared semantics by Alex Bennée · 8 years ago
  93. 8d92e26 target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions by Peter Maydell · 8 years ago
  94. 792dac3 target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode by Peter Maydell · 8 years ago
  95. 5d721b7 ARM: KVM: Enable in-kernel timers with user space gic by Alexander Graf · 8 years ago
  96. 8da54b2 target/arm: Exit after clearing aarch64 interrupt mask by Richard Henderson · 8 years ago
  97. a65afaa Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging by Peter Maydell · 8 years ago
  98. 15f8b14 numa: move numa_node from CPUState into target specific classes by Igor Mammedov · 8 years ago
  99. e75449a target/aarch64: optimize indirect branches by Emilio G. Cota · 8 years ago
  100. e787223 target/aarch64: optimize cross-page direct jumps in softmmu by Emilio G. Cota · 8 years ago