- b5cf742 accel/tcg: Remove TranslatorOps.breakpoint_check by Richard Henderson · 3 years, 8 months ago
- 70c6eb4 target/xtensa: Use translator_use_goto_tb by Richard Henderson · 3 years, 9 months ago
- 1797b08 tcg: Avoid including 'trace-tcg.h' in target translate.c by Philippe Mathieu-Daudé · 3 years, 8 months ago
- 583e6a5 target/xtensa: clean up unaligned access by Max Filippov · 3 years, 10 months ago
- 735aa90 target/xtensa: fix access ring in l32ex by Max Filippov · 3 years, 10 months ago
- cb2d627 target/xtensa: don't generate extra EXCP_DEBUG on exception by Max Filippov · 3 years, 11 months ago
- f689bef target/xtensa: Make sure that tb->size != 0 by Ilya Leoshkevich · 3 years, 11 months ago
- 6b5fe13 semihosting: Move include/hw/semihosting/ -> include/semihosting/ by Philippe Mathieu-Daudé · 4 years ago
- f8c6137 target/xtensa: implement FPU division and square root by Max Filippov · 5 years ago
- cfa9f05 target/xtensa: add DFPU registers and opcodes by Max Filippov · 4 years, 8 months ago
- 5dbb4c9 target/xtensa: don't access BR regfile directly by Max Filippov · 4 years, 8 months ago
- ff35a7d target/xtensa: move FSR/FCR register accessors by Max Filippov · 10 years ago
- 5680f20 target/xtensa: rename FPU2000 translators and helpers by Max Filippov · 10 years ago
- ed07f68 target/xtensa: support copying registers up to 64 bits wide by Max Filippov · 5 years ago
- ee659da target/xtensa: add geometry to xtensa_get_regfile_by_name by Max Filippov · 4 years, 8 months ago
- 91dc2b2 target/xtensa: make opcode properties more dynamic by Max Filippov · 4 years, 10 months ago
- 8a3a814 target/xtensa: drop gen_io_end call by Max Filippov · 4 years, 9 months ago
- 62ed68e target/xtensa: fix simcall for newer hardware by Max Filippov · 4 years, 10 months ago
- 59afd43 target/xtensa: work around missing SR definitions by Max Filippov · 4 years, 10 months ago
- fde557a target/xtensa: statically allocate xtensa_insnbufs in DisasContext by Max Filippov · 5 years ago
- 1a03362 target/xtensa: fix pasto in pfwait.r opcode name by Max Filippov · 5 years ago
- 1f089c6 target/xtensa: add FIXME for translation memory leak by Alex Bennée · 5 years ago
- dcb32f1 tcg: Search includes from the project root source directory by Philippe Mathieu-Daudé · 5 years ago
- 6c43805 target/xtensa: fix ps.ring use in MPU configs by Max Filippov · 5 years ago
- 4d246bb target/xtensa: fetch code with translator_ld by Emilio G. Cota · 6 years ago
- 9e9b10c icount: remove unnecessary gen_io_end calls by Pavel Dovgalyuk · 6 years ago
- d5938f2 Clean up inclusion of sysemu/sysemu.h by Markus Armbruster · 6 years ago
- f1672e6 semihosting: move semihosting configuration into its own directory by Alex Bennée · 6 years ago
- 293c76c Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging by Peter Maydell · 6 years ago
- b345e14 target/xtensa: implement exclusive access option by Max Filippov · 6 years ago
- c884400 target/xtensa: implement block prefetch option opcodes by Max Filippov · 6 years ago
- 75eed0e target/xtensa: implement DIWBUI.P opcode by Max Filippov · 6 years ago
- e1c4786 target/xtensa: Use tcg_gen_abs_i32 by Richard Henderson · 6 years ago
- 4d04ea3 target/xtensa: implement MPU option by Max Filippov · 6 years ago
- 631a77a target/xtensa: add parity/ECC option SRs by Max Filippov · 6 years ago
- 5941960 target/xtensa: get rid of centralized SR properties by Max Filippov · 6 years ago
- 8b86d6d tcg: Hoist max_insns computation to tb_gen_code by Richard Henderson · 6 years ago
- 90c84c5 qom/cpu: Simplify how CPUClass:cpu_dump_state() prints by Markus Armbruster · 6 years ago
- b9ec521 target/xtensa: fix break_dependency for repeated resources by Max Filippov · 6 years ago
- eb3f429 target/xtensa: implement PREFCTL SR by Max Filippov · 6 years ago
- 068e538 target/xtensa: prioritize load/store in FLIX bundles by Max Filippov · 6 years ago
- 89bec9e target/xtensa: break circular register dependencies by Max Filippov · 6 years ago
- 575e962 target/xtensa: reorganize access to boolean registers by Max Filippov · 6 years ago
- 7aa7834 target/xtensa: reorganize access to MAC16 registers by Max Filippov · 6 years ago
- b0b24bd target/xtensa: reorganize register handling in translators by Max Filippov · 6 years ago
- c949009 target/xtensa: only rotate window in the retw helper by Max Filippov · 6 years ago
- 8df3fd3 target/xtensa: move WINDOW_BASE SR update to postprocessing by Max Filippov · 6 years ago
- 45b71a7 target/xtensa: add generic instruction post-processing by Max Filippov · 6 years ago
- 20e9fd0 target/xtensa: sort FLIX instruction opcodes by Max Filippov · 6 years ago
- fa6bc73 target/xtensa: implement wide branches and loops by Max Filippov · 6 years ago
- d863fcf target/xtensa: allow multiple names for single opcode by Max Filippov · 6 years ago
- 7590397 target/xtensa: don't require opcode table sorting by Max Filippov · 6 years ago
- 9791e7e target/xtensa: get rid of gen_callw[i] by Max Filippov · 6 years ago
- fe7869d target/xtensa: don't specify windowed registers manually by Max Filippov · 6 years ago
- fa92bd4 target/xtensa: fix access to the INTERRUPT SR by Max Filippov · 6 years ago
- 5d630ce target/xtensa: rework zero overhead loops implementation by Max Filippov · 6 years ago
- d74624e target/xtensa: extract gen_check_interrupts call by Max Filippov · 7 years ago
- c7159ac target/xtensa: make rsr/wsr helpers return void by Max Filippov · 7 years ago
- bf52510 target/xtensa: extract unconditional TB termination via slot 0 by Max Filippov · 7 years ago
- 06ec08a target/xtensa: always end TB on CCOUNT access/CCOMPARE write by Max Filippov · 7 years ago
- 9dccbd1 target/xtensa: change SR number checks to assertions by Max Filippov · 7 years ago
- 226444a target/xtensa: extract unconditional TB termination by Max Filippov · 7 years ago
- 4a03895 target/xtensa: extract test for division by zero by Max Filippov · 7 years ago
- 582fef0 target/xtensa: extract test for cpdisabled exception by Max Filippov · 7 years ago
- 90d6494 target/xtensa: extract test for alloca exception by Max Filippov · 7 years ago
- f473019 target/xtensa: extract test for window underflow exception by Max Filippov · 7 years ago
- 6416d16 target/xtensa: extract test for window overflow exception by Max Filippov · 7 years ago
- 1547781 target/xtensa: extract test for debug exception by Max Filippov · 7 years ago
- 4c6ec5f target/xtensa: extract test for syscall instruction by Max Filippov · 7 years ago
- 21a2dad target/xtensa: extract test for privileged instruction by Max Filippov · 7 years ago
- 0946097 target/xtensa: extract test for an illegal instruction by Max Filippov · 7 years ago
- 7a54cfb target/xtensa: fix s32c1i TCGMemOp flags by Max Filippov · 6 years ago
- e8e05fd target/xtensa: fix FPU2000 bugs by Max Filippov · 7 years ago
- 9c509ff target/xtensa: Convert to TranslatorOps by Richard Henderson · 7 years ago
- 1d38a70 target/xtensa: Change gen_intermediate_code dc to pointer by Richard Henderson · 7 years ago
- 3cc18ee target/xtensa: Convert to DisasContextBase by Richard Henderson · 7 years ago
- f3531da target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN by Richard Henderson · 7 years ago
- f40385c target/xtensa: check zero overhead loop alignment by Max Filippov · 7 years ago
- 8e96f59 target/xtensa: Add trailing '\n' to qemu_log() calls by Philippe Mathieu-Daudé · 7 years ago
- 07ea28b tcg: Pass tb and index to tcg_gen_exit_tb separately by Richard Henderson · 7 years ago
- 9802316 Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into staging by Peter Maydell · 7 years ago
- 4a4ff4c Remove unnecessary variables for function return value by Laurent Vivier · 7 years ago
- f29c0b1 target/xtensa: Honor CPU_DUMP_FPU by Richard Henderson · 7 years ago
- f5583c5 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510' into staging by Peter Maydell · 7 years ago
- 426afc3 target/xtensa: Use new min/max expanders by Richard Henderson · 7 years ago
- 4e8b44b target/xtensa: avoid integer overflow in next_page PC check by Emilio G. Cota · 7 years ago
- ba7651f target/xtensa: add linux-user support by Max Filippov · 8 years ago
- 9fb4034 target/xtensa: support MTTCG by Max Filippov · 8 years ago
- b9317a2 target/xtensa: mark register windows in the dump by Max Filippov · 7 years ago
- b55b1af target/xtensa: dump correct physical registers by Max Filippov · 7 years ago
- 82de978 Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into staging by Peter Maydell · 7 years ago
- 847a647 target/xtensa: disas/xtensa: fix coverity warnings by Max Filippov · 7 years ago
- a3380cf target/xtensa: Remove duplicate typedef of DisasContext by Peter Maydell · 7 years ago
- c5ac936 target/xtensa: implement const16 by Max Filippov · 7 years ago
- e987274 target/xtensa: implement GPIO32 by Max Filippov · 8 years ago
- d1e9b00 target/xtensa: implement salt/saltu by Max Filippov · 8 years ago
- 13f6a7c target/xtensa: add internal/noop SRs and opcodes by Max Filippov · 8 years ago
- 5b9b276 target/xtensa: drop DisasContext::litbase by Max Filippov · 8 years ago
- 33071f6 target/xtensa: use libisa for instruction decoding by Max Filippov · 7 years ago
- c04e169 target/xtensa: extract FPU2000 opcode translators by Max Filippov · 7 years ago
