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0f26386c27d977d523c1e88410414af7739a1730
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target-arm
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translate.c
fb0e8e7
Fix masking of PC lower bits when doing exception returns
by Peter Maydell
· 8 years ago
9b6a3ea
target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
by Peter Maydell
· 8 years ago
61e4c43
target-arm: Generate fences in ARMv7 frontend
by Pranith Kumar
· 8 years ago
7c25504
exec: [tcg] Track which vCPU is performing translation and execution
by Lluís Vilanova
· 9 years ago
fe8fcf3
target-arm: Don't permit ARMv8-only Neon insns on ARMv7
by Peter Maydell
· 9 years ago
aaa1f95
target-arm: A64: Create Instruction Syndromes for Data Aborts
by Edgar E. Iglesias
· 9 years ago
63c9155
cpu: move exec-all.h inclusion out of cpu.h
by Paolo Bonzini
· 9 years ago
90aa39a
tcg: Allow goto_tb to any target PC in user mode
by Sergey Fedorov
· 9 years ago
5b053a4
tcg: Clean up direct block chaining safety checks
by Sergey Fedorov
· 9 years ago
0648607
target-arm: dfilter support for in_asm
by Alex Bennée
· 9 years ago
8bfd055
target-arm: Implement MRS (banked) and MSR (banked) instructions
by Peter Maydell
· 9 years ago
ba63cf4
target-arm: Only trap SRS from S-EL1 if specified mode is MON
by Ralf-Philipp Weinmann
· 9 years ago
e334bd3
target-arm: implement BE32 mode in system emulation
by Paolo Bonzini
· 9 years ago
9886ecd
target-arm: implement setend
by Paolo Bonzini
· 9 years ago
91cca2c
target-arm: introduce tbflag for endianness
by Peter Crosthwaite
· 9 years ago
dacf0a2
target-arm: introduce disas flag for endianness
by Paolo Bonzini
· 9 years ago
12dcc32
target-arm: pass DisasContext to gen_aa32_ld*/st*
by Paolo Bonzini
· 9 years ago
f9fd40e
target-arm: implement SCTLR.B, drop bswap_code
by Paolo Bonzini
· 9 years ago
1bcea73
tcg: Add type for vCPU pointers
by Lluís Vilanova
· 9 years ago
235ea1f
target-arm: Give CPSR setting on 32-bit exception return its own helper
by Peter Maydell
· 9 years ago
f01377f
target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case
by Peter Maydell
· 9 years ago
cbc0326
target-arm: Clean up trap/undef handling of SRS
by Peter Maydell
· 9 years ago
7d197d2
target-arm: Fix IL bit reported for Thumb VFP and Neon traps
by Peter Maydell
· 9 years ago
4df3225
target-arm: Fix IL bit reported for Thumb coprocessor traps
by Peter Maydell
· 9 years ago
3f208fd
target-arm: Add isread parameter to CPAccessFns
by Peter Maydell
· 9 years ago
e1ccc05
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr
by Richard Henderson
· 11 years ago
2015770
tcg: Remove lingering references to gen_opc_buf
by Richard Henderson
· 9 years ago
508127e
log: do not unnecessarily include qom/cpu.h
by Paolo Bonzini
· 9 years ago
74c21bd
target-arm: Clean up includes
by Peter Maydell
· 9 years ago
7999a5c
target-arm: Fix and improve AA32 singlestep translation completion code
by Sergey Fedorov
· 9 years ago
3090147
target-arm: raise exception on misaligned LDREX operands
by Andrew Baumann
· 9 years ago
ce8a1b5
target-arm: Update condexec before arch BP check in AA32 translation
by Sergey Fedorov
· 9 years ago
43bfa4a
target-arm: Update condexec before CP access check in AA32 translation
by Sergey Fedorov
· 9 years ago
ed6c644
target-arm: Update PC before calling gen_helper_check_breakpoints()
by Sergey Fedorov
· 9 years ago
577bf80
target-arm: Clean up DISAS_UPDATE usage in AArch32 translation code
by Sergey Fedorov
· 9 years ago
06e5cf7
target-arm: Report S/NS status in the CPU debug logs
by Peter Maydell
· 9 years ago
522a0d4
target-*: Advance pc after recognizing a breakpoint
by Richard Henderson
· 9 years ago
541ebcd
target-arm/translate.c: Handle non-executable page-straddling Thumb insns
by Peter Maydell
· 9 years ago
5d98bf8
target-arm: Fix CPU breakpoint handling
by Sergey Fedorov
· 9 years ago
6df99de
target-arm: Break the TB after ISB to execute self-modified code correctly
by Sergey Sorokin
· 9 years ago
4e5e121
tcg: Remove gen_intermediate_code_pc
by Richard Henderson
· 9 years ago
bad729e
tcg: Pass data argument to restore_state_to_opc
by Richard Henderson
· 9 years ago
190ce7f
tcg: Add TCG_MAX_INSNS
by Richard Henderson
· 9 years ago
52e971d
target-arm: Add condexec state to insn_start
by Richard Henderson
· 9 years ago
b933066
target-*: Introduce and use cpu_breakpoint_test
by Richard Henderson
· 9 years ago
959082f
target-*: Increment num_insns immediately after tcg_gen_insn_start
by Richard Henderson
· 9 years ago
667b8e2
target-*: Unconditionally emit tcg_gen_insn_start
by Richard Henderson
· 9 years ago
765b842
tcg: Rename debug_insn_start to insn_start
by Richard Henderson
· 9 years ago
9305eac
target-arm: Handle always condition codes within arm_test_cc
by Richard Henderson
· 9 years ago
6c2c63d
target-arm: Introduce DisasCompare
by Richard Henderson
· 9 years ago
78bcaa3
target-arm: Share all common TCG temporaries
by Richard Henderson
· 9 years ago
b6af097
maint: remove / fix many doubled words
by Daniel P. Berrange
· 9 years ago
cef9ee7
target-arm: Fix default_exception_el() function for the case when EL3 is not supported
by Sergey Sorokin
· 9 years ago
ecc7b3a
tcg: Remove tcg_gen_trunc_i64_i32
by Richard Henderson
· 9 years ago
c87e5a6
target-arm: Implement YIELD insn to yield in ARM and Thumb translators
by Peter Maydell
· 9 years ago
d49190c
disas: Remove uses of CPU env
by Peter Crosthwaite
· 10 years ago
3977ee5
target-arm: Correct "preferred return address" for cpreg access exceptions
by Peter Maydell
· 10 years ago
62b44f0
target-arm: Add the THUMB_DSP feature
by Aurelio C. Remonda
· 10 years ago
3960c33
target-arm: Avoid buffer overrun on UNPREDICTABLE ldrd/strd
by Peter Maydell
· 10 years ago
84549b6
target-arm: Don't halt on WFI unless we don't have any work
by Peter Maydell
· 10 years ago
9dbbc74
target-arm: Extend FP checks to use an EL
by Greg Bellows
· 10 years ago
7371036
target-arm: Add exception target el infrastructure
by Greg Bellows
· 10 years ago
da3e53d
target-arm: Fix handling of STM (user) with r15 in register list
by Peter Maydell
· 10 years ago
42a268c
tcg: Change translator-side labels to a pointer
by Richard Henderson
· 10 years ago
fe700ad
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
by Richard Henderson
· 11 years ago
0a7df5d
tcg: Move emit of INDEX_op_end into gen_tb_end
by Richard Henderson
· 11 years ago
579d21c
target-arm: Use correct mmu_idx for unprivileged loads and stores
by Peter Maydell
· 10 years ago
c1e3781
target-arm: Define correct mmu_idx values and pass them in TB flags
by Peter Maydell
· 10 years ago
45140a5
target-arm: check that LSB <= MSB in BFI instruction
by Kirill Batuzov
· 10 years ago
cd42d5b
gen-icount: check cflags instead of use_icount global
by Paolo Bonzini
· 10 years ago
bd79255
translate: check cflags instead of use_icount global
by Paolo Bonzini
· 10 years ago
51a79b0
target-arm: add secure state bit to CPREG hash
by Peter Maydell
· 10 years ago
3f342b9
target-arm: add non-secure Translation Block flag
by Sergey Fedorov
· 10 years ago
f4df221
target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()
by Peter Maydell
· 10 years ago
7dcc1f8
target-arm/translate.c: Don't pass CPUARMState around in the decoder
by Peter Maydell
· 10 years ago
b53d892
target-arm/translate.c: Don't use IS_M()
by Peter Maydell
· 10 years ago
d614a51
target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()
by Peter Maydell
· 10 years ago
2b51668
target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macros
by Peter Maydell
· 10 years ago
dcbff19
target-arm: rename arm_current_pl to arm_current_el
by Greg Bellows
· 10 years ago
23adb86
target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0
by Peter Maydell
· 10 years ago
37e6456
target-arm: Add support for A32 and T32 HVC and SMC insns
by Peter Maydell
· 10 years ago
c0f4af1
target-arm: Don't handle c15_cpar changes via tb_flush()
by Peter Maydell
· 10 years ago
50225ad
target-arm: Implement ARMv8 single-stepping for AArch32 code
by Peter Maydell
· 10 years ago
4051e12
target-arm: Don't allow AArch32 to access RES0 CPSR bits
by Peter Maydell
· 10 years ago
a7e30d8
trace: [tcg] Include TCG-tracing header on all targets
by Lluís Vilanova
· 11 years ago
3b1a413
target-arm: Delete unused iwmmxt_msadb helper
by Peter Maydell
· 11 years ago
aa63346
target-arm: A32/T32: Mask CRC value in calling code, not helper
by Peter Maydell
· 11 years ago
4e624ed
target-arm: add support for v8 VMULL.P64 instruction
by Peter Maydell
· 11 years ago
526d009
target-arm: Allow 3reg_wide undefreq to encode more bad size options
by Peter Maydell
· 11 years ago
f1ecb91
target-arm: add support for v8 SHA1 and SHA256 instructions
by Ard Biesheuvel
· 11 years ago
1d85476
target-arm: move arm_*_code to a separate file
by Paolo Bonzini
· 11 years ago
2ef6175
tcg: Invert the inclusion of helper.h
by Richard Henderson
· 11 years ago
28c9457
target-arm: Add SPSR entries for EL2/HYP and EL3/MON
by Edgar E. Iglesias
· 11 years ago
6ce2faf
target-arm: A32: Use get_mem_index for load/stores
by Edgar E. Iglesias
· 11 years ago
c119779
target-arm/translate.c: Use get_mem_index() for SRS memory accesses
by Peter Maydell
· 11 years ago
a99caa4
target-arm/translate.c: Clean up mmu index handling for ldrt/strt
by Peter Maydell
· 11 years ago
33bbd75
arm: translate.c: Fix smlald Instruction
by Peter Crosthwaite
· 11 years ago
1773111
target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32
by Peter Maydell
· 11 years ago
a50c0f5
target-arm: Implement ARMv8 MVFR registers
by Peter Maydell
· 11 years ago
2c7ffc4
target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1
by Peter Maydell
· 11 years ago
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