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qemu / qemu / 09cca043bf68719f93f0ce1f1efafbec4ca72229 / target / mips / cpu.h
  1. 8ec7e3c target/mips: Use an exception for semihosting by Richard Henderson · 2 years, 10 months ago
  2. 5de4359 target/mips: Fix emulation of nanoMIPS BPOSGE32C instruction by Dragan Mladjenovic · 2 years, 10 months ago
  3. a6bc80f target/mips: Fix WatchHi.M handling by Marcin Nowakowski · 3 years, 9 months ago
  4. e03b568 Replace config-time define HOST_WORDS_BIGENDIAN by Marc-André Lureau · 3 years ago
  5. f14ad81 Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into staging by Peter Maydell · 3 years ago
  6. 5e0c126 target/mips: Remove duplicated MIPSCPU::cp0_count_rate by Philippe Mathieu-Daudé · 3 years, 3 months ago
  7. b36e239 target: Use ArchCPU as interface to target CPU by Philippe Mathieu-Daudé · 3 years, 1 month ago
  8. 9295b1a target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro by Philippe Mathieu-Daudé · 3 years, 1 month ago
  9. 1ea4a06 target: Use CPUArchState as interface to target-specific CPU state by Philippe Mathieu-Daudé · 3 years, 1 month ago
  10. 8b1d5b3 include/exec: Move cpu_signal_handler declaration by Richard Henderson · 3 years, 7 months ago
  11. 85ccd96 target/mips: Restrict some system specific declarations to sysemu by Philippe Mathieu-Daudé · 3 years, 10 months ago
  12. cefd68f target/mips: Promote 128-bit multimedia registers as global ones by Philippe Mathieu-Daudé · 4 years, 1 month ago
  13. e78d4ab target/mips: Remove unused MMU definitions by Philippe Mathieu-Daudé · 4 years, 1 month ago
  14. 25a1362 target/mips: Introduce ase_msa_available() helper by Philippe Mathieu-Daudé · 4 years, 3 months ago
  15. b0586b3 target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() by Philippe Mathieu-Daudé · 4 years, 3 months ago
  16. 07ae8cc target/mips/addr: Add translation helpers for KSEG1 by Jiaxun Yang · 4 years, 3 months ago
  17. 8cd0b41 target/mips: Add CP0 Config0 register definitions for MIPS3 ISA by Philippe Mathieu-Daudé · 4 years, 3 months ago
  18. ce54384 linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro by Philippe Mathieu-Daudé · 4 years, 3 months ago
  19. 17c2c32 target/mips: Introduce ase_mt_available() helper by Philippe Mathieu-Daudé · 4 years, 3 months ago
  20. 2fd9c5a hw/mips: Move address translation helpers to target/mips/ by Philippe Mathieu-Daudé · 4 years, 3 months ago
  21. df6adb6 target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument by Philippe Mathieu-Daudé · 4 years, 3 months ago
  22. ac70f97 target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT() by Philippe Mathieu-Daudé · 4 years, 3 months ago
  23. d40b55b target/mips: Fix PageMask with variable page size by Jiaxun Yang · 4 years, 4 months ago
  24. 7aaab96 target/mips/cpu: Introduce mips_cpu_create_with_clock() helper by Philippe Mathieu-Daudé · 4 years, 5 months ago
  25. a0713e8 target/mips/cpu: Allow the CPU to use dynamic frequencies by Philippe Mathieu-Daudé · 4 years, 5 months ago
  26. d0bec21 target/mips/cpu: Make cp0_count_rate a property by Philippe Mathieu-Daudé · 4 years, 5 months ago
  27. d225b51 target/mips: Move cp0_count_ns to CPUMIPSState by Philippe Mathieu-Daudé · 4 years, 5 months ago
  28. af86899 target/mips: Add Loongson-3 CPU definition by Huacai Chen · 4 years, 9 months ago
  29. 99029be target/mips: Add implementation of GINVT instruction by Yongbok Kim · 5 years ago
  30. feafe82 target/mips: Amend CP0 WatchHi register implementation by Yongbok Kim · 5 years ago
  31. 7dd547e target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX by Richard Henderson · 5 years ago
  32. 14d92ef target/mips: Clean up handling of CP0 register 31 by Aleksandar Markovic · 6 years ago
  33. af4bb6d target/mips: Clean up handling of CP0 register 29 by Aleksandar Markovic · 6 years ago
  34. a30e2f2 target/mips: Clean up handling of CP0 register 28 by Aleksandar Markovic · 6 years ago
  35. dbbf08b target/mips: Clean up handling of CP0 register 26 by Aleksandar Markovic · 6 years ago
  36. 4cbf4b6 target/mips: Clean up handling of CP0 register 23 by Aleksandar Markovic · 6 years ago
  37. be274dc target/mips: Clean up handling of CP0 register 19 by Aleksandar Markovic · 6 years ago
  38. e8dcfe8 target/mips: Clean up handling of CP0 register 18 by Aleksandar Markovic · 6 years ago
  39. 433efb4 target/mips: Clean up handling of CP0 register 16 by Aleksandar Markovic · 6 years ago
  40. 4466cd4 target/mips: Clean up handling of CP0 register 15 by Aleksandar Markovic · 6 years ago
  41. 35e4b54 target/mips: Clean up handling of CP0 register 14 by Aleksandar Markovic · 6 years ago
  42. e3c7559 target/mips: Clean up handling of CP0 register 13 by Aleksandar Markovic · 6 years ago
  43. 2b08486 target/mips: Clean up handling of CP0 register 12 by Aleksandar Markovic · 6 years ago
  44. 860ffef target/mips: Clean up handling of CP0 register 10 by Aleksandar Markovic · 6 years ago
  45. 67d167d target/mips: Clean up handling of CP0 register 8 by Aleksandar Markovic · 6 years ago
  46. 9023594 target/mips: Clean up handling of CP0 register 6 by Aleksandar Markovic · 6 years ago
  47. a1e7635 target/mips: Clean up handling of CP0 register 5 by Aleksandar Markovic · 6 years ago
  48. 020fe37 target/mips: Clean up handling of CP0 register 4 by Aleksandar Markovic · 6 years ago
  49. acd3731 target/mips: Clean up handling of CP0 register 3 by Aleksandar Markovic · 6 years ago
  50. 6d27d5b target/mips: Clean up handling of CP0 register 2 by Aleksandar Markovic · 6 years ago
  51. 30deb46 target/mips: Clean up handling of CP0 register 1 by Aleksandar Markovic · 6 years ago
  52. 1b142da target/mips: Clean up handling of CP0 register 0 by Aleksandar Markovic · 6 years ago
  53. 52bf977 configure: Define target access alignment in configure by tony.nguyen@bt.com · 6 years ago
  54. 502700d target/mips: rationalise softfloat includes by Alex Bennée · 6 years ago
  55. a8d2532 Include qemu-common.h exactly where needed by Markus Armbruster · 6 years ago
  56. e8b5fae cpu: Remove CPU_COMMON by Richard Henderson · 6 years ago
  57. 5b146dc cpu: Introduce CPUNegativeOffsetState by Richard Henderson · 6 years ago
  58. 677c4d6 cpu: Move ENV_OFFSET to exec/gen-icount.h by Richard Henderson · 6 years ago
  59. 5a7330b target/mips: Use env_cpu, env_archcpu by Richard Henderson · 6 years ago
  60. 29a0af6 cpu: Replace ENV_GET_CPU with env_cpu by Richard Henderson · 6 years ago
  61. 2161a61 cpu: Define ArchCPU by Richard Henderson · 6 years ago
  62. 4f7c64b cpu: Define CPUArchState with typedef by Richard Henderson · 6 years ago
  63. 74433bf tcg: Split out target/arch/cpu-param.h by Richard Henderson · 6 years ago
  64. 9e72f33 target/mips: realign comments to fix checkpatch warnings by Jules Irenge · 6 years ago
  65. 8ebf2e1 target/mips: add or remove space to fix checkpatch errors by Jules Irenge · 6 years ago
  66. 0442428 target: Simplify how the TARGET_cpu_list() print by Markus Armbruster · 6 years ago
  67. 0454728 target/mips: introduce MTTCG-enabled builds by Aleksandar Markovic · 6 years ago
  68. 33a07fa target/mips: reimplement SC instruction emulation and use cmpxchg by Leon Alrae · 6 years ago
  69. c7c7e1e target/mips: compare virtual addresses in LL/SC sequence by Leon Alrae · 6 years ago
  70. 5b1e098 target/mips: Correct the second argument type of cpu_supports_isa() by Aleksandar Markovic · 6 years ago
  71. a168a79 target/mips: Introduce 32 R5900 multimedia registers by Fredrik Noring · 6 years ago
  72. 3ef521e target/mips: Add CP0 register MemoryMapID by Aleksandar Markovic · 6 years ago
  73. 04992c8 target/mips: Amend preprocessor constants for CP0 registers by Aleksandar Markovic · 6 years ago
  74. 043715d target/mips: Update ITU to utilize SAARI and SAAR CP0 registers by Yongbok Kim · 6 years ago
  75. 5fb2dcd target/mips: Provide R/W access to SAARI and SAAR CP0 registers by Yongbok Kim · 6 years ago
  76. 167db30 target/mips: Add fields for SAARI and SAAR CP0 registers by Yongbok Kim · 6 years ago
  77. efd27d3 target/mips: Add preprocessor constants for 32 major CP0 registers by Aleksandar Markovic · 6 years ago
  78. ea9c5e8 target/mips: Move comment containing summary of CP0 registers by Aleksandar Markovic · 6 years ago
  79. eb5559f target/mips: Introduce MXU registers by Craig Janeczek · 6 years ago
  80. 103be64 target/mips: Add CP0 PWCtl register by Yongbok Kim · 6 years ago
  81. 20b28eb target/mips: Add CP0 PWSize register by Yongbok Kim · 6 years ago
  82. fa75ad1 target/mips: Add CP0 PWField register by Yongbok Kim · 6 years ago
  83. 5e31fdd target/mips: Add CP0 PWBase register by Yongbok Kim · 6 years ago
  84. 908f6be target/mips: Improve DSP R2/R3-related naming by Stefan Markovic · 6 years ago
  85. 6208f09 target/mips: Add bit definitions for DSP R3 ASE by Stefan Markovic · 6 years ago
  86. f9c9cd6 target/mips: Increase 'supported ISAs/ASEs' flag holder size by Philippe Mathieu-Daudé · 6 years ago
  87. 50e7edc target/mips: Add a comment before each CP0 register section in cpu.h by Aleksandar Markovic · 6 years ago
  88. a86d421 target/mips: Add a comment with an overview of CP0 registers by Aleksandar Markovic · 6 years ago
  89. 0b16dcd target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair by Aleksandar Rikalo · 7 years ago
  90. 25beba9 target/mips: Add CP0 BadInstrX register by Stefan Markovic · 7 years ago
  91. 0413d7a target/mips: Update some CP0 registers bit definitions by Aleksandar Markovic · 7 years ago
  92. 3f71e72 cpu: get rid of unused cpu_init() defines by Igor Mammedov · 7 years ago
  93. 0dacec8 cpu: add CPU_RESOLVING_TYPE macro by Igor Mammedov · 7 years ago
  94. a7519f2 mips: malta/boston: replace cpu_model with cpu_type by Igor Mammedov · 7 years ago
  95. c4c8146c mips: replace cpu_mips_init() with cpu_generic_init() by Igor Mammedov · 7 years ago
  96. 26aa3d9 mips: introduce internal.h and cleanup cpu.h by Philippe Mathieu-Daudé · 7 years ago
  97. cec56a7 target/mips: Add segmentation control registers by James Hogan · 8 years ago
  98. 42c8661 target/mips: Add an MMU mode for ERL by James Hogan · 8 years ago
  99. b0fc600 target/mips: Abstract mmu_idx from hflags by James Hogan · 8 years ago
  100. 74dbf82 target/mips: Add CP0_Ebase.WG (write gate) support by James Hogan · 8 years ago