Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * RISC-V Control and Status Registers. |
| 3 | * |
| 4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu |
| 5 | * Copyright (c) 2017-2018 SiFive, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2 or later, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qemu/log.h" |
Philippe Mathieu-Daudé | b8012ec | 2022-02-07 09:27:54 +0100 | [diff] [blame] | 22 | #include "qemu/timer.h" |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 23 | #include "cpu.h" |
Daniel Henrique Barboza | 36c1118 | 2023-09-25 14:56:53 -0300 | [diff] [blame] | 24 | #include "tcg/tcg-cpu.h" |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 25 | #include "pmu.h" |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 26 | #include "time_helper.h" |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 27 | #include "exec/exec-all.h" |
Alex Bennée | 548c960 | 2023-03-02 18:57:43 -0800 | [diff] [blame] | 28 | #include "exec/tb-flush.h" |
Philippe Mathieu-Daudé | 03ff4f8 | 2022-01-22 14:23:41 +0100 | [diff] [blame] | 29 | #include "sysemu/cpu-timers.h" |
Weiwei Li | 7744238 | 2022-04-23 10:35:08 +0800 | [diff] [blame] | 30 | #include "qemu/guest-random.h" |
| 31 | #include "qapi/error.h" |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 32 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 33 | /* CSR function table public API */ |
| 34 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) |
| 35 | { |
| 36 | *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; |
| 37 | } |
| 38 | |
| 39 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) |
| 40 | { |
| 41 | csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; |
| 42 | } |
| 43 | |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 44 | /* Predicates */ |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 45 | #if !defined(CONFIG_USER_ONLY) |
Weiwei Li | ce3af0b | 2023-03-07 16:14:00 +0800 | [diff] [blame] | 46 | RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 47 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 48 | bool virt = env->virt_enabled; |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 49 | |
Daniel Henrique Barboza | a9a4e39 | 2023-02-24 14:45:19 -0300 | [diff] [blame] | 50 | if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 51 | return RISCV_EXCP_NONE; |
| 52 | } |
| 53 | |
| 54 | if (!(env->mstateen[index] & bit)) { |
| 55 | return RISCV_EXCP_ILLEGAL_INST; |
| 56 | } |
| 57 | |
| 58 | if (virt) { |
| 59 | if (!(env->hstateen[index] & bit)) { |
| 60 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 61 | } |
| 62 | |
| 63 | if (env->priv == PRV_U && !(env->sstateen[index] & bit)) { |
| 64 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { |
| 69 | if (!(env->sstateen[index] & bit)) { |
| 70 | return RISCV_EXCP_ILLEGAL_INST; |
| 71 | } |
| 72 | } |
| 73 | |
| 74 | return RISCV_EXCP_NONE; |
| 75 | } |
| 76 | #endif |
| 77 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 78 | static RISCVException fs(CPURISCVState *env, int csrno) |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 79 | { |
| 80 | #if !defined(CONFIG_USER_ONLY) |
Weiwei Li | c163b3b | 2022-02-11 12:39:16 +0800 | [diff] [blame] | 81 | if (!env->debugger && !riscv_cpu_fp_enabled(env) && |
Daniel Henrique Barboza | a9a4e39 | 2023-02-24 14:45:19 -0300 | [diff] [blame] | 82 | !riscv_cpu_cfg(env)->ext_zfinx) { |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 83 | return RISCV_EXCP_ILLEGAL_INST; |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 84 | } |
Mayuresh Chitale | 9514fc7 | 2023-05-18 23:20:56 +0530 | [diff] [blame] | 85 | |
| 86 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
| 87 | return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); |
| 88 | } |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 89 | #endif |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 90 | return RISCV_EXCP_NONE; |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 91 | } |
| 92 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 93 | static RISCVException vs(CPURISCVState *env, int csrno) |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 94 | { |
Jason Chien | 9fb41a4 | 2024-03-28 10:23:10 +0800 | [diff] [blame] | 95 | if (riscv_cpu_cfg(env)->ext_zve32x) { |
Frank Chang | 6bc3dfa | 2021-12-10 15:55:57 +0800 | [diff] [blame] | 96 | #if !defined(CONFIG_USER_ONLY) |
| 97 | if (!env->debugger && !riscv_cpu_vector_enabled(env)) { |
| 98 | return RISCV_EXCP_ILLEGAL_INST; |
| 99 | } |
| 100 | #endif |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 101 | return RISCV_EXCP_NONE; |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 102 | } |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 103 | return RISCV_EXCP_ILLEGAL_INST; |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 104 | } |
| 105 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 106 | static RISCVException ctr(CPURISCVState *env, int csrno) |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 107 | { |
| 108 | #if !defined(CONFIG_USER_ONLY) |
Bin Meng | 94e2970 | 2023-02-28 18:40:25 +0800 | [diff] [blame] | 109 | RISCVCPU *cpu = env_archcpu(env); |
Atish Patra | 562009e | 2022-06-20 16:15:51 -0700 | [diff] [blame] | 110 | int ctr_index; |
Atish Patra | ade445e | 2022-08-24 15:16:58 -0700 | [diff] [blame] | 111 | target_ulong ctr_mask; |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 112 | int base_csrno = CSR_CYCLE; |
Atish Patra | 18d6d89 | 2022-06-20 16:15:54 -0700 | [diff] [blame] | 113 | bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; |
Alistair Francis | 0a13a5b | 2019-06-17 18:31:22 -0700 | [diff] [blame] | 114 | |
Atish Patra | 18d6d89 | 2022-06-20 16:15:54 -0700 | [diff] [blame] | 115 | if (rv32 && csrno >= CSR_CYCLEH) { |
| 116 | /* Offset for RV32 hpmcounternh counters */ |
| 117 | base_csrno += 0x80; |
| 118 | } |
| 119 | ctr_index = csrno - base_csrno; |
Atish Patra | ade445e | 2022-08-24 15:16:58 -0700 | [diff] [blame] | 120 | ctr_mask = BIT(ctr_index); |
Atish Patra | 18d6d89 | 2022-06-20 16:15:54 -0700 | [diff] [blame] | 121 | |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 122 | if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || |
| 123 | (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) { |
Daniel Henrique Barboza | c004099 | 2023-10-23 12:39:24 -0300 | [diff] [blame] | 124 | if (!riscv_cpu_cfg(env)->ext_zicntr) { |
| 125 | return RISCV_EXCP_ILLEGAL_INST; |
| 126 | } |
| 127 | |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 128 | goto skip_ext_pmu_check; |
| 129 | } |
| 130 | |
Atish Patra | ade445e | 2022-08-24 15:16:58 -0700 | [diff] [blame] | 131 | if (!(cpu->pmu_avail_ctrs & ctr_mask)) { |
Atish Patra | 18d6d89 | 2022-06-20 16:15:54 -0700 | [diff] [blame] | 132 | /* No counter is enabled in PMU or the counter is out of range */ |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 133 | return RISCV_EXCP_ILLEGAL_INST; |
Alistair Francis | 0a13a5b | 2019-06-17 18:31:22 -0700 | [diff] [blame] | 134 | } |
Alistair Francis | e39a832 | 2020-08-12 12:13:49 -0700 | [diff] [blame] | 135 | |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 136 | skip_ext_pmu_check: |
| 137 | |
Bin Meng | fb517fd | 2023-02-28 21:45:30 +0800 | [diff] [blame] | 138 | if (env->debugger) { |
| 139 | return RISCV_EXCP_NONE; |
| 140 | } |
| 141 | |
Weiwei Li | a412829 | 2022-08-17 16:37:56 +0800 | [diff] [blame] | 142 | if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) { |
Atish Patra | ade445e | 2022-08-24 15:16:58 -0700 | [diff] [blame] | 143 | return RISCV_EXCP_ILLEGAL_INST; |
Atish Patra | a5a92fd | 2022-06-20 16:15:52 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 146 | if (env->virt_enabled) { |
Weiwei Li | a412829 | 2022-08-17 16:37:56 +0800 | [diff] [blame] | 147 | if (!get_field(env->hcounteren, ctr_mask) || |
| 148 | (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) { |
Atish Patra | ade445e | 2022-08-24 15:16:58 -0700 | [diff] [blame] | 149 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
Alistair Francis | e39a832 | 2020-08-12 12:13:49 -0700 | [diff] [blame] | 150 | } |
| 151 | } |
Weiwei Li | a412829 | 2022-08-17 16:37:56 +0800 | [diff] [blame] | 152 | |
| 153 | if (riscv_has_ext(env, RVS) && env->priv == PRV_U && |
| 154 | !get_field(env->scounteren, ctr_mask)) { |
| 155 | return RISCV_EXCP_ILLEGAL_INST; |
| 156 | } |
| 157 | |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 158 | #endif |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 159 | return RISCV_EXCP_NONE; |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 160 | } |
| 161 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 162 | static RISCVException ctr32(CPURISCVState *env, int csrno) |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 163 | { |
Richard Henderson | db23e5d | 2021-10-19 20:16:58 -0700 | [diff] [blame] | 164 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 165 | return RISCV_EXCP_ILLEGAL_INST; |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | return ctr(env, csrno); |
| 169 | } |
| 170 | |
Weiwei Li | ce3af0b | 2023-03-07 16:14:00 +0800 | [diff] [blame] | 171 | static RISCVException zcmt(CPURISCVState *env, int csrno) |
| 172 | { |
| 173 | if (!riscv_cpu_cfg(env)->ext_zcmt) { |
| 174 | return RISCV_EXCP_ILLEGAL_INST; |
| 175 | } |
| 176 | |
| 177 | #if !defined(CONFIG_USER_ONLY) |
| 178 | RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); |
| 179 | if (ret != RISCV_EXCP_NONE) { |
| 180 | return ret; |
| 181 | } |
| 182 | #endif |
| 183 | |
| 184 | return RISCV_EXCP_NONE; |
| 185 | } |
| 186 | |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 187 | #if !defined(CONFIG_USER_ONLY) |
Atish Patra | 18d6d89 | 2022-06-20 16:15:54 -0700 | [diff] [blame] | 188 | static RISCVException mctr(CPURISCVState *env, int csrno) |
| 189 | { |
Rob Bradford | 7c1bb1d | 2023-10-31 15:37:14 +0000 | [diff] [blame] | 190 | RISCVCPU *cpu = env_archcpu(env); |
| 191 | uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs; |
Atish Patra | 18d6d89 | 2022-06-20 16:15:54 -0700 | [diff] [blame] | 192 | int ctr_index; |
| 193 | int base_csrno = CSR_MHPMCOUNTER3; |
| 194 | |
| 195 | if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) { |
| 196 | /* Offset for RV32 mhpmcounternh counters */ |
Alistair Francis | 9a7c6da | 2024-01-08 10:13:26 +1000 | [diff] [blame] | 197 | csrno -= 0x80; |
Atish Patra | 18d6d89 | 2022-06-20 16:15:54 -0700 | [diff] [blame] | 198 | } |
Alistair Francis | 9a7c6da | 2024-01-08 10:13:26 +1000 | [diff] [blame] | 199 | |
| 200 | g_assert(csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31); |
| 201 | |
Atish Patra | 18d6d89 | 2022-06-20 16:15:54 -0700 | [diff] [blame] | 202 | ctr_index = csrno - base_csrno; |
Rob Bradford | 7c1bb1d | 2023-10-31 15:37:14 +0000 | [diff] [blame] | 203 | if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) { |
Weiwei Li | 3b57254 | 2023-04-05 16:58:12 +0800 | [diff] [blame] | 204 | /* The PMU is not enabled or counter is out of range */ |
Atish Patra | 18d6d89 | 2022-06-20 16:15:54 -0700 | [diff] [blame] | 205 | return RISCV_EXCP_ILLEGAL_INST; |
| 206 | } |
| 207 | |
| 208 | return RISCV_EXCP_NONE; |
| 209 | } |
| 210 | |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 211 | static RISCVException mctr32(CPURISCVState *env, int csrno) |
| 212 | { |
| 213 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
| 214 | return RISCV_EXCP_ILLEGAL_INST; |
| 215 | } |
| 216 | |
| 217 | return mctr(env, csrno); |
| 218 | } |
| 219 | |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 220 | static RISCVException sscofpmf(CPURISCVState *env, int csrno) |
| 221 | { |
Weiwei Li | 9c33e08 | 2023-03-09 15:13:26 +0800 | [diff] [blame] | 222 | if (!riscv_cpu_cfg(env)->ext_sscofpmf) { |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 223 | return RISCV_EXCP_ILLEGAL_INST; |
| 224 | } |
| 225 | |
| 226 | return RISCV_EXCP_NONE; |
| 227 | } |
| 228 | |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 229 | static RISCVException sscofpmf_32(CPURISCVState *env, int csrno) |
| 230 | { |
| 231 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
| 232 | return RISCV_EXCP_ILLEGAL_INST; |
| 233 | } |
| 234 | |
| 235 | return sscofpmf(env, csrno); |
| 236 | } |
| 237 | |
Kaiwen Xue | b54a84c | 2024-07-11 15:31:08 -0700 | [diff] [blame] | 238 | static RISCVException smcntrpmf(CPURISCVState *env, int csrno) |
| 239 | { |
| 240 | if (!riscv_cpu_cfg(env)->ext_smcntrpmf) { |
| 241 | return RISCV_EXCP_ILLEGAL_INST; |
| 242 | } |
| 243 | |
| 244 | return RISCV_EXCP_NONE; |
| 245 | } |
| 246 | |
| 247 | static RISCVException smcntrpmf_32(CPURISCVState *env, int csrno) |
| 248 | { |
| 249 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
| 250 | return RISCV_EXCP_ILLEGAL_INST; |
| 251 | } |
| 252 | |
| 253 | return smcntrpmf(env, csrno); |
| 254 | } |
| 255 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 256 | static RISCVException any(CPURISCVState *env, int csrno) |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 257 | { |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 258 | return RISCV_EXCP_NONE; |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 259 | } |
| 260 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 261 | static RISCVException any32(CPURISCVState *env, int csrno) |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 262 | { |
Richard Henderson | db23e5d | 2021-10-19 20:16:58 -0700 | [diff] [blame] | 263 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 264 | return RISCV_EXCP_ILLEGAL_INST; |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | return any(env, csrno); |
| 268 | |
| 269 | } |
| 270 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 271 | static RISCVException aia_any(CPURISCVState *env, int csrno) |
Anup Patel | d0237b4 | 2022-02-04 23:16:48 +0530 | [diff] [blame] | 272 | { |
Daniel Henrique Barboza | 01af27e | 2023-02-24 14:45:20 -0300 | [diff] [blame] | 273 | if (!riscv_cpu_cfg(env)->ext_smaia) { |
Anup Patel | d0237b4 | 2022-02-04 23:16:48 +0530 | [diff] [blame] | 274 | return RISCV_EXCP_ILLEGAL_INST; |
| 275 | } |
| 276 | |
| 277 | return any(env, csrno); |
| 278 | } |
| 279 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 280 | static RISCVException aia_any32(CPURISCVState *env, int csrno) |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 281 | { |
Daniel Henrique Barboza | 01af27e | 2023-02-24 14:45:20 -0300 | [diff] [blame] | 282 | if (!riscv_cpu_cfg(env)->ext_smaia) { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 283 | return RISCV_EXCP_ILLEGAL_INST; |
| 284 | } |
| 285 | |
| 286 | return any32(env, csrno); |
| 287 | } |
| 288 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 289 | static RISCVException smode(CPURISCVState *env, int csrno) |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 290 | { |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 291 | if (riscv_has_ext(env, RVS)) { |
| 292 | return RISCV_EXCP_NONE; |
| 293 | } |
| 294 | |
| 295 | return RISCV_EXCP_ILLEGAL_INST; |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 296 | } |
| 297 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 298 | static RISCVException smode32(CPURISCVState *env, int csrno) |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 299 | { |
| 300 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
| 301 | return RISCV_EXCP_ILLEGAL_INST; |
| 302 | } |
| 303 | |
| 304 | return smode(env, csrno); |
| 305 | } |
| 306 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 307 | static RISCVException aia_smode(CPURISCVState *env, int csrno) |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 308 | { |
Daniel Henrique Barboza | 01af27e | 2023-02-24 14:45:20 -0300 | [diff] [blame] | 309 | if (!riscv_cpu_cfg(env)->ext_ssaia) { |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 310 | return RISCV_EXCP_ILLEGAL_INST; |
| 311 | } |
| 312 | |
| 313 | return smode(env, csrno); |
| 314 | } |
| 315 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 316 | static RISCVException aia_smode32(CPURISCVState *env, int csrno) |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 317 | { |
Daniel Henrique Barboza | 01af27e | 2023-02-24 14:45:20 -0300 | [diff] [blame] | 318 | if (!riscv_cpu_cfg(env)->ext_ssaia) { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 319 | return RISCV_EXCP_ILLEGAL_INST; |
| 320 | } |
| 321 | |
| 322 | return smode32(env, csrno); |
| 323 | } |
| 324 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 325 | static RISCVException hmode(CPURISCVState *env, int csrno) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 326 | { |
Weiwei Li | 62a09b9 | 2022-07-18 21:09:54 +0800 | [diff] [blame] | 327 | if (riscv_has_ext(env, RVH)) { |
Weiwei Li | 5de1245 | 2022-07-18 21:09:55 +0800 | [diff] [blame] | 328 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 329 | } |
| 330 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 331 | return RISCV_EXCP_ILLEGAL_INST; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 332 | } |
| 333 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 334 | static RISCVException hmode32(CPURISCVState *env, int csrno) |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 335 | { |
Richard Henderson | db23e5d | 2021-10-19 20:16:58 -0700 | [diff] [blame] | 336 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
Weiwei Li | 62a09b9 | 2022-07-18 21:09:54 +0800 | [diff] [blame] | 337 | return RISCV_EXCP_ILLEGAL_INST; |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 338 | } |
| 339 | |
| 340 | return hmode(env, csrno); |
| 341 | |
| 342 | } |
| 343 | |
Weiwei Li | c126f83 | 2022-07-18 21:09:53 +0800 | [diff] [blame] | 344 | static RISCVException umode(CPURISCVState *env, int csrno) |
| 345 | { |
| 346 | if (riscv_has_ext(env, RVU)) { |
| 347 | return RISCV_EXCP_NONE; |
| 348 | } |
| 349 | |
| 350 | return RISCV_EXCP_ILLEGAL_INST; |
| 351 | } |
| 352 | |
| 353 | static RISCVException umode32(CPURISCVState *env, int csrno) |
| 354 | { |
| 355 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
| 356 | return RISCV_EXCP_ILLEGAL_INST; |
| 357 | } |
| 358 | |
| 359 | return umode(env, csrno); |
| 360 | } |
| 361 | |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 362 | static RISCVException mstateen(CPURISCVState *env, int csrno) |
| 363 | { |
Weiwei Li | 9c33e08 | 2023-03-09 15:13:26 +0800 | [diff] [blame] | 364 | if (!riscv_cpu_cfg(env)->ext_smstateen) { |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 365 | return RISCV_EXCP_ILLEGAL_INST; |
| 366 | } |
| 367 | |
| 368 | return any(env, csrno); |
| 369 | } |
| 370 | |
| 371 | static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) |
| 372 | { |
Weiwei Li | 9c33e08 | 2023-03-09 15:13:26 +0800 | [diff] [blame] | 373 | if (!riscv_cpu_cfg(env)->ext_smstateen) { |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 374 | return RISCV_EXCP_ILLEGAL_INST; |
| 375 | } |
| 376 | |
Bin Meng | 0308fc6 | 2023-02-28 21:45:32 +0800 | [diff] [blame] | 377 | RISCVException ret = hmode(env, csrno); |
| 378 | if (ret != RISCV_EXCP_NONE) { |
| 379 | return ret; |
| 380 | } |
| 381 | |
| 382 | if (env->debugger) { |
| 383 | return RISCV_EXCP_NONE; |
| 384 | } |
| 385 | |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 386 | if (env->priv < PRV_M) { |
| 387 | if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) { |
| 388 | return RISCV_EXCP_ILLEGAL_INST; |
| 389 | } |
| 390 | } |
| 391 | |
Bin Meng | 0308fc6 | 2023-02-28 21:45:32 +0800 | [diff] [blame] | 392 | return RISCV_EXCP_NONE; |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 393 | } |
| 394 | |
| 395 | static RISCVException hstateen(CPURISCVState *env, int csrno) |
| 396 | { |
| 397 | return hstateen_pred(env, csrno, CSR_HSTATEEN0); |
| 398 | } |
| 399 | |
| 400 | static RISCVException hstateenh(CPURISCVState *env, int csrno) |
| 401 | { |
| 402 | return hstateen_pred(env, csrno, CSR_HSTATEEN0H); |
| 403 | } |
| 404 | |
| 405 | static RISCVException sstateen(CPURISCVState *env, int csrno) |
| 406 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 407 | bool virt = env->virt_enabled; |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 408 | int index = csrno - CSR_SSTATEEN0; |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 409 | |
Daniel Henrique Barboza | a9a4e39 | 2023-02-24 14:45:19 -0300 | [diff] [blame] | 410 | if (!riscv_cpu_cfg(env)->ext_smstateen) { |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 411 | return RISCV_EXCP_ILLEGAL_INST; |
| 412 | } |
| 413 | |
Bin Meng | 0308fc6 | 2023-02-28 21:45:32 +0800 | [diff] [blame] | 414 | RISCVException ret = smode(env, csrno); |
| 415 | if (ret != RISCV_EXCP_NONE) { |
| 416 | return ret; |
| 417 | } |
| 418 | |
| 419 | if (env->debugger) { |
| 420 | return RISCV_EXCP_NONE; |
| 421 | } |
| 422 | |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 423 | if (env->priv < PRV_M) { |
| 424 | if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) { |
| 425 | return RISCV_EXCP_ILLEGAL_INST; |
| 426 | } |
| 427 | |
| 428 | if (virt) { |
| 429 | if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) { |
| 430 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 431 | } |
| 432 | } |
| 433 | } |
| 434 | |
Bin Meng | 0308fc6 | 2023-02-28 21:45:32 +0800 | [diff] [blame] | 435 | return RISCV_EXCP_NONE; |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 436 | } |
| 437 | |
Bin Meng | fb5bd4d | 2023-02-28 21:45:35 +0800 | [diff] [blame] | 438 | static RISCVException sstc(CPURISCVState *env, int csrno) |
| 439 | { |
Bin Meng | fb5bd4d | 2023-02-28 21:45:35 +0800 | [diff] [blame] | 440 | bool hmode_check = false; |
| 441 | |
Weiwei Li | 9c33e08 | 2023-03-09 15:13:26 +0800 | [diff] [blame] | 442 | if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) { |
Bin Meng | fb5bd4d | 2023-02-28 21:45:35 +0800 | [diff] [blame] | 443 | return RISCV_EXCP_ILLEGAL_INST; |
| 444 | } |
| 445 | |
| 446 | if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) { |
| 447 | hmode_check = true; |
| 448 | } |
| 449 | |
| 450 | RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno); |
| 451 | if (ret != RISCV_EXCP_NONE) { |
| 452 | return ret; |
| 453 | } |
| 454 | |
| 455 | if (env->debugger) { |
| 456 | return RISCV_EXCP_NONE; |
| 457 | } |
| 458 | |
| 459 | if (env->priv == PRV_M) { |
| 460 | return RISCV_EXCP_NONE; |
| 461 | } |
| 462 | |
| 463 | /* |
| 464 | * No need of separate function for rv32 as menvcfg stores both menvcfg |
| 465 | * menvcfgh for RV32. |
| 466 | */ |
| 467 | if (!(get_field(env->mcounteren, COUNTEREN_TM) && |
| 468 | get_field(env->menvcfg, MENVCFG_STCE))) { |
| 469 | return RISCV_EXCP_ILLEGAL_INST; |
| 470 | } |
| 471 | |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 472 | if (env->virt_enabled) { |
Bin Meng | fb5bd4d | 2023-02-28 21:45:35 +0800 | [diff] [blame] | 473 | if (!(get_field(env->hcounteren, COUNTEREN_TM) && |
| 474 | get_field(env->henvcfg, HENVCFG_STCE))) { |
| 475 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 476 | } |
| 477 | } |
| 478 | |
| 479 | return RISCV_EXCP_NONE; |
| 480 | } |
| 481 | |
| 482 | static RISCVException sstc_32(CPURISCVState *env, int csrno) |
| 483 | { |
| 484 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
| 485 | return RISCV_EXCP_ILLEGAL_INST; |
| 486 | } |
| 487 | |
| 488 | return sstc(env, csrno); |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 489 | } |
| 490 | |
Yi Chen | d6db7c9 | 2023-04-06 18:15:59 +0800 | [diff] [blame] | 491 | static RISCVException satp(CPURISCVState *env, int csrno) |
| 492 | { |
| 493 | if (env->priv == PRV_S && !env->virt_enabled && |
| 494 | get_field(env->mstatus, MSTATUS_TVM)) { |
| 495 | return RISCV_EXCP_ILLEGAL_INST; |
| 496 | } |
| 497 | if (env->priv == PRV_S && env->virt_enabled && |
| 498 | get_field(env->hstatus, HSTATUS_VTVM)) { |
| 499 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 500 | } |
| 501 | |
| 502 | return smode(env, csrno); |
| 503 | } |
| 504 | |
| 505 | static RISCVException hgatp(CPURISCVState *env, int csrno) |
| 506 | { |
| 507 | if (env->priv == PRV_S && !env->virt_enabled && |
| 508 | get_field(env->mstatus, MSTATUS_TVM)) { |
| 509 | return RISCV_EXCP_ILLEGAL_INST; |
| 510 | } |
| 511 | |
| 512 | return hmode(env, csrno); |
| 513 | } |
| 514 | |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 515 | /* Checks if PointerMasking registers could be accessed */ |
| 516 | static RISCVException pointer_masking(CPURISCVState *env, int csrno) |
| 517 | { |
| 518 | /* Check if j-ext is present */ |
| 519 | if (riscv_has_ext(env, RVJ)) { |
| 520 | return RISCV_EXCP_NONE; |
| 521 | } |
| 522 | return RISCV_EXCP_ILLEGAL_INST; |
| 523 | } |
| 524 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 525 | static RISCVException aia_hmode(CPURISCVState *env, int csrno) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 526 | { |
Daniel Henrique Barboza | 01af27e | 2023-02-24 14:45:20 -0300 | [diff] [blame] | 527 | if (!riscv_cpu_cfg(env)->ext_ssaia) { |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 528 | return RISCV_EXCP_ILLEGAL_INST; |
| 529 | } |
| 530 | |
| 531 | return hmode(env, csrno); |
| 532 | } |
| 533 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 534 | static RISCVException aia_hmode32(CPURISCVState *env, int csrno) |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 535 | { |
Daniel Henrique Barboza | 01af27e | 2023-02-24 14:45:20 -0300 | [diff] [blame] | 536 | if (!riscv_cpu_cfg(env)->ext_ssaia) { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 537 | return RISCV_EXCP_ILLEGAL_INST; |
| 538 | } |
| 539 | |
| 540 | return hmode32(env, csrno); |
| 541 | } |
| 542 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 543 | static RISCVException pmp(CPURISCVState *env, int csrno) |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 544 | { |
Daniel Henrique Barboza | 3fe40ef | 2023-02-22 15:52:02 -0300 | [diff] [blame] | 545 | if (riscv_cpu_cfg(env)->pmp) { |
Bin Meng | 04733fb | 2023-02-28 18:40:26 +0800 | [diff] [blame] | 546 | if (csrno <= CSR_PMPCFG3) { |
| 547 | uint32_t reg_index = csrno - CSR_PMPCFG0; |
| 548 | |
| 549 | /* TODO: RV128 restriction check */ |
| 550 | if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { |
| 551 | return RISCV_EXCP_ILLEGAL_INST; |
| 552 | } |
| 553 | } |
| 554 | |
Alistair Francis | 0e62f92 | 2021-04-01 11:17:39 -0400 | [diff] [blame] | 555 | return RISCV_EXCP_NONE; |
| 556 | } |
| 557 | |
| 558 | return RISCV_EXCP_ILLEGAL_INST; |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 559 | } |
Hou Weiying | 2582a95 | 2021-04-19 16:16:53 +1000 | [diff] [blame] | 560 | |
Heinrich Schuchardt | 2f32dca | 2023-10-30 12:21:05 +0200 | [diff] [blame] | 561 | static RISCVException have_mseccfg(CPURISCVState *env, int csrno) |
Hou Weiying | 2582a95 | 2021-04-19 16:16:53 +1000 | [diff] [blame] | 562 | { |
Himanshu Chauhan | 095fe72 | 2023-10-19 12:25:46 +0530 | [diff] [blame] | 563 | if (riscv_cpu_cfg(env)->ext_smepmp) { |
Hou Weiying | 2582a95 | 2021-04-19 16:16:53 +1000 | [diff] [blame] | 564 | return RISCV_EXCP_NONE; |
| 565 | } |
Heinrich Schuchardt | 2f32dca | 2023-10-30 12:21:05 +0200 | [diff] [blame] | 566 | if (riscv_cpu_cfg(env)->ext_zkr) { |
| 567 | return RISCV_EXCP_NONE; |
| 568 | } |
Hou Weiying | 2582a95 | 2021-04-19 16:16:53 +1000 | [diff] [blame] | 569 | |
| 570 | return RISCV_EXCP_ILLEGAL_INST; |
| 571 | } |
Bin Meng | b609254 | 2022-04-21 08:33:21 +0800 | [diff] [blame] | 572 | |
| 573 | static RISCVException debug(CPURISCVState *env, int csrno) |
| 574 | { |
Daniel Henrique Barboza | cdfb290 | 2023-02-22 15:51:59 -0300 | [diff] [blame] | 575 | if (riscv_cpu_cfg(env)->debug) { |
Bin Meng | b609254 | 2022-04-21 08:33:21 +0800 | [diff] [blame] | 576 | return RISCV_EXCP_NONE; |
| 577 | } |
| 578 | |
| 579 | return RISCV_EXCP_ILLEGAL_INST; |
| 580 | } |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 581 | #endif |
| 582 | |
Weiwei Li | 7744238 | 2022-04-23 10:35:08 +0800 | [diff] [blame] | 583 | static RISCVException seed(CPURISCVState *env, int csrno) |
| 584 | { |
Daniel Henrique Barboza | 01af27e | 2023-02-24 14:45:20 -0300 | [diff] [blame] | 585 | if (!riscv_cpu_cfg(env)->ext_zkr) { |
Weiwei Li | 7744238 | 2022-04-23 10:35:08 +0800 | [diff] [blame] | 586 | return RISCV_EXCP_ILLEGAL_INST; |
| 587 | } |
| 588 | |
| 589 | #if !defined(CONFIG_USER_ONLY) |
Bin Meng | ddb1074 | 2023-02-28 21:45:31 +0800 | [diff] [blame] | 590 | if (env->debugger) { |
| 591 | return RISCV_EXCP_NONE; |
| 592 | } |
| 593 | |
Weiwei Li | 7744238 | 2022-04-23 10:35:08 +0800 | [diff] [blame] | 594 | /* |
| 595 | * With a CSR read-write instruction: |
| 596 | * 1) The seed CSR is always available in machine mode as normal. |
| 597 | * 2) Attempted access to seed from virtual modes VS and VU always raises |
| 598 | * an exception(virtual instruction exception only if mseccfg.sseed=1). |
| 599 | * 3) Without the corresponding access control bit set to 1, any attempted |
| 600 | * access to seed from U, S or HS modes will raise an illegal instruction |
| 601 | * exception. |
| 602 | */ |
| 603 | if (env->priv == PRV_M) { |
| 604 | return RISCV_EXCP_NONE; |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 605 | } else if (env->virt_enabled) { |
Weiwei Li | 7744238 | 2022-04-23 10:35:08 +0800 | [diff] [blame] | 606 | if (env->mseccfg & MSECCFG_SSEED) { |
| 607 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 608 | } else { |
| 609 | return RISCV_EXCP_ILLEGAL_INST; |
| 610 | } |
| 611 | } else { |
| 612 | if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { |
| 613 | return RISCV_EXCP_NONE; |
| 614 | } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { |
| 615 | return RISCV_EXCP_NONE; |
| 616 | } else { |
| 617 | return RISCV_EXCP_ILLEGAL_INST; |
| 618 | } |
| 619 | } |
| 620 | #else |
| 621 | return RISCV_EXCP_NONE; |
| 622 | #endif |
| 623 | } |
| 624 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 625 | /* User Floating-Point CSRs */ |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 626 | static RISCVException read_fflags(CPURISCVState *env, int csrno, |
| 627 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 628 | { |
Michael Clark | fb73883 | 2019-01-14 23:58:23 +0000 | [diff] [blame] | 629 | *val = riscv_cpu_get_fflags(env); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 630 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 631 | } |
| 632 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 633 | static RISCVException write_fflags(CPURISCVState *env, int csrno, |
| 634 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 635 | { |
| 636 | #if !defined(CONFIG_USER_ONLY) |
Weiwei Li | c163b3b | 2022-02-11 12:39:16 +0800 | [diff] [blame] | 637 | if (riscv_has_ext(env, RVF)) { |
| 638 | env->mstatus |= MSTATUS_FS; |
| 639 | } |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 640 | #endif |
Michael Clark | fb73883 | 2019-01-14 23:58:23 +0000 | [diff] [blame] | 641 | riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 642 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 643 | } |
| 644 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 645 | static RISCVException read_frm(CPURISCVState *env, int csrno, |
| 646 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 647 | { |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 648 | *val = env->frm; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 649 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 650 | } |
| 651 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 652 | static RISCVException write_frm(CPURISCVState *env, int csrno, |
| 653 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 654 | { |
| 655 | #if !defined(CONFIG_USER_ONLY) |
Weiwei Li | c163b3b | 2022-02-11 12:39:16 +0800 | [diff] [blame] | 656 | if (riscv_has_ext(env, RVF)) { |
| 657 | env->mstatus |= MSTATUS_FS; |
| 658 | } |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 659 | #endif |
| 660 | env->frm = val & (FSR_RD >> FSR_RD_SHIFT); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 661 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 662 | } |
| 663 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 664 | static RISCVException read_fcsr(CPURISCVState *env, int csrno, |
| 665 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 666 | { |
Michael Clark | fb73883 | 2019-01-14 23:58:23 +0000 | [diff] [blame] | 667 | *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 668 | | (env->frm << FSR_RD_SHIFT); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 669 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 670 | } |
| 671 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 672 | static RISCVException write_fcsr(CPURISCVState *env, int csrno, |
| 673 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 674 | { |
| 675 | #if !defined(CONFIG_USER_ONLY) |
Weiwei Li | c163b3b | 2022-02-11 12:39:16 +0800 | [diff] [blame] | 676 | if (riscv_has_ext(env, RVF)) { |
| 677 | env->mstatus |= MSTATUS_FS; |
| 678 | } |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 679 | #endif |
| 680 | env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; |
Michael Clark | fb73883 | 2019-01-14 23:58:23 +0000 | [diff] [blame] | 681 | riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 682 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 683 | } |
| 684 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 685 | static RISCVException read_vtype(CPURISCVState *env, int csrno, |
| 686 | target_ulong *val) |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 687 | { |
LIU Zhiwei | d96a271 | 2022-01-20 20:20:42 +0800 | [diff] [blame] | 688 | uint64_t vill; |
| 689 | switch (env->xl) { |
| 690 | case MXL_RV32: |
| 691 | vill = (uint32_t)env->vill << 31; |
| 692 | break; |
| 693 | case MXL_RV64: |
| 694 | vill = (uint64_t)env->vill << 63; |
| 695 | break; |
| 696 | default: |
| 697 | g_assert_not_reached(); |
| 698 | } |
| 699 | *val = (target_ulong)vill | env->vtype; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 700 | return RISCV_EXCP_NONE; |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 701 | } |
| 702 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 703 | static RISCVException read_vl(CPURISCVState *env, int csrno, |
| 704 | target_ulong *val) |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 705 | { |
| 706 | *val = env->vl; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 707 | return RISCV_EXCP_NONE; |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 708 | } |
| 709 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 710 | static RISCVException read_vlenb(CPURISCVState *env, int csrno, |
| 711 | target_ulong *val) |
Greentime Hu | 2e56505 | 2021-12-10 15:55:56 +0800 | [diff] [blame] | 712 | { |
Daniel Henrique Barboza | 39b5efa | 2024-01-22 13:10:56 -0300 | [diff] [blame] | 713 | *val = riscv_cpu_cfg(env)->vlenb; |
Greentime Hu | 2e56505 | 2021-12-10 15:55:56 +0800 | [diff] [blame] | 714 | return RISCV_EXCP_NONE; |
| 715 | } |
| 716 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 717 | static RISCVException read_vxrm(CPURISCVState *env, int csrno, |
| 718 | target_ulong *val) |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 719 | { |
| 720 | *val = env->vxrm; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 721 | return RISCV_EXCP_NONE; |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 722 | } |
| 723 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 724 | static RISCVException write_vxrm(CPURISCVState *env, int csrno, |
| 725 | target_ulong val) |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 726 | { |
LIU Zhiwei | 61b4b69 | 2021-12-10 15:55:49 +0800 | [diff] [blame] | 727 | #if !defined(CONFIG_USER_ONLY) |
| 728 | env->mstatus |= MSTATUS_VS; |
| 729 | #endif |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 730 | env->vxrm = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 731 | return RISCV_EXCP_NONE; |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 732 | } |
| 733 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 734 | static RISCVException read_vxsat(CPURISCVState *env, int csrno, |
| 735 | target_ulong *val) |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 736 | { |
| 737 | *val = env->vxsat; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 738 | return RISCV_EXCP_NONE; |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 739 | } |
| 740 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 741 | static RISCVException write_vxsat(CPURISCVState *env, int csrno, |
| 742 | target_ulong val) |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 743 | { |
LIU Zhiwei | 61b4b69 | 2021-12-10 15:55:49 +0800 | [diff] [blame] | 744 | #if !defined(CONFIG_USER_ONLY) |
| 745 | env->mstatus |= MSTATUS_VS; |
| 746 | #endif |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 747 | env->vxsat = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 748 | return RISCV_EXCP_NONE; |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 749 | } |
| 750 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 751 | static RISCVException read_vstart(CPURISCVState *env, int csrno, |
| 752 | target_ulong *val) |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 753 | { |
| 754 | *val = env->vstart; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 755 | return RISCV_EXCP_NONE; |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 756 | } |
| 757 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 758 | static RISCVException write_vstart(CPURISCVState *env, int csrno, |
| 759 | target_ulong val) |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 760 | { |
LIU Zhiwei | 61b4b69 | 2021-12-10 15:55:49 +0800 | [diff] [blame] | 761 | #if !defined(CONFIG_USER_ONLY) |
| 762 | env->mstatus |= MSTATUS_VS; |
| 763 | #endif |
Frank Chang | f714361 | 2021-12-10 15:56:52 +0800 | [diff] [blame] | 764 | /* |
| 765 | * The vstart CSR is defined to have only enough writable bits |
| 766 | * to hold the largest element index, i.e. lg2(VLEN) bits. |
| 767 | */ |
Daniel Henrique Barboza | 39b5efa | 2024-01-22 13:10:56 -0300 | [diff] [blame] | 768 | env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3)); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 769 | return RISCV_EXCP_NONE; |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 770 | } |
| 771 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 772 | static RISCVException read_vcsr(CPURISCVState *env, int csrno, |
| 773 | target_ulong *val) |
LIU Zhiwei | 4594fa5 | 2021-12-10 15:55:55 +0800 | [diff] [blame] | 774 | { |
| 775 | *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); |
| 776 | return RISCV_EXCP_NONE; |
| 777 | } |
| 778 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 779 | static RISCVException write_vcsr(CPURISCVState *env, int csrno, |
| 780 | target_ulong val) |
LIU Zhiwei | 4594fa5 | 2021-12-10 15:55:55 +0800 | [diff] [blame] | 781 | { |
| 782 | #if !defined(CONFIG_USER_ONLY) |
| 783 | env->mstatus |= MSTATUS_VS; |
| 784 | #endif |
| 785 | env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; |
| 786 | env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; |
| 787 | return RISCV_EXCP_NONE; |
| 788 | } |
| 789 | |
Atish Patra | b2d7a7c | 2024-07-11 15:31:10 -0700 | [diff] [blame] | 790 | #if defined(CONFIG_USER_ONLY) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 791 | /* User Timers and Counters */ |
Atish Patra | b2d7a7c | 2024-07-11 15:31:10 -0700 | [diff] [blame] | 792 | static target_ulong get_ticks(bool shift) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 793 | { |
Atish Patra | b2d7a7c | 2024-07-11 15:31:10 -0700 | [diff] [blame] | 794 | int64_t val = cpu_get_host_ticks(); |
| 795 | target_ulong result = shift ? val >> 32 : val; |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 796 | |
| 797 | return result; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 798 | } |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 799 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 800 | static RISCVException read_time(CPURISCVState *env, int csrno, |
| 801 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 802 | { |
| 803 | *val = cpu_get_host_ticks(); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 804 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 805 | } |
| 806 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 807 | static RISCVException read_timeh(CPURISCVState *env, int csrno, |
| 808 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 809 | { |
| 810 | *val = cpu_get_host_ticks() >> 32; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 811 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 812 | } |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 813 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 814 | static RISCVException read_hpmcounter(CPURISCVState *env, int csrno, |
| 815 | target_ulong *val) |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 816 | { |
Atish Patra | b2d7a7c | 2024-07-11 15:31:10 -0700 | [diff] [blame] | 817 | *val = get_ticks(false); |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 818 | return RISCV_EXCP_NONE; |
| 819 | } |
| 820 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 821 | static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, |
| 822 | target_ulong *val) |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 823 | { |
Atish Patra | b2d7a7c | 2024-07-11 15:31:10 -0700 | [diff] [blame] | 824 | *val = get_ticks(true); |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 825 | return RISCV_EXCP_NONE; |
| 826 | } |
| 827 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 828 | #else /* CONFIG_USER_ONLY */ |
| 829 | |
Kaiwen Xue | b54a84c | 2024-07-11 15:31:08 -0700 | [diff] [blame] | 830 | static RISCVException read_mcyclecfg(CPURISCVState *env, int csrno, |
| 831 | target_ulong *val) |
| 832 | { |
| 833 | *val = env->mcyclecfg; |
| 834 | return RISCV_EXCP_NONE; |
| 835 | } |
| 836 | |
| 837 | static RISCVException write_mcyclecfg(CPURISCVState *env, int csrno, |
| 838 | target_ulong val) |
| 839 | { |
| 840 | uint64_t inh_avail_mask; |
| 841 | |
| 842 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 843 | env->mcyclecfg = val; |
| 844 | } else { |
| 845 | /* Set xINH fields if priv mode supported */ |
| 846 | inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MCYCLECFG_BIT_MINH; |
| 847 | inh_avail_mask |= riscv_has_ext(env, RVU) ? MCYCLECFG_BIT_UINH : 0; |
| 848 | inh_avail_mask |= riscv_has_ext(env, RVS) ? MCYCLECFG_BIT_SINH : 0; |
| 849 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 850 | riscv_has_ext(env, RVU)) ? MCYCLECFG_BIT_VUINH : 0; |
| 851 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 852 | riscv_has_ext(env, RVS)) ? MCYCLECFG_BIT_VSINH : 0; |
| 853 | env->mcyclecfg = val & inh_avail_mask; |
| 854 | } |
| 855 | |
| 856 | return RISCV_EXCP_NONE; |
| 857 | } |
| 858 | |
| 859 | static RISCVException read_mcyclecfgh(CPURISCVState *env, int csrno, |
| 860 | target_ulong *val) |
| 861 | { |
| 862 | *val = env->mcyclecfgh; |
| 863 | return RISCV_EXCP_NONE; |
| 864 | } |
| 865 | |
| 866 | static RISCVException write_mcyclecfgh(CPURISCVState *env, int csrno, |
| 867 | target_ulong val) |
| 868 | { |
| 869 | target_ulong inh_avail_mask = (target_ulong)(~MHPMEVENTH_FILTER_MASK | |
| 870 | MCYCLECFGH_BIT_MINH); |
| 871 | |
| 872 | /* Set xINH fields if priv mode supported */ |
| 873 | inh_avail_mask |= riscv_has_ext(env, RVU) ? MCYCLECFGH_BIT_UINH : 0; |
| 874 | inh_avail_mask |= riscv_has_ext(env, RVS) ? MCYCLECFGH_BIT_SINH : 0; |
| 875 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 876 | riscv_has_ext(env, RVU)) ? MCYCLECFGH_BIT_VUINH : 0; |
| 877 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 878 | riscv_has_ext(env, RVS)) ? MCYCLECFGH_BIT_VSINH : 0; |
| 879 | |
| 880 | env->mcyclecfgh = val & inh_avail_mask; |
| 881 | return RISCV_EXCP_NONE; |
| 882 | } |
| 883 | |
| 884 | static RISCVException read_minstretcfg(CPURISCVState *env, int csrno, |
| 885 | target_ulong *val) |
| 886 | { |
| 887 | *val = env->minstretcfg; |
| 888 | return RISCV_EXCP_NONE; |
| 889 | } |
| 890 | |
| 891 | static RISCVException write_minstretcfg(CPURISCVState *env, int csrno, |
| 892 | target_ulong val) |
| 893 | { |
| 894 | uint64_t inh_avail_mask; |
| 895 | |
| 896 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 897 | env->minstretcfg = val; |
| 898 | } else { |
| 899 | inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MINSTRETCFG_BIT_MINH; |
| 900 | inh_avail_mask |= riscv_has_ext(env, RVU) ? MINSTRETCFG_BIT_UINH : 0; |
| 901 | inh_avail_mask |= riscv_has_ext(env, RVS) ? MINSTRETCFG_BIT_SINH : 0; |
| 902 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 903 | riscv_has_ext(env, RVU)) ? MINSTRETCFG_BIT_VUINH : 0; |
| 904 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 905 | riscv_has_ext(env, RVS)) ? MINSTRETCFG_BIT_VSINH : 0; |
| 906 | env->minstretcfg = val & inh_avail_mask; |
| 907 | } |
| 908 | return RISCV_EXCP_NONE; |
| 909 | } |
| 910 | |
| 911 | static RISCVException read_minstretcfgh(CPURISCVState *env, int csrno, |
| 912 | target_ulong *val) |
| 913 | { |
| 914 | *val = env->minstretcfgh; |
| 915 | return RISCV_EXCP_NONE; |
| 916 | } |
| 917 | |
| 918 | static RISCVException write_minstretcfgh(CPURISCVState *env, int csrno, |
| 919 | target_ulong val) |
| 920 | { |
| 921 | target_ulong inh_avail_mask = (target_ulong)(~MHPMEVENTH_FILTER_MASK | |
| 922 | MINSTRETCFGH_BIT_MINH); |
| 923 | |
| 924 | inh_avail_mask |= riscv_has_ext(env, RVU) ? MINSTRETCFGH_BIT_UINH : 0; |
| 925 | inh_avail_mask |= riscv_has_ext(env, RVS) ? MINSTRETCFGH_BIT_SINH : 0; |
| 926 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 927 | riscv_has_ext(env, RVU)) ? MINSTRETCFGH_BIT_VUINH : 0; |
| 928 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 929 | riscv_has_ext(env, RVS)) ? MINSTRETCFGH_BIT_VSINH : 0; |
| 930 | |
| 931 | env->minstretcfgh = val & inh_avail_mask; |
| 932 | return RISCV_EXCP_NONE; |
| 933 | } |
| 934 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 935 | static RISCVException read_mhpmevent(CPURISCVState *env, int csrno, |
| 936 | target_ulong *val) |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 937 | { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 938 | int evt_index = csrno - CSR_MCOUNTINHIBIT; |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 939 | |
| 940 | *val = env->mhpmevent_val[evt_index]; |
| 941 | |
| 942 | return RISCV_EXCP_NONE; |
| 943 | } |
| 944 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 945 | static RISCVException write_mhpmevent(CPURISCVState *env, int csrno, |
| 946 | target_ulong val) |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 947 | { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 948 | int evt_index = csrno - CSR_MCOUNTINHIBIT; |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 949 | uint64_t mhpmevt_val = val; |
Atish Patra | 3b31b7b | 2024-07-11 15:31:09 -0700 | [diff] [blame] | 950 | uint64_t inh_avail_mask; |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 951 | |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 952 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
Atish Patra | 3b31b7b | 2024-07-11 15:31:09 -0700 | [diff] [blame] | 953 | env->mhpmevent_val[evt_index] = val; |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 954 | mhpmevt_val = mhpmevt_val | |
| 955 | ((uint64_t)env->mhpmeventh_val[evt_index] << 32); |
Atish Patra | 3b31b7b | 2024-07-11 15:31:09 -0700 | [diff] [blame] | 956 | } else { |
| 957 | inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MHPMEVENT_BIT_MINH; |
| 958 | inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH : 0; |
| 959 | inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENT_BIT_SINH : 0; |
| 960 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 961 | riscv_has_ext(env, RVU)) ? MHPMEVENT_BIT_VUINH : 0; |
| 962 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 963 | riscv_has_ext(env, RVS)) ? MHPMEVENT_BIT_VSINH : 0; |
| 964 | mhpmevt_val = val & inh_avail_mask; |
| 965 | env->mhpmevent_val[evt_index] = mhpmevt_val; |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 966 | } |
Atish Patra | 3b31b7b | 2024-07-11 15:31:09 -0700 | [diff] [blame] | 967 | |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 968 | riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); |
| 969 | |
| 970 | return RISCV_EXCP_NONE; |
| 971 | } |
| 972 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 973 | static RISCVException read_mhpmeventh(CPURISCVState *env, int csrno, |
| 974 | target_ulong *val) |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 975 | { |
| 976 | int evt_index = csrno - CSR_MHPMEVENT3H + 3; |
| 977 | |
| 978 | *val = env->mhpmeventh_val[evt_index]; |
| 979 | |
| 980 | return RISCV_EXCP_NONE; |
| 981 | } |
| 982 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 983 | static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno, |
| 984 | target_ulong val) |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 985 | { |
| 986 | int evt_index = csrno - CSR_MHPMEVENT3H + 3; |
Atish Patra | 3b31b7b | 2024-07-11 15:31:09 -0700 | [diff] [blame] | 987 | uint64_t mhpmevth_val; |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 988 | uint64_t mhpmevt_val = env->mhpmevent_val[evt_index]; |
Atish Patra | 3b31b7b | 2024-07-11 15:31:09 -0700 | [diff] [blame] | 989 | target_ulong inh_avail_mask = (target_ulong)(~MHPMEVENTH_FILTER_MASK | |
| 990 | MHPMEVENTH_BIT_MINH); |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 991 | |
Atish Patra | 3b31b7b | 2024-07-11 15:31:09 -0700 | [diff] [blame] | 992 | inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENTH_BIT_UINH : 0; |
| 993 | inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENTH_BIT_SINH : 0; |
| 994 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 995 | riscv_has_ext(env, RVU)) ? MHPMEVENTH_BIT_VUINH : 0; |
| 996 | inh_avail_mask |= (riscv_has_ext(env, RVH) && |
| 997 | riscv_has_ext(env, RVS)) ? MHPMEVENTH_BIT_VSINH : 0; |
| 998 | |
| 999 | mhpmevth_val = val & inh_avail_mask; |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 1000 | mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32); |
Atish Patra | 3b31b7b | 2024-07-11 15:31:09 -0700 | [diff] [blame] | 1001 | env->mhpmeventh_val[evt_index] = mhpmevth_val; |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 1002 | |
| 1003 | riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); |
| 1004 | |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1005 | return RISCV_EXCP_NONE; |
| 1006 | } |
| 1007 | |
Atish Patra | b2d7a7c | 2024-07-11 15:31:10 -0700 | [diff] [blame] | 1008 | static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env, |
| 1009 | int counter_idx, |
| 1010 | bool upper_half) |
| 1011 | { |
| 1012 | int inst = riscv_pmu_ctr_monitor_instructions(env, counter_idx); |
| 1013 | uint64_t *counter_arr_virt = env->pmu_fixed_ctrs[inst].counter_virt; |
| 1014 | uint64_t *counter_arr = env->pmu_fixed_ctrs[inst].counter; |
| 1015 | target_ulong result = 0; |
| 1016 | uint64_t curr_val = 0; |
| 1017 | uint64_t cfg_val = 0; |
| 1018 | |
| 1019 | if (counter_idx == 0) { |
| 1020 | cfg_val = upper_half ? ((uint64_t)env->mcyclecfgh << 32) : |
| 1021 | env->mcyclecfg; |
| 1022 | } else if (counter_idx == 2) { |
| 1023 | cfg_val = upper_half ? ((uint64_t)env->minstretcfgh << 32) : |
| 1024 | env->minstretcfg; |
| 1025 | } else { |
| 1026 | cfg_val = upper_half ? |
| 1027 | ((uint64_t)env->mhpmeventh_val[counter_idx] << 32) : |
| 1028 | env->mhpmevent_val[counter_idx]; |
| 1029 | cfg_val &= MHPMEVENT_FILTER_MASK; |
| 1030 | } |
| 1031 | |
| 1032 | if (!cfg_val) { |
| 1033 | if (icount_enabled()) { |
| 1034 | curr_val = inst ? icount_get_raw() : icount_get(); |
| 1035 | } else { |
| 1036 | curr_val = cpu_get_host_ticks(); |
| 1037 | } |
| 1038 | |
| 1039 | goto done; |
| 1040 | } |
| 1041 | |
Rajnesh Kanwal | 7411240 | 2024-07-11 15:31:14 -0700 | [diff] [blame] | 1042 | /* Update counter before reading. */ |
| 1043 | riscv_pmu_update_fixed_ctrs(env, env->priv, env->virt_enabled); |
| 1044 | |
Atish Patra | b2d7a7c | 2024-07-11 15:31:10 -0700 | [diff] [blame] | 1045 | if (!(cfg_val & MCYCLECFG_BIT_MINH)) { |
| 1046 | curr_val += counter_arr[PRV_M]; |
| 1047 | } |
| 1048 | |
| 1049 | if (!(cfg_val & MCYCLECFG_BIT_SINH)) { |
| 1050 | curr_val += counter_arr[PRV_S]; |
| 1051 | } |
| 1052 | |
| 1053 | if (!(cfg_val & MCYCLECFG_BIT_UINH)) { |
| 1054 | curr_val += counter_arr[PRV_U]; |
| 1055 | } |
| 1056 | |
| 1057 | if (!(cfg_val & MCYCLECFG_BIT_VSINH)) { |
| 1058 | curr_val += counter_arr_virt[PRV_S]; |
| 1059 | } |
| 1060 | |
| 1061 | if (!(cfg_val & MCYCLECFG_BIT_VUINH)) { |
| 1062 | curr_val += counter_arr_virt[PRV_U]; |
| 1063 | } |
| 1064 | |
| 1065 | done: |
| 1066 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 1067 | result = upper_half ? curr_val >> 32 : curr_val; |
| 1068 | } else { |
| 1069 | result = curr_val; |
| 1070 | } |
| 1071 | |
| 1072 | return result; |
| 1073 | } |
| 1074 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 1075 | static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno, |
| 1076 | target_ulong val) |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1077 | { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1078 | int ctr_idx = csrno - CSR_MCYCLE; |
| 1079 | PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 1080 | uint64_t mhpmctr_val = val; |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1081 | |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1082 | counter->mhpmcounter_val = val; |
Rajnesh Kanwal | 22c721c | 2024-07-11 15:31:13 -0700 | [diff] [blame] | 1083 | if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && |
| 1084 | (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || |
| 1085 | riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { |
Atish Patra | b2d7a7c | 2024-07-11 15:31:10 -0700 | [diff] [blame] | 1086 | counter->mhpmcounter_prev = riscv_pmu_ctr_get_fixed_counters_val(env, |
| 1087 | ctr_idx, false); |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 1088 | if (ctr_idx > 2) { |
| 1089 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 1090 | mhpmctr_val = mhpmctr_val | |
| 1091 | ((uint64_t)counter->mhpmcounterh_val << 32); |
| 1092 | } |
| 1093 | riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); |
| 1094 | } |
| 1095 | } else { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1096 | /* Other counters can keep incrementing from the given value */ |
| 1097 | counter->mhpmcounter_prev = val; |
| 1098 | } |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1099 | |
| 1100 | return RISCV_EXCP_NONE; |
| 1101 | } |
| 1102 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 1103 | static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno, |
| 1104 | target_ulong val) |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1105 | { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1106 | int ctr_idx = csrno - CSR_MCYCLEH; |
| 1107 | PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 1108 | uint64_t mhpmctr_val = counter->mhpmcounter_val; |
| 1109 | uint64_t mhpmctrh_val = val; |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1110 | |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1111 | counter->mhpmcounterh_val = val; |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 1112 | mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32); |
Rajnesh Kanwal | 22c721c | 2024-07-11 15:31:13 -0700 | [diff] [blame] | 1113 | if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && |
| 1114 | (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || |
| 1115 | riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { |
Atish Patra | b2d7a7c | 2024-07-11 15:31:10 -0700 | [diff] [blame] | 1116 | counter->mhpmcounterh_prev = riscv_pmu_ctr_get_fixed_counters_val(env, |
| 1117 | ctr_idx, true); |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 1118 | if (ctr_idx > 2) { |
| 1119 | riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); |
| 1120 | } |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1121 | } else { |
| 1122 | counter->mhpmcounterh_prev = val; |
| 1123 | } |
| 1124 | |
| 1125 | return RISCV_EXCP_NONE; |
| 1126 | } |
| 1127 | |
Rajnesh Kanwal | 7411240 | 2024-07-11 15:31:14 -0700 | [diff] [blame] | 1128 | RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1129 | bool upper_half, uint32_t ctr_idx) |
| 1130 | { |
Xu Lu | 5cb0e7a | 2023-12-26 12:05:00 +0800 | [diff] [blame] | 1131 | PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; |
| 1132 | target_ulong ctr_prev = upper_half ? counter->mhpmcounterh_prev : |
| 1133 | counter->mhpmcounter_prev; |
| 1134 | target_ulong ctr_val = upper_half ? counter->mhpmcounterh_val : |
| 1135 | counter->mhpmcounter_val; |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1136 | |
| 1137 | if (get_field(env->mcountinhibit, BIT(ctr_idx))) { |
Weiwei Li | 3b57254 | 2023-04-05 16:58:12 +0800 | [diff] [blame] | 1138 | /* |
Atish Patra | 4602347 | 2024-07-11 15:31:11 -0700 | [diff] [blame] | 1139 | * Counter should not increment if inhibit bit is set. Just return the |
| 1140 | * current counter value. |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1141 | */ |
Atish Patra | 4602347 | 2024-07-11 15:31:11 -0700 | [diff] [blame] | 1142 | *val = ctr_val; |
| 1143 | return RISCV_EXCP_NONE; |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1144 | } |
| 1145 | |
Weiwei Li | 3b57254 | 2023-04-05 16:58:12 +0800 | [diff] [blame] | 1146 | /* |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1147 | * The kernel computes the perf delta by subtracting the current value from |
| 1148 | * the value it initialized previously (ctr_val). |
| 1149 | */ |
Atish Patra | b2d7a7c | 2024-07-11 15:31:10 -0700 | [diff] [blame] | 1150 | if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || |
| 1151 | riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { |
| 1152 | *val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, upper_half) - |
| 1153 | ctr_prev + ctr_val; |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1154 | } else { |
| 1155 | *val = ctr_val; |
| 1156 | } |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1157 | |
| 1158 | return RISCV_EXCP_NONE; |
| 1159 | } |
| 1160 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 1161 | static RISCVException read_hpmcounter(CPURISCVState *env, int csrno, |
| 1162 | target_ulong *val) |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1163 | { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1164 | uint16_t ctr_index; |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1165 | |
| 1166 | if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1167 | ctr_index = csrno - CSR_MCYCLE; |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1168 | } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1169 | ctr_index = csrno - CSR_CYCLE; |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1170 | } else { |
| 1171 | return RISCV_EXCP_ILLEGAL_INST; |
| 1172 | } |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1173 | |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1174 | return riscv_pmu_read_ctr(env, val, false, ctr_index); |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1175 | } |
| 1176 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 1177 | static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, |
| 1178 | target_ulong *val) |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1179 | { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1180 | uint16_t ctr_index; |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1181 | |
| 1182 | if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1183 | ctr_index = csrno - CSR_MCYCLEH; |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1184 | } else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1185 | ctr_index = csrno - CSR_CYCLEH; |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1186 | } else { |
| 1187 | return RISCV_EXCP_ILLEGAL_INST; |
| 1188 | } |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1189 | |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 1190 | return riscv_pmu_read_ctr(env, val, true, ctr_index); |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 1191 | } |
| 1192 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 1193 | static RISCVException read_scountovf(CPURISCVState *env, int csrno, |
| 1194 | target_ulong *val) |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 1195 | { |
| 1196 | int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; |
| 1197 | int i; |
| 1198 | *val = 0; |
| 1199 | target_ulong *mhpm_evt_val; |
| 1200 | uint64_t of_bit_mask; |
| 1201 | |
| 1202 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 1203 | mhpm_evt_val = env->mhpmeventh_val; |
| 1204 | of_bit_mask = MHPMEVENTH_BIT_OF; |
| 1205 | } else { |
| 1206 | mhpm_evt_val = env->mhpmevent_val; |
| 1207 | of_bit_mask = MHPMEVENT_BIT_OF; |
| 1208 | } |
| 1209 | |
| 1210 | for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) { |
| 1211 | if ((get_field(env->mcounteren, BIT(i))) && |
| 1212 | (mhpm_evt_val[i] & of_bit_mask)) { |
| 1213 | *val |= BIT(i); |
| 1214 | } |
| 1215 | } |
| 1216 | |
| 1217 | return RISCV_EXCP_NONE; |
| 1218 | } |
| 1219 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1220 | static RISCVException read_time(CPURISCVState *env, int csrno, |
| 1221 | target_ulong *val) |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 1222 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 1223 | uint64_t delta = env->virt_enabled ? env->htimedelta : 0; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 1224 | |
| 1225 | if (!env->rdtime_fn) { |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1226 | return RISCV_EXCP_ILLEGAL_INST; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 1227 | } |
| 1228 | |
Bin Meng | a47ef6e | 2020-09-01 09:39:10 +0800 | [diff] [blame] | 1229 | *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1230 | return RISCV_EXCP_NONE; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 1231 | } |
| 1232 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1233 | static RISCVException read_timeh(CPURISCVState *env, int csrno, |
| 1234 | target_ulong *val) |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 1235 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 1236 | uint64_t delta = env->virt_enabled ? env->htimedelta : 0; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 1237 | |
| 1238 | if (!env->rdtime_fn) { |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1239 | return RISCV_EXCP_ILLEGAL_INST; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 1240 | } |
| 1241 | |
Bin Meng | a47ef6e | 2020-09-01 09:39:10 +0800 | [diff] [blame] | 1242 | *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1243 | return RISCV_EXCP_NONE; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 1244 | } |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 1245 | |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1246 | static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 1247 | target_ulong *val) |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1248 | { |
| 1249 | *val = env->vstimecmp; |
| 1250 | |
| 1251 | return RISCV_EXCP_NONE; |
| 1252 | } |
| 1253 | |
| 1254 | static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 1255 | target_ulong *val) |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1256 | { |
| 1257 | *val = env->vstimecmp >> 32; |
| 1258 | |
| 1259 | return RISCV_EXCP_NONE; |
| 1260 | } |
| 1261 | |
| 1262 | static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 1263 | target_ulong val) |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1264 | { |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1265 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 1266 | env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val); |
| 1267 | } else { |
| 1268 | env->vstimecmp = val; |
| 1269 | } |
| 1270 | |
Weiwei Li | bbb9fc2 | 2023-03-09 15:13:28 +0800 | [diff] [blame] | 1271 | riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1272 | env->htimedelta, MIP_VSTIP); |
| 1273 | |
| 1274 | return RISCV_EXCP_NONE; |
| 1275 | } |
| 1276 | |
| 1277 | static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 1278 | target_ulong val) |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1279 | { |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1280 | env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val); |
Weiwei Li | bbb9fc2 | 2023-03-09 15:13:28 +0800 | [diff] [blame] | 1281 | riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1282 | env->htimedelta, MIP_VSTIP); |
| 1283 | |
| 1284 | return RISCV_EXCP_NONE; |
| 1285 | } |
| 1286 | |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 1287 | static RISCVException read_stimecmp(CPURISCVState *env, int csrno, |
| 1288 | target_ulong *val) |
| 1289 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 1290 | if (env->virt_enabled) { |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1291 | *val = env->vstimecmp; |
| 1292 | } else { |
| 1293 | *val = env->stimecmp; |
| 1294 | } |
| 1295 | |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 1296 | return RISCV_EXCP_NONE; |
| 1297 | } |
| 1298 | |
| 1299 | static RISCVException read_stimecmph(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 1300 | target_ulong *val) |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 1301 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 1302 | if (env->virt_enabled) { |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1303 | *val = env->vstimecmp >> 32; |
| 1304 | } else { |
| 1305 | *val = env->stimecmp >> 32; |
| 1306 | } |
| 1307 | |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 1308 | return RISCV_EXCP_NONE; |
| 1309 | } |
| 1310 | |
| 1311 | static RISCVException write_stimecmp(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 1312 | target_ulong val) |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 1313 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 1314 | if (env->virt_enabled) { |
Andrew Bresticker | e471a8c | 2022-12-15 17:45:41 -0500 | [diff] [blame] | 1315 | if (env->hvictl & HVICTL_VTI) { |
| 1316 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 1317 | } |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1318 | return write_vstimecmp(env, csrno, val); |
| 1319 | } |
| 1320 | |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 1321 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 1322 | env->stimecmp = deposit64(env->stimecmp, 0, 32, (uint64_t)val); |
| 1323 | } else { |
| 1324 | env->stimecmp = val; |
| 1325 | } |
| 1326 | |
Weiwei Li | bbb9fc2 | 2023-03-09 15:13:28 +0800 | [diff] [blame] | 1327 | riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 1328 | |
| 1329 | return RISCV_EXCP_NONE; |
| 1330 | } |
| 1331 | |
| 1332 | static RISCVException write_stimecmph(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 1333 | target_ulong val) |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 1334 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 1335 | if (env->virt_enabled) { |
Andrew Bresticker | e471a8c | 2022-12-15 17:45:41 -0500 | [diff] [blame] | 1336 | if (env->hvictl & HVICTL_VTI) { |
| 1337 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 1338 | } |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 1339 | return write_vstimecmph(env, csrno, val); |
| 1340 | } |
| 1341 | |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 1342 | env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val); |
Weiwei Li | bbb9fc2 | 2023-03-09 15:13:28 +0800 | [diff] [blame] | 1343 | riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 1344 | |
| 1345 | return RISCV_EXCP_NONE; |
| 1346 | } |
| 1347 | |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 1348 | #define VSTOPI_NUM_SRCS 5 |
| 1349 | |
Rajnesh Kanwal | 92c82a1 | 2024-05-20 13:51:57 +0100 | [diff] [blame] | 1350 | /* |
| 1351 | * All core local interrupts except the fixed ones 0:12. This macro is for |
| 1352 | * virtual interrupts logic so please don't change this to avoid messing up |
| 1353 | * the whole support, For reference see AIA spec: `5.3 Interrupt filtering and |
| 1354 | * virtual interrupts for supervisor level` and `6.3.2 Virtual interrupts for |
| 1355 | * VS level`. |
| 1356 | */ |
| 1357 | #define LOCAL_INTERRUPTS (~0x1FFFULL) |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 1358 | |
| 1359 | static const uint64_t delegable_ints = |
| 1360 | S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; |
| 1361 | static const uint64_t vs_delegable_ints = |
| 1362 | (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP; |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1363 | static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 1364 | HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; |
Jose Martins | bc083a5 | 2021-05-22 16:59:02 +0100 | [diff] [blame] | 1365 | #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ |
| 1366 | (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ |
| 1367 | (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ |
| 1368 | (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ |
| 1369 | (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ |
| 1370 | (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ |
| 1371 | (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ |
| 1372 | (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ |
| 1373 | (1ULL << (RISCV_EXCP_U_ECALL)) | \ |
| 1374 | (1ULL << (RISCV_EXCP_S_ECALL)) | \ |
| 1375 | (1ULL << (RISCV_EXCP_VS_ECALL)) | \ |
| 1376 | (1ULL << (RISCV_EXCP_M_ECALL)) | \ |
| 1377 | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ |
| 1378 | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ |
| 1379 | (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ |
| 1380 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ |
| 1381 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ |
| 1382 | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ |
| 1383 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) |
| 1384 | static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & |
| 1385 | ~((1ULL << (RISCV_EXCP_S_ECALL)) | |
| 1386 | (1ULL << (RISCV_EXCP_VS_ECALL)) | |
| 1387 | (1ULL << (RISCV_EXCP_M_ECALL)) | |
| 1388 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | |
| 1389 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | |
| 1390 | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | |
| 1391 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1392 | static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | |
| 1393 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | |
LIU Zhiwei | f310df5 | 2022-01-20 20:20:49 +0800 | [diff] [blame] | 1394 | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 1395 | |
| 1396 | /* |
| 1397 | * Spec allows for bits 13:63 to be either read-only or writable. |
| 1398 | * So far we have interrupt LCOFIP in that region which is writable. |
| 1399 | * |
| 1400 | * Also, spec allows to inject virtual interrupts in this region even |
| 1401 | * without any hardware interrupts for that interrupt number. |
| 1402 | * |
| 1403 | * For now interrupt in 13:63 region are all kept writable. 13 being |
| 1404 | * LCOFIP and 14:63 being virtual only. Change this in future if we |
| 1405 | * introduce more interrupts that are not writable. |
| 1406 | */ |
| 1407 | |
| 1408 | /* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. */ |
Rajnesh Kanwal | 87088fa | 2024-05-20 13:51:56 +0100 | [diff] [blame] | 1409 | static const uint64_t mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP | |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 1410 | LOCAL_INTERRUPTS; |
Rajnesh Kanwal | 87088fa | 2024-05-20 13:51:56 +0100 | [diff] [blame] | 1411 | static const uint64_t mvien_writable_mask = MIP_SSIP | MIP_SEIP | |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 1412 | LOCAL_INTERRUPTS; |
| 1413 | |
Rajnesh Kanwal | 87088fa | 2024-05-20 13:51:56 +0100 | [diff] [blame] | 1414 | static const uint64_t sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS; |
| 1415 | static const uint64_t hip_writable_mask = MIP_VSSIP; |
| 1416 | static const uint64_t hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 1417 | MIP_VSEIP | LOCAL_INTERRUPTS; |
Rajnesh Kanwal | 87088fa | 2024-05-20 13:51:56 +0100 | [diff] [blame] | 1418 | static const uint64_t hvien_writable_mask = LOCAL_INTERRUPTS; |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 1419 | |
Rajnesh Kanwal | 87088fa | 2024-05-20 13:51:56 +0100 | [diff] [blame] | 1420 | static const uint64_t vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1421 | |
Alexandre Ghiti | 6f23aae | 2023-03-03 14:12:50 +0100 | [diff] [blame] | 1422 | const bool valid_vm_1_10_32[16] = { |
Alexandre Ghiti | bf1a6ab | 2023-03-03 14:12:49 +0100 | [diff] [blame] | 1423 | [VM_1_10_MBARE] = true, |
| 1424 | [VM_1_10_SV32] = true |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1425 | }; |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 1426 | |
Alexandre Ghiti | 6f23aae | 2023-03-03 14:12:50 +0100 | [diff] [blame] | 1427 | const bool valid_vm_1_10_64[16] = { |
Alexandre Ghiti | bf1a6ab | 2023-03-03 14:12:49 +0100 | [diff] [blame] | 1428 | [VM_1_10_MBARE] = true, |
| 1429 | [VM_1_10_SV39] = true, |
| 1430 | [VM_1_10_SV48] = true, |
| 1431 | [VM_1_10_SV57] = true |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1432 | }; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1433 | |
| 1434 | /* Machine Information Registers */ |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1435 | static RISCVException read_zero(CPURISCVState *env, int csrno, |
| 1436 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1437 | { |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1438 | *val = 0; |
| 1439 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1440 | } |
| 1441 | |
Anup Patel | d0237b4 | 2022-02-04 23:16:48 +0530 | [diff] [blame] | 1442 | static RISCVException write_ignore(CPURISCVState *env, int csrno, |
| 1443 | target_ulong val) |
| 1444 | { |
| 1445 | return RISCV_EXCP_NONE; |
| 1446 | } |
| 1447 | |
Frank Chang | 9951ba9 | 2022-04-22 12:04:34 +0800 | [diff] [blame] | 1448 | static RISCVException read_mvendorid(CPURISCVState *env, int csrno, |
| 1449 | target_ulong *val) |
| 1450 | { |
Weiwei Li | 9c33e08 | 2023-03-09 15:13:26 +0800 | [diff] [blame] | 1451 | *val = riscv_cpu_cfg(env)->mvendorid; |
Frank Chang | 9951ba9 | 2022-04-22 12:04:34 +0800 | [diff] [blame] | 1452 | return RISCV_EXCP_NONE; |
| 1453 | } |
| 1454 | |
| 1455 | static RISCVException read_marchid(CPURISCVState *env, int csrno, |
| 1456 | target_ulong *val) |
| 1457 | { |
Weiwei Li | 9c33e08 | 2023-03-09 15:13:26 +0800 | [diff] [blame] | 1458 | *val = riscv_cpu_cfg(env)->marchid; |
Frank Chang | 9951ba9 | 2022-04-22 12:04:34 +0800 | [diff] [blame] | 1459 | return RISCV_EXCP_NONE; |
| 1460 | } |
| 1461 | |
Frank Chang | 075eeda | 2022-05-23 23:31:46 +0800 | [diff] [blame] | 1462 | static RISCVException read_mimpid(CPURISCVState *env, int csrno, |
| 1463 | target_ulong *val) |
Frank Chang | 9951ba9 | 2022-04-22 12:04:34 +0800 | [diff] [blame] | 1464 | { |
Weiwei Li | 9c33e08 | 2023-03-09 15:13:26 +0800 | [diff] [blame] | 1465 | *val = riscv_cpu_cfg(env)->mimpid; |
Frank Chang | 9951ba9 | 2022-04-22 12:04:34 +0800 | [diff] [blame] | 1466 | return RISCV_EXCP_NONE; |
| 1467 | } |
| 1468 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1469 | static RISCVException read_mhartid(CPURISCVState *env, int csrno, |
| 1470 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1471 | { |
| 1472 | *val = env->mhartid; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1473 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1474 | } |
| 1475 | |
| 1476 | /* Machine Trap Setup */ |
Richard Henderson | b550f89 | 2021-10-19 20:17:09 -0700 | [diff] [blame] | 1477 | |
| 1478 | /* We do not store SD explicitly, only compute it on demand. */ |
| 1479 | static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) |
| 1480 | { |
| 1481 | if ((status & MSTATUS_FS) == MSTATUS_FS || |
Frank Chang | c36b2f1 | 2021-12-10 15:55:50 +0800 | [diff] [blame] | 1482 | (status & MSTATUS_VS) == MSTATUS_VS || |
Richard Henderson | b550f89 | 2021-10-19 20:17:09 -0700 | [diff] [blame] | 1483 | (status & MSTATUS_XS) == MSTATUS_XS) { |
| 1484 | switch (xl) { |
| 1485 | case MXL_RV32: |
| 1486 | return status | MSTATUS32_SD; |
| 1487 | case MXL_RV64: |
| 1488 | return status | MSTATUS64_SD; |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 1489 | case MXL_RV128: |
| 1490 | return MSTATUSH128_SD; |
Richard Henderson | b550f89 | 2021-10-19 20:17:09 -0700 | [diff] [blame] | 1491 | default: |
| 1492 | g_assert_not_reached(); |
| 1493 | } |
| 1494 | } |
| 1495 | return status; |
| 1496 | } |
| 1497 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1498 | static RISCVException read_mstatus(CPURISCVState *env, int csrno, |
| 1499 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1500 | { |
Richard Henderson | b550f89 | 2021-10-19 20:17:09 -0700 | [diff] [blame] | 1501 | *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1502 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1503 | } |
| 1504 | |
Alexandre Ghiti | bf1a6ab | 2023-03-03 14:12:49 +0100 | [diff] [blame] | 1505 | static bool validate_vm(CPURISCVState *env, target_ulong vm) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1506 | { |
Irina Ryapolova | 57020a4 | 2024-01-09 17:59:21 +0300 | [diff] [blame] | 1507 | uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.map; |
| 1508 | return get_field(mode_supported, (1 << vm)); |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1509 | } |
| 1510 | |
Irina Ryapolova | 1349f96 | 2024-01-09 17:59:22 +0300 | [diff] [blame] | 1511 | static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xatp, |
| 1512 | target_ulong val) |
| 1513 | { |
| 1514 | target_ulong mask; |
| 1515 | bool vm; |
| 1516 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 1517 | vm = validate_vm(env, get_field(val, SATP32_MODE)); |
| 1518 | mask = (val ^ old_xatp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); |
| 1519 | } else { |
| 1520 | vm = validate_vm(env, get_field(val, SATP64_MODE)); |
| 1521 | mask = (val ^ old_xatp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); |
| 1522 | } |
| 1523 | |
| 1524 | if (vm && mask) { |
| 1525 | /* |
| 1526 | * The ISA defines SATP.MODE=Bare as "no translation", but we still |
| 1527 | * pass these through QEMU's TLB emulation as it improves |
| 1528 | * performance. Flushing the TLB on SATP writes with paging |
| 1529 | * enabled avoids leaking those invalid cached mappings. |
| 1530 | */ |
| 1531 | tlb_flush(env_cpu(env)); |
| 1532 | return val; |
| 1533 | } |
| 1534 | return old_xatp; |
| 1535 | } |
| 1536 | |
Weiwei Li | 0c98cce | 2023-04-07 09:47:43 +0800 | [diff] [blame] | 1537 | static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp, |
| 1538 | target_ulong val) |
| 1539 | { |
| 1540 | bool valid = false; |
| 1541 | target_ulong new_mpp = get_field(val, MSTATUS_MPP); |
| 1542 | |
| 1543 | switch (new_mpp) { |
| 1544 | case PRV_M: |
| 1545 | valid = true; |
| 1546 | break; |
| 1547 | case PRV_S: |
| 1548 | valid = riscv_has_ext(env, RVS); |
| 1549 | break; |
| 1550 | case PRV_U: |
| 1551 | valid = riscv_has_ext(env, RVU); |
| 1552 | break; |
| 1553 | } |
| 1554 | |
| 1555 | /* Remain field unchanged if new_mpp value is invalid */ |
| 1556 | if (!valid) { |
| 1557 | val = set_field(val, MSTATUS_MPP, old_mpp); |
| 1558 | } |
| 1559 | |
| 1560 | return val; |
| 1561 | } |
| 1562 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1563 | static RISCVException write_mstatus(CPURISCVState *env, int csrno, |
| 1564 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1565 | { |
Yifei Jiang | 284d697 | 2020-10-26 19:55:25 +0800 | [diff] [blame] | 1566 | uint64_t mstatus = env->mstatus; |
| 1567 | uint64_t mask = 0; |
LIU Zhiwei | f310df5 | 2022-01-20 20:20:49 +0800 | [diff] [blame] | 1568 | RISCVMXL xl = riscv_cpu_mxl(env); |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1569 | |
Weiwei Li | 0c98cce | 2023-04-07 09:47:43 +0800 | [diff] [blame] | 1570 | /* |
| 1571 | * MPP field have been made WARL since priv version 1.11. However, |
| 1572 | * legalization for it will not break any software running on 1.10. |
| 1573 | */ |
| 1574 | val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val); |
| 1575 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1576 | /* flush tlb on mstatus fields that affect VM */ |
Richard Henderson | 696bacd | 2023-04-12 13:43:24 +0200 | [diff] [blame] | 1577 | if ((val ^ mstatus) & MSTATUS_MXR) { |
Alistair Francis | 1a9540d | 2020-05-05 13:04:50 -0700 | [diff] [blame] | 1578 | tlb_flush(env_cpu(env)); |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1579 | } |
Alistair Francis | 1a9540d | 2020-05-05 13:04:50 -0700 | [diff] [blame] | 1580 | mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | |
Weiwei Li | c163b3b | 2022-02-11 12:39:16 +0800 | [diff] [blame] | 1581 | MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | |
Alistair Francis | 1a9540d | 2020-05-05 13:04:50 -0700 | [diff] [blame] | 1582 | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | |
LIU Zhiwei | 7767f8b | 2023-12-15 10:33:13 +0800 | [diff] [blame] | 1583 | MSTATUS_TW; |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 1584 | |
Weiwei Li | c163b3b | 2022-02-11 12:39:16 +0800 | [diff] [blame] | 1585 | if (riscv_has_ext(env, RVF)) { |
| 1586 | mask |= MSTATUS_FS; |
| 1587 | } |
LIU Zhiwei | 7767f8b | 2023-12-15 10:33:13 +0800 | [diff] [blame] | 1588 | if (riscv_has_ext(env, RVV)) { |
| 1589 | mask |= MSTATUS_VS; |
| 1590 | } |
Weiwei Li | c163b3b | 2022-02-11 12:39:16 +0800 | [diff] [blame] | 1591 | |
LIU Zhiwei | f297245 | 2022-01-20 20:20:50 +0800 | [diff] [blame] | 1592 | if (xl != MXL_RV32 || env->debugger) { |
Weiwei Li | 03dd405 | 2023-06-03 21:42:35 +0800 | [diff] [blame] | 1593 | if (riscv_has_ext(env, RVH)) { |
| 1594 | mask |= MSTATUS_MPV | MSTATUS_GVA; |
| 1595 | } |
LIU Zhiwei | f310df5 | 2022-01-20 20:20:49 +0800 | [diff] [blame] | 1596 | if ((val & MSTATUS64_UXL) != 0) { |
| 1597 | mask |= MSTATUS64_UXL; |
| 1598 | } |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 1599 | } |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1600 | |
| 1601 | mstatus = (mstatus & ~mask) | (val & mask); |
| 1602 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1603 | env->mstatus = mstatus; |
| 1604 | |
Weiwei Li | 30a0d77 | 2023-05-24 09:59:33 +0800 | [diff] [blame] | 1605 | /* |
| 1606 | * Except in debug mode, UXL/SXL can only be modified by higher |
| 1607 | * privilege mode. So xl will not be changed in normal mode. |
| 1608 | */ |
| 1609 | if (env->debugger) { |
| 1610 | env->xl = cpu_recompute_xl(env); |
Weiwei Li | 30a0d77 | 2023-05-24 09:59:33 +0800 | [diff] [blame] | 1611 | } |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 1612 | |
| 1613 | riscv_cpu_update_mask(env); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1614 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1615 | } |
| 1616 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1617 | static RISCVException read_mstatush(CPURISCVState *env, int csrno, |
| 1618 | target_ulong *val) |
Alistair Francis | 551fa7e | 2020-01-31 17:03:05 -0800 | [diff] [blame] | 1619 | { |
Yifei Jiang | 284d697 | 2020-10-26 19:55:25 +0800 | [diff] [blame] | 1620 | *val = env->mstatus >> 32; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1621 | return RISCV_EXCP_NONE; |
Alistair Francis | 551fa7e | 2020-01-31 17:03:05 -0800 | [diff] [blame] | 1622 | } |
| 1623 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1624 | static RISCVException write_mstatush(CPURISCVState *env, int csrno, |
| 1625 | target_ulong val) |
Alistair Francis | 551fa7e | 2020-01-31 17:03:05 -0800 | [diff] [blame] | 1626 | { |
Yifei Jiang | 284d697 | 2020-10-26 19:55:25 +0800 | [diff] [blame] | 1627 | uint64_t valh = (uint64_t)val << 32; |
Weiwei Li | 03dd405 | 2023-06-03 21:42:35 +0800 | [diff] [blame] | 1628 | uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; |
Yifei Jiang | 284d697 | 2020-10-26 19:55:25 +0800 | [diff] [blame] | 1629 | |
Yifei Jiang | 284d697 | 2020-10-26 19:55:25 +0800 | [diff] [blame] | 1630 | env->mstatus = (env->mstatus & ~mask) | (valh & mask); |
Alistair Francis | 551fa7e | 2020-01-31 17:03:05 -0800 | [diff] [blame] | 1631 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1632 | return RISCV_EXCP_NONE; |
Alistair Francis | 551fa7e | 2020-01-31 17:03:05 -0800 | [diff] [blame] | 1633 | } |
Alistair Francis | 551fa7e | 2020-01-31 17:03:05 -0800 | [diff] [blame] | 1634 | |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 1635 | static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, |
| 1636 | Int128 *val) |
| 1637 | { |
Weiwei Li | 246f879 | 2023-04-05 16:58:13 +0800 | [diff] [blame] | 1638 | *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, |
| 1639 | env->mstatus)); |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 1640 | return RISCV_EXCP_NONE; |
| 1641 | } |
| 1642 | |
| 1643 | static RISCVException read_misa_i128(CPURISCVState *env, int csrno, |
| 1644 | Int128 *val) |
| 1645 | { |
| 1646 | *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); |
| 1647 | return RISCV_EXCP_NONE; |
| 1648 | } |
| 1649 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1650 | static RISCVException read_misa(CPURISCVState *env, int csrno, |
| 1651 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1652 | { |
Richard Henderson | e91a722 | 2021-10-19 20:16:57 -0700 | [diff] [blame] | 1653 | target_ulong misa; |
| 1654 | |
| 1655 | switch (env->misa_mxl) { |
| 1656 | case MXL_RV32: |
| 1657 | misa = (target_ulong)MXL_RV32 << 30; |
| 1658 | break; |
| 1659 | #ifdef TARGET_RISCV64 |
| 1660 | case MXL_RV64: |
| 1661 | misa = (target_ulong)MXL_RV64 << 62; |
| 1662 | break; |
| 1663 | #endif |
| 1664 | default: |
| 1665 | g_assert_not_reached(); |
| 1666 | } |
| 1667 | |
| 1668 | *val = misa | env->misa_ext; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1669 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1670 | } |
| 1671 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1672 | static RISCVException write_misa(CPURISCVState *env, int csrno, |
| 1673 | target_ulong val) |
Michael Clark | f18637c | 2019-01-14 23:59:00 +0000 | [diff] [blame] | 1674 | { |
Daniel Henrique Barboza | faf3b5d | 2023-05-17 10:57:14 -0300 | [diff] [blame] | 1675 | RISCVCPU *cpu = env_archcpu(env); |
| 1676 | uint32_t orig_misa_ext = env->misa_ext; |
| 1677 | Error *local_err = NULL; |
| 1678 | |
Daniel Henrique Barboza | 54bd9b6 | 2023-02-22 15:51:58 -0300 | [diff] [blame] | 1679 | if (!riscv_cpu_cfg(env)->misa_w) { |
Michael Clark | f18637c | 2019-01-14 23:59:00 +0000 | [diff] [blame] | 1680 | /* drop write to misa */ |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1681 | return RISCV_EXCP_NONE; |
Michael Clark | f18637c | 2019-01-14 23:59:00 +0000 | [diff] [blame] | 1682 | } |
| 1683 | |
Michael Clark | f18637c | 2019-01-14 23:59:00 +0000 | [diff] [blame] | 1684 | /* Mask extensions that are not supported by this hart */ |
Richard Henderson | e91a722 | 2021-10-19 20:16:57 -0700 | [diff] [blame] | 1685 | val &= env->misa_ext_mask; |
Michael Clark | f18637c | 2019-01-14 23:59:00 +0000 | [diff] [blame] | 1686 | |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 1687 | /* |
| 1688 | * Suppress 'C' if next instruction is not aligned |
Michael Clark | f18637c | 2019-01-14 23:59:00 +0000 | [diff] [blame] | 1689 | * TODO: this should check next_pc |
| 1690 | */ |
| 1691 | if ((val & RVC) && (GETPC() & ~3) != 0) { |
| 1692 | val &= ~RVC; |
| 1693 | } |
| 1694 | |
Daniel Henrique Barboza | faf3b5d | 2023-05-17 10:57:14 -0300 | [diff] [blame] | 1695 | /* Disable RVG if any of its dependencies are disabled */ |
| 1696 | if (!(val & RVI && val & RVM && val & RVA && |
| 1697 | val & RVF && val & RVD)) { |
| 1698 | val &= ~RVG; |
| 1699 | } |
| 1700 | |
Richard Henderson | e91a722 | 2021-10-19 20:16:57 -0700 | [diff] [blame] | 1701 | /* If nothing changed, do nothing. */ |
| 1702 | if (val == env->misa_ext) { |
| 1703 | return RISCV_EXCP_NONE; |
Alistair Francis | 4fd7455 | 2021-04-24 13:33:18 +1000 | [diff] [blame] | 1704 | } |
Michael Clark | f18637c | 2019-01-14 23:59:00 +0000 | [diff] [blame] | 1705 | |
Daniel Henrique Barboza | faf3b5d | 2023-05-17 10:57:14 -0300 | [diff] [blame] | 1706 | env->misa_ext = val; |
| 1707 | riscv_cpu_validate_set_extensions(cpu, &local_err); |
| 1708 | if (local_err != NULL) { |
| 1709 | /* Rollback on validation error */ |
| 1710 | qemu_log_mask(LOG_GUEST_ERROR, "Unable to write MISA ext value " |
| 1711 | "0x%x, keeping existing MISA ext 0x%x\n", |
| 1712 | env->misa_ext, orig_misa_ext); |
| 1713 | |
| 1714 | env->misa_ext = orig_misa_ext; |
| 1715 | |
| 1716 | return RISCV_EXCP_NONE; |
| 1717 | } |
| 1718 | |
| 1719 | if (!(env->misa_ext & RVF)) { |
Weiwei Li | c163b3b | 2022-02-11 12:39:16 +0800 | [diff] [blame] | 1720 | env->mstatus &= ~MSTATUS_FS; |
| 1721 | } |
| 1722 | |
Michael Clark | f18637c | 2019-01-14 23:59:00 +0000 | [diff] [blame] | 1723 | /* flush translation cache */ |
Richard Henderson | e91a722 | 2021-10-19 20:16:57 -0700 | [diff] [blame] | 1724 | tb_flush(env_cpu(env)); |
LIU Zhiwei | 440544e | 2022-01-20 20:20:32 +0800 | [diff] [blame] | 1725 | env->xl = riscv_cpu_mxl(env); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1726 | return RISCV_EXCP_NONE; |
Michael Clark | f18637c | 2019-01-14 23:59:00 +0000 | [diff] [blame] | 1727 | } |
| 1728 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1729 | static RISCVException read_medeleg(CPURISCVState *env, int csrno, |
| 1730 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1731 | { |
| 1732 | *val = env->medeleg; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1733 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1734 | } |
| 1735 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1736 | static RISCVException write_medeleg(CPURISCVState *env, int csrno, |
| 1737 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1738 | { |
Jose Martins | bc083a5 | 2021-05-22 16:59:02 +0100 | [diff] [blame] | 1739 | env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1740 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1741 | } |
| 1742 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1743 | static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno, |
| 1744 | uint64_t *ret_val, |
| 1745 | uint64_t new_val, uint64_t wr_mask) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1746 | { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1747 | uint64_t mask = wr_mask & delegable_ints; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1748 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1749 | if (ret_val) { |
| 1750 | *ret_val = env->mideleg; |
| 1751 | } |
| 1752 | |
| 1753 | env->mideleg = (env->mideleg & ~mask) | (new_val & mask); |
| 1754 | |
Alistair Francis | 713d836 | 2020-01-31 17:02:15 -0800 | [diff] [blame] | 1755 | if (riscv_has_ext(env, RVH)) { |
Anup Patel | 881df35 | 2022-02-04 23:16:38 +0530 | [diff] [blame] | 1756 | env->mideleg |= HS_MODE_INTERRUPTS; |
Alistair Francis | 713d836 | 2020-01-31 17:02:15 -0800 | [diff] [blame] | 1757 | } |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1758 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1759 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1760 | } |
| 1761 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1762 | static RISCVException rmw_mideleg(CPURISCVState *env, int csrno, |
| 1763 | target_ulong *ret_val, |
| 1764 | target_ulong new_val, target_ulong wr_mask) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1765 | { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1766 | uint64_t rval; |
| 1767 | RISCVException ret; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1768 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1769 | ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); |
| 1770 | if (ret_val) { |
| 1771 | *ret_val = rval; |
Anup Patel | 881df35 | 2022-02-04 23:16:38 +0530 | [diff] [blame] | 1772 | } |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1773 | |
| 1774 | return ret; |
| 1775 | } |
| 1776 | |
| 1777 | static RISCVException rmw_midelegh(CPURISCVState *env, int csrno, |
| 1778 | target_ulong *ret_val, |
| 1779 | target_ulong new_val, |
| 1780 | target_ulong wr_mask) |
| 1781 | { |
| 1782 | uint64_t rval; |
| 1783 | RISCVException ret; |
| 1784 | |
| 1785 | ret = rmw_mideleg64(env, csrno, &rval, |
| 1786 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 1787 | if (ret_val) { |
| 1788 | *ret_val = rval >> 32; |
| 1789 | } |
| 1790 | |
| 1791 | return ret; |
| 1792 | } |
| 1793 | |
| 1794 | static RISCVException rmw_mie64(CPURISCVState *env, int csrno, |
| 1795 | uint64_t *ret_val, |
| 1796 | uint64_t new_val, uint64_t wr_mask) |
| 1797 | { |
| 1798 | uint64_t mask = wr_mask & all_ints; |
| 1799 | |
| 1800 | if (ret_val) { |
| 1801 | *ret_val = env->mie; |
| 1802 | } |
| 1803 | |
| 1804 | env->mie = (env->mie & ~mask) | (new_val & mask); |
| 1805 | |
| 1806 | if (!riscv_has_ext(env, RVH)) { |
Rajnesh Kanwal | a7b6917 | 2023-10-16 12:17:31 +0100 | [diff] [blame] | 1807 | env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS); |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1808 | } |
| 1809 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 1810 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 1811 | } |
| 1812 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 1813 | static RISCVException rmw_mie(CPURISCVState *env, int csrno, |
| 1814 | target_ulong *ret_val, |
| 1815 | target_ulong new_val, target_ulong wr_mask) |
| 1816 | { |
| 1817 | uint64_t rval; |
| 1818 | RISCVException ret; |
| 1819 | |
| 1820 | ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); |
| 1821 | if (ret_val) { |
| 1822 | *ret_val = rval; |
| 1823 | } |
| 1824 | |
| 1825 | return ret; |
| 1826 | } |
| 1827 | |
| 1828 | static RISCVException rmw_mieh(CPURISCVState *env, int csrno, |
| 1829 | target_ulong *ret_val, |
| 1830 | target_ulong new_val, target_ulong wr_mask) |
| 1831 | { |
| 1832 | uint64_t rval; |
| 1833 | RISCVException ret; |
| 1834 | |
| 1835 | ret = rmw_mie64(env, csrno, &rval, |
| 1836 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 1837 | if (ret_val) { |
| 1838 | *ret_val = rval >> 32; |
| 1839 | } |
| 1840 | |
| 1841 | return ret; |
| 1842 | } |
| 1843 | |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 1844 | static RISCVException rmw_mvien64(CPURISCVState *env, int csrno, |
| 1845 | uint64_t *ret_val, |
| 1846 | uint64_t new_val, uint64_t wr_mask) |
| 1847 | { |
| 1848 | uint64_t mask = wr_mask & mvien_writable_mask; |
| 1849 | |
| 1850 | if (ret_val) { |
| 1851 | *ret_val = env->mvien; |
| 1852 | } |
| 1853 | |
| 1854 | env->mvien = (env->mvien & ~mask) | (new_val & mask); |
| 1855 | |
| 1856 | return RISCV_EXCP_NONE; |
| 1857 | } |
| 1858 | |
| 1859 | static RISCVException rmw_mvien(CPURISCVState *env, int csrno, |
| 1860 | target_ulong *ret_val, |
| 1861 | target_ulong new_val, target_ulong wr_mask) |
| 1862 | { |
| 1863 | uint64_t rval; |
| 1864 | RISCVException ret; |
| 1865 | |
| 1866 | ret = rmw_mvien64(env, csrno, &rval, new_val, wr_mask); |
| 1867 | if (ret_val) { |
| 1868 | *ret_val = rval; |
| 1869 | } |
| 1870 | |
| 1871 | return ret; |
| 1872 | } |
| 1873 | |
| 1874 | static RISCVException rmw_mvienh(CPURISCVState *env, int csrno, |
| 1875 | target_ulong *ret_val, |
| 1876 | target_ulong new_val, target_ulong wr_mask) |
| 1877 | { |
| 1878 | uint64_t rval; |
| 1879 | RISCVException ret; |
| 1880 | |
| 1881 | ret = rmw_mvien64(env, csrno, &rval, |
| 1882 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 1883 | if (ret_val) { |
| 1884 | *ret_val = rval >> 32; |
| 1885 | } |
| 1886 | |
| 1887 | return ret; |
| 1888 | } |
| 1889 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 1890 | static RISCVException read_mtopi(CPURISCVState *env, int csrno, |
| 1891 | target_ulong *val) |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 1892 | { |
| 1893 | int irq; |
| 1894 | uint8_t iprio; |
| 1895 | |
| 1896 | irq = riscv_cpu_mirq_pending(env); |
| 1897 | if (irq <= 0 || irq > 63) { |
| 1898 | *val = 0; |
| 1899 | } else { |
| 1900 | iprio = env->miprio[irq]; |
| 1901 | if (!iprio) { |
| 1902 | if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { |
| 1903 | iprio = IPRIO_MMAXIPRIO; |
| 1904 | } |
| 1905 | } |
| 1906 | *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; |
| 1907 | *val |= iprio; |
| 1908 | } |
| 1909 | |
| 1910 | return RISCV_EXCP_NONE; |
| 1911 | } |
| 1912 | |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 1913 | static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) |
| 1914 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 1915 | if (!env->virt_enabled) { |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 1916 | return csrno; |
| 1917 | } |
| 1918 | |
| 1919 | switch (csrno) { |
| 1920 | case CSR_SISELECT: |
| 1921 | return CSR_VSISELECT; |
| 1922 | case CSR_SIREG: |
| 1923 | return CSR_VSIREG; |
Anup Patel | ac4b030 | 2022-02-04 23:16:51 +0530 | [diff] [blame] | 1924 | case CSR_STOPEI: |
| 1925 | return CSR_VSTOPEI; |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 1926 | default: |
| 1927 | return csrno; |
| 1928 | }; |
| 1929 | } |
| 1930 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 1931 | static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, |
| 1932 | target_ulong *val, target_ulong new_val, |
| 1933 | target_ulong wr_mask) |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 1934 | { |
| 1935 | target_ulong *iselect; |
| 1936 | |
| 1937 | /* Translate CSR number for VS-mode */ |
| 1938 | csrno = aia_xlate_vs_csrno(env, csrno); |
| 1939 | |
| 1940 | /* Find the iselect CSR based on CSR number */ |
| 1941 | switch (csrno) { |
| 1942 | case CSR_MISELECT: |
| 1943 | iselect = &env->miselect; |
| 1944 | break; |
| 1945 | case CSR_SISELECT: |
| 1946 | iselect = &env->siselect; |
| 1947 | break; |
| 1948 | case CSR_VSISELECT: |
| 1949 | iselect = &env->vsiselect; |
| 1950 | break; |
| 1951 | default: |
| 1952 | return RISCV_EXCP_ILLEGAL_INST; |
| 1953 | }; |
| 1954 | |
| 1955 | if (val) { |
| 1956 | *val = *iselect; |
| 1957 | } |
| 1958 | |
| 1959 | wr_mask &= ISELECT_MASK; |
| 1960 | if (wr_mask) { |
| 1961 | *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); |
| 1962 | } |
| 1963 | |
| 1964 | return RISCV_EXCP_NONE; |
| 1965 | } |
| 1966 | |
| 1967 | static int rmw_iprio(target_ulong xlen, |
| 1968 | target_ulong iselect, uint8_t *iprio, |
| 1969 | target_ulong *val, target_ulong new_val, |
| 1970 | target_ulong wr_mask, int ext_irq_no) |
| 1971 | { |
| 1972 | int i, firq, nirqs; |
| 1973 | target_ulong old_val; |
| 1974 | |
| 1975 | if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) { |
| 1976 | return -EINVAL; |
| 1977 | } |
| 1978 | if (xlen != 32 && iselect & 0x1) { |
| 1979 | return -EINVAL; |
| 1980 | } |
| 1981 | |
| 1982 | nirqs = 4 * (xlen / 32); |
| 1983 | firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs); |
| 1984 | |
| 1985 | old_val = 0; |
| 1986 | for (i = 0; i < nirqs; i++) { |
| 1987 | old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i); |
| 1988 | } |
| 1989 | |
| 1990 | if (val) { |
| 1991 | *val = old_val; |
| 1992 | } |
| 1993 | |
| 1994 | if (wr_mask) { |
| 1995 | new_val = (old_val & ~wr_mask) | (new_val & wr_mask); |
| 1996 | for (i = 0; i < nirqs; i++) { |
| 1997 | /* |
| 1998 | * M-level and S-level external IRQ priority always read-only |
| 1999 | * zero. This means default priority order is always preferred |
| 2000 | * for M-level and S-level external IRQs. |
| 2001 | */ |
| 2002 | if ((firq + i) == ext_irq_no) { |
| 2003 | continue; |
| 2004 | } |
| 2005 | iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff; |
| 2006 | } |
| 2007 | } |
| 2008 | |
| 2009 | return 0; |
| 2010 | } |
| 2011 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 2012 | static RISCVException rmw_xireg(CPURISCVState *env, int csrno, |
| 2013 | target_ulong *val, target_ulong new_val, |
| 2014 | target_ulong wr_mask) |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 2015 | { |
Tommy Wu | 4df2823 | 2023-08-15 23:16:43 -0700 | [diff] [blame] | 2016 | bool virt, isel_reserved; |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 2017 | uint8_t *iprio; |
| 2018 | int ret = -EINVAL; |
| 2019 | target_ulong priv, isel, vgein; |
| 2020 | |
| 2021 | /* Translate CSR number for VS-mode */ |
| 2022 | csrno = aia_xlate_vs_csrno(env, csrno); |
| 2023 | |
| 2024 | /* Decode register details from CSR number */ |
| 2025 | virt = false; |
Tommy Wu | 4df2823 | 2023-08-15 23:16:43 -0700 | [diff] [blame] | 2026 | isel_reserved = false; |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 2027 | switch (csrno) { |
| 2028 | case CSR_MIREG: |
| 2029 | iprio = env->miprio; |
| 2030 | isel = env->miselect; |
| 2031 | priv = PRV_M; |
| 2032 | break; |
| 2033 | case CSR_SIREG: |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 2034 | if (env->priv == PRV_S && env->mvien & MIP_SEIP && |
| 2035 | env->siselect >= ISELECT_IMSIC_EIDELIVERY && |
| 2036 | env->siselect <= ISELECT_IMSIC_EIE63) { |
| 2037 | goto done; |
| 2038 | } |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 2039 | iprio = env->siprio; |
| 2040 | isel = env->siselect; |
| 2041 | priv = PRV_S; |
| 2042 | break; |
| 2043 | case CSR_VSIREG: |
| 2044 | iprio = env->hviprio; |
| 2045 | isel = env->vsiselect; |
| 2046 | priv = PRV_S; |
| 2047 | virt = true; |
| 2048 | break; |
| 2049 | default: |
| 2050 | goto done; |
| 2051 | }; |
| 2052 | |
| 2053 | /* Find the selected guest interrupt file */ |
| 2054 | vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; |
| 2055 | |
| 2056 | if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) { |
| 2057 | /* Local interrupt priority registers not available for VS-mode */ |
| 2058 | if (!virt) { |
| 2059 | ret = rmw_iprio(riscv_cpu_mxl_bits(env), |
| 2060 | isel, iprio, val, new_val, wr_mask, |
| 2061 | (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); |
| 2062 | } |
| 2063 | } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) { |
| 2064 | /* IMSIC registers only available when machine implements it. */ |
| 2065 | if (env->aia_ireg_rmw_fn[priv]) { |
| 2066 | /* Selected guest interrupt file should not be zero */ |
| 2067 | if (virt && (!vgein || env->geilen < vgein)) { |
| 2068 | goto done; |
| 2069 | } |
| 2070 | /* Call machine specific IMSIC register emulation */ |
| 2071 | ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], |
| 2072 | AIA_MAKE_IREG(isel, priv, virt, vgein, |
| 2073 | riscv_cpu_mxl_bits(env)), |
| 2074 | val, new_val, wr_mask); |
| 2075 | } |
Tommy Wu | 4df2823 | 2023-08-15 23:16:43 -0700 | [diff] [blame] | 2076 | } else { |
| 2077 | isel_reserved = true; |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 2078 | } |
| 2079 | |
| 2080 | done: |
| 2081 | if (ret) { |
Tommy Wu | 4df2823 | 2023-08-15 23:16:43 -0700 | [diff] [blame] | 2082 | return (env->virt_enabled && virt && !isel_reserved) ? |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 2083 | RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; |
| 2084 | } |
| 2085 | return RISCV_EXCP_NONE; |
| 2086 | } |
| 2087 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 2088 | static RISCVException rmw_xtopei(CPURISCVState *env, int csrno, |
| 2089 | target_ulong *val, target_ulong new_val, |
| 2090 | target_ulong wr_mask) |
Anup Patel | ac4b030 | 2022-02-04 23:16:51 +0530 | [diff] [blame] | 2091 | { |
| 2092 | bool virt; |
| 2093 | int ret = -EINVAL; |
| 2094 | target_ulong priv, vgein; |
| 2095 | |
| 2096 | /* Translate CSR number for VS-mode */ |
| 2097 | csrno = aia_xlate_vs_csrno(env, csrno); |
| 2098 | |
| 2099 | /* Decode register details from CSR number */ |
| 2100 | virt = false; |
| 2101 | switch (csrno) { |
| 2102 | case CSR_MTOPEI: |
| 2103 | priv = PRV_M; |
| 2104 | break; |
| 2105 | case CSR_STOPEI: |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 2106 | if (env->mvien & MIP_SEIP && env->priv == PRV_S) { |
| 2107 | goto done; |
| 2108 | } |
Anup Patel | ac4b030 | 2022-02-04 23:16:51 +0530 | [diff] [blame] | 2109 | priv = PRV_S; |
| 2110 | break; |
| 2111 | case CSR_VSTOPEI: |
| 2112 | priv = PRV_S; |
| 2113 | virt = true; |
| 2114 | break; |
| 2115 | default: |
| 2116 | goto done; |
| 2117 | }; |
| 2118 | |
| 2119 | /* IMSIC CSRs only available when machine implements IMSIC. */ |
| 2120 | if (!env->aia_ireg_rmw_fn[priv]) { |
| 2121 | goto done; |
| 2122 | } |
| 2123 | |
| 2124 | /* Find the selected guest interrupt file */ |
| 2125 | vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; |
| 2126 | |
| 2127 | /* Selected guest interrupt file should be valid */ |
| 2128 | if (virt && (!vgein || env->geilen < vgein)) { |
| 2129 | goto done; |
| 2130 | } |
| 2131 | |
| 2132 | /* Call machine specific IMSIC register emulation for TOPEI */ |
| 2133 | ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], |
| 2134 | AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, |
| 2135 | riscv_cpu_mxl_bits(env)), |
| 2136 | val, new_val, wr_mask); |
| 2137 | |
| 2138 | done: |
| 2139 | if (ret) { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 2140 | return (env->virt_enabled && virt) ? |
Anup Patel | ac4b030 | 2022-02-04 23:16:51 +0530 | [diff] [blame] | 2141 | RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; |
| 2142 | } |
| 2143 | return RISCV_EXCP_NONE; |
| 2144 | } |
| 2145 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2146 | static RISCVException read_mtvec(CPURISCVState *env, int csrno, |
| 2147 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2148 | { |
| 2149 | *val = env->mtvec; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2150 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2151 | } |
| 2152 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2153 | static RISCVException write_mtvec(CPURISCVState *env, int csrno, |
| 2154 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2155 | { |
| 2156 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ |
Michael Clark | acbbb94 | 2019-03-16 01:21:03 +0000 | [diff] [blame] | 2157 | if ((val & 3) < 2) { |
| 2158 | env->mtvec = val; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2159 | } else { |
Michael Clark | acbbb94 | 2019-03-16 01:21:03 +0000 | [diff] [blame] | 2160 | qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2161 | } |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2162 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2163 | } |
| 2164 | |
Atish Patra | b1675ee | 2022-06-20 16:15:55 -0700 | [diff] [blame] | 2165 | static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno, |
| 2166 | target_ulong *val) |
| 2167 | { |
Atish Patra | b1675ee | 2022-06-20 16:15:55 -0700 | [diff] [blame] | 2168 | *val = env->mcountinhibit; |
| 2169 | return RISCV_EXCP_NONE; |
| 2170 | } |
| 2171 | |
| 2172 | static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, |
| 2173 | target_ulong val) |
| 2174 | { |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 2175 | int cidx; |
| 2176 | PMUCTRState *counter; |
Rob Bradford | ebe16b9 | 2023-08-02 13:49:06 +0100 | [diff] [blame] | 2177 | RISCVCPU *cpu = env_archcpu(env); |
Rajnesh Kanwal | 22c721c | 2024-07-11 15:31:13 -0700 | [diff] [blame] | 2178 | uint32_t present_ctrs = cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR; |
| 2179 | target_ulong updated_ctrs = (env->mcountinhibit ^ val) & present_ctrs; |
| 2180 | uint64_t mhpmctr_val, prev_count, curr_count; |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 2181 | |
Rob Bradford | ebe16b9 | 2023-08-02 13:49:06 +0100 | [diff] [blame] | 2182 | /* WARL register - disable unavailable counters; TM bit is always 0 */ |
Rajnesh Kanwal | 22c721c | 2024-07-11 15:31:13 -0700 | [diff] [blame] | 2183 | env->mcountinhibit = val & present_ctrs; |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 2184 | |
| 2185 | /* Check if any other counter is also monitoring cycles/instructions */ |
| 2186 | for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { |
Rajnesh Kanwal | 22c721c | 2024-07-11 15:31:13 -0700 | [diff] [blame] | 2187 | if (!(updated_ctrs & BIT(cidx)) || |
| 2188 | (!riscv_pmu_ctr_monitor_cycles(env, cidx) && |
| 2189 | !riscv_pmu_ctr_monitor_instructions(env, cidx))) { |
| 2190 | continue; |
| 2191 | } |
| 2192 | |
| 2193 | counter = &env->pmu_ctrs[cidx]; |
| 2194 | |
| 2195 | if (!get_field(env->mcountinhibit, BIT(cidx))) { |
| 2196 | counter->mhpmcounter_prev = |
| 2197 | riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false); |
| 2198 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 2199 | counter->mhpmcounterh_prev = |
| 2200 | riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true); |
| 2201 | } |
| 2202 | |
| 2203 | if (cidx > 2) { |
| 2204 | mhpmctr_val = counter->mhpmcounter_val; |
Atish Patra | 4602347 | 2024-07-11 15:31:11 -0700 | [diff] [blame] | 2205 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
Rajnesh Kanwal | 22c721c | 2024-07-11 15:31:13 -0700 | [diff] [blame] | 2206 | mhpmctr_val = mhpmctr_val | |
| 2207 | ((uint64_t)counter->mhpmcounterh_val << 32); |
Atish Patra | 4602347 | 2024-07-11 15:31:11 -0700 | [diff] [blame] | 2208 | } |
Rajnesh Kanwal | 22c721c | 2024-07-11 15:31:13 -0700 | [diff] [blame] | 2209 | riscv_pmu_setup_timer(env, mhpmctr_val, cidx); |
| 2210 | } |
| 2211 | } else { |
| 2212 | curr_count = riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false); |
| 2213 | |
| 2214 | mhpmctr_val = counter->mhpmcounter_val; |
| 2215 | prev_count = counter->mhpmcounter_prev; |
| 2216 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 2217 | uint64_t tmp = |
| 2218 | riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true); |
| 2219 | |
| 2220 | curr_count = curr_count | (tmp << 32); |
| 2221 | mhpmctr_val = mhpmctr_val | |
| 2222 | ((uint64_t)counter->mhpmcounterh_val << 32); |
| 2223 | prev_count = prev_count | |
| 2224 | ((uint64_t)counter->mhpmcounterh_prev << 32); |
| 2225 | } |
| 2226 | |
| 2227 | /* Adjust the counter for later reads. */ |
| 2228 | mhpmctr_val = curr_count - prev_count + mhpmctr_val; |
| 2229 | counter->mhpmcounter_val = mhpmctr_val; |
| 2230 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 2231 | counter->mhpmcounterh_val = mhpmctr_val >> 32; |
Atish Patra | 4602347 | 2024-07-11 15:31:11 -0700 | [diff] [blame] | 2232 | } |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 2233 | } |
| 2234 | } |
| 2235 | |
Atish Patra | b1675ee | 2022-06-20 16:15:55 -0700 | [diff] [blame] | 2236 | return RISCV_EXCP_NONE; |
| 2237 | } |
| 2238 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2239 | static RISCVException read_mcounteren(CPURISCVState *env, int csrno, |
| 2240 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2241 | { |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2242 | *val = env->mcounteren; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2243 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2244 | } |
| 2245 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2246 | static RISCVException write_mcounteren(CPURISCVState *env, int csrno, |
| 2247 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2248 | { |
Rob Bradford | ebe16b9 | 2023-08-02 13:49:06 +0100 | [diff] [blame] | 2249 | RISCVCPU *cpu = env_archcpu(env); |
| 2250 | |
| 2251 | /* WARL register - disable unavailable counters */ |
| 2252 | env->mcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM | |
| 2253 | COUNTEREN_IR); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2254 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2255 | } |
| 2256 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2257 | /* Machine Trap Handling */ |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 2258 | static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, |
| 2259 | Int128 *val) |
| 2260 | { |
| 2261 | *val = int128_make128(env->mscratch, env->mscratchh); |
| 2262 | return RISCV_EXCP_NONE; |
| 2263 | } |
| 2264 | |
| 2265 | static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, |
| 2266 | Int128 val) |
| 2267 | { |
| 2268 | env->mscratch = int128_getlo(val); |
| 2269 | env->mscratchh = int128_gethi(val); |
| 2270 | return RISCV_EXCP_NONE; |
| 2271 | } |
| 2272 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2273 | static RISCVException read_mscratch(CPURISCVState *env, int csrno, |
| 2274 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2275 | { |
| 2276 | *val = env->mscratch; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2277 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2278 | } |
| 2279 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2280 | static RISCVException write_mscratch(CPURISCVState *env, int csrno, |
| 2281 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2282 | { |
| 2283 | env->mscratch = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2284 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2285 | } |
| 2286 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2287 | static RISCVException read_mepc(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2288 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2289 | { |
| 2290 | *val = env->mepc; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2291 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2292 | } |
| 2293 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2294 | static RISCVException write_mepc(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2295 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2296 | { |
| 2297 | env->mepc = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2298 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2299 | } |
| 2300 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2301 | static RISCVException read_mcause(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2302 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2303 | { |
| 2304 | *val = env->mcause; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2305 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2306 | } |
| 2307 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2308 | static RISCVException write_mcause(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2309 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2310 | { |
| 2311 | env->mcause = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2312 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2313 | } |
| 2314 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2315 | static RISCVException read_mtval(CPURISCVState *env, int csrno, |
| 2316 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2317 | { |
Atish Patra | ac12b60 | 2021-03-19 12:45:29 -0700 | [diff] [blame] | 2318 | *val = env->mtval; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2319 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2320 | } |
| 2321 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2322 | static RISCVException write_mtval(CPURISCVState *env, int csrno, |
| 2323 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2324 | { |
Atish Patra | ac12b60 | 2021-03-19 12:45:29 -0700 | [diff] [blame] | 2325 | env->mtval = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2326 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2327 | } |
| 2328 | |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2329 | /* Execution environment configuration setup */ |
| 2330 | static RISCVException read_menvcfg(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2331 | target_ulong *val) |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2332 | { |
| 2333 | *val = env->menvcfg; |
| 2334 | return RISCV_EXCP_NONE; |
| 2335 | } |
| 2336 | |
| 2337 | static RISCVException write_menvcfg(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2338 | target_ulong val) |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2339 | { |
Weiwei Li | 9c33e08 | 2023-03-09 15:13:26 +0800 | [diff] [blame] | 2340 | const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2341 | uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; |
| 2342 | |
| 2343 | if (riscv_cpu_mxl(env) == MXL_RV64) { |
Weiwei Li | 73ec0ea | 2023-02-24 12:08:47 +0800 | [diff] [blame] | 2344 | mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | |
Weiwei Li | 0d190bd | 2023-02-24 12:08:49 +0800 | [diff] [blame] | 2345 | (cfg->ext_sstc ? MENVCFG_STCE : 0) | |
Weiwei Li | ed67d63 | 2023-08-16 22:19:16 +0800 | [diff] [blame] | 2346 | (cfg->ext_svadu ? MENVCFG_ADUE : 0); |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2347 | } |
| 2348 | env->menvcfg = (env->menvcfg & ~mask) | (val & mask); |
| 2349 | |
| 2350 | return RISCV_EXCP_NONE; |
| 2351 | } |
| 2352 | |
| 2353 | static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2354 | target_ulong *val) |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2355 | { |
| 2356 | *val = env->menvcfg >> 32; |
| 2357 | return RISCV_EXCP_NONE; |
| 2358 | } |
| 2359 | |
| 2360 | static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2361 | target_ulong val) |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2362 | { |
Weiwei Li | 9c33e08 | 2023-03-09 15:13:26 +0800 | [diff] [blame] | 2363 | const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); |
Weiwei Li | 73ec0ea | 2023-02-24 12:08:47 +0800 | [diff] [blame] | 2364 | uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | |
Weiwei Li | 0d190bd | 2023-02-24 12:08:49 +0800 | [diff] [blame] | 2365 | (cfg->ext_sstc ? MENVCFG_STCE : 0) | |
Weiwei Li | ed67d63 | 2023-08-16 22:19:16 +0800 | [diff] [blame] | 2366 | (cfg->ext_svadu ? MENVCFG_ADUE : 0); |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2367 | uint64_t valh = (uint64_t)val << 32; |
| 2368 | |
| 2369 | env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); |
| 2370 | |
| 2371 | return RISCV_EXCP_NONE; |
| 2372 | } |
| 2373 | |
| 2374 | static RISCVException read_senvcfg(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2375 | target_ulong *val) |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2376 | { |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2377 | RISCVException ret; |
| 2378 | |
| 2379 | ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); |
| 2380 | if (ret != RISCV_EXCP_NONE) { |
| 2381 | return ret; |
| 2382 | } |
| 2383 | |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2384 | *val = env->senvcfg; |
| 2385 | return RISCV_EXCP_NONE; |
| 2386 | } |
| 2387 | |
| 2388 | static RISCVException write_senvcfg(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2389 | target_ulong val) |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2390 | { |
| 2391 | uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2392 | RISCVException ret; |
| 2393 | |
| 2394 | ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); |
| 2395 | if (ret != RISCV_EXCP_NONE) { |
| 2396 | return ret; |
| 2397 | } |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2398 | |
| 2399 | env->senvcfg = (env->senvcfg & ~mask) | (val & mask); |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2400 | return RISCV_EXCP_NONE; |
| 2401 | } |
| 2402 | |
| 2403 | static RISCVException read_henvcfg(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2404 | target_ulong *val) |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2405 | { |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2406 | RISCVException ret; |
| 2407 | |
| 2408 | ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); |
| 2409 | if (ret != RISCV_EXCP_NONE) { |
| 2410 | return ret; |
| 2411 | } |
| 2412 | |
Weiwei Li | 6f3eb1a | 2023-02-24 12:08:48 +0800 | [diff] [blame] | 2413 | /* |
| 2414 | * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 |
| 2415 | * henvcfg.stce is read_only 0 when menvcfg.stce = 0 |
Andrew Jones | 148189f | 2024-02-15 19:39:53 -0300 | [diff] [blame] | 2416 | * henvcfg.adue is read_only 0 when menvcfg.adue = 0 |
Weiwei Li | 6f3eb1a | 2023-02-24 12:08:48 +0800 | [diff] [blame] | 2417 | */ |
Weiwei Li | ed67d63 | 2023-08-16 22:19:16 +0800 | [diff] [blame] | 2418 | *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | |
Weiwei Li | 0d190bd | 2023-02-24 12:08:49 +0800 | [diff] [blame] | 2419 | env->menvcfg); |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2420 | return RISCV_EXCP_NONE; |
| 2421 | } |
| 2422 | |
| 2423 | static RISCVException write_henvcfg(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2424 | target_ulong val) |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2425 | { |
| 2426 | uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2427 | RISCVException ret; |
| 2428 | |
| 2429 | ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); |
| 2430 | if (ret != RISCV_EXCP_NONE) { |
| 2431 | return ret; |
| 2432 | } |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2433 | |
| 2434 | if (riscv_cpu_mxl(env) == MXL_RV64) { |
Weiwei Li | ed67d63 | 2023-08-16 22:19:16 +0800 | [diff] [blame] | 2435 | mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE); |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2436 | } |
| 2437 | |
| 2438 | env->henvcfg = (env->henvcfg & ~mask) | (val & mask); |
| 2439 | |
| 2440 | return RISCV_EXCP_NONE; |
| 2441 | } |
| 2442 | |
| 2443 | static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2444 | target_ulong *val) |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2445 | { |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2446 | RISCVException ret; |
| 2447 | |
| 2448 | ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); |
| 2449 | if (ret != RISCV_EXCP_NONE) { |
| 2450 | return ret; |
| 2451 | } |
| 2452 | |
Weiwei Li | ed67d63 | 2023-08-16 22:19:16 +0800 | [diff] [blame] | 2453 | *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | |
Weiwei Li | 6f3eb1a | 2023-02-24 12:08:48 +0800 | [diff] [blame] | 2454 | env->menvcfg)) >> 32; |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2455 | return RISCV_EXCP_NONE; |
| 2456 | } |
| 2457 | |
| 2458 | static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2459 | target_ulong val) |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2460 | { |
Weiwei Li | 0d190bd | 2023-02-24 12:08:49 +0800 | [diff] [blame] | 2461 | uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | |
Weiwei Li | ed67d63 | 2023-08-16 22:19:16 +0800 | [diff] [blame] | 2462 | HENVCFG_ADUE); |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2463 | uint64_t valh = (uint64_t)val << 32; |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2464 | RISCVException ret; |
| 2465 | |
| 2466 | ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); |
| 2467 | if (ret != RISCV_EXCP_NONE) { |
| 2468 | return ret; |
| 2469 | } |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2470 | |
| 2471 | env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 2472 | return RISCV_EXCP_NONE; |
| 2473 | } |
| 2474 | |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2475 | static RISCVException read_mstateen(CPURISCVState *env, int csrno, |
| 2476 | target_ulong *val) |
| 2477 | { |
| 2478 | *val = env->mstateen[csrno - CSR_MSTATEEN0]; |
| 2479 | |
| 2480 | return RISCV_EXCP_NONE; |
| 2481 | } |
| 2482 | |
| 2483 | static RISCVException write_mstateen(CPURISCVState *env, int csrno, |
| 2484 | uint64_t wr_mask, target_ulong new_val) |
| 2485 | { |
| 2486 | uint64_t *reg; |
| 2487 | |
| 2488 | reg = &env->mstateen[csrno - CSR_MSTATEEN0]; |
| 2489 | *reg = (*reg & ~wr_mask) | (new_val & wr_mask); |
| 2490 | |
| 2491 | return RISCV_EXCP_NONE; |
| 2492 | } |
| 2493 | |
| 2494 | static RISCVException write_mstateen0(CPURISCVState *env, int csrno, |
| 2495 | target_ulong new_val) |
| 2496 | { |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2497 | uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; |
Mayuresh Chitale | 9514fc7 | 2023-05-18 23:20:56 +0530 | [diff] [blame] | 2498 | if (!riscv_has_ext(env, RVF)) { |
| 2499 | wr_mask |= SMSTATEEN0_FCSR; |
| 2500 | } |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2501 | |
Fea.Wang | 7750e10 | 2024-06-06 21:54:51 +0800 | [diff] [blame] | 2502 | if (env->priv_ver >= PRIV_VERSION_1_13_0) { |
| 2503 | wr_mask |= SMSTATEEN0_P1P13; |
| 2504 | } |
| 2505 | |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2506 | return write_mstateen(env, csrno, wr_mask, new_val); |
| 2507 | } |
| 2508 | |
| 2509 | static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2510 | target_ulong new_val) |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2511 | { |
| 2512 | return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); |
| 2513 | } |
| 2514 | |
| 2515 | static RISCVException read_mstateenh(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2516 | target_ulong *val) |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2517 | { |
| 2518 | *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; |
| 2519 | |
| 2520 | return RISCV_EXCP_NONE; |
| 2521 | } |
| 2522 | |
| 2523 | static RISCVException write_mstateenh(CPURISCVState *env, int csrno, |
| 2524 | uint64_t wr_mask, target_ulong new_val) |
| 2525 | { |
| 2526 | uint64_t *reg, val; |
| 2527 | |
| 2528 | reg = &env->mstateen[csrno - CSR_MSTATEEN0H]; |
| 2529 | val = (uint64_t)new_val << 32; |
| 2530 | val |= *reg & 0xFFFFFFFF; |
| 2531 | *reg = (*reg & ~wr_mask) | (val & wr_mask); |
| 2532 | |
| 2533 | return RISCV_EXCP_NONE; |
| 2534 | } |
| 2535 | |
| 2536 | static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2537 | target_ulong new_val) |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2538 | { |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2539 | uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2540 | |
Fea.Wang | 7750e10 | 2024-06-06 21:54:51 +0800 | [diff] [blame] | 2541 | if (env->priv_ver >= PRIV_VERSION_1_13_0) { |
| 2542 | wr_mask |= SMSTATEEN0_P1P13; |
| 2543 | } |
| 2544 | |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2545 | return write_mstateenh(env, csrno, wr_mask, new_val); |
| 2546 | } |
| 2547 | |
| 2548 | static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2549 | target_ulong new_val) |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2550 | { |
| 2551 | return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); |
| 2552 | } |
| 2553 | |
| 2554 | static RISCVException read_hstateen(CPURISCVState *env, int csrno, |
| 2555 | target_ulong *val) |
| 2556 | { |
| 2557 | int index = csrno - CSR_HSTATEEN0; |
| 2558 | |
| 2559 | *val = env->hstateen[index] & env->mstateen[index]; |
| 2560 | |
| 2561 | return RISCV_EXCP_NONE; |
| 2562 | } |
| 2563 | |
| 2564 | static RISCVException write_hstateen(CPURISCVState *env, int csrno, |
| 2565 | uint64_t mask, target_ulong new_val) |
| 2566 | { |
| 2567 | int index = csrno - CSR_HSTATEEN0; |
| 2568 | uint64_t *reg, wr_mask; |
| 2569 | |
| 2570 | reg = &env->hstateen[index]; |
| 2571 | wr_mask = env->mstateen[index] & mask; |
| 2572 | *reg = (*reg & ~wr_mask) | (new_val & wr_mask); |
| 2573 | |
| 2574 | return RISCV_EXCP_NONE; |
| 2575 | } |
| 2576 | |
| 2577 | static RISCVException write_hstateen0(CPURISCVState *env, int csrno, |
| 2578 | target_ulong new_val) |
| 2579 | { |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2580 | uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2581 | |
Mayuresh Chitale | 9514fc7 | 2023-05-18 23:20:56 +0530 | [diff] [blame] | 2582 | if (!riscv_has_ext(env, RVF)) { |
| 2583 | wr_mask |= SMSTATEEN0_FCSR; |
| 2584 | } |
| 2585 | |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2586 | return write_hstateen(env, csrno, wr_mask, new_val); |
| 2587 | } |
| 2588 | |
| 2589 | static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2590 | target_ulong new_val) |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2591 | { |
| 2592 | return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); |
| 2593 | } |
| 2594 | |
| 2595 | static RISCVException read_hstateenh(CPURISCVState *env, int csrno, |
| 2596 | target_ulong *val) |
| 2597 | { |
| 2598 | int index = csrno - CSR_HSTATEEN0H; |
| 2599 | |
| 2600 | *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32); |
| 2601 | |
| 2602 | return RISCV_EXCP_NONE; |
| 2603 | } |
| 2604 | |
| 2605 | static RISCVException write_hstateenh(CPURISCVState *env, int csrno, |
| 2606 | uint64_t mask, target_ulong new_val) |
| 2607 | { |
| 2608 | int index = csrno - CSR_HSTATEEN0H; |
| 2609 | uint64_t *reg, wr_mask, val; |
| 2610 | |
| 2611 | reg = &env->hstateen[index]; |
| 2612 | val = (uint64_t)new_val << 32; |
| 2613 | val |= *reg & 0xFFFFFFFF; |
| 2614 | wr_mask = env->mstateen[index] & mask; |
| 2615 | *reg = (*reg & ~wr_mask) | (val & wr_mask); |
| 2616 | |
| 2617 | return RISCV_EXCP_NONE; |
| 2618 | } |
| 2619 | |
| 2620 | static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, |
| 2621 | target_ulong new_val) |
| 2622 | { |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2623 | uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2624 | |
| 2625 | return write_hstateenh(env, csrno, wr_mask, new_val); |
| 2626 | } |
| 2627 | |
| 2628 | static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 2629 | target_ulong new_val) |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2630 | { |
| 2631 | return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); |
| 2632 | } |
| 2633 | |
| 2634 | static RISCVException read_sstateen(CPURISCVState *env, int csrno, |
| 2635 | target_ulong *val) |
| 2636 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 2637 | bool virt = env->virt_enabled; |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2638 | int index = csrno - CSR_SSTATEEN0; |
| 2639 | |
| 2640 | *val = env->sstateen[index] & env->mstateen[index]; |
| 2641 | if (virt) { |
| 2642 | *val &= env->hstateen[index]; |
| 2643 | } |
| 2644 | |
| 2645 | return RISCV_EXCP_NONE; |
| 2646 | } |
| 2647 | |
| 2648 | static RISCVException write_sstateen(CPURISCVState *env, int csrno, |
| 2649 | uint64_t mask, target_ulong new_val) |
| 2650 | { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 2651 | bool virt = env->virt_enabled; |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2652 | int index = csrno - CSR_SSTATEEN0; |
| 2653 | uint64_t wr_mask; |
| 2654 | uint64_t *reg; |
| 2655 | |
| 2656 | wr_mask = env->mstateen[index] & mask; |
| 2657 | if (virt) { |
| 2658 | wr_mask &= env->hstateen[index]; |
| 2659 | } |
| 2660 | |
| 2661 | reg = &env->sstateen[index]; |
| 2662 | *reg = (*reg & ~wr_mask) | (new_val & wr_mask); |
| 2663 | |
| 2664 | return RISCV_EXCP_NONE; |
| 2665 | } |
| 2666 | |
| 2667 | static RISCVException write_sstateen0(CPURISCVState *env, int csrno, |
| 2668 | target_ulong new_val) |
| 2669 | { |
Mayuresh Chitale | 252b06f | 2022-10-16 18:17:23 +0530 | [diff] [blame] | 2670 | uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2671 | |
Mayuresh Chitale | 9514fc7 | 2023-05-18 23:20:56 +0530 | [diff] [blame] | 2672 | if (!riscv_has_ext(env, RVF)) { |
| 2673 | wr_mask |= SMSTATEEN0_FCSR; |
| 2674 | } |
| 2675 | |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 2676 | return write_sstateen(env, csrno, wr_mask, new_val); |
| 2677 | } |
| 2678 | |
| 2679 | static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno, |
| 2680 | target_ulong new_val) |
| 2681 | { |
| 2682 | return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); |
| 2683 | } |
| 2684 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 2685 | static RISCVException rmw_mip64(CPURISCVState *env, int csrno, |
| 2686 | uint64_t *ret_val, |
| 2687 | uint64_t new_val, uint64_t wr_mask) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2688 | { |
Alistair Francis | 33fe584 | 2022-03-17 16:18:17 +1000 | [diff] [blame] | 2689 | uint64_t old_mip, mask = wr_mask & delegable_ints; |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 2690 | uint32_t gin; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2691 | |
Alistair Francis | 33fe584 | 2022-03-17 16:18:17 +1000 | [diff] [blame] | 2692 | if (mask & MIP_SEIP) { |
| 2693 | env->software_seip = new_val & MIP_SEIP; |
| 2694 | new_val |= env->external_seip * MIP_SEIP; |
| 2695 | } |
| 2696 | |
Weiwei Li | bbb9fc2 | 2023-03-09 15:13:28 +0800 | [diff] [blame] | 2697 | if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) && |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 2698 | get_field(env->menvcfg, MENVCFG_STCE)) { |
| 2699 | /* sstc extension forbids STIP & VSTIP to be writeable in mip */ |
| 2700 | mask = mask & ~(MIP_STIP | MIP_VSTIP); |
| 2701 | } |
| 2702 | |
Michael Clark | 71877e2 | 2019-01-04 23:24:04 +0000 | [diff] [blame] | 2703 | if (mask) { |
Weiwei Li | bbb9fc2 | 2023-03-09 15:13:28 +0800 | [diff] [blame] | 2704 | old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask)); |
Michael Clark | 71877e2 | 2019-01-04 23:24:04 +0000 | [diff] [blame] | 2705 | } else { |
Alistair Francis | 7ec5d30 | 2019-10-08 15:04:18 -0700 | [diff] [blame] | 2706 | old_mip = env->mip; |
Michael Clark | 71877e2 | 2019-01-04 23:24:04 +0000 | [diff] [blame] | 2707 | } |
| 2708 | |
Anup Patel | cd032fe | 2022-02-04 23:16:39 +0530 | [diff] [blame] | 2709 | if (csrno != CSR_HVIP) { |
| 2710 | gin = get_field(env->hstatus, HSTATUS_VGEIN); |
| 2711 | old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0; |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 2712 | old_mip |= env->vstime_irq ? MIP_VSTIP : 0; |
Anup Patel | cd032fe | 2022-02-04 23:16:39 +0530 | [diff] [blame] | 2713 | } |
| 2714 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 2715 | if (ret_val) { |
| 2716 | *ret_val = old_mip; |
Michael Clark | 71877e2 | 2019-01-04 23:24:04 +0000 | [diff] [blame] | 2717 | } |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2718 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2719 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2720 | } |
| 2721 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 2722 | static RISCVException rmw_mip(CPURISCVState *env, int csrno, |
| 2723 | target_ulong *ret_val, |
| 2724 | target_ulong new_val, target_ulong wr_mask) |
| 2725 | { |
| 2726 | uint64_t rval; |
| 2727 | RISCVException ret; |
| 2728 | |
| 2729 | ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask); |
| 2730 | if (ret_val) { |
| 2731 | *ret_val = rval; |
| 2732 | } |
| 2733 | |
| 2734 | return ret; |
| 2735 | } |
| 2736 | |
| 2737 | static RISCVException rmw_miph(CPURISCVState *env, int csrno, |
| 2738 | target_ulong *ret_val, |
| 2739 | target_ulong new_val, target_ulong wr_mask) |
| 2740 | { |
| 2741 | uint64_t rval; |
| 2742 | RISCVException ret; |
| 2743 | |
| 2744 | ret = rmw_mip64(env, csrno, &rval, |
| 2745 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 2746 | if (ret_val) { |
| 2747 | *ret_val = rval >> 32; |
| 2748 | } |
| 2749 | |
| 2750 | return ret; |
| 2751 | } |
| 2752 | |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 2753 | /* |
| 2754 | * The function is written for two use-cases: |
| 2755 | * 1- To access mvip csr as is for m-mode access. |
| 2756 | * 2- To access sip as a combination of mip and mvip for s-mode. |
| 2757 | * |
| 2758 | * Both report bits 1, 5, 9 and 13:63 but with the exception of |
| 2759 | * STIP being read-only zero in case of mvip when sstc extension |
| 2760 | * is present. |
| 2761 | * Also, sip needs to be read-only zero when both mideleg[i] and |
| 2762 | * mvien[i] are zero but mvip needs to be an alias of mip. |
| 2763 | */ |
| 2764 | static RISCVException rmw_mvip64(CPURISCVState *env, int csrno, |
| 2765 | uint64_t *ret_val, |
| 2766 | uint64_t new_val, uint64_t wr_mask) |
| 2767 | { |
| 2768 | RISCVCPU *cpu = env_archcpu(env); |
| 2769 | target_ulong ret_mip = 0; |
| 2770 | RISCVException ret; |
| 2771 | uint64_t old_mvip; |
| 2772 | |
| 2773 | /* |
| 2774 | * mideleg[i] mvien[i] |
| 2775 | * 0 0 No delegation. mvip[i] is alias of mip[i]. |
| 2776 | * 0 1 mvip[i] becomes source of interrupt, mip bypassed. |
| 2777 | * 1 X mip[i] is source of interrupt and mvip[i] aliases |
| 2778 | * mip[i]. |
| 2779 | * |
| 2780 | * So alias condition would be for bits: |
| 2781 | * ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (mideleg | ~mvien)) | |
| 2782 | * (!sstc & MIP_STIP) |
| 2783 | * |
| 2784 | * Non-alias condition will be for bits: |
| 2785 | * (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (~mideleg & mvien) |
| 2786 | * |
| 2787 | * alias_mask denotes the bits that come from mip nalias_mask denotes bits |
| 2788 | * that come from hvip. |
| 2789 | */ |
| 2790 | uint64_t alias_mask = ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & |
| 2791 | (env->mideleg | ~env->mvien)) | MIP_STIP; |
| 2792 | uint64_t nalias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & |
| 2793 | (~env->mideleg & env->mvien); |
| 2794 | uint64_t wr_mask_mvip; |
| 2795 | uint64_t wr_mask_mip; |
| 2796 | |
| 2797 | /* |
| 2798 | * mideleg[i] mvien[i] |
| 2799 | * 0 0 sip[i] read-only zero. |
| 2800 | * 0 1 sip[i] alias of mvip[i]. |
| 2801 | * 1 X sip[i] alias of mip[i]. |
| 2802 | * |
| 2803 | * Both alias and non-alias mask remain same for sip except for bits |
| 2804 | * which are zero in both mideleg and mvien. |
| 2805 | */ |
| 2806 | if (csrno == CSR_SIP) { |
| 2807 | /* Remove bits that are zero in both mideleg and mvien. */ |
| 2808 | alias_mask &= (env->mideleg | env->mvien); |
| 2809 | nalias_mask &= (env->mideleg | env->mvien); |
| 2810 | } |
| 2811 | |
| 2812 | /* |
| 2813 | * If sstc is present, mvip.STIP is not an alias of mip.STIP so clear |
| 2814 | * that our in mip returned value. |
| 2815 | */ |
| 2816 | if (cpu->cfg.ext_sstc && (env->priv == PRV_M) && |
| 2817 | get_field(env->menvcfg, MENVCFG_STCE)) { |
| 2818 | alias_mask &= ~MIP_STIP; |
| 2819 | } |
| 2820 | |
| 2821 | wr_mask_mip = wr_mask & alias_mask & mvip_writable_mask; |
| 2822 | wr_mask_mvip = wr_mask & nalias_mask & mvip_writable_mask; |
| 2823 | |
| 2824 | /* |
| 2825 | * For bits set in alias_mask, mvip needs to be alias of mip, so forward |
| 2826 | * this to rmw_mip. |
| 2827 | */ |
| 2828 | ret = rmw_mip(env, CSR_MIP, &ret_mip, new_val, wr_mask_mip); |
| 2829 | if (ret != RISCV_EXCP_NONE) { |
| 2830 | return ret; |
| 2831 | } |
| 2832 | |
| 2833 | old_mvip = env->mvip; |
| 2834 | |
| 2835 | /* |
| 2836 | * Write to mvip. Update only non-alias bits. Alias bits were updated |
| 2837 | * in mip in rmw_mip above. |
| 2838 | */ |
| 2839 | if (wr_mask_mvip) { |
| 2840 | env->mvip = (env->mvip & ~wr_mask_mvip) | (new_val & wr_mask_mvip); |
| 2841 | |
| 2842 | /* |
| 2843 | * Given mvip is separate source from mip, we need to trigger interrupt |
| 2844 | * from here separately. Normally this happen from riscv_cpu_update_mip. |
| 2845 | */ |
| 2846 | riscv_cpu_interrupt(env); |
| 2847 | } |
| 2848 | |
| 2849 | if (ret_val) { |
| 2850 | ret_mip &= alias_mask; |
| 2851 | old_mvip &= nalias_mask; |
| 2852 | |
| 2853 | *ret_val = old_mvip | ret_mip; |
| 2854 | } |
| 2855 | |
| 2856 | return RISCV_EXCP_NONE; |
| 2857 | } |
| 2858 | |
| 2859 | static RISCVException rmw_mvip(CPURISCVState *env, int csrno, |
| 2860 | target_ulong *ret_val, |
| 2861 | target_ulong new_val, target_ulong wr_mask) |
| 2862 | { |
| 2863 | uint64_t rval; |
| 2864 | RISCVException ret; |
| 2865 | |
| 2866 | ret = rmw_mvip64(env, csrno, &rval, new_val, wr_mask); |
| 2867 | if (ret_val) { |
| 2868 | *ret_val = rval; |
| 2869 | } |
| 2870 | |
| 2871 | return ret; |
| 2872 | } |
| 2873 | |
| 2874 | static RISCVException rmw_mviph(CPURISCVState *env, int csrno, |
| 2875 | target_ulong *ret_val, |
| 2876 | target_ulong new_val, target_ulong wr_mask) |
| 2877 | { |
| 2878 | uint64_t rval; |
| 2879 | RISCVException ret; |
| 2880 | |
| 2881 | ret = rmw_mvip64(env, csrno, &rval, |
| 2882 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 2883 | if (ret_val) { |
| 2884 | *ret_val = rval >> 32; |
| 2885 | } |
| 2886 | |
| 2887 | return ret; |
| 2888 | } |
| 2889 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2890 | /* Supervisor Trap Setup */ |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 2891 | static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, |
| 2892 | Int128 *val) |
| 2893 | { |
| 2894 | uint64_t mask = sstatus_v1_10_mask; |
| 2895 | uint64_t sstatus = env->mstatus & mask; |
LIU Zhiwei | f297245 | 2022-01-20 20:20:50 +0800 | [diff] [blame] | 2896 | if (env->xl != MXL_RV32 || env->debugger) { |
LIU Zhiwei | f310df5 | 2022-01-20 20:20:49 +0800 | [diff] [blame] | 2897 | mask |= SSTATUS64_UXL; |
| 2898 | } |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 2899 | |
| 2900 | *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); |
| 2901 | return RISCV_EXCP_NONE; |
| 2902 | } |
| 2903 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2904 | static RISCVException read_sstatus(CPURISCVState *env, int csrno, |
| 2905 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2906 | { |
Alistair Francis | 1a9540d | 2020-05-05 13:04:50 -0700 | [diff] [blame] | 2907 | target_ulong mask = (sstatus_v1_10_mask); |
LIU Zhiwei | f297245 | 2022-01-20 20:20:50 +0800 | [diff] [blame] | 2908 | if (env->xl != MXL_RV32 || env->debugger) { |
LIU Zhiwei | f310df5 | 2022-01-20 20:20:49 +0800 | [diff] [blame] | 2909 | mask |= SSTATUS64_UXL; |
| 2910 | } |
Richard Henderson | b550f89 | 2021-10-19 20:17:09 -0700 | [diff] [blame] | 2911 | /* TODO: Use SXL not MXL. */ |
| 2912 | *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2913 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2914 | } |
| 2915 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 2916 | static RISCVException write_sstatus(CPURISCVState *env, int csrno, |
| 2917 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2918 | { |
Alistair Francis | 1a9540d | 2020-05-05 13:04:50 -0700 | [diff] [blame] | 2919 | target_ulong mask = (sstatus_v1_10_mask); |
LIU Zhiwei | f310df5 | 2022-01-20 20:20:49 +0800 | [diff] [blame] | 2920 | |
LIU Zhiwei | f297245 | 2022-01-20 20:20:50 +0800 | [diff] [blame] | 2921 | if (env->xl != MXL_RV32 || env->debugger) { |
LIU Zhiwei | f310df5 | 2022-01-20 20:20:49 +0800 | [diff] [blame] | 2922 | if ((val & SSTATUS64_UXL) != 0) { |
| 2923 | mask |= SSTATUS64_UXL; |
| 2924 | } |
| 2925 | } |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2926 | target_ulong newval = (env->mstatus & ~mask) | (val & mask); |
| 2927 | return write_mstatus(env, CSR_MSTATUS, newval); |
| 2928 | } |
| 2929 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 2930 | static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, |
| 2931 | uint64_t *ret_val, |
| 2932 | uint64_t new_val, uint64_t wr_mask) |
Georg Kotheimer | 9d5451e | 2021-03-11 10:47:38 +0100 | [diff] [blame] | 2933 | { |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 2934 | uint64_t alias_mask = (LOCAL_INTERRUPTS | VS_MODE_INTERRUPTS) & |
| 2935 | env->hideleg; |
| 2936 | uint64_t nalias_mask = LOCAL_INTERRUPTS & (~env->hideleg & env->hvien); |
| 2937 | uint64_t rval, rval_vs, vsbits; |
| 2938 | uint64_t wr_mask_vsie; |
| 2939 | uint64_t wr_mask_mie; |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 2940 | RISCVException ret; |
Georg Kotheimer | 9d5451e | 2021-03-11 10:47:38 +0100 | [diff] [blame] | 2941 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 2942 | /* Bring VS-level bits to correct position */ |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 2943 | vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); |
| 2944 | new_val &= ~(VS_MODE_INTERRUPTS >> 1); |
| 2945 | new_val |= vsbits << 1; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 2946 | |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 2947 | vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); |
| 2948 | wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); |
| 2949 | wr_mask |= vsbits << 1; |
| 2950 | |
| 2951 | wr_mask_mie = wr_mask & alias_mask; |
| 2952 | wr_mask_vsie = wr_mask & nalias_mask; |
| 2953 | |
| 2954 | ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask_mie); |
| 2955 | |
| 2956 | rval_vs = env->vsie & nalias_mask; |
| 2957 | env->vsie = (env->vsie & ~wr_mask_vsie) | (new_val & wr_mask_vsie); |
| 2958 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 2959 | if (ret_val) { |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 2960 | rval &= alias_mask; |
| 2961 | vsbits = rval & VS_MODE_INTERRUPTS; |
| 2962 | rval &= ~VS_MODE_INTERRUPTS; |
| 2963 | *ret_val = rval | (vsbits >> 1) | rval_vs; |
Alistair Francis | d0e53ce | 2020-01-31 17:02:17 -0800 | [diff] [blame] | 2964 | } |
| 2965 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 2966 | return ret; |
| 2967 | } |
| 2968 | |
| 2969 | static RISCVException rmw_vsie(CPURISCVState *env, int csrno, |
| 2970 | target_ulong *ret_val, |
| 2971 | target_ulong new_val, target_ulong wr_mask) |
| 2972 | { |
| 2973 | uint64_t rval; |
| 2974 | RISCVException ret; |
| 2975 | |
| 2976 | ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask); |
| 2977 | if (ret_val) { |
| 2978 | *ret_val = rval; |
| 2979 | } |
| 2980 | |
| 2981 | return ret; |
| 2982 | } |
| 2983 | |
| 2984 | static RISCVException rmw_vsieh(CPURISCVState *env, int csrno, |
| 2985 | target_ulong *ret_val, |
| 2986 | target_ulong new_val, target_ulong wr_mask) |
| 2987 | { |
| 2988 | uint64_t rval; |
| 2989 | RISCVException ret; |
| 2990 | |
| 2991 | ret = rmw_vsie64(env, csrno, &rval, |
| 2992 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 2993 | if (ret_val) { |
| 2994 | *ret_val = rval >> 32; |
| 2995 | } |
| 2996 | |
| 2997 | return ret; |
| 2998 | } |
| 2999 | |
| 3000 | static RISCVException rmw_sie64(CPURISCVState *env, int csrno, |
| 3001 | uint64_t *ret_val, |
| 3002 | uint64_t new_val, uint64_t wr_mask) |
| 3003 | { |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 3004 | uint64_t nalias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & |
| 3005 | (~env->mideleg & env->mvien); |
| 3006 | uint64_t alias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & env->mideleg; |
| 3007 | uint64_t sie_mask = wr_mask & nalias_mask; |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3008 | RISCVException ret; |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3009 | |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 3010 | /* |
| 3011 | * mideleg[i] mvien[i] |
| 3012 | * 0 0 sie[i] read-only zero. |
| 3013 | * 0 1 sie[i] is a separate writable bit. |
| 3014 | * 1 X sie[i] alias of mie[i]. |
| 3015 | * |
| 3016 | * Both alias and non-alias mask remain same for sip except for bits |
| 3017 | * which are zero in both mideleg and mvien. |
| 3018 | */ |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 3019 | if (env->virt_enabled) { |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3020 | if (env->hvictl & HVICTL_VTI) { |
| 3021 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 3022 | } |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3023 | ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 3024 | if (ret_val) { |
| 3025 | *ret_val &= alias_mask; |
| 3026 | } |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3027 | } else { |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 3028 | ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & alias_mask); |
| 3029 | if (ret_val) { |
| 3030 | *ret_val &= alias_mask; |
| 3031 | *ret_val |= env->sie & nalias_mask; |
| 3032 | } |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3033 | |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 3034 | env->sie = (env->sie & ~sie_mask) | (new_val & sie_mask); |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3035 | } |
| 3036 | |
| 3037 | return ret; |
| 3038 | } |
| 3039 | |
| 3040 | static RISCVException rmw_sie(CPURISCVState *env, int csrno, |
| 3041 | target_ulong *ret_val, |
| 3042 | target_ulong new_val, target_ulong wr_mask) |
| 3043 | { |
| 3044 | uint64_t rval; |
| 3045 | RISCVException ret; |
| 3046 | |
| 3047 | ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask); |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3048 | if (ret == RISCV_EXCP_NONE && ret_val) { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3049 | *ret_val = rval; |
| 3050 | } |
| 3051 | |
| 3052 | return ret; |
| 3053 | } |
| 3054 | |
| 3055 | static RISCVException rmw_sieh(CPURISCVState *env, int csrno, |
| 3056 | target_ulong *ret_val, |
| 3057 | target_ulong new_val, target_ulong wr_mask) |
| 3058 | { |
| 3059 | uint64_t rval; |
| 3060 | RISCVException ret; |
| 3061 | |
| 3062 | ret = rmw_sie64(env, csrno, &rval, |
| 3063 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 3064 | if (ret_val) { |
| 3065 | *ret_val = rval >> 32; |
| 3066 | } |
| 3067 | |
| 3068 | return ret; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3069 | } |
| 3070 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3071 | static RISCVException read_stvec(CPURISCVState *env, int csrno, |
| 3072 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3073 | { |
| 3074 | *val = env->stvec; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3075 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3076 | } |
| 3077 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3078 | static RISCVException write_stvec(CPURISCVState *env, int csrno, |
| 3079 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3080 | { |
| 3081 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ |
Michael Clark | acbbb94 | 2019-03-16 01:21:03 +0000 | [diff] [blame] | 3082 | if ((val & 3) < 2) { |
| 3083 | env->stvec = val; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3084 | } else { |
Michael Clark | acbbb94 | 2019-03-16 01:21:03 +0000 | [diff] [blame] | 3085 | qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3086 | } |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3087 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3088 | } |
| 3089 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3090 | static RISCVException read_scounteren(CPURISCVState *env, int csrno, |
| 3091 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3092 | { |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3093 | *val = env->scounteren; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3094 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3095 | } |
| 3096 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3097 | static RISCVException write_scounteren(CPURISCVState *env, int csrno, |
| 3098 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3099 | { |
Atish Patra | 8cff74c | 2024-07-11 15:31:12 -0700 | [diff] [blame] | 3100 | RISCVCPU *cpu = env_archcpu(env); |
| 3101 | |
| 3102 | /* WARL register - disable unavailable counters */ |
| 3103 | env->scounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM | |
| 3104 | COUNTEREN_IR); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3105 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3106 | } |
| 3107 | |
| 3108 | /* Supervisor Trap Handling */ |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 3109 | static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno, |
| 3110 | Int128 *val) |
| 3111 | { |
| 3112 | *val = int128_make128(env->sscratch, env->sscratchh); |
| 3113 | return RISCV_EXCP_NONE; |
| 3114 | } |
| 3115 | |
| 3116 | static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno, |
| 3117 | Int128 val) |
| 3118 | { |
| 3119 | env->sscratch = int128_getlo(val); |
| 3120 | env->sscratchh = int128_gethi(val); |
| 3121 | return RISCV_EXCP_NONE; |
| 3122 | } |
| 3123 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3124 | static RISCVException read_sscratch(CPURISCVState *env, int csrno, |
| 3125 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3126 | { |
| 3127 | *val = env->sscratch; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3128 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3129 | } |
| 3130 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3131 | static RISCVException write_sscratch(CPURISCVState *env, int csrno, |
| 3132 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3133 | { |
| 3134 | env->sscratch = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3135 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3136 | } |
| 3137 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3138 | static RISCVException read_sepc(CPURISCVState *env, int csrno, |
| 3139 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3140 | { |
| 3141 | *val = env->sepc; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3142 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3143 | } |
| 3144 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3145 | static RISCVException write_sepc(CPURISCVState *env, int csrno, |
| 3146 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3147 | { |
| 3148 | env->sepc = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3149 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3150 | } |
| 3151 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3152 | static RISCVException read_scause(CPURISCVState *env, int csrno, |
| 3153 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3154 | { |
| 3155 | *val = env->scause; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3156 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3157 | } |
| 3158 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3159 | static RISCVException write_scause(CPURISCVState *env, int csrno, |
| 3160 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3161 | { |
| 3162 | env->scause = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3163 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3164 | } |
| 3165 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3166 | static RISCVException read_stval(CPURISCVState *env, int csrno, |
| 3167 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3168 | { |
Atish Patra | ac12b60 | 2021-03-19 12:45:29 -0700 | [diff] [blame] | 3169 | *val = env->stval; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3170 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3171 | } |
| 3172 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3173 | static RISCVException write_stval(CPURISCVState *env, int csrno, |
| 3174 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3175 | { |
Atish Patra | ac12b60 | 2021-03-19 12:45:29 -0700 | [diff] [blame] | 3176 | env->stval = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3177 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3178 | } |
| 3179 | |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 3180 | static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, |
| 3181 | uint64_t *ret_val, |
| 3182 | uint64_t new_val, uint64_t wr_mask); |
| 3183 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3184 | static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, |
| 3185 | uint64_t *ret_val, |
| 3186 | uint64_t new_val, uint64_t wr_mask) |
Georg Kotheimer | 9d5451e | 2021-03-11 10:47:38 +0100 | [diff] [blame] | 3187 | { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3188 | RISCVException ret; |
Andrew Bresticker | 06d85c2 | 2022-12-15 17:45:40 -0500 | [diff] [blame] | 3189 | uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 3190 | uint64_t vsbits; |
| 3191 | |
| 3192 | /* Add virtualized bits into vsip mask. */ |
| 3193 | mask |= env->hvien & ~env->hideleg; |
Richard Henderson | 3397952 | 2021-08-23 12:55:21 -0700 | [diff] [blame] | 3194 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3195 | /* Bring VS-level bits to correct position */ |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 3196 | vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); |
| 3197 | new_val &= ~(VS_MODE_INTERRUPTS >> 1); |
| 3198 | new_val |= vsbits << 1; |
| 3199 | vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); |
| 3200 | wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); |
| 3201 | wr_mask |= vsbits << 1; |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3202 | |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 3203 | ret = rmw_hvip64(env, csrno, &rval, new_val, |
| 3204 | wr_mask & mask & vsip_writable_mask); |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3205 | if (ret_val) { |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 3206 | rval &= mask; |
| 3207 | vsbits = rval & VS_MODE_INTERRUPTS; |
| 3208 | rval &= ~VS_MODE_INTERRUPTS; |
| 3209 | *ret_val = rval | (vsbits >> 1); |
Richard Henderson | 3397952 | 2021-08-23 12:55:21 -0700 | [diff] [blame] | 3210 | } |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3211 | |
| 3212 | return ret; |
| 3213 | } |
| 3214 | |
| 3215 | static RISCVException rmw_vsip(CPURISCVState *env, int csrno, |
| 3216 | target_ulong *ret_val, |
| 3217 | target_ulong new_val, target_ulong wr_mask) |
| 3218 | { |
| 3219 | uint64_t rval; |
| 3220 | RISCVException ret; |
| 3221 | |
| 3222 | ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask); |
| 3223 | if (ret_val) { |
| 3224 | *ret_val = rval; |
| 3225 | } |
| 3226 | |
| 3227 | return ret; |
| 3228 | } |
| 3229 | |
| 3230 | static RISCVException rmw_vsiph(CPURISCVState *env, int csrno, |
| 3231 | target_ulong *ret_val, |
| 3232 | target_ulong new_val, target_ulong wr_mask) |
| 3233 | { |
| 3234 | uint64_t rval; |
| 3235 | RISCVException ret; |
| 3236 | |
| 3237 | ret = rmw_vsip64(env, csrno, &rval, |
| 3238 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 3239 | if (ret_val) { |
| 3240 | *ret_val = rval >> 32; |
| 3241 | } |
| 3242 | |
| 3243 | return ret; |
| 3244 | } |
| 3245 | |
| 3246 | static RISCVException rmw_sip64(CPURISCVState *env, int csrno, |
| 3247 | uint64_t *ret_val, |
| 3248 | uint64_t new_val, uint64_t wr_mask) |
| 3249 | { |
| 3250 | RISCVException ret; |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 3251 | uint64_t mask = (env->mideleg | env->mvien) & sip_writable_mask; |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3252 | |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 3253 | if (env->virt_enabled) { |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3254 | if (env->hvictl & HVICTL_VTI) { |
| 3255 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 3256 | } |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3257 | ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); |
| 3258 | } else { |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 3259 | ret = rmw_mvip64(env, csrno, ret_val, new_val, wr_mask & mask); |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3260 | } |
| 3261 | |
| 3262 | if (ret_val) { |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 3263 | *ret_val &= (env->mideleg | env->mvien) & |
| 3264 | (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3265 | } |
| 3266 | |
Georg Kotheimer | 9d5451e | 2021-03-11 10:47:38 +0100 | [diff] [blame] | 3267 | return ret; |
| 3268 | } |
| 3269 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3270 | static RISCVException rmw_sip(CPURISCVState *env, int csrno, |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3271 | target_ulong *ret_val, |
| 3272 | target_ulong new_val, target_ulong wr_mask) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3273 | { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3274 | uint64_t rval; |
| 3275 | RISCVException ret; |
Alistair Francis | a2e9f57 | 2020-01-31 17:02:20 -0800 | [diff] [blame] | 3276 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3277 | ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask); |
| 3278 | if (ret_val) { |
| 3279 | *ret_val = rval; |
Alistair Francis | a2e9f57 | 2020-01-31 17:02:20 -0800 | [diff] [blame] | 3280 | } |
| 3281 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3282 | return ret; |
| 3283 | } |
| 3284 | |
| 3285 | static RISCVException rmw_siph(CPURISCVState *env, int csrno, |
| 3286 | target_ulong *ret_val, |
| 3287 | target_ulong new_val, target_ulong wr_mask) |
| 3288 | { |
| 3289 | uint64_t rval; |
| 3290 | RISCVException ret; |
| 3291 | |
| 3292 | ret = rmw_sip64(env, csrno, &rval, |
| 3293 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 3294 | if (ret_val) { |
| 3295 | *ret_val = rval >> 32; |
Richard Henderson | 3397952 | 2021-08-23 12:55:21 -0700 | [diff] [blame] | 3296 | } |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3297 | |
Jonathan Behrens | 087b051 | 2019-05-07 18:36:46 -0400 | [diff] [blame] | 3298 | return ret; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3299 | } |
| 3300 | |
| 3301 | /* Supervisor Protection and Translation */ |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3302 | static RISCVException read_satp(CPURISCVState *env, int csrno, |
| 3303 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3304 | { |
Daniel Henrique Barboza | dcf654a | 2023-02-22 15:52:04 -0300 | [diff] [blame] | 3305 | if (!riscv_cpu_cfg(env)->mmu) { |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3306 | *val = 0; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3307 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3308 | } |
Yi Chen | d6db7c9 | 2023-04-06 18:15:59 +0800 | [diff] [blame] | 3309 | *val = env->satp; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3310 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3311 | } |
| 3312 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3313 | static RISCVException write_satp(CPURISCVState *env, int csrno, |
| 3314 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3315 | { |
Daniel Henrique Barboza | dcf654a | 2023-02-22 15:52:04 -0300 | [diff] [blame] | 3316 | if (!riscv_cpu_cfg(env)->mmu) { |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3317 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3318 | } |
Alistair Francis | 419ddf0 | 2021-04-24 13:33:31 +1000 | [diff] [blame] | 3319 | |
Irina Ryapolova | 1349f96 | 2024-01-09 17:59:22 +0300 | [diff] [blame] | 3320 | env->satp = legalize_xatp(env, env->satp, val); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3321 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 3322 | } |
| 3323 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3324 | static RISCVException read_vstopi(CPURISCVState *env, int csrno, |
| 3325 | target_ulong *val) |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 3326 | { |
| 3327 | int irq, ret; |
| 3328 | target_ulong topei; |
| 3329 | uint64_t vseip, vsgein; |
| 3330 | uint32_t iid, iprio, hviid, hviprio, gein; |
| 3331 | uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS]; |
| 3332 | |
| 3333 | gein = get_field(env->hstatus, HSTATUS_VGEIN); |
| 3334 | hviid = get_field(env->hvictl, HVICTL_IID); |
| 3335 | hviprio = get_field(env->hvictl, HVICTL_IPRIO); |
| 3336 | |
| 3337 | if (gein) { |
| 3338 | vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; |
| 3339 | vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP; |
| 3340 | if (gein <= env->geilen && vseip) { |
| 3341 | siid[scount] = IRQ_S_EXT; |
| 3342 | siprio[scount] = IPRIO_MMAXIPRIO + 1; |
| 3343 | if (env->aia_ireg_rmw_fn[PRV_S]) { |
| 3344 | /* |
| 3345 | * Call machine specific IMSIC register emulation for |
| 3346 | * reading TOPEI. |
| 3347 | */ |
| 3348 | ret = env->aia_ireg_rmw_fn[PRV_S]( |
| 3349 | env->aia_ireg_rmw_fn_arg[PRV_S], |
| 3350 | AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein, |
| 3351 | riscv_cpu_mxl_bits(env)), |
| 3352 | &topei, 0, 0); |
| 3353 | if (!ret && topei) { |
| 3354 | siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK; |
| 3355 | } |
| 3356 | } |
| 3357 | scount++; |
| 3358 | } |
| 3359 | } else { |
| 3360 | if (hviid == IRQ_S_EXT && hviprio) { |
| 3361 | siid[scount] = IRQ_S_EXT; |
| 3362 | siprio[scount] = hviprio; |
| 3363 | scount++; |
| 3364 | } |
| 3365 | } |
| 3366 | |
| 3367 | if (env->hvictl & HVICTL_VTI) { |
| 3368 | if (hviid != IRQ_S_EXT) { |
| 3369 | siid[scount] = hviid; |
| 3370 | siprio[scount] = hviprio; |
| 3371 | scount++; |
| 3372 | } |
| 3373 | } else { |
| 3374 | irq = riscv_cpu_vsirq_pending(env); |
| 3375 | if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) { |
| 3376 | siid[scount] = irq; |
| 3377 | siprio[scount] = env->hviprio[irq]; |
| 3378 | scount++; |
| 3379 | } |
| 3380 | } |
| 3381 | |
| 3382 | iid = 0; |
| 3383 | iprio = UINT_MAX; |
| 3384 | for (s = 0; s < scount; s++) { |
| 3385 | if (siprio[s] < iprio) { |
| 3386 | iid = siid[s]; |
| 3387 | iprio = siprio[s]; |
| 3388 | } |
| 3389 | } |
| 3390 | |
| 3391 | if (iid) { |
| 3392 | if (env->hvictl & HVICTL_IPRIOM) { |
| 3393 | if (iprio > IPRIO_MMAXIPRIO) { |
| 3394 | iprio = IPRIO_MMAXIPRIO; |
| 3395 | } |
| 3396 | if (!iprio) { |
| 3397 | if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { |
| 3398 | iprio = IPRIO_MMAXIPRIO; |
| 3399 | } |
| 3400 | } |
| 3401 | } else { |
| 3402 | iprio = 1; |
| 3403 | } |
| 3404 | } else { |
| 3405 | iprio = 0; |
| 3406 | } |
| 3407 | |
| 3408 | *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; |
| 3409 | *val |= iprio; |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 3410 | |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 3411 | return RISCV_EXCP_NONE; |
| 3412 | } |
| 3413 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3414 | static RISCVException read_stopi(CPURISCVState *env, int csrno, |
| 3415 | target_ulong *val) |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 3416 | { |
| 3417 | int irq; |
| 3418 | uint8_t iprio; |
| 3419 | |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 3420 | if (env->virt_enabled) { |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 3421 | return read_vstopi(env, CSR_VSTOPI, val); |
| 3422 | } |
| 3423 | |
| 3424 | irq = riscv_cpu_sirq_pending(env); |
| 3425 | if (irq <= 0 || irq > 63) { |
| 3426 | *val = 0; |
| 3427 | } else { |
| 3428 | iprio = env->siprio[irq]; |
| 3429 | if (!iprio) { |
| 3430 | if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { |
| 3431 | iprio = IPRIO_MMAXIPRIO; |
| 3432 | } |
| 3433 | } |
| 3434 | *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; |
| 3435 | *val |= iprio; |
| 3436 | } |
| 3437 | |
| 3438 | return RISCV_EXCP_NONE; |
| 3439 | } |
| 3440 | |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3441 | /* Hypervisor Extensions */ |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3442 | static RISCVException read_hstatus(CPURISCVState *env, int csrno, |
| 3443 | target_ulong *val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3444 | { |
| 3445 | *val = env->hstatus; |
Richard Henderson | db23e5d | 2021-10-19 20:16:58 -0700 | [diff] [blame] | 3446 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 3447 | /* We only support 64-bit VSXL */ |
| 3448 | *val = set_field(*val, HSTATUS_VSXL, 2); |
| 3449 | } |
Alistair Francis | 30f663b | 2020-08-12 12:13:41 -0700 | [diff] [blame] | 3450 | /* We only support little endian */ |
| 3451 | *val = set_field(*val, HSTATUS_VSBE, 0); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3452 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3453 | } |
| 3454 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3455 | static RISCVException write_hstatus(CPURISCVState *env, int csrno, |
| 3456 | target_ulong val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3457 | { |
| 3458 | env->hstatus = val; |
Richard Henderson | db23e5d | 2021-10-19 20:16:58 -0700 | [diff] [blame] | 3459 | if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { |
Weiwei Li | 246f879 | 2023-04-05 16:58:13 +0800 | [diff] [blame] | 3460 | qemu_log_mask(LOG_UNIMP, |
| 3461 | "QEMU does not support mixed HSXLEN options."); |
Alistair Francis | f8dc878 | 2020-08-12 12:13:38 -0700 | [diff] [blame] | 3462 | } |
Alistair Francis | 30f663b | 2020-08-12 12:13:41 -0700 | [diff] [blame] | 3463 | if (get_field(val, HSTATUS_VSBE) != 0) { |
| 3464 | qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); |
| 3465 | } |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3466 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3467 | } |
| 3468 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3469 | static RISCVException read_hedeleg(CPURISCVState *env, int csrno, |
| 3470 | target_ulong *val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3471 | { |
| 3472 | *val = env->hedeleg; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3473 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3474 | } |
| 3475 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3476 | static RISCVException write_hedeleg(CPURISCVState *env, int csrno, |
| 3477 | target_ulong val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3478 | { |
Jose Martins | bc083a5 | 2021-05-22 16:59:02 +0100 | [diff] [blame] | 3479 | env->hedeleg = val & vs_delegable_excps; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3480 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3481 | } |
| 3482 | |
Fea.Wang | 2779698 | 2024-06-06 21:54:52 +0800 | [diff] [blame] | 3483 | static RISCVException read_hedelegh(CPURISCVState *env, int csrno, |
| 3484 | target_ulong *val) |
| 3485 | { |
| 3486 | RISCVException ret; |
| 3487 | ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); |
| 3488 | if (ret != RISCV_EXCP_NONE) { |
| 3489 | return ret; |
| 3490 | } |
| 3491 | |
| 3492 | /* Reserved, now read zero */ |
| 3493 | *val = 0; |
| 3494 | return RISCV_EXCP_NONE; |
| 3495 | } |
| 3496 | |
| 3497 | static RISCVException write_hedelegh(CPURISCVState *env, int csrno, |
| 3498 | target_ulong val) |
| 3499 | { |
| 3500 | RISCVException ret; |
| 3501 | ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); |
| 3502 | if (ret != RISCV_EXCP_NONE) { |
| 3503 | return ret; |
| 3504 | } |
| 3505 | |
| 3506 | /* Reserved, now write ignore */ |
| 3507 | return RISCV_EXCP_NONE; |
| 3508 | } |
| 3509 | |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 3510 | static RISCVException rmw_hvien64(CPURISCVState *env, int csrno, |
| 3511 | uint64_t *ret_val, |
| 3512 | uint64_t new_val, uint64_t wr_mask) |
| 3513 | { |
| 3514 | uint64_t mask = wr_mask & hvien_writable_mask; |
| 3515 | |
| 3516 | if (ret_val) { |
| 3517 | *ret_val = env->hvien; |
| 3518 | } |
| 3519 | |
| 3520 | env->hvien = (env->hvien & ~mask) | (new_val & mask); |
| 3521 | |
| 3522 | return RISCV_EXCP_NONE; |
| 3523 | } |
| 3524 | |
| 3525 | static RISCVException rmw_hvien(CPURISCVState *env, int csrno, |
| 3526 | target_ulong *ret_val, |
| 3527 | target_ulong new_val, target_ulong wr_mask) |
| 3528 | { |
| 3529 | uint64_t rval; |
| 3530 | RISCVException ret; |
| 3531 | |
| 3532 | ret = rmw_hvien64(env, csrno, &rval, new_val, wr_mask); |
| 3533 | if (ret_val) { |
| 3534 | *ret_val = rval; |
| 3535 | } |
| 3536 | |
| 3537 | return ret; |
| 3538 | } |
| 3539 | |
| 3540 | static RISCVException rmw_hvienh(CPURISCVState *env, int csrno, |
| 3541 | target_ulong *ret_val, |
| 3542 | target_ulong new_val, target_ulong wr_mask) |
| 3543 | { |
| 3544 | uint64_t rval; |
| 3545 | RISCVException ret; |
| 3546 | |
| 3547 | ret = rmw_hvien64(env, csrno, &rval, |
| 3548 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 3549 | if (ret_val) { |
| 3550 | *ret_val = rval >> 32; |
| 3551 | } |
| 3552 | |
| 3553 | return ret; |
| 3554 | } |
| 3555 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3556 | static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, |
| 3557 | uint64_t *ret_val, |
| 3558 | uint64_t new_val, uint64_t wr_mask) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3559 | { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3560 | uint64_t mask = wr_mask & vs_delegable_ints; |
| 3561 | |
| 3562 | if (ret_val) { |
| 3563 | *ret_val = env->hideleg & vs_delegable_ints; |
| 3564 | } |
| 3565 | |
| 3566 | env->hideleg = (env->hideleg & ~mask) | (new_val & mask); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3567 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3568 | } |
| 3569 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3570 | static RISCVException rmw_hideleg(CPURISCVState *env, int csrno, |
| 3571 | target_ulong *ret_val, |
| 3572 | target_ulong new_val, target_ulong wr_mask) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3573 | { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3574 | uint64_t rval; |
| 3575 | RISCVException ret; |
| 3576 | |
| 3577 | ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); |
| 3578 | if (ret_val) { |
| 3579 | *ret_val = rval; |
| 3580 | } |
| 3581 | |
| 3582 | return ret; |
| 3583 | } |
| 3584 | |
| 3585 | static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno, |
| 3586 | target_ulong *ret_val, |
| 3587 | target_ulong new_val, target_ulong wr_mask) |
| 3588 | { |
| 3589 | uint64_t rval; |
| 3590 | RISCVException ret; |
| 3591 | |
| 3592 | ret = rmw_hideleg64(env, csrno, &rval, |
| 3593 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 3594 | if (ret_val) { |
| 3595 | *ret_val = rval >> 32; |
| 3596 | } |
| 3597 | |
| 3598 | return ret; |
| 3599 | } |
| 3600 | |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 3601 | /* |
| 3602 | * The function is written for two use-cases: |
| 3603 | * 1- To access hvip csr as is for HS-mode access. |
| 3604 | * 2- To access vsip as a combination of hvip, and mip for vs-mode. |
| 3605 | * |
| 3606 | * Both report bits 2, 6, 10 and 13:63. |
| 3607 | * vsip needs to be read-only zero when both hideleg[i] and |
| 3608 | * hvien[i] are zero. |
| 3609 | */ |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3610 | static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, |
| 3611 | uint64_t *ret_val, |
| 3612 | uint64_t new_val, uint64_t wr_mask) |
| 3613 | { |
| 3614 | RISCVException ret; |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 3615 | uint64_t old_hvip; |
| 3616 | uint64_t ret_mip; |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3617 | |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 3618 | /* |
| 3619 | * For bits 10, 6 and 2, vsip[i] is an alias of hip[i]. These bits are |
| 3620 | * present in hip, hvip and mip. Where mip[i] is alias of hip[i] and hvip[i] |
| 3621 | * is OR'ed in hip[i] to inject virtual interrupts from hypervisor. These |
| 3622 | * bits are actually being maintained in mip so we read them from there. |
| 3623 | * This way we have a single source of truth and allows for easier |
| 3624 | * implementation. |
| 3625 | * |
| 3626 | * For bits 13:63 we have: |
| 3627 | * |
| 3628 | * hideleg[i] hvien[i] |
| 3629 | * 0 0 No delegation. vsip[i] readonly zero. |
| 3630 | * 0 1 vsip[i] is alias of hvip[i], sip bypassed. |
| 3631 | * 1 X vsip[i] is alias of sip[i], hvip bypassed. |
| 3632 | * |
| 3633 | * alias_mask denotes the bits that come from sip (mip here given we |
| 3634 | * maintain all bits there). nalias_mask denotes bits that come from |
| 3635 | * hvip. |
| 3636 | */ |
| 3637 | uint64_t alias_mask = (env->hideleg | ~env->hvien) | VS_MODE_INTERRUPTS; |
| 3638 | uint64_t nalias_mask = (~env->hideleg & env->hvien); |
| 3639 | uint64_t wr_mask_hvip; |
| 3640 | uint64_t wr_mask_mip; |
| 3641 | |
| 3642 | /* |
| 3643 | * Both alias and non-alias mask remain same for vsip except: |
| 3644 | * 1- For VS* bits if they are zero in hideleg. |
| 3645 | * 2- For 13:63 bits if they are zero in both hideleg and hvien. |
| 3646 | */ |
| 3647 | if (csrno == CSR_VSIP) { |
| 3648 | /* zero-out VS* bits that are not delegated to VS mode. */ |
| 3649 | alias_mask &= (env->hideleg | ~VS_MODE_INTERRUPTS); |
| 3650 | |
| 3651 | /* |
| 3652 | * zero-out 13:63 bits that are zero in both hideleg and hvien. |
| 3653 | * nalias_mask mask can not contain any VS* bits so only second |
| 3654 | * condition applies on it. |
| 3655 | */ |
| 3656 | nalias_mask &= (env->hideleg | env->hvien); |
| 3657 | alias_mask &= (env->hideleg | env->hvien); |
| 3658 | } |
| 3659 | |
| 3660 | wr_mask_hvip = wr_mask & nalias_mask & hvip_writable_mask; |
| 3661 | wr_mask_mip = wr_mask & alias_mask & hvip_writable_mask; |
| 3662 | |
| 3663 | /* Aliased bits, bits 10, 6, 2 need to come from mip. */ |
| 3664 | ret = rmw_mip64(env, csrno, &ret_mip, new_val, wr_mask_mip); |
| 3665 | if (ret != RISCV_EXCP_NONE) { |
| 3666 | return ret; |
| 3667 | } |
| 3668 | |
| 3669 | old_hvip = env->hvip; |
| 3670 | |
| 3671 | if (wr_mask_hvip) { |
| 3672 | env->hvip = (env->hvip & ~wr_mask_hvip) | (new_val & wr_mask_hvip); |
| 3673 | |
| 3674 | /* |
| 3675 | * Given hvip is separate source from mip, we need to trigger interrupt |
| 3676 | * from here separately. Normally this happen from riscv_cpu_update_mip. |
| 3677 | */ |
| 3678 | riscv_cpu_interrupt(env); |
| 3679 | } |
| 3680 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3681 | if (ret_val) { |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 3682 | /* Only take VS* bits from mip. */ |
| 3683 | ret_mip &= alias_mask; |
| 3684 | |
| 3685 | /* Take in non-delegated 13:63 bits from hvip. */ |
| 3686 | old_hvip &= nalias_mask; |
| 3687 | |
| 3688 | *ret_val = ret_mip | old_hvip; |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3689 | } |
| 3690 | |
| 3691 | return ret; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3692 | } |
| 3693 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3694 | static RISCVException rmw_hvip(CPURISCVState *env, int csrno, |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3695 | target_ulong *ret_val, |
| 3696 | target_ulong new_val, target_ulong wr_mask) |
Alistair Francis | 8302809 | 2020-08-12 12:13:44 -0700 | [diff] [blame] | 3697 | { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3698 | uint64_t rval; |
| 3699 | RISCVException ret; |
Alistair Francis | 8302809 | 2020-08-12 12:13:44 -0700 | [diff] [blame] | 3700 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3701 | ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask); |
| 3702 | if (ret_val) { |
| 3703 | *ret_val = rval; |
Richard Henderson | 3397952 | 2021-08-23 12:55:21 -0700 | [diff] [blame] | 3704 | } |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3705 | |
| 3706 | return ret; |
| 3707 | } |
| 3708 | |
| 3709 | static RISCVException rmw_hviph(CPURISCVState *env, int csrno, |
| 3710 | target_ulong *ret_val, |
| 3711 | target_ulong new_val, target_ulong wr_mask) |
| 3712 | { |
| 3713 | uint64_t rval; |
| 3714 | RISCVException ret; |
| 3715 | |
| 3716 | ret = rmw_hvip64(env, csrno, &rval, |
| 3717 | ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); |
| 3718 | if (ret_val) { |
| 3719 | *ret_val = rval >> 32; |
| 3720 | } |
| 3721 | |
Alistair Francis | 8302809 | 2020-08-12 12:13:44 -0700 | [diff] [blame] | 3722 | return ret; |
| 3723 | } |
| 3724 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3725 | static RISCVException rmw_hip(CPURISCVState *env, int csrno, |
| 3726 | target_ulong *ret_value, |
| 3727 | target_ulong new_value, target_ulong write_mask) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3728 | { |
Anup Patel | cd032fe | 2022-02-04 23:16:39 +0530 | [diff] [blame] | 3729 | int ret = rmw_mip(env, csrno, ret_value, new_value, |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3730 | write_mask & hip_writable_mask); |
| 3731 | |
Richard Henderson | 3397952 | 2021-08-23 12:55:21 -0700 | [diff] [blame] | 3732 | if (ret_value) { |
Anup Patel | 881df35 | 2022-02-04 23:16:38 +0530 | [diff] [blame] | 3733 | *ret_value &= HS_MODE_INTERRUPTS; |
Richard Henderson | 3397952 | 2021-08-23 12:55:21 -0700 | [diff] [blame] | 3734 | } |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3735 | return ret; |
| 3736 | } |
| 3737 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3738 | static RISCVException rmw_hie(CPURISCVState *env, int csrno, |
| 3739 | target_ulong *ret_val, |
| 3740 | target_ulong new_val, target_ulong wr_mask) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3741 | { |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3742 | uint64_t rval; |
| 3743 | RISCVException ret; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3744 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 3745 | ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS); |
| 3746 | if (ret_val) { |
| 3747 | *ret_val = rval & HS_MODE_INTERRUPTS; |
| 3748 | } |
| 3749 | |
| 3750 | return ret; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3751 | } |
| 3752 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3753 | static RISCVException read_hcounteren(CPURISCVState *env, int csrno, |
| 3754 | target_ulong *val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3755 | { |
| 3756 | *val = env->hcounteren; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3757 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3758 | } |
| 3759 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3760 | static RISCVException write_hcounteren(CPURISCVState *env, int csrno, |
| 3761 | target_ulong val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3762 | { |
Atish Patra | 8cff74c | 2024-07-11 15:31:12 -0700 | [diff] [blame] | 3763 | RISCVCPU *cpu = env_archcpu(env); |
| 3764 | |
| 3765 | /* WARL register - disable unavailable counters */ |
| 3766 | env->hcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM | |
| 3767 | COUNTEREN_IR); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3768 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3769 | } |
| 3770 | |
Anup Patel | cd032fe | 2022-02-04 23:16:39 +0530 | [diff] [blame] | 3771 | static RISCVException read_hgeie(CPURISCVState *env, int csrno, |
| 3772 | target_ulong *val) |
| 3773 | { |
| 3774 | if (val) { |
| 3775 | *val = env->hgeie; |
| 3776 | } |
| 3777 | return RISCV_EXCP_NONE; |
| 3778 | } |
| 3779 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3780 | static RISCVException write_hgeie(CPURISCVState *env, int csrno, |
| 3781 | target_ulong val) |
Alistair Francis | 8302809 | 2020-08-12 12:13:44 -0700 | [diff] [blame] | 3782 | { |
Anup Patel | cd032fe | 2022-02-04 23:16:39 +0530 | [diff] [blame] | 3783 | /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ |
| 3784 | val &= ((((target_ulong)1) << env->geilen) - 1) << 1; |
| 3785 | env->hgeie = val; |
| 3786 | /* Update mip.SGEIP bit */ |
Weiwei Li | bbb9fc2 | 2023-03-09 15:13:28 +0800 | [diff] [blame] | 3787 | riscv_cpu_update_mip(env, MIP_SGEIP, |
Anup Patel | cd032fe | 2022-02-04 23:16:39 +0530 | [diff] [blame] | 3788 | BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3789 | return RISCV_EXCP_NONE; |
Alistair Francis | 8302809 | 2020-08-12 12:13:44 -0700 | [diff] [blame] | 3790 | } |
| 3791 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3792 | static RISCVException read_htval(CPURISCVState *env, int csrno, |
| 3793 | target_ulong *val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3794 | { |
| 3795 | *val = env->htval; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3796 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3797 | } |
| 3798 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3799 | static RISCVException write_htval(CPURISCVState *env, int csrno, |
| 3800 | target_ulong val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3801 | { |
| 3802 | env->htval = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3803 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3804 | } |
| 3805 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3806 | static RISCVException read_htinst(CPURISCVState *env, int csrno, |
| 3807 | target_ulong *val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3808 | { |
| 3809 | *val = env->htinst; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3810 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3811 | } |
| 3812 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3813 | static RISCVException write_htinst(CPURISCVState *env, int csrno, |
| 3814 | target_ulong val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3815 | { |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3816 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3817 | } |
| 3818 | |
Anup Patel | cd032fe | 2022-02-04 23:16:39 +0530 | [diff] [blame] | 3819 | static RISCVException read_hgeip(CPURISCVState *env, int csrno, |
| 3820 | target_ulong *val) |
Alistair Francis | 8302809 | 2020-08-12 12:13:44 -0700 | [diff] [blame] | 3821 | { |
Richard Henderson | 377cbb4 | 2021-08-23 12:55:22 -0700 | [diff] [blame] | 3822 | if (val) { |
Anup Patel | cd032fe | 2022-02-04 23:16:39 +0530 | [diff] [blame] | 3823 | *val = env->hgeip; |
Richard Henderson | 377cbb4 | 2021-08-23 12:55:22 -0700 | [diff] [blame] | 3824 | } |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3825 | return RISCV_EXCP_NONE; |
Alistair Francis | 8302809 | 2020-08-12 12:13:44 -0700 | [diff] [blame] | 3826 | } |
| 3827 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3828 | static RISCVException read_hgatp(CPURISCVState *env, int csrno, |
| 3829 | target_ulong *val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3830 | { |
| 3831 | *val = env->hgatp; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3832 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3833 | } |
| 3834 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3835 | static RISCVException write_hgatp(CPURISCVState *env, int csrno, |
| 3836 | target_ulong val) |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3837 | { |
Irina Ryapolova | 1349f96 | 2024-01-09 17:59:22 +0300 | [diff] [blame] | 3838 | env->hgatp = legalize_xatp(env, env->hgatp, val); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3839 | return RISCV_EXCP_NONE; |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 3840 | } |
| 3841 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3842 | static RISCVException read_htimedelta(CPURISCVState *env, int csrno, |
| 3843 | target_ulong *val) |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3844 | { |
| 3845 | if (!env->rdtime_fn) { |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3846 | return RISCV_EXCP_ILLEGAL_INST; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3847 | } |
| 3848 | |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3849 | *val = env->htimedelta; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3850 | return RISCV_EXCP_NONE; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3851 | } |
| 3852 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3853 | static RISCVException write_htimedelta(CPURISCVState *env, int csrno, |
| 3854 | target_ulong val) |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3855 | { |
| 3856 | if (!env->rdtime_fn) { |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3857 | return RISCV_EXCP_ILLEGAL_INST; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3858 | } |
| 3859 | |
Richard Henderson | db23e5d | 2021-10-19 20:16:58 -0700 | [diff] [blame] | 3860 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
Alistair Francis | 8987cdc4 | 2020-12-16 10:23:02 -0800 | [diff] [blame] | 3861 | env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); |
| 3862 | } else { |
| 3863 | env->htimedelta = val; |
| 3864 | } |
Anup Patel | 2cfb3b6 | 2023-01-20 18:29:47 +0530 | [diff] [blame] | 3865 | |
Weiwei Li | bbb9fc2 | 2023-03-09 15:13:28 +0800 | [diff] [blame] | 3866 | if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { |
| 3867 | riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, |
Anup Patel | 2cfb3b6 | 2023-01-20 18:29:47 +0530 | [diff] [blame] | 3868 | env->htimedelta, MIP_VSTIP); |
| 3869 | } |
| 3870 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3871 | return RISCV_EXCP_NONE; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3872 | } |
| 3873 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3874 | static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, |
| 3875 | target_ulong *val) |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3876 | { |
| 3877 | if (!env->rdtime_fn) { |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3878 | return RISCV_EXCP_ILLEGAL_INST; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3879 | } |
| 3880 | |
| 3881 | *val = env->htimedelta >> 32; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3882 | return RISCV_EXCP_NONE; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3883 | } |
| 3884 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3885 | static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, |
| 3886 | target_ulong val) |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3887 | { |
| 3888 | if (!env->rdtime_fn) { |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3889 | return RISCV_EXCP_ILLEGAL_INST; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3890 | } |
| 3891 | |
| 3892 | env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); |
Anup Patel | 2cfb3b6 | 2023-01-20 18:29:47 +0530 | [diff] [blame] | 3893 | |
Weiwei Li | bbb9fc2 | 2023-03-09 15:13:28 +0800 | [diff] [blame] | 3894 | if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { |
| 3895 | riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, |
Anup Patel | 2cfb3b6 | 2023-01-20 18:29:47 +0530 | [diff] [blame] | 3896 | env->htimedelta, MIP_VSTIP); |
| 3897 | } |
| 3898 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 3899 | return RISCV_EXCP_NONE; |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3900 | } |
Anup Patel | c695724 | 2020-02-02 19:12:16 +0530 | [diff] [blame] | 3901 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3902 | static RISCVException read_hvictl(CPURISCVState *env, int csrno, |
| 3903 | target_ulong *val) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3904 | { |
| 3905 | *val = env->hvictl; |
| 3906 | return RISCV_EXCP_NONE; |
| 3907 | } |
| 3908 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3909 | static RISCVException write_hvictl(CPURISCVState *env, int csrno, |
| 3910 | target_ulong val) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3911 | { |
| 3912 | env->hvictl = val & HVICTL_VALID_MASK; |
| 3913 | return RISCV_EXCP_NONE; |
| 3914 | } |
| 3915 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3916 | static RISCVException read_hvipriox(CPURISCVState *env, int first_index, |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3917 | uint8_t *iprio, target_ulong *val) |
| 3918 | { |
| 3919 | int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); |
| 3920 | |
| 3921 | /* First index has to be a multiple of number of irqs per register */ |
| 3922 | if (first_index % num_irqs) { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 3923 | return (env->virt_enabled) ? |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3924 | RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; |
| 3925 | } |
| 3926 | |
| 3927 | /* Fill-up return value */ |
| 3928 | *val = 0; |
| 3929 | for (i = 0; i < num_irqs; i++) { |
| 3930 | if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { |
| 3931 | continue; |
| 3932 | } |
| 3933 | if (rdzero) { |
| 3934 | continue; |
| 3935 | } |
| 3936 | *val |= ((target_ulong)iprio[irq]) << (i * 8); |
| 3937 | } |
| 3938 | |
| 3939 | return RISCV_EXCP_NONE; |
| 3940 | } |
| 3941 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3942 | static RISCVException write_hvipriox(CPURISCVState *env, int first_index, |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3943 | uint8_t *iprio, target_ulong val) |
| 3944 | { |
| 3945 | int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); |
| 3946 | |
| 3947 | /* First index has to be a multiple of number of irqs per register */ |
| 3948 | if (first_index % num_irqs) { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 3949 | return (env->virt_enabled) ? |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3950 | RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; |
| 3951 | } |
| 3952 | |
Michael Tokarev | 42fe749 | 2023-07-14 14:19:10 +0300 | [diff] [blame] | 3953 | /* Fill-up priority array */ |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3954 | for (i = 0; i < num_irqs; i++) { |
| 3955 | if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { |
| 3956 | continue; |
| 3957 | } |
| 3958 | if (rdzero) { |
| 3959 | iprio[irq] = 0; |
| 3960 | } else { |
| 3961 | iprio[irq] = (val >> (i * 8)) & 0xff; |
| 3962 | } |
| 3963 | } |
| 3964 | |
| 3965 | return RISCV_EXCP_NONE; |
| 3966 | } |
| 3967 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3968 | static RISCVException read_hviprio1(CPURISCVState *env, int csrno, |
| 3969 | target_ulong *val) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3970 | { |
| 3971 | return read_hvipriox(env, 0, env->hviprio, val); |
| 3972 | } |
| 3973 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3974 | static RISCVException write_hviprio1(CPURISCVState *env, int csrno, |
| 3975 | target_ulong val) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3976 | { |
| 3977 | return write_hvipriox(env, 0, env->hviprio, val); |
| 3978 | } |
| 3979 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3980 | static RISCVException read_hviprio1h(CPURISCVState *env, int csrno, |
| 3981 | target_ulong *val) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3982 | { |
| 3983 | return read_hvipriox(env, 4, env->hviprio, val); |
| 3984 | } |
| 3985 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3986 | static RISCVException write_hviprio1h(CPURISCVState *env, int csrno, |
| 3987 | target_ulong val) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3988 | { |
| 3989 | return write_hvipriox(env, 4, env->hviprio, val); |
| 3990 | } |
| 3991 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3992 | static RISCVException read_hviprio2(CPURISCVState *env, int csrno, |
| 3993 | target_ulong *val) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 3994 | { |
| 3995 | return read_hvipriox(env, 8, env->hviprio, val); |
| 3996 | } |
| 3997 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 3998 | static RISCVException write_hviprio2(CPURISCVState *env, int csrno, |
| 3999 | target_ulong val) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 4000 | { |
| 4001 | return write_hvipriox(env, 8, env->hviprio, val); |
| 4002 | } |
| 4003 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 4004 | static RISCVException read_hviprio2h(CPURISCVState *env, int csrno, |
| 4005 | target_ulong *val) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 4006 | { |
| 4007 | return read_hvipriox(env, 12, env->hviprio, val); |
| 4008 | } |
| 4009 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 4010 | static RISCVException write_hviprio2h(CPURISCVState *env, int csrno, |
| 4011 | target_ulong val) |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 4012 | { |
| 4013 | return write_hvipriox(env, 12, env->hviprio, val); |
| 4014 | } |
| 4015 | |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4016 | /* Virtual CSR Registers */ |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4017 | static RISCVException read_vsstatus(CPURISCVState *env, int csrno, |
| 4018 | target_ulong *val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4019 | { |
| 4020 | *val = env->vsstatus; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4021 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4022 | } |
| 4023 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4024 | static RISCVException write_vsstatus(CPURISCVState *env, int csrno, |
| 4025 | target_ulong val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4026 | { |
Yifei Jiang | 284d697 | 2020-10-26 19:55:25 +0800 | [diff] [blame] | 4027 | uint64_t mask = (target_ulong)-1; |
LIU Zhiwei | f310df5 | 2022-01-20 20:20:49 +0800 | [diff] [blame] | 4028 | if ((val & VSSTATUS64_UXL) == 0) { |
| 4029 | mask &= ~VSSTATUS64_UXL; |
| 4030 | } |
Yifei Jiang | 284d697 | 2020-10-26 19:55:25 +0800 | [diff] [blame] | 4031 | env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4032 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4033 | } |
| 4034 | |
LIU Zhiwei | a5cb044 | 2024-01-30 19:08:44 +0800 | [diff] [blame] | 4035 | static RISCVException read_vstvec(CPURISCVState *env, int csrno, |
| 4036 | target_ulong *val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4037 | { |
| 4038 | *val = env->vstvec; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4039 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4040 | } |
| 4041 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4042 | static RISCVException write_vstvec(CPURISCVState *env, int csrno, |
| 4043 | target_ulong val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4044 | { |
Jiayi Li | 910c18a | 2024-07-01 10:25:53 +0800 | [diff] [blame] | 4045 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ |
| 4046 | if ((val & 3) < 2) { |
| 4047 | env->vstvec = val; |
| 4048 | } else { |
| 4049 | qemu_log_mask(LOG_UNIMP, "CSR_VSTVEC: reserved mode not supported\n"); |
| 4050 | } |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4051 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4052 | } |
| 4053 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4054 | static RISCVException read_vsscratch(CPURISCVState *env, int csrno, |
| 4055 | target_ulong *val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4056 | { |
| 4057 | *val = env->vsscratch; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4058 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4059 | } |
| 4060 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4061 | static RISCVException write_vsscratch(CPURISCVState *env, int csrno, |
| 4062 | target_ulong val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4063 | { |
| 4064 | env->vsscratch = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4065 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4066 | } |
| 4067 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4068 | static RISCVException read_vsepc(CPURISCVState *env, int csrno, |
| 4069 | target_ulong *val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4070 | { |
| 4071 | *val = env->vsepc; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4072 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4073 | } |
| 4074 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4075 | static RISCVException write_vsepc(CPURISCVState *env, int csrno, |
| 4076 | target_ulong val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4077 | { |
| 4078 | env->vsepc = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4079 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4080 | } |
| 4081 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4082 | static RISCVException read_vscause(CPURISCVState *env, int csrno, |
| 4083 | target_ulong *val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4084 | { |
| 4085 | *val = env->vscause; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4086 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4087 | } |
| 4088 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4089 | static RISCVException write_vscause(CPURISCVState *env, int csrno, |
| 4090 | target_ulong val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4091 | { |
| 4092 | env->vscause = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4093 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4094 | } |
| 4095 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4096 | static RISCVException read_vstval(CPURISCVState *env, int csrno, |
| 4097 | target_ulong *val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4098 | { |
| 4099 | *val = env->vstval; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4100 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4101 | } |
| 4102 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4103 | static RISCVException write_vstval(CPURISCVState *env, int csrno, |
| 4104 | target_ulong val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4105 | { |
| 4106 | env->vstval = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4107 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4108 | } |
| 4109 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4110 | static RISCVException read_vsatp(CPURISCVState *env, int csrno, |
| 4111 | target_ulong *val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4112 | { |
| 4113 | *val = env->vsatp; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4114 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4115 | } |
| 4116 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4117 | static RISCVException write_vsatp(CPURISCVState *env, int csrno, |
| 4118 | target_ulong val) |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4119 | { |
Irina Ryapolova | 1349f96 | 2024-01-09 17:59:22 +0300 | [diff] [blame] | 4120 | env->vsatp = legalize_xatp(env, env->vsatp, val); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4121 | return RISCV_EXCP_NONE; |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 4122 | } |
| 4123 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4124 | static RISCVException read_mtval2(CPURISCVState *env, int csrno, |
| 4125 | target_ulong *val) |
Alistair Francis | 34cfb5f | 2020-01-31 17:02:10 -0800 | [diff] [blame] | 4126 | { |
| 4127 | *val = env->mtval2; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4128 | return RISCV_EXCP_NONE; |
Alistair Francis | 34cfb5f | 2020-01-31 17:02:10 -0800 | [diff] [blame] | 4129 | } |
| 4130 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4131 | static RISCVException write_mtval2(CPURISCVState *env, int csrno, |
| 4132 | target_ulong val) |
Alistair Francis | 34cfb5f | 2020-01-31 17:02:10 -0800 | [diff] [blame] | 4133 | { |
| 4134 | env->mtval2 = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4135 | return RISCV_EXCP_NONE; |
Alistair Francis | 34cfb5f | 2020-01-31 17:02:10 -0800 | [diff] [blame] | 4136 | } |
| 4137 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4138 | static RISCVException read_mtinst(CPURISCVState *env, int csrno, |
| 4139 | target_ulong *val) |
Alistair Francis | 34cfb5f | 2020-01-31 17:02:10 -0800 | [diff] [blame] | 4140 | { |
| 4141 | *val = env->mtinst; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4142 | return RISCV_EXCP_NONE; |
Alistair Francis | 34cfb5f | 2020-01-31 17:02:10 -0800 | [diff] [blame] | 4143 | } |
| 4144 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4145 | static RISCVException write_mtinst(CPURISCVState *env, int csrno, |
| 4146 | target_ulong val) |
Alistair Francis | 34cfb5f | 2020-01-31 17:02:10 -0800 | [diff] [blame] | 4147 | { |
| 4148 | env->mtinst = val; |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4149 | return RISCV_EXCP_NONE; |
Alistair Francis | 34cfb5f | 2020-01-31 17:02:10 -0800 | [diff] [blame] | 4150 | } |
| 4151 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4152 | /* Physical Memory Protection */ |
Hou Weiying | 2582a95 | 2021-04-19 16:16:53 +1000 | [diff] [blame] | 4153 | static RISCVException read_mseccfg(CPURISCVState *env, int csrno, |
| 4154 | target_ulong *val) |
| 4155 | { |
| 4156 | *val = mseccfg_csr_read(env); |
| 4157 | return RISCV_EXCP_NONE; |
| 4158 | } |
| 4159 | |
| 4160 | static RISCVException write_mseccfg(CPURISCVState *env, int csrno, |
Bin Meng | 8c7fedd | 2023-02-28 18:40:22 +0800 | [diff] [blame] | 4161 | target_ulong val) |
Hou Weiying | 2582a95 | 2021-04-19 16:16:53 +1000 | [diff] [blame] | 4162 | { |
| 4163 | mseccfg_csr_write(env, val); |
| 4164 | return RISCV_EXCP_NONE; |
| 4165 | } |
| 4166 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4167 | static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, |
| 4168 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4169 | { |
LIU Zhiwei | 79f26b3 | 2022-01-20 20:20:28 +0800 | [diff] [blame] | 4170 | uint32_t reg_index = csrno - CSR_PMPCFG0; |
| 4171 | |
Bin Meng | 77ad639 | 2023-02-28 18:40:24 +0800 | [diff] [blame] | 4172 | *val = pmpcfg_csr_read(env, reg_index); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4173 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4174 | } |
| 4175 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4176 | static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, |
| 4177 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4178 | { |
LIU Zhiwei | 79f26b3 | 2022-01-20 20:20:28 +0800 | [diff] [blame] | 4179 | uint32_t reg_index = csrno - CSR_PMPCFG0; |
| 4180 | |
Bin Meng | 77ad639 | 2023-02-28 18:40:24 +0800 | [diff] [blame] | 4181 | pmpcfg_csr_write(env, reg_index, val); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4182 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4183 | } |
| 4184 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4185 | static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, |
| 4186 | target_ulong *val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4187 | { |
| 4188 | *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4189 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4190 | } |
| 4191 | |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4192 | static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, |
| 4193 | target_ulong val) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4194 | { |
| 4195 | pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4196 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4197 | } |
| 4198 | |
Bin Meng | b609254 | 2022-04-21 08:33:21 +0800 | [diff] [blame] | 4199 | static RISCVException read_tselect(CPURISCVState *env, int csrno, |
| 4200 | target_ulong *val) |
| 4201 | { |
| 4202 | *val = tselect_csr_read(env); |
| 4203 | return RISCV_EXCP_NONE; |
| 4204 | } |
| 4205 | |
| 4206 | static RISCVException write_tselect(CPURISCVState *env, int csrno, |
| 4207 | target_ulong val) |
| 4208 | { |
| 4209 | tselect_csr_write(env, val); |
| 4210 | return RISCV_EXCP_NONE; |
| 4211 | } |
| 4212 | |
| 4213 | static RISCVException read_tdata(CPURISCVState *env, int csrno, |
| 4214 | target_ulong *val) |
| 4215 | { |
| 4216 | /* return 0 in tdata1 to end the trigger enumeration */ |
Frank Chang | a42bd00 | 2022-09-09 21:42:08 +0800 | [diff] [blame] | 4217 | if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) { |
Bin Meng | b609254 | 2022-04-21 08:33:21 +0800 | [diff] [blame] | 4218 | *val = 0; |
| 4219 | return RISCV_EXCP_NONE; |
| 4220 | } |
| 4221 | |
| 4222 | if (!tdata_available(env, csrno - CSR_TDATA1)) { |
| 4223 | return RISCV_EXCP_ILLEGAL_INST; |
| 4224 | } |
| 4225 | |
| 4226 | *val = tdata_csr_read(env, csrno - CSR_TDATA1); |
| 4227 | return RISCV_EXCP_NONE; |
| 4228 | } |
| 4229 | |
| 4230 | static RISCVException write_tdata(CPURISCVState *env, int csrno, |
| 4231 | target_ulong val) |
| 4232 | { |
| 4233 | if (!tdata_available(env, csrno - CSR_TDATA1)) { |
| 4234 | return RISCV_EXCP_ILLEGAL_INST; |
| 4235 | } |
| 4236 | |
| 4237 | tdata_csr_write(env, csrno - CSR_TDATA1, val); |
| 4238 | return RISCV_EXCP_NONE; |
| 4239 | } |
| 4240 | |
Frank Chang | 31b9798 | 2022-09-09 21:42:12 +0800 | [diff] [blame] | 4241 | static RISCVException read_tinfo(CPURISCVState *env, int csrno, |
| 4242 | target_ulong *val) |
| 4243 | { |
| 4244 | *val = tinfo_csr_read(env); |
| 4245 | return RISCV_EXCP_NONE; |
| 4246 | } |
| 4247 | |
Alvin Chang | 0c4e579 | 2023-12-19 20:32:44 +0800 | [diff] [blame] | 4248 | static RISCVException read_mcontext(CPURISCVState *env, int csrno, |
| 4249 | target_ulong *val) |
| 4250 | { |
| 4251 | *val = env->mcontext; |
| 4252 | return RISCV_EXCP_NONE; |
| 4253 | } |
| 4254 | |
| 4255 | static RISCVException write_mcontext(CPURISCVState *env, int csrno, |
| 4256 | target_ulong val) |
| 4257 | { |
| 4258 | bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; |
| 4259 | int32_t mask; |
| 4260 | |
| 4261 | if (riscv_has_ext(env, RVH)) { |
| 4262 | /* Spec suggest 7-bit for RV32 and 14-bit for RV64 w/ H extension */ |
| 4263 | mask = rv32 ? MCONTEXT32_HCONTEXT : MCONTEXT64_HCONTEXT; |
| 4264 | } else { |
| 4265 | /* Spec suggest 6-bit for RV32 and 13-bit for RV64 w/o H extension */ |
| 4266 | mask = rv32 ? MCONTEXT32 : MCONTEXT64; |
| 4267 | } |
| 4268 | |
| 4269 | env->mcontext = val & mask; |
| 4270 | return RISCV_EXCP_NONE; |
| 4271 | } |
| 4272 | |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4273 | /* |
| 4274 | * Functions to access Pointer Masking feature registers |
| 4275 | * We have to check if current priv lvl could modify |
| 4276 | * csr in given mode |
| 4277 | */ |
| 4278 | static bool check_pm_current_disabled(CPURISCVState *env, int csrno) |
| 4279 | { |
| 4280 | int csr_priv = get_field(csrno, 0x300); |
| 4281 | int pm_current; |
| 4282 | |
LIU Zhiwei | 47bdec8 | 2022-01-20 20:20:36 +0800 | [diff] [blame] | 4283 | if (env->debugger) { |
| 4284 | return false; |
| 4285 | } |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4286 | /* |
| 4287 | * If priv lvls differ that means we're accessing csr from higher priv lvl, |
| 4288 | * so allow the access |
| 4289 | */ |
| 4290 | if (env->priv != csr_priv) { |
| 4291 | return false; |
| 4292 | } |
| 4293 | switch (env->priv) { |
| 4294 | case PRV_M: |
| 4295 | pm_current = get_field(env->mmte, M_PM_CURRENT); |
| 4296 | break; |
| 4297 | case PRV_S: |
| 4298 | pm_current = get_field(env->mmte, S_PM_CURRENT); |
| 4299 | break; |
| 4300 | case PRV_U: |
| 4301 | pm_current = get_field(env->mmte, U_PM_CURRENT); |
| 4302 | break; |
| 4303 | default: |
| 4304 | g_assert_not_reached(); |
| 4305 | } |
| 4306 | /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ |
| 4307 | return !pm_current; |
| 4308 | } |
| 4309 | |
| 4310 | static RISCVException read_mmte(CPURISCVState *env, int csrno, |
| 4311 | target_ulong *val) |
| 4312 | { |
| 4313 | *val = env->mmte & MMTE_MASK; |
| 4314 | return RISCV_EXCP_NONE; |
| 4315 | } |
| 4316 | |
| 4317 | static RISCVException write_mmte(CPURISCVState *env, int csrno, |
| 4318 | target_ulong val) |
| 4319 | { |
| 4320 | uint64_t mstatus; |
| 4321 | target_ulong wpri_val = val & MMTE_MASK; |
| 4322 | |
| 4323 | if (val != wpri_val) { |
Weiwei Li | 246f879 | 2023-04-05 16:58:13 +0800 | [diff] [blame] | 4324 | qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" |
| 4325 | TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x", |
| 4326 | val, "vs expected 0x", wpri_val); |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4327 | } |
| 4328 | /* for machine mode pm.current is hardwired to 1 */ |
| 4329 | wpri_val |= MMTE_M_PM_CURRENT; |
| 4330 | |
| 4331 | /* hardwiring pm.instruction bit to 0, since it's not supported yet */ |
| 4332 | wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); |
LIU Zhiwei | 42967f4 | 2023-04-12 13:43:10 +0200 | [diff] [blame] | 4333 | env->mmte = wpri_val | EXT_STATUS_DIRTY; |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4334 | riscv_cpu_update_mask(env); |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4335 | |
| 4336 | /* Set XS and SD bits, since PM CSRs are dirty */ |
| 4337 | mstatus = env->mstatus | MSTATUS_XS; |
| 4338 | write_mstatus(env, csrno, mstatus); |
| 4339 | return RISCV_EXCP_NONE; |
| 4340 | } |
| 4341 | |
| 4342 | static RISCVException read_smte(CPURISCVState *env, int csrno, |
| 4343 | target_ulong *val) |
| 4344 | { |
| 4345 | *val = env->mmte & SMTE_MASK; |
| 4346 | return RISCV_EXCP_NONE; |
| 4347 | } |
| 4348 | |
| 4349 | static RISCVException write_smte(CPURISCVState *env, int csrno, |
| 4350 | target_ulong val) |
| 4351 | { |
| 4352 | target_ulong wpri_val = val & SMTE_MASK; |
| 4353 | |
| 4354 | if (val != wpri_val) { |
Weiwei Li | 246f879 | 2023-04-05 16:58:13 +0800 | [diff] [blame] | 4355 | qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" |
| 4356 | TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x", |
| 4357 | val, "vs expected 0x", wpri_val); |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4358 | } |
| 4359 | |
| 4360 | /* if pm.current==0 we can't modify current PM CSRs */ |
| 4361 | if (check_pm_current_disabled(env, csrno)) { |
| 4362 | return RISCV_EXCP_NONE; |
| 4363 | } |
| 4364 | |
| 4365 | wpri_val |= (env->mmte & ~SMTE_MASK); |
| 4366 | write_mmte(env, csrno, wpri_val); |
| 4367 | return RISCV_EXCP_NONE; |
| 4368 | } |
| 4369 | |
| 4370 | static RISCVException read_umte(CPURISCVState *env, int csrno, |
| 4371 | target_ulong *val) |
| 4372 | { |
| 4373 | *val = env->mmte & UMTE_MASK; |
| 4374 | return RISCV_EXCP_NONE; |
| 4375 | } |
| 4376 | |
| 4377 | static RISCVException write_umte(CPURISCVState *env, int csrno, |
| 4378 | target_ulong val) |
| 4379 | { |
| 4380 | target_ulong wpri_val = val & UMTE_MASK; |
| 4381 | |
| 4382 | if (val != wpri_val) { |
Weiwei Li | 246f879 | 2023-04-05 16:58:13 +0800 | [diff] [blame] | 4383 | qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" |
| 4384 | TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x", |
| 4385 | val, "vs expected 0x", wpri_val); |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4386 | } |
| 4387 | |
| 4388 | if (check_pm_current_disabled(env, csrno)) { |
| 4389 | return RISCV_EXCP_NONE; |
| 4390 | } |
| 4391 | |
| 4392 | wpri_val |= (env->mmte & ~UMTE_MASK); |
| 4393 | write_mmte(env, csrno, wpri_val); |
| 4394 | return RISCV_EXCP_NONE; |
| 4395 | } |
| 4396 | |
| 4397 | static RISCVException read_mpmmask(CPURISCVState *env, int csrno, |
| 4398 | target_ulong *val) |
| 4399 | { |
| 4400 | *val = env->mpmmask; |
| 4401 | return RISCV_EXCP_NONE; |
| 4402 | } |
| 4403 | |
| 4404 | static RISCVException write_mpmmask(CPURISCVState *env, int csrno, |
| 4405 | target_ulong val) |
| 4406 | { |
| 4407 | uint64_t mstatus; |
| 4408 | |
| 4409 | env->mpmmask = val; |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 4410 | if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4411 | env->cur_pmmask = val; |
| 4412 | } |
LIU Zhiwei | 42967f4 | 2023-04-12 13:43:10 +0200 | [diff] [blame] | 4413 | env->mmte |= EXT_STATUS_DIRTY; |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4414 | |
| 4415 | /* Set XS and SD bits, since PM CSRs are dirty */ |
| 4416 | mstatus = env->mstatus | MSTATUS_XS; |
| 4417 | write_mstatus(env, csrno, mstatus); |
| 4418 | return RISCV_EXCP_NONE; |
| 4419 | } |
| 4420 | |
| 4421 | static RISCVException read_spmmask(CPURISCVState *env, int csrno, |
| 4422 | target_ulong *val) |
| 4423 | { |
| 4424 | *val = env->spmmask; |
| 4425 | return RISCV_EXCP_NONE; |
| 4426 | } |
| 4427 | |
| 4428 | static RISCVException write_spmmask(CPURISCVState *env, int csrno, |
| 4429 | target_ulong val) |
| 4430 | { |
| 4431 | uint64_t mstatus; |
| 4432 | |
| 4433 | /* if pm.current==0 we can't modify current PM CSRs */ |
| 4434 | if (check_pm_current_disabled(env, csrno)) { |
| 4435 | return RISCV_EXCP_NONE; |
| 4436 | } |
| 4437 | env->spmmask = val; |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 4438 | if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4439 | env->cur_pmmask = val; |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 4440 | if (cpu_get_xl(env, PRV_S) == MXL_RV32) { |
| 4441 | env->cur_pmmask &= UINT32_MAX; |
| 4442 | } |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4443 | } |
LIU Zhiwei | 42967f4 | 2023-04-12 13:43:10 +0200 | [diff] [blame] | 4444 | env->mmte |= EXT_STATUS_DIRTY; |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4445 | |
| 4446 | /* Set XS and SD bits, since PM CSRs are dirty */ |
| 4447 | mstatus = env->mstatus | MSTATUS_XS; |
| 4448 | write_mstatus(env, csrno, mstatus); |
| 4449 | return RISCV_EXCP_NONE; |
| 4450 | } |
| 4451 | |
| 4452 | static RISCVException read_upmmask(CPURISCVState *env, int csrno, |
| 4453 | target_ulong *val) |
| 4454 | { |
| 4455 | *val = env->upmmask; |
| 4456 | return RISCV_EXCP_NONE; |
| 4457 | } |
| 4458 | |
| 4459 | static RISCVException write_upmmask(CPURISCVState *env, int csrno, |
| 4460 | target_ulong val) |
| 4461 | { |
| 4462 | uint64_t mstatus; |
| 4463 | |
| 4464 | /* if pm.current==0 we can't modify current PM CSRs */ |
| 4465 | if (check_pm_current_disabled(env, csrno)) { |
| 4466 | return RISCV_EXCP_NONE; |
| 4467 | } |
| 4468 | env->upmmask = val; |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 4469 | if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4470 | env->cur_pmmask = val; |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 4471 | if (cpu_get_xl(env, PRV_U) == MXL_RV32) { |
| 4472 | env->cur_pmmask &= UINT32_MAX; |
| 4473 | } |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4474 | } |
LIU Zhiwei | 42967f4 | 2023-04-12 13:43:10 +0200 | [diff] [blame] | 4475 | env->mmte |= EXT_STATUS_DIRTY; |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4476 | |
| 4477 | /* Set XS and SD bits, since PM CSRs are dirty */ |
| 4478 | mstatus = env->mstatus | MSTATUS_XS; |
| 4479 | write_mstatus(env, csrno, mstatus); |
| 4480 | return RISCV_EXCP_NONE; |
| 4481 | } |
| 4482 | |
| 4483 | static RISCVException read_mpmbase(CPURISCVState *env, int csrno, |
| 4484 | target_ulong *val) |
| 4485 | { |
| 4486 | *val = env->mpmbase; |
| 4487 | return RISCV_EXCP_NONE; |
| 4488 | } |
| 4489 | |
| 4490 | static RISCVException write_mpmbase(CPURISCVState *env, int csrno, |
| 4491 | target_ulong val) |
| 4492 | { |
| 4493 | uint64_t mstatus; |
| 4494 | |
| 4495 | env->mpmbase = val; |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 4496 | if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4497 | env->cur_pmbase = val; |
| 4498 | } |
LIU Zhiwei | 42967f4 | 2023-04-12 13:43:10 +0200 | [diff] [blame] | 4499 | env->mmte |= EXT_STATUS_DIRTY; |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4500 | |
| 4501 | /* Set XS and SD bits, since PM CSRs are dirty */ |
| 4502 | mstatus = env->mstatus | MSTATUS_XS; |
| 4503 | write_mstatus(env, csrno, mstatus); |
| 4504 | return RISCV_EXCP_NONE; |
| 4505 | } |
| 4506 | |
| 4507 | static RISCVException read_spmbase(CPURISCVState *env, int csrno, |
| 4508 | target_ulong *val) |
| 4509 | { |
| 4510 | *val = env->spmbase; |
| 4511 | return RISCV_EXCP_NONE; |
| 4512 | } |
| 4513 | |
| 4514 | static RISCVException write_spmbase(CPURISCVState *env, int csrno, |
| 4515 | target_ulong val) |
| 4516 | { |
| 4517 | uint64_t mstatus; |
| 4518 | |
| 4519 | /* if pm.current==0 we can't modify current PM CSRs */ |
| 4520 | if (check_pm_current_disabled(env, csrno)) { |
| 4521 | return RISCV_EXCP_NONE; |
| 4522 | } |
| 4523 | env->spmbase = val; |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 4524 | if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4525 | env->cur_pmbase = val; |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 4526 | if (cpu_get_xl(env, PRV_S) == MXL_RV32) { |
| 4527 | env->cur_pmbase &= UINT32_MAX; |
| 4528 | } |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4529 | } |
LIU Zhiwei | 42967f4 | 2023-04-12 13:43:10 +0200 | [diff] [blame] | 4530 | env->mmte |= EXT_STATUS_DIRTY; |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4531 | |
| 4532 | /* Set XS and SD bits, since PM CSRs are dirty */ |
| 4533 | mstatus = env->mstatus | MSTATUS_XS; |
| 4534 | write_mstatus(env, csrno, mstatus); |
| 4535 | return RISCV_EXCP_NONE; |
| 4536 | } |
| 4537 | |
| 4538 | static RISCVException read_upmbase(CPURISCVState *env, int csrno, |
| 4539 | target_ulong *val) |
| 4540 | { |
| 4541 | *val = env->upmbase; |
| 4542 | return RISCV_EXCP_NONE; |
| 4543 | } |
| 4544 | |
| 4545 | static RISCVException write_upmbase(CPURISCVState *env, int csrno, |
| 4546 | target_ulong val) |
| 4547 | { |
| 4548 | uint64_t mstatus; |
| 4549 | |
| 4550 | /* if pm.current==0 we can't modify current PM CSRs */ |
| 4551 | if (check_pm_current_disabled(env, csrno)) { |
| 4552 | return RISCV_EXCP_NONE; |
| 4553 | } |
| 4554 | env->upmbase = val; |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 4555 | if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4556 | env->cur_pmbase = val; |
Weiwei Li | ef1ba32 | 2023-06-14 11:25:47 +0800 | [diff] [blame] | 4557 | if (cpu_get_xl(env, PRV_U) == MXL_RV32) { |
| 4558 | env->cur_pmbase &= UINT32_MAX; |
| 4559 | } |
LIU Zhiwei | 40bfa5f | 2022-01-20 20:20:38 +0800 | [diff] [blame] | 4560 | } |
LIU Zhiwei | 42967f4 | 2023-04-12 13:43:10 +0200 | [diff] [blame] | 4561 | env->mmte |= EXT_STATUS_DIRTY; |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 4562 | |
| 4563 | /* Set XS and SD bits, since PM CSRs are dirty */ |
| 4564 | mstatus = env->mstatus | MSTATUS_XS; |
| 4565 | write_mstatus(env, csrno, mstatus); |
| 4566 | return RISCV_EXCP_NONE; |
| 4567 | } |
| 4568 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4569 | #endif |
| 4570 | |
Weiwei Li | 7744238 | 2022-04-23 10:35:08 +0800 | [diff] [blame] | 4571 | /* Crypto Extension */ |
Andrew Jones | 8699777 | 2024-04-22 15:46:06 +0200 | [diff] [blame] | 4572 | target_ulong riscv_new_csr_seed(target_ulong new_value, |
| 4573 | target_ulong write_mask) |
Weiwei Li | 7744238 | 2022-04-23 10:35:08 +0800 | [diff] [blame] | 4574 | { |
| 4575 | uint16_t random_v; |
| 4576 | Error *random_e = NULL; |
| 4577 | int random_r; |
| 4578 | target_ulong rval; |
| 4579 | |
| 4580 | random_r = qemu_guest_getrandom(&random_v, 2, &random_e); |
| 4581 | if (unlikely(random_r < 0)) { |
| 4582 | /* |
| 4583 | * Failed, for unknown reasons in the crypto subsystem. |
| 4584 | * The best we can do is log the reason and return a |
| 4585 | * failure indication to the guest. There is no reason |
| 4586 | * we know to expect the failure to be transitory, so |
| 4587 | * indicate DEAD to avoid having the guest spin on WAIT. |
| 4588 | */ |
| 4589 | qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", |
| 4590 | __func__, error_get_pretty(random_e)); |
| 4591 | error_free(random_e); |
| 4592 | rval = SEED_OPST_DEAD; |
| 4593 | } else { |
| 4594 | rval = random_v | SEED_OPST_ES16; |
| 4595 | } |
| 4596 | |
Andrew Jones | 8699777 | 2024-04-22 15:46:06 +0200 | [diff] [blame] | 4597 | return rval; |
| 4598 | } |
| 4599 | |
| 4600 | static RISCVException rmw_seed(CPURISCVState *env, int csrno, |
| 4601 | target_ulong *ret_value, |
| 4602 | target_ulong new_value, |
| 4603 | target_ulong write_mask) |
| 4604 | { |
| 4605 | target_ulong rval; |
| 4606 | |
| 4607 | rval = riscv_new_csr_seed(new_value, write_mask); |
| 4608 | |
Weiwei Li | 7744238 | 2022-04-23 10:35:08 +0800 | [diff] [blame] | 4609 | if (ret_value) { |
| 4610 | *ret_value = rval; |
| 4611 | } |
| 4612 | |
| 4613 | return RISCV_EXCP_NONE; |
| 4614 | } |
| 4615 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4616 | /* |
| 4617 | * riscv_csrrw - read and/or update control and status register |
| 4618 | * |
| 4619 | * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); |
| 4620 | * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); |
| 4621 | * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); |
| 4622 | * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); |
| 4623 | */ |
| 4624 | |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 4625 | static inline RISCVException riscv_csrrw_check(CPURISCVState *env, |
| 4626 | int csrno, |
Yu-Ming Chang | 38c83e8 | 2024-03-08 15:48:03 +0800 | [diff] [blame] | 4627 | bool write) |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4628 | { |
Bin Meng | 65e728a | 2021-08-07 22:10:25 +0800 | [diff] [blame] | 4629 | /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ |
Bin Meng | a7e407b | 2023-02-28 18:40:23 +0800 | [diff] [blame] | 4630 | bool read_only = get_field(csrno, 0xC00) == 3; |
Atish Patra | 7100fe6c | 2022-03-03 10:54:40 -0800 | [diff] [blame] | 4631 | int csr_min_priv = csr_ops[csrno].min_priv_ver; |
Weiwei Li | eacaf44 | 2022-08-03 20:36:52 +0800 | [diff] [blame] | 4632 | |
Bin Meng | a5e0f68 | 2023-02-28 18:40:18 +0800 | [diff] [blame] | 4633 | /* ensure the CSR extension is enabled */ |
Daniel Henrique Barboza | 960b389 | 2023-10-12 13:46:02 -0300 | [diff] [blame] | 4634 | if (!riscv_cpu_cfg(env)->ext_zicsr) { |
Weiwei Li | eacaf44 | 2022-08-03 20:36:52 +0800 | [diff] [blame] | 4635 | return RISCV_EXCP_ILLEGAL_INST; |
| 4636 | } |
| 4637 | |
Bin Meng | eae04c4 | 2023-04-17 12:30:54 +0800 | [diff] [blame] | 4638 | /* ensure CSR is implemented by checking predicate */ |
| 4639 | if (!csr_ops[csrno].predicate) { |
| 4640 | return RISCV_EXCP_ILLEGAL_INST; |
| 4641 | } |
| 4642 | |
Bin Meng | a5e0f68 | 2023-02-28 18:40:18 +0800 | [diff] [blame] | 4643 | /* privileged spec version check */ |
Weiwei Li | eacaf44 | 2022-08-03 20:36:52 +0800 | [diff] [blame] | 4644 | if (env->priv_ver < csr_min_priv) { |
| 4645 | return RISCV_EXCP_ILLEGAL_INST; |
| 4646 | } |
| 4647 | |
Bin Meng | a5e0f68 | 2023-02-28 18:40:18 +0800 | [diff] [blame] | 4648 | /* read / write check */ |
Yu-Ming Chang | 38c83e8 | 2024-03-08 15:48:03 +0800 | [diff] [blame] | 4649 | if (write && read_only) { |
Weiwei Li | eacaf44 | 2022-08-03 20:36:52 +0800 | [diff] [blame] | 4650 | return RISCV_EXCP_ILLEGAL_INST; |
| 4651 | } |
| 4652 | |
Bin Meng | a5e0f68 | 2023-02-28 18:40:18 +0800 | [diff] [blame] | 4653 | /* |
| 4654 | * The predicate() not only does existence check but also does some |
| 4655 | * access control check which triggers for example virtual instruction |
| 4656 | * exception in some cases. When writing read-only CSRs in those cases |
| 4657 | * illegal instruction exception should be triggered instead of virtual |
| 4658 | * instruction exception. Hence this comes after the read / write check. |
| 4659 | */ |
Weiwei Li | eacaf44 | 2022-08-03 20:36:52 +0800 | [diff] [blame] | 4660 | RISCVException ret = csr_ops[csrno].predicate(env, csrno); |
| 4661 | if (ret != RISCV_EXCP_NONE) { |
| 4662 | return ret; |
| 4663 | } |
| 4664 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4665 | #if !defined(CONFIG_USER_ONLY) |
Anup Patel | c1fbcec | 2022-05-11 20:15:21 +0530 | [diff] [blame] | 4666 | int csr_priv, effective_priv = env->priv; |
Alistair Francis | 0a42f4c | 2020-01-31 17:01:56 -0800 | [diff] [blame] | 4667 | |
Weiwei Li | 5de1245 | 2022-07-18 21:09:55 +0800 | [diff] [blame] | 4668 | if (riscv_has_ext(env, RVH) && env->priv == PRV_S && |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 4669 | !env->virt_enabled) { |
Alistair Francis | 0a42f4c | 2020-01-31 17:01:56 -0800 | [diff] [blame] | 4670 | /* |
Michael Tokarev | 42fe749 | 2023-07-14 14:19:10 +0300 | [diff] [blame] | 4671 | * We are in HS mode. Add 1 to the effective privilege level to |
Weiwei Li | 5de1245 | 2022-07-18 21:09:55 +0800 | [diff] [blame] | 4672 | * allow us to access the Hypervisor CSRs. |
Alistair Francis | 0a42f4c | 2020-01-31 17:01:56 -0800 | [diff] [blame] | 4673 | */ |
| 4674 | effective_priv++; |
Bin Meng | e6e03dc | 2019-09-20 07:47:14 -0700 | [diff] [blame] | 4675 | } |
Alistair Francis | 0a42f4c | 2020-01-31 17:01:56 -0800 | [diff] [blame] | 4676 | |
Anup Patel | c1fbcec | 2022-05-11 20:15:21 +0530 | [diff] [blame] | 4677 | csr_priv = get_field(csrno, 0x300); |
| 4678 | if (!env->debugger && (effective_priv < csr_priv)) { |
Weiwei Li | 3825652 | 2023-04-05 16:58:10 +0800 | [diff] [blame] | 4679 | if (csr_priv == (PRV_S + 1) && env->virt_enabled) { |
Anup Patel | c1fbcec | 2022-05-11 20:15:21 +0530 | [diff] [blame] | 4680 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 4681 | } |
Alistair Francis | 533c91e | 2021-04-01 11:18:07 -0400 | [diff] [blame] | 4682 | return RISCV_EXCP_ILLEGAL_INST; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4683 | } |
| 4684 | #endif |
Weiwei Li | eacaf44 | 2022-08-03 20:36:52 +0800 | [diff] [blame] | 4685 | return RISCV_EXCP_NONE; |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 4686 | } |
| 4687 | |
| 4688 | static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, |
| 4689 | target_ulong *ret_value, |
| 4690 | target_ulong new_value, |
| 4691 | target_ulong write_mask) |
| 4692 | { |
| 4693 | RISCVException ret; |
Nikita Shubin | e7a0340 | 2023-08-08 12:09:14 +0300 | [diff] [blame] | 4694 | target_ulong old_value = 0; |
Michael Clark | a88365c | 2019-01-04 23:24:14 +0000 | [diff] [blame] | 4695 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4696 | /* execute combined read/write operation if it exists */ |
| 4697 | if (csr_ops[csrno].op) { |
Alistair Francis | 533c91e | 2021-04-01 11:18:07 -0400 | [diff] [blame] | 4698 | return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4699 | } |
| 4700 | |
Nikita Shubin | e7a0340 | 2023-08-08 12:09:14 +0300 | [diff] [blame] | 4701 | /* |
| 4702 | * ret_value == NULL means that rd=x0 and we're coming from helper_csrw() |
| 4703 | * and we can't throw side effects caused by CSR reads. |
| 4704 | */ |
| 4705 | if (ret_value) { |
| 4706 | /* if no accessor exists then return failure */ |
| 4707 | if (!csr_ops[csrno].read) { |
| 4708 | return RISCV_EXCP_ILLEGAL_INST; |
| 4709 | } |
| 4710 | /* read old value */ |
| 4711 | ret = csr_ops[csrno].read(env, csrno, &old_value); |
| 4712 | if (ret != RISCV_EXCP_NONE) { |
| 4713 | return ret; |
| 4714 | } |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4715 | } |
| 4716 | |
| 4717 | /* write value if writable and write mask set, otherwise drop writes */ |
| 4718 | if (write_mask) { |
| 4719 | new_value = (old_value & ~write_mask) | (new_value & write_mask); |
| 4720 | if (csr_ops[csrno].write) { |
| 4721 | ret = csr_ops[csrno].write(env, csrno, new_value); |
Alistair Francis | 605def6 | 2021-04-01 11:17:57 -0400 | [diff] [blame] | 4722 | if (ret != RISCV_EXCP_NONE) { |
Alistair Francis | 533c91e | 2021-04-01 11:18:07 -0400 | [diff] [blame] | 4723 | return ret; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4724 | } |
| 4725 | } |
| 4726 | } |
| 4727 | |
| 4728 | /* return old value */ |
| 4729 | if (ret_value) { |
| 4730 | *ret_value = old_value; |
| 4731 | } |
| 4732 | |
Alistair Francis | 533c91e | 2021-04-01 11:18:07 -0400 | [diff] [blame] | 4733 | return RISCV_EXCP_NONE; |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4734 | } |
| 4735 | |
Yu-Ming Chang | 38c83e8 | 2024-03-08 15:48:03 +0800 | [diff] [blame] | 4736 | RISCVException riscv_csrr(CPURISCVState *env, int csrno, |
| 4737 | target_ulong *ret_value) |
| 4738 | { |
| 4739 | RISCVException ret = riscv_csrrw_check(env, csrno, false); |
| 4740 | if (ret != RISCV_EXCP_NONE) { |
| 4741 | return ret; |
| 4742 | } |
| 4743 | |
| 4744 | return riscv_csrrw_do64(env, csrno, ret_value, 0, 0); |
| 4745 | } |
| 4746 | |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 4747 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
| 4748 | target_ulong *ret_value, |
| 4749 | target_ulong new_value, target_ulong write_mask) |
Frédéric Pétrot | 961738f | 2022-01-06 22:01:06 +0100 | [diff] [blame] | 4750 | { |
Yu-Ming Chang | 38c83e8 | 2024-03-08 15:48:03 +0800 | [diff] [blame] | 4751 | RISCVException ret = riscv_csrrw_check(env, csrno, true); |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 4752 | if (ret != RISCV_EXCP_NONE) { |
| 4753 | return ret; |
Frédéric Pétrot | 961738f | 2022-01-06 22:01:06 +0100 | [diff] [blame] | 4754 | } |
| 4755 | |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 4756 | return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); |
| 4757 | } |
| 4758 | |
| 4759 | static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, |
| 4760 | Int128 *ret_value, |
| 4761 | Int128 new_value, |
| 4762 | Int128 write_mask) |
| 4763 | { |
| 4764 | RISCVException ret; |
| 4765 | Int128 old_value; |
| 4766 | |
| 4767 | /* read old value */ |
| 4768 | ret = csr_ops[csrno].read128(env, csrno, &old_value); |
| 4769 | if (ret != RISCV_EXCP_NONE) { |
| 4770 | return ret; |
| 4771 | } |
| 4772 | |
| 4773 | /* write value if writable and write mask set, otherwise drop writes */ |
| 4774 | if (int128_nz(write_mask)) { |
| 4775 | new_value = int128_or(int128_and(old_value, int128_not(write_mask)), |
| 4776 | int128_and(new_value, write_mask)); |
| 4777 | if (csr_ops[csrno].write128) { |
| 4778 | ret = csr_ops[csrno].write128(env, csrno, new_value); |
| 4779 | if (ret != RISCV_EXCP_NONE) { |
| 4780 | return ret; |
| 4781 | } |
| 4782 | } else if (csr_ops[csrno].write) { |
| 4783 | /* avoids having to write wrappers for all registers */ |
| 4784 | ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value)); |
| 4785 | if (ret != RISCV_EXCP_NONE) { |
| 4786 | return ret; |
| 4787 | } |
| 4788 | } |
| 4789 | } |
| 4790 | |
| 4791 | /* return old value */ |
| 4792 | if (ret_value) { |
| 4793 | *ret_value = old_value; |
| 4794 | } |
| 4795 | |
| 4796 | return RISCV_EXCP_NONE; |
| 4797 | } |
| 4798 | |
Yu-Ming Chang | 38c83e8 | 2024-03-08 15:48:03 +0800 | [diff] [blame] | 4799 | RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, |
| 4800 | Int128 *ret_value) |
| 4801 | { |
| 4802 | RISCVException ret; |
| 4803 | |
| 4804 | ret = riscv_csrrw_check(env, csrno, false); |
| 4805 | if (ret != RISCV_EXCP_NONE) { |
| 4806 | return ret; |
| 4807 | } |
| 4808 | |
| 4809 | if (csr_ops[csrno].read128) { |
| 4810 | return riscv_csrrw_do128(env, csrno, ret_value, |
| 4811 | int128_zero(), int128_zero()); |
| 4812 | } |
| 4813 | |
| 4814 | /* |
| 4815 | * Fall back to 64-bit version for now, if the 128-bit alternative isn't |
| 4816 | * at all defined. |
| 4817 | * Note, some CSRs don't need to extend to MXLEN (64 upper bits non |
| 4818 | * significant), for those, this fallback is correctly handling the |
| 4819 | * accesses |
| 4820 | */ |
| 4821 | target_ulong old_value; |
| 4822 | ret = riscv_csrrw_do64(env, csrno, &old_value, |
| 4823 | (target_ulong)0, |
| 4824 | (target_ulong)0); |
| 4825 | if (ret == RISCV_EXCP_NONE && ret_value) { |
| 4826 | *ret_value = int128_make64(old_value); |
| 4827 | } |
| 4828 | return ret; |
| 4829 | } |
| 4830 | |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 4831 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, |
| 4832 | Int128 *ret_value, |
| 4833 | Int128 new_value, Int128 write_mask) |
| 4834 | { |
| 4835 | RISCVException ret; |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 4836 | |
Yu-Ming Chang | 38c83e8 | 2024-03-08 15:48:03 +0800 | [diff] [blame] | 4837 | ret = riscv_csrrw_check(env, csrno, true); |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 4838 | if (ret != RISCV_EXCP_NONE) { |
| 4839 | return ret; |
| 4840 | } |
| 4841 | |
| 4842 | if (csr_ops[csrno].read128) { |
| 4843 | return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); |
| 4844 | } |
| 4845 | |
| 4846 | /* |
| 4847 | * Fall back to 64-bit version for now, if the 128-bit alternative isn't |
| 4848 | * at all defined. |
| 4849 | * Note, some CSRs don't need to extend to MXLEN (64 upper bits non |
Weiwei Li | 246f879 | 2023-04-05 16:58:13 +0800 | [diff] [blame] | 4850 | * significant), for those, this fallback is correctly handling the |
| 4851 | * accesses |
Frédéric Pétrot | 457c360 | 2022-01-06 22:01:08 +0100 | [diff] [blame] | 4852 | */ |
| 4853 | target_ulong old_value; |
| 4854 | ret = riscv_csrrw_do64(env, csrno, &old_value, |
| 4855 | int128_getlo(new_value), |
| 4856 | int128_getlo(write_mask)); |
| 4857 | if (ret == RISCV_EXCP_NONE && ret_value) { |
| 4858 | *ret_value = int128_make64(old_value); |
| 4859 | } |
Frédéric Pétrot | 961738f | 2022-01-06 22:01:06 +0100 | [diff] [blame] | 4860 | return ret; |
| 4861 | } |
| 4862 | |
Jim Wilson | 753e3fe | 2019-03-15 03:26:58 -0700 | [diff] [blame] | 4863 | /* |
| 4864 | * Debugger support. If not in user mode, set env->debugger before the |
| 4865 | * riscv_csrrw call and clear it after the call. |
| 4866 | */ |
Alistair Francis | 533c91e | 2021-04-01 11:18:07 -0400 | [diff] [blame] | 4867 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, |
| 4868 | target_ulong *ret_value, |
| 4869 | target_ulong new_value, |
| 4870 | target_ulong write_mask) |
Jim Wilson | 753e3fe | 2019-03-15 03:26:58 -0700 | [diff] [blame] | 4871 | { |
Alistair Francis | 533c91e | 2021-04-01 11:18:07 -0400 | [diff] [blame] | 4872 | RISCVException ret; |
Jim Wilson | 753e3fe | 2019-03-15 03:26:58 -0700 | [diff] [blame] | 4873 | #if !defined(CONFIG_USER_ONLY) |
| 4874 | env->debugger = true; |
| 4875 | #endif |
Yu-Ming Chang | 38c83e8 | 2024-03-08 15:48:03 +0800 | [diff] [blame] | 4876 | if (!write_mask) { |
| 4877 | ret = riscv_csrr(env, csrno, ret_value); |
| 4878 | } else { |
| 4879 | ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); |
| 4880 | } |
Jim Wilson | 753e3fe | 2019-03-15 03:26:58 -0700 | [diff] [blame] | 4881 | #if !defined(CONFIG_USER_ONLY) |
| 4882 | env->debugger = false; |
| 4883 | #endif |
| 4884 | return ret; |
| 4885 | } |
| 4886 | |
Weiwei Li | ce3af0b | 2023-03-07 16:14:00 +0800 | [diff] [blame] | 4887 | static RISCVException read_jvt(CPURISCVState *env, int csrno, |
| 4888 | target_ulong *val) |
| 4889 | { |
| 4890 | *val = env->jvt; |
| 4891 | return RISCV_EXCP_NONE; |
| 4892 | } |
| 4893 | |
| 4894 | static RISCVException write_jvt(CPURISCVState *env, int csrno, |
| 4895 | target_ulong val) |
| 4896 | { |
| 4897 | env->jvt = val; |
| 4898 | return RISCV_EXCP_NONE; |
| 4899 | } |
| 4900 | |
Bin Meng | eae04c4 | 2023-04-17 12:30:54 +0800 | [diff] [blame] | 4901 | /* |
| 4902 | * Control and Status Register function table |
| 4903 | * riscv_csr_operations::predicate() must be provided for an implemented CSR |
| 4904 | */ |
Bin Meng | 56118ee | 2021-01-12 12:52:01 +0800 | [diff] [blame] | 4905 | riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4906 | /* User Floating-Point CSRs */ |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 4907 | [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, |
| 4908 | [CSR_FRM] = { "frm", fs, read_frm, write_frm }, |
| 4909 | [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, |
LIU Zhiwei | 8e3a1f1 | 2020-07-01 23:24:51 +0800 | [diff] [blame] | 4910 | /* Vector CSRs */ |
Frank Chang | 0e66014 | 2023-02-08 14:32:08 +0800 | [diff] [blame] | 4911 | [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, |
| 4912 | [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, |
| 4913 | [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, |
| 4914 | [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, |
| 4915 | [CSR_VL] = { "vl", vs, read_vl }, |
| 4916 | [CSR_VTYPE] = { "vtype", vs, read_vtype }, |
| 4917 | [CSR_VLENB] = { "vlenb", vs, read_vlenb }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4918 | /* User Timers and Counters */ |
Atish Patra | 3780e33 | 2022-06-20 16:15:57 -0700 | [diff] [blame] | 4919 | [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter }, |
| 4920 | [CSR_INSTRET] = { "instret", ctr, read_hpmcounter }, |
| 4921 | [CSR_CYCLEH] = { "cycleh", ctr32, read_hpmcounterh }, |
| 4922 | [CSR_INSTRETH] = { "instreth", ctr32, read_hpmcounterh }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4923 | |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 4924 | /* |
| 4925 | * In privileged mode, the monitor will have to emulate TIME CSRs only if |
| 4926 | * rdtime callback is not provided by machine/platform emulation. |
| 4927 | */ |
| 4928 | [CSR_TIME] = { "time", ctr, read_time }, |
| 4929 | [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4930 | |
Weiwei Li | 7744238 | 2022-04-23 10:35:08 +0800 | [diff] [blame] | 4931 | /* Crypto Extension */ |
| 4932 | [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed }, |
| 4933 | |
Weiwei Li | ce3af0b | 2023-03-07 16:14:00 +0800 | [diff] [blame] | 4934 | /* Zcmt Extension */ |
| 4935 | [CSR_JVT] = {"jvt", zcmt, read_jvt, write_jvt}, |
| 4936 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4937 | #if !defined(CONFIG_USER_ONLY) |
| 4938 | /* Machine Timers and Counters */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 4939 | [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, |
| 4940 | write_mhpmcounter }, |
| 4941 | [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, |
| 4942 | write_mhpmcounter }, |
| 4943 | [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, |
| 4944 | write_mhpmcounterh }, |
| 4945 | [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, |
| 4946 | write_mhpmcounterh }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4947 | |
| 4948 | /* Machine Information Registers */ |
Frank Chang | 9951ba9 | 2022-04-22 12:04:34 +0800 | [diff] [blame] | 4949 | [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, |
| 4950 | [CSR_MARCHID] = { "marchid", any, read_marchid }, |
Frank Chang | 075eeda | 2022-05-23 23:31:46 +0800 | [diff] [blame] | 4951 | [CSR_MIMPID] = { "mimpid", any, read_mimpid }, |
Frank Chang | 9951ba9 | 2022-04-22 12:04:34 +0800 | [diff] [blame] | 4952 | [CSR_MHARTID] = { "mhartid", any, read_mhartid }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4953 | |
Atish Patra | 3e6a417 | 2022-03-03 10:54:38 -0800 | [diff] [blame] | 4954 | [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 4955 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4956 | /* Machine Trap Setup */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 4957 | [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, |
| 4958 | NULL, read_mstatus_i128 }, |
| 4959 | [CSR_MISA] = { "misa", any, read_misa, write_misa, |
| 4960 | NULL, read_misa_i128 }, |
| 4961 | [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, |
| 4962 | [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, |
| 4963 | [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, |
| 4964 | [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, |
Weiwei Li | c126f83 | 2022-07-18 21:09:53 +0800 | [diff] [blame] | 4965 | [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 4966 | write_mcounteren }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4967 | |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 4968 | [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, |
| 4969 | write_mstatush }, |
Fea.Wang | 2779698 | 2024-06-06 21:54:52 +0800 | [diff] [blame] | 4970 | [CSR_MEDELEGH] = { "medelegh", any32, read_zero, write_ignore, |
| 4971 | .min_priv_ver = PRIV_VERSION_1_13_0 }, |
| 4972 | [CSR_HEDELEGH] = { "hedelegh", hmode32, read_hedelegh, write_hedelegh, |
| 4973 | .min_priv_ver = PRIV_VERSION_1_13_0 }, |
Alistair Francis | 551fa7e | 2020-01-31 17:03:05 -0800 | [diff] [blame] | 4974 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4975 | /* Machine Trap Handling */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 4976 | [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, |
| 4977 | NULL, read_mscratch_i128, write_mscratch_i128 }, |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 4978 | [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, |
| 4979 | [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, |
Atish Patra | ac12b60 | 2021-03-19 12:45:29 -0700 | [diff] [blame] | 4980 | [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 4981 | [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 4982 | |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 4983 | /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ |
| 4984 | [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, |
| 4985 | [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, |
| 4986 | |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 4987 | /* Machine-Level Interrupts (AIA) */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 4988 | [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, |
| 4989 | [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, |
Anup Patel | ac4b030 | 2022-02-04 23:16:51 +0530 | [diff] [blame] | 4990 | |
Anup Patel | d0237b4 | 2022-02-04 23:16:48 +0530 | [diff] [blame] | 4991 | /* Virtual Interrupts for Supervisor Level (AIA) */ |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 4992 | [CSR_MVIEN] = { "mvien", aia_any, NULL, NULL, rmw_mvien }, |
| 4993 | [CSR_MVIP] = { "mvip", aia_any, NULL, NULL, rmw_mvip }, |
Anup Patel | d0237b4 | 2022-02-04 23:16:48 +0530 | [diff] [blame] | 4994 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 4995 | /* Machine-Level High-Half CSRs (AIA) */ |
| 4996 | [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, |
| 4997 | [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh }, |
Rajnesh Kanwal | 1697837 | 2023-10-16 12:17:35 +0100 | [diff] [blame] | 4998 | [CSR_MVIENH] = { "mvienh", aia_any32, NULL, NULL, rmw_mvienh }, |
| 4999 | [CSR_MVIPH] = { "mviph", aia_any32, NULL, NULL, rmw_mviph }, |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 5000 | [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, |
| 5001 | |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 5002 | /* Execution environment configuration */ |
Weiwei Li | c126f83 | 2022-07-18 21:09:53 +0800 | [diff] [blame] | 5003 | [CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5004 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Weiwei Li | c126f83 | 2022-07-18 21:09:53 +0800 | [diff] [blame] | 5005 | [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5006 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 5007 | [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5008 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 5009 | [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5010 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 5011 | [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5012 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | 29a9ec9 | 2022-03-03 10:54:39 -0800 | [diff] [blame] | 5013 | |
Mayuresh Chitale | 3bee0e4 | 2022-10-16 18:17:22 +0530 | [diff] [blame] | 5014 | /* Smstateen extension CSRs */ |
| 5015 | [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0, |
| 5016 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5017 | [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh, |
| 5018 | write_mstateen0h, |
| 5019 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5020 | [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen, |
| 5021 | write_mstateen_1_3, |
| 5022 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5023 | [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh, |
| 5024 | write_mstateenh_1_3, |
| 5025 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5026 | [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen, |
| 5027 | write_mstateen_1_3, |
| 5028 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5029 | [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh, |
| 5030 | write_mstateenh_1_3, |
| 5031 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5032 | [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen, |
| 5033 | write_mstateen_1_3, |
| 5034 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5035 | [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh, |
| 5036 | write_mstateenh_1_3, |
| 5037 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5038 | [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0, |
| 5039 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5040 | [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh, |
| 5041 | write_hstateen0h, |
| 5042 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5043 | [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen, |
| 5044 | write_hstateen_1_3, |
| 5045 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5046 | [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh, |
| 5047 | write_hstateenh_1_3, |
| 5048 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5049 | [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen, |
| 5050 | write_hstateen_1_3, |
| 5051 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5052 | [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh, |
| 5053 | write_hstateenh_1_3, |
| 5054 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5055 | [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen, |
| 5056 | write_hstateen_1_3, |
| 5057 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5058 | [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh, |
| 5059 | write_hstateenh_1_3, |
| 5060 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5061 | [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0, |
| 5062 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5063 | [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen, |
| 5064 | write_sstateen_1_3, |
| 5065 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5066 | [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen, |
| 5067 | write_sstateen_1_3, |
| 5068 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5069 | [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen, |
| 5070 | write_sstateen_1_3, |
| 5071 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5072 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 5073 | /* Supervisor Trap Setup */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5074 | [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, |
Weiwei Li | 246f879 | 2023-04-05 16:58:13 +0800 | [diff] [blame] | 5075 | NULL, read_sstatus_i128 }, |
| 5076 | [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, |
| 5077 | [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5078 | [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, |
Weiwei Li | 246f879 | 2023-04-05 16:58:13 +0800 | [diff] [blame] | 5079 | write_scounteren }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 5080 | |
| 5081 | /* Supervisor Trap Handling */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5082 | [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, |
| 5083 | NULL, read_sscratch_i128, write_sscratch_i128 }, |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 5084 | [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, |
| 5085 | [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5086 | [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 5087 | [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, |
Atish Patra | 43888c2 | 2022-08-24 15:13:56 -0700 | [diff] [blame] | 5088 | [CSR_STIMECMP] = { "stimecmp", sstc, read_stimecmp, write_stimecmp, |
| 5089 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5090 | [CSR_STIMECMPH] = { "stimecmph", sstc_32, read_stimecmph, write_stimecmph, |
| 5091 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | 3ec0fe1 | 2022-08-24 15:13:57 -0700 | [diff] [blame] | 5092 | [CSR_VSTIMECMP] = { "vstimecmp", sstc, read_vstimecmp, |
| 5093 | write_vstimecmp, |
| 5094 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5095 | [CSR_VSTIMECMPH] = { "vstimecmph", sstc_32, read_vstimecmph, |
| 5096 | write_vstimecmph, |
| 5097 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 5098 | |
| 5099 | /* Supervisor Protection and Translation */ |
Yi Chen | d6db7c9 | 2023-04-06 18:15:59 +0800 | [diff] [blame] | 5100 | [CSR_SATP] = { "satp", satp, read_satp, write_satp }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 5101 | |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 5102 | /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ |
| 5103 | [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect }, |
| 5104 | [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg }, |
| 5105 | |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 5106 | /* Supervisor-Level Interrupts (AIA) */ |
Anup Patel | ac4b030 | 2022-02-04 23:16:51 +0530 | [diff] [blame] | 5107 | [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, |
Anup Patel | df01af3 | 2022-06-16 08:45:42 +0530 | [diff] [blame] | 5108 | [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, |
Anup Patel | ac4b030 | 2022-02-04 23:16:51 +0530 | [diff] [blame] | 5109 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 5110 | /* Supervisor-Level High-Half CSRs (AIA) */ |
| 5111 | [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, |
| 5112 | [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, |
| 5113 | |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5114 | [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, |
| 5115 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5116 | [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, |
| 5117 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | a4b2fa4 | 2022-03-03 10:54:37 -0800 | [diff] [blame] | 5118 | [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5119 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5120 | [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, |
| 5121 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5122 | [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, |
| 5123 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5124 | [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, |
| 5125 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5126 | [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, |
| 5127 | write_hcounteren, |
| 5128 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5129 | [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, |
| 5130 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5131 | [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, |
| 5132 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5133 | [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, |
| 5134 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | a4b2fa4 | 2022-03-03 10:54:37 -0800 | [diff] [blame] | 5135 | [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5136 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Yi Chen | d6db7c9 | 2023-04-06 18:15:59 +0800 | [diff] [blame] | 5137 | [CSR_HGATP] = { "hgatp", hgatp, read_hgatp, write_hgatp, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5138 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5139 | [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, |
| 5140 | write_htimedelta, |
| 5141 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5142 | [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, |
| 5143 | write_htimedeltah, |
| 5144 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Alistair Francis | ff2cc12 | 2020-01-31 17:02:04 -0800 | [diff] [blame] | 5145 | |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5146 | [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, |
| 5147 | write_vsstatus, |
| 5148 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5149 | [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, |
| 5150 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5151 | [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , |
| 5152 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5153 | [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, |
| 5154 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5155 | [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, |
| 5156 | write_vsscratch, |
| 5157 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5158 | [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, |
| 5159 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5160 | [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, |
| 5161 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5162 | [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, |
| 5163 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5164 | [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, |
| 5165 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Alistair Francis | 8747c9e | 2020-01-31 17:02:07 -0800 | [diff] [blame] | 5166 | |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5167 | [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, |
| 5168 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5169 | [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, |
| 5170 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Alistair Francis | 34cfb5f | 2020-01-31 17:02:10 -0800 | [diff] [blame] | 5171 | |
Anup Patel | 2b60239 | 2022-02-04 23:16:47 +0530 | [diff] [blame] | 5172 | /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 5173 | [CSR_HVIEN] = { "hvien", aia_hmode, NULL, NULL, rmw_hvien }, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5174 | [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, |
| 5175 | write_hvictl }, |
| 5176 | [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, |
| 5177 | write_hviprio1 }, |
| 5178 | [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, |
| 5179 | write_hviprio2 }, |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 5180 | /* |
| 5181 | * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) |
| 5182 | */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5183 | [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, |
| 5184 | rmw_xiselect }, |
| 5185 | [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, |
Anup Patel | d1ceff4 | 2022-02-04 23:16:50 +0530 | [diff] [blame] | 5186 | |
Anup Patel | c7de92b | 2022-02-04 23:16:49 +0530 | [diff] [blame] | 5187 | /* VS-Level Interrupts (H-extension with AIA) */ |
Anup Patel | ac4b030 | 2022-02-04 23:16:51 +0530 | [diff] [blame] | 5188 | [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, |
Anup Patel | df01af3 | 2022-06-16 08:45:42 +0530 | [diff] [blame] | 5189 | [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, |
Anup Patel | ac4b030 | 2022-02-04 23:16:51 +0530 | [diff] [blame] | 5190 | |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 5191 | /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5192 | [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, |
| 5193 | rmw_hidelegh }, |
Rajnesh Kanwal | 40336d5 | 2023-10-16 12:17:36 +0100 | [diff] [blame] | 5194 | [CSR_HVIENH] = { "hvienh", aia_hmode32, NULL, NULL, rmw_hvienh }, |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 5195 | [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5196 | [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, |
| 5197 | write_hviprio1h }, |
| 5198 | [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, |
| 5199 | write_hviprio2h }, |
Anup Patel | d028ac7 | 2022-02-04 23:16:46 +0530 | [diff] [blame] | 5200 | [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, |
| 5201 | [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, |
| 5202 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 5203 | /* Physical Memory Protection */ |
Heinrich Schuchardt | 2f32dca | 2023-10-30 12:21:05 +0200 | [diff] [blame] | 5204 | [CSR_MSECCFG] = { "mseccfg", have_mseccfg, read_mseccfg, write_mseccfg, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5205 | .min_priv_ver = PRIV_VERSION_1_11_0 }, |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 5206 | [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, |
| 5207 | [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, |
| 5208 | [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, |
| 5209 | [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, |
| 5210 | [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, |
| 5211 | [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, |
| 5212 | [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, |
| 5213 | [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, |
| 5214 | [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, |
| 5215 | [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, |
| 5216 | [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, |
| 5217 | [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, |
| 5218 | [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, |
| 5219 | [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, |
| 5220 | [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, |
| 5221 | [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, |
| 5222 | [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, |
| 5223 | [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, |
| 5224 | [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, |
| 5225 | [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 5226 | |
Bin Meng | b609254 | 2022-04-21 08:33:21 +0800 | [diff] [blame] | 5227 | /* Debug CSRs */ |
Alvin Chang | 0c4e579 | 2023-12-19 20:32:44 +0800 | [diff] [blame] | 5228 | [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, |
| 5229 | [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, |
| 5230 | [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, |
| 5231 | [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, |
| 5232 | [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore }, |
| 5233 | [CSR_MCONTEXT] = { "mcontext", debug, read_mcontext, write_mcontext }, |
Bin Meng | b609254 | 2022-04-21 08:33:21 +0800 | [diff] [blame] | 5234 | |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 5235 | /* User Pointer Masking */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5236 | [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, |
| 5237 | [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, |
| 5238 | write_upmmask }, |
| 5239 | [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, |
| 5240 | write_upmbase }, |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 5241 | /* Machine Pointer Masking */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5242 | [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, |
| 5243 | [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, |
| 5244 | write_mpmmask }, |
| 5245 | [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, |
| 5246 | write_mpmbase }, |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 5247 | /* Supervisor Pointer Masking */ |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5248 | [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, |
| 5249 | [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, |
| 5250 | write_spmmask }, |
| 5251 | [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, |
| 5252 | write_spmbase }, |
Alexey Baturo | 4bbe803 | 2021-10-25 20:36:04 +0300 | [diff] [blame] | 5253 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 5254 | /* Performance Counters */ |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5255 | [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter }, |
| 5256 | [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter }, |
| 5257 | [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_hpmcounter }, |
| 5258 | [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_hpmcounter }, |
| 5259 | [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_hpmcounter }, |
| 5260 | [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_hpmcounter }, |
| 5261 | [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_hpmcounter }, |
| 5262 | [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_hpmcounter }, |
| 5263 | [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_hpmcounter }, |
| 5264 | [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_hpmcounter }, |
| 5265 | [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_hpmcounter }, |
| 5266 | [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_hpmcounter }, |
| 5267 | [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_hpmcounter }, |
| 5268 | [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_hpmcounter }, |
| 5269 | [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_hpmcounter }, |
| 5270 | [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_hpmcounter }, |
| 5271 | [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_hpmcounter }, |
| 5272 | [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_hpmcounter }, |
| 5273 | [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_hpmcounter }, |
| 5274 | [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_hpmcounter }, |
| 5275 | [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_hpmcounter }, |
| 5276 | [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_hpmcounter }, |
| 5277 | [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_hpmcounter }, |
| 5278 | [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_hpmcounter }, |
| 5279 | [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_hpmcounter }, |
| 5280 | [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_hpmcounter }, |
| 5281 | [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_hpmcounter }, |
| 5282 | [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter }, |
| 5283 | [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter }, |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 5284 | |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5285 | [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5286 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5287 | [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5288 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5289 | [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5290 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5291 | [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5292 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5293 | [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5294 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5295 | [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5296 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5297 | [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5298 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5299 | [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5300 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5301 | [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5302 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5303 | [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5304 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5305 | [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5306 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5307 | [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5308 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5309 | [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5310 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5311 | [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5312 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5313 | [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5314 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5315 | [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5316 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5317 | [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5318 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5319 | [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5320 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5321 | [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5322 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5323 | [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5324 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5325 | [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5326 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5327 | [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5328 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5329 | [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5330 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5331 | [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5332 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5333 | [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5334 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5335 | [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5336 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5337 | [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5338 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5339 | [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5340 | write_mhpmcounter }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5341 | [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5342 | write_mhpmcounter }, |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 5343 | |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5344 | [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5345 | write_mcountinhibit, |
| 5346 | .min_priv_ver = PRIV_VERSION_1_11_0 }, |
Atish Patra | b1675ee | 2022-06-20 16:15:55 -0700 | [diff] [blame] | 5347 | |
Kaiwen Xue | b54a84c | 2024-07-11 15:31:08 -0700 | [diff] [blame] | 5348 | [CSR_MCYCLECFG] = { "mcyclecfg", smcntrpmf, read_mcyclecfg, |
| 5349 | write_mcyclecfg, |
| 5350 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5351 | [CSR_MINSTRETCFG] = { "minstretcfg", smcntrpmf, read_minstretcfg, |
| 5352 | write_minstretcfg, |
| 5353 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5354 | |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5355 | [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5356 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5357 | [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5358 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5359 | [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5360 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5361 | [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5362 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5363 | [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5364 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5365 | [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5366 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5367 | [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5368 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5369 | [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5370 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5371 | [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5372 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5373 | [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5374 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5375 | [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5376 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5377 | [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5378 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5379 | [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5380 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5381 | [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5382 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5383 | [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5384 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5385 | [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5386 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5387 | [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5388 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5389 | [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5390 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5391 | [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5392 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5393 | [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5394 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5395 | [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5396 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5397 | [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5398 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5399 | [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5400 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5401 | [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5402 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5403 | [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5404 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5405 | [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5406 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5407 | [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5408 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5409 | [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5410 | write_mhpmevent }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5411 | [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5412 | write_mhpmevent }, |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 5413 | |
Kaiwen Xue | b54a84c | 2024-07-11 15:31:08 -0700 | [diff] [blame] | 5414 | [CSR_MCYCLECFGH] = { "mcyclecfgh", smcntrpmf_32, read_mcyclecfgh, |
| 5415 | write_mcyclecfgh, |
| 5416 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5417 | [CSR_MINSTRETCFGH] = { "minstretcfgh", smcntrpmf_32, read_minstretcfgh, |
| 5418 | write_minstretcfgh, |
| 5419 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
| 5420 | |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5421 | [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5422 | write_mhpmeventh, |
| 5423 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5424 | [CSR_MHPMEVENT4H] = { "mhpmevent4h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5425 | write_mhpmeventh, |
| 5426 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5427 | [CSR_MHPMEVENT5H] = { "mhpmevent5h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5428 | write_mhpmeventh, |
| 5429 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5430 | [CSR_MHPMEVENT6H] = { "mhpmevent6h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5431 | write_mhpmeventh, |
| 5432 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5433 | [CSR_MHPMEVENT7H] = { "mhpmevent7h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5434 | write_mhpmeventh, |
| 5435 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5436 | [CSR_MHPMEVENT8H] = { "mhpmevent8h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5437 | write_mhpmeventh, |
| 5438 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5439 | [CSR_MHPMEVENT9H] = { "mhpmevent9h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5440 | write_mhpmeventh, |
| 5441 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5442 | [CSR_MHPMEVENT10H] = { "mhpmevent10h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5443 | write_mhpmeventh, |
| 5444 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5445 | [CSR_MHPMEVENT11H] = { "mhpmevent11h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5446 | write_mhpmeventh, |
| 5447 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5448 | [CSR_MHPMEVENT12H] = { "mhpmevent12h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5449 | write_mhpmeventh, |
| 5450 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5451 | [CSR_MHPMEVENT13H] = { "mhpmevent13h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5452 | write_mhpmeventh, |
| 5453 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5454 | [CSR_MHPMEVENT14H] = { "mhpmevent14h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5455 | write_mhpmeventh, |
| 5456 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5457 | [CSR_MHPMEVENT15H] = { "mhpmevent15h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5458 | write_mhpmeventh, |
| 5459 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5460 | [CSR_MHPMEVENT16H] = { "mhpmevent16h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5461 | write_mhpmeventh, |
| 5462 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5463 | [CSR_MHPMEVENT17H] = { "mhpmevent17h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5464 | write_mhpmeventh, |
| 5465 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5466 | [CSR_MHPMEVENT18H] = { "mhpmevent18h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5467 | write_mhpmeventh, |
| 5468 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5469 | [CSR_MHPMEVENT19H] = { "mhpmevent19h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5470 | write_mhpmeventh, |
| 5471 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5472 | [CSR_MHPMEVENT20H] = { "mhpmevent20h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5473 | write_mhpmeventh, |
| 5474 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5475 | [CSR_MHPMEVENT21H] = { "mhpmevent21h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5476 | write_mhpmeventh, |
| 5477 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5478 | [CSR_MHPMEVENT22H] = { "mhpmevent22h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5479 | write_mhpmeventh, |
| 5480 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5481 | [CSR_MHPMEVENT23H] = { "mhpmevent23h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5482 | write_mhpmeventh, |
| 5483 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5484 | [CSR_MHPMEVENT24H] = { "mhpmevent24h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5485 | write_mhpmeventh, |
| 5486 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5487 | [CSR_MHPMEVENT25H] = { "mhpmevent25h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5488 | write_mhpmeventh, |
| 5489 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5490 | [CSR_MHPMEVENT26H] = { "mhpmevent26h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5491 | write_mhpmeventh, |
| 5492 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5493 | [CSR_MHPMEVENT27H] = { "mhpmevent27h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5494 | write_mhpmeventh, |
| 5495 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5496 | [CSR_MHPMEVENT28H] = { "mhpmevent28h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5497 | write_mhpmeventh, |
| 5498 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5499 | [CSR_MHPMEVENT29H] = { "mhpmevent29h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5500 | write_mhpmeventh, |
| 5501 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5502 | [CSR_MHPMEVENT30H] = { "mhpmevent30h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5503 | write_mhpmeventh, |
| 5504 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | be470e5 | 2024-07-11 15:31:05 -0700 | [diff] [blame] | 5505 | [CSR_MHPMEVENT31H] = { "mhpmevent31h", sscofpmf_32, read_mhpmeventh, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5506 | write_mhpmeventh, |
| 5507 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 5508 | |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5509 | [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh }, |
| 5510 | [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh }, |
| 5511 | [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh }, |
| 5512 | [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_hpmcounterh }, |
| 5513 | [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_hpmcounterh }, |
| 5514 | [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_hpmcounterh }, |
| 5515 | [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_hpmcounterh }, |
| 5516 | [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_hpmcounterh }, |
| 5517 | [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_hpmcounterh }, |
| 5518 | [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_hpmcounterh }, |
| 5519 | [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_hpmcounterh }, |
| 5520 | [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_hpmcounterh }, |
| 5521 | [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_hpmcounterh }, |
| 5522 | [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_hpmcounterh }, |
| 5523 | [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_hpmcounterh }, |
| 5524 | [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_hpmcounterh }, |
| 5525 | [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_hpmcounterh }, |
| 5526 | [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_hpmcounterh }, |
| 5527 | [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_hpmcounterh }, |
| 5528 | [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_hpmcounterh }, |
| 5529 | [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_hpmcounterh }, |
| 5530 | [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_hpmcounterh }, |
| 5531 | [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_hpmcounterh }, |
| 5532 | [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_hpmcounterh }, |
| 5533 | [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_hpmcounterh }, |
| 5534 | [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_hpmcounterh }, |
| 5535 | [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_hpmcounterh }, |
| 5536 | [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh }, |
| 5537 | [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh }, |
Bin Meng | 8ceac5d | 2021-01-12 12:52:02 +0800 | [diff] [blame] | 5538 | |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5539 | [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5540 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5541 | [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5542 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5543 | [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5544 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5545 | [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5546 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5547 | [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5548 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5549 | [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5550 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5551 | [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5552 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5553 | [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5554 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5555 | [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5556 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5557 | [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5558 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5559 | [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5560 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5561 | [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5562 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5563 | [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5564 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5565 | [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5566 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5567 | [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5568 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5569 | [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5570 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5571 | [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5572 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5573 | [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5574 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5575 | [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5576 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5577 | [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5578 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5579 | [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5580 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5581 | [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5582 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5583 | [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5584 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5585 | [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5586 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5587 | [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5588 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5589 | [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5590 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5591 | [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5592 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5593 | [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5594 | write_mhpmcounterh }, |
Atish Patra | 621f35b | 2022-06-20 16:15:56 -0700 | [diff] [blame] | 5595 | [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh, |
Weiwei Li | 108c4f2 | 2022-07-18 21:09:52 +0800 | [diff] [blame] | 5596 | write_mhpmcounterh }, |
Atish Patra | f055156 | 2022-08-24 15:17:01 -0700 | [diff] [blame] | 5597 | [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf, |
| 5598 | .min_priv_ver = PRIV_VERSION_1_12_0 }, |
Atish Patra | 1466448 | 2022-08-24 15:16:57 -0700 | [diff] [blame] | 5599 | |
Michael Clark | c7b9517 | 2019-01-04 23:23:55 +0000 | [diff] [blame] | 5600 | #endif /* !CONFIG_USER_ONLY */ |
| 5601 | }; |