Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1 | DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) |
| 2 | DEF_HELPER_2(raise_exception, noreturn, env, i32) |
Pavel Dovgaluk | 9c708c7 | 2015-07-10 12:57:08 +0300 | [diff] [blame] | 3 | DEF_HELPER_1(raise_exception_debug, noreturn, env) |
ths | 7dd9e55 | 2008-06-08 07:42:23 +0000 | [diff] [blame] | 4 | |
Leon Alrae | 3b3c169 | 2015-06-19 11:08:43 +0100 | [diff] [blame] | 5 | DEF_HELPER_1(do_semihosting, void, env) |
| 6 | |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 7 | #ifdef TARGET_MIPS64 |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 8 | DEF_HELPER_4(sdl, void, env, tl, tl, int) |
| 9 | DEF_HELPER_4(sdr, void, env, tl, tl, int) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 10 | #endif |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 11 | DEF_HELPER_4(swl, void, env, tl, tl, int) |
| 12 | DEF_HELPER_4(swr, void, env, tl, tl, int) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 13 | |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 14 | #ifndef CONFIG_USER_ONLY |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 15 | DEF_HELPER_3(ll, tl, env, tl, int) |
| 16 | DEF_HELPER_4(sc, tl, env, tl, tl, int) |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 17 | #ifdef TARGET_MIPS64 |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 18 | DEF_HELPER_3(lld, tl, env, tl, int) |
| 19 | DEF_HELPER_4(scd, tl, env, tl, tl, int) |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 20 | #endif |
| 21 | #endif |
| 22 | |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 23 | DEF_HELPER_FLAGS_1(clo, TCG_CALL_NO_RWG_SE, tl, tl) |
| 24 | DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, tl, tl) |
ths | 7dd9e55 | 2008-06-08 07:42:23 +0000 | [diff] [blame] | 25 | #ifdef TARGET_MIPS64 |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 26 | DEF_HELPER_FLAGS_1(dclo, TCG_CALL_NO_RWG_SE, tl, tl) |
| 27 | DEF_HELPER_FLAGS_1(dclz, TCG_CALL_NO_RWG_SE, tl, tl) |
ths | 7dd9e55 | 2008-06-08 07:42:23 +0000 | [diff] [blame] | 28 | #endif |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 29 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 30 | DEF_HELPER_3(muls, tl, env, tl, tl) |
| 31 | DEF_HELPER_3(mulsu, tl, env, tl, tl) |
| 32 | DEF_HELPER_3(macc, tl, env, tl, tl) |
| 33 | DEF_HELPER_3(maccu, tl, env, tl, tl) |
| 34 | DEF_HELPER_3(msac, tl, env, tl, tl) |
| 35 | DEF_HELPER_3(msacu, tl, env, tl, tl) |
| 36 | DEF_HELPER_3(mulhi, tl, env, tl, tl) |
| 37 | DEF_HELPER_3(mulhiu, tl, env, tl, tl) |
| 38 | DEF_HELPER_3(mulshi, tl, env, tl, tl) |
| 39 | DEF_HELPER_3(mulshiu, tl, env, tl, tl) |
| 40 | DEF_HELPER_3(macchi, tl, env, tl, tl) |
| 41 | DEF_HELPER_3(macchiu, tl, env, tl, tl) |
| 42 | DEF_HELPER_3(msachi, tl, env, tl, tl) |
| 43 | DEF_HELPER_3(msachiu, tl, env, tl, tl) |
ths | 92af06d | 2008-06-20 14:35:19 +0000 | [diff] [blame] | 44 | |
Yongbok Kim | 15eacb9 | 2014-06-27 08:49:05 +0100 | [diff] [blame] | 45 | DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) |
| 46 | #ifdef TARGET_MIPS64 |
| 47 | DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) |
| 48 | #endif |
| 49 | |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 50 | #ifndef CONFIG_USER_ONLY |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 51 | /* CP0 helpers */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 52 | DEF_HELPER_1(mfc0_mvpcontrol, tl, env) |
| 53 | DEF_HELPER_1(mfc0_mvpconf0, tl, env) |
| 54 | DEF_HELPER_1(mfc0_mvpconf1, tl, env) |
| 55 | DEF_HELPER_1(mftc0_vpecontrol, tl, env) |
| 56 | DEF_HELPER_1(mftc0_vpeconf0, tl, env) |
| 57 | DEF_HELPER_1(mfc0_random, tl, env) |
| 58 | DEF_HELPER_1(mfc0_tcstatus, tl, env) |
| 59 | DEF_HELPER_1(mftc0_tcstatus, tl, env) |
| 60 | DEF_HELPER_1(mfc0_tcbind, tl, env) |
| 61 | DEF_HELPER_1(mftc0_tcbind, tl, env) |
| 62 | DEF_HELPER_1(mfc0_tcrestart, tl, env) |
| 63 | DEF_HELPER_1(mftc0_tcrestart, tl, env) |
| 64 | DEF_HELPER_1(mfc0_tchalt, tl, env) |
| 65 | DEF_HELPER_1(mftc0_tchalt, tl, env) |
| 66 | DEF_HELPER_1(mfc0_tccontext, tl, env) |
| 67 | DEF_HELPER_1(mftc0_tccontext, tl, env) |
| 68 | DEF_HELPER_1(mfc0_tcschedule, tl, env) |
| 69 | DEF_HELPER_1(mftc0_tcschedule, tl, env) |
| 70 | DEF_HELPER_1(mfc0_tcschefback, tl, env) |
| 71 | DEF_HELPER_1(mftc0_tcschefback, tl, env) |
| 72 | DEF_HELPER_1(mfc0_count, tl, env) |
| 73 | DEF_HELPER_1(mftc0_entryhi, tl, env) |
| 74 | DEF_HELPER_1(mftc0_status, tl, env) |
| 75 | DEF_HELPER_1(mftc0_cause, tl, env) |
| 76 | DEF_HELPER_1(mftc0_epc, tl, env) |
| 77 | DEF_HELPER_1(mftc0_ebase, tl, env) |
| 78 | DEF_HELPER_2(mftc0_configx, tl, env, tl) |
| 79 | DEF_HELPER_1(mfc0_lladdr, tl, env) |
Yongbok Kim | f6d4dd8 | 2016-03-24 15:49:58 +0000 | [diff] [blame] | 80 | DEF_HELPER_1(mfc0_maar, tl, env) |
| 81 | DEF_HELPER_1(mfhc0_maar, tl, env) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 82 | DEF_HELPER_2(mfc0_watchlo, tl, env, i32) |
| 83 | DEF_HELPER_2(mfc0_watchhi, tl, env, i32) |
| 84 | DEF_HELPER_1(mfc0_debug, tl, env) |
| 85 | DEF_HELPER_1(mftc0_debug, tl, env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 86 | #ifdef TARGET_MIPS64 |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 87 | DEF_HELPER_1(dmfc0_tcrestart, tl, env) |
| 88 | DEF_HELPER_1(dmfc0_tchalt, tl, env) |
| 89 | DEF_HELPER_1(dmfc0_tccontext, tl, env) |
| 90 | DEF_HELPER_1(dmfc0_tcschedule, tl, env) |
| 91 | DEF_HELPER_1(dmfc0_tcschefback, tl, env) |
| 92 | DEF_HELPER_1(dmfc0_lladdr, tl, env) |
Yongbok Kim | f6d4dd8 | 2016-03-24 15:49:58 +0000 | [diff] [blame] | 93 | DEF_HELPER_1(dmfc0_maar, tl, env) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 94 | DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 95 | #endif /* TARGET_MIPS64 */ |
| 96 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 97 | DEF_HELPER_2(mtc0_index, void, env, tl) |
| 98 | DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) |
| 99 | DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) |
| 100 | DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) |
| 101 | DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) |
| 102 | DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) |
| 103 | DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) |
| 104 | DEF_HELPER_2(mtc0_yqmask, void, env, tl) |
| 105 | DEF_HELPER_2(mtc0_vpeopt, void, env, tl) |
| 106 | DEF_HELPER_2(mtc0_entrylo0, void, env, tl) |
| 107 | DEF_HELPER_2(mtc0_tcstatus, void, env, tl) |
| 108 | DEF_HELPER_2(mttc0_tcstatus, void, env, tl) |
| 109 | DEF_HELPER_2(mtc0_tcbind, void, env, tl) |
| 110 | DEF_HELPER_2(mttc0_tcbind, void, env, tl) |
| 111 | DEF_HELPER_2(mtc0_tcrestart, void, env, tl) |
| 112 | DEF_HELPER_2(mttc0_tcrestart, void, env, tl) |
| 113 | DEF_HELPER_2(mtc0_tchalt, void, env, tl) |
| 114 | DEF_HELPER_2(mttc0_tchalt, void, env, tl) |
| 115 | DEF_HELPER_2(mtc0_tccontext, void, env, tl) |
| 116 | DEF_HELPER_2(mttc0_tccontext, void, env, tl) |
| 117 | DEF_HELPER_2(mtc0_tcschedule, void, env, tl) |
| 118 | DEF_HELPER_2(mttc0_tcschedule, void, env, tl) |
| 119 | DEF_HELPER_2(mtc0_tcschefback, void, env, tl) |
| 120 | DEF_HELPER_2(mttc0_tcschefback, void, env, tl) |
| 121 | DEF_HELPER_2(mtc0_entrylo1, void, env, tl) |
| 122 | DEF_HELPER_2(mtc0_context, void, env, tl) |
| 123 | DEF_HELPER_2(mtc0_pagemask, void, env, tl) |
| 124 | DEF_HELPER_2(mtc0_pagegrain, void, env, tl) |
| 125 | DEF_HELPER_2(mtc0_wired, void, env, tl) |
| 126 | DEF_HELPER_2(mtc0_srsconf0, void, env, tl) |
| 127 | DEF_HELPER_2(mtc0_srsconf1, void, env, tl) |
| 128 | DEF_HELPER_2(mtc0_srsconf2, void, env, tl) |
| 129 | DEF_HELPER_2(mtc0_srsconf3, void, env, tl) |
| 130 | DEF_HELPER_2(mtc0_srsconf4, void, env, tl) |
| 131 | DEF_HELPER_2(mtc0_hwrena, void, env, tl) |
| 132 | DEF_HELPER_2(mtc0_count, void, env, tl) |
| 133 | DEF_HELPER_2(mtc0_entryhi, void, env, tl) |
| 134 | DEF_HELPER_2(mttc0_entryhi, void, env, tl) |
| 135 | DEF_HELPER_2(mtc0_compare, void, env, tl) |
| 136 | DEF_HELPER_2(mtc0_status, void, env, tl) |
| 137 | DEF_HELPER_2(mttc0_status, void, env, tl) |
| 138 | DEF_HELPER_2(mtc0_intctl, void, env, tl) |
| 139 | DEF_HELPER_2(mtc0_srsctl, void, env, tl) |
| 140 | DEF_HELPER_2(mtc0_cause, void, env, tl) |
| 141 | DEF_HELPER_2(mttc0_cause, void, env, tl) |
| 142 | DEF_HELPER_2(mtc0_ebase, void, env, tl) |
| 143 | DEF_HELPER_2(mttc0_ebase, void, env, tl) |
| 144 | DEF_HELPER_2(mtc0_config0, void, env, tl) |
| 145 | DEF_HELPER_2(mtc0_config2, void, env, tl) |
Maciej W. Rozycki | 90f12d7 | 2014-11-18 03:59:07 +0000 | [diff] [blame] | 146 | DEF_HELPER_2(mtc0_config3, void, env, tl) |
Petar Jovanovic | b4160af | 2014-01-24 13:45:05 +0100 | [diff] [blame] | 147 | DEF_HELPER_2(mtc0_config4, void, env, tl) |
Petar Jovanovic | b4dd99a | 2014-01-17 19:25:57 +0100 | [diff] [blame] | 148 | DEF_HELPER_2(mtc0_config5, void, env, tl) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 149 | DEF_HELPER_2(mtc0_lladdr, void, env, tl) |
Yongbok Kim | f6d4dd8 | 2016-03-24 15:49:58 +0000 | [diff] [blame] | 150 | DEF_HELPER_2(mtc0_maar, void, env, tl) |
| 151 | DEF_HELPER_2(mthc0_maar, void, env, tl) |
| 152 | DEF_HELPER_2(mtc0_maari, void, env, tl) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 153 | DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) |
| 154 | DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) |
| 155 | DEF_HELPER_2(mtc0_xcontext, void, env, tl) |
| 156 | DEF_HELPER_2(mtc0_framemask, void, env, tl) |
| 157 | DEF_HELPER_2(mtc0_debug, void, env, tl) |
| 158 | DEF_HELPER_2(mttc0_debug, void, env, tl) |
| 159 | DEF_HELPER_2(mtc0_performance0, void, env, tl) |
Leon Alrae | 0d74a22 | 2016-03-25 13:49:36 +0000 | [diff] [blame] | 160 | DEF_HELPER_2(mtc0_errctl, void, env, tl) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 161 | DEF_HELPER_2(mtc0_taglo, void, env, tl) |
| 162 | DEF_HELPER_2(mtc0_datalo, void, env, tl) |
| 163 | DEF_HELPER_2(mtc0_taghi, void, env, tl) |
| 164 | DEF_HELPER_2(mtc0_datahi, void, env, tl) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 165 | |
Leon Alrae | 7207c7f | 2014-07-07 11:23:59 +0100 | [diff] [blame] | 166 | #if defined(TARGET_MIPS64) |
| 167 | DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) |
| 168 | DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) |
| 169 | #endif |
| 170 | |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 171 | /* MIPS MT functions */ |
Richard Henderson | f5daeec | 2013-09-14 15:38:30 -0700 | [diff] [blame] | 172 | DEF_HELPER_2(mftgpr, tl, env, i32) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 173 | DEF_HELPER_2(mftlo, tl, env, i32) |
| 174 | DEF_HELPER_2(mfthi, tl, env, i32) |
| 175 | DEF_HELPER_2(mftacx, tl, env, i32) |
| 176 | DEF_HELPER_1(mftdsp, tl, env) |
| 177 | DEF_HELPER_3(mttgpr, void, env, tl, i32) |
| 178 | DEF_HELPER_3(mttlo, void, env, tl, i32) |
| 179 | DEF_HELPER_3(mtthi, void, env, tl, i32) |
| 180 | DEF_HELPER_3(mttacx, void, env, tl, i32) |
| 181 | DEF_HELPER_2(mttdsp, void, env, tl) |
Nathan Froyd | 9ed5726 | 2010-10-29 07:48:46 -0700 | [diff] [blame] | 182 | DEF_HELPER_0(dmt, tl) |
| 183 | DEF_HELPER_0(emt, tl) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 184 | DEF_HELPER_1(dvpe, tl, env) |
| 185 | DEF_HELPER_1(evpe, tl, env) |
Yongbok Kim | 01bc435 | 2016-02-03 12:31:07 +0000 | [diff] [blame] | 186 | |
| 187 | /* R6 Multi-threading */ |
| 188 | DEF_HELPER_1(dvp, tl, env) |
| 189 | DEF_HELPER_1(evp, tl, env) |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 190 | #endif /* !CONFIG_USER_ONLY */ |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 191 | |
| 192 | /* microMIPS functions */ |
Richard Henderson | f5daeec | 2013-09-14 15:38:30 -0700 | [diff] [blame] | 193 | DEF_HELPER_4(lwm, void, env, tl, tl, i32) |
| 194 | DEF_HELPER_4(swm, void, env, tl, tl, i32) |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 195 | #ifdef TARGET_MIPS64 |
Richard Henderson | f5daeec | 2013-09-14 15:38:30 -0700 | [diff] [blame] | 196 | DEF_HELPER_4(ldm, void, env, tl, tl, i32) |
| 197 | DEF_HELPER_4(sdm, void, env, tl, tl, i32) |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 198 | #endif |
| 199 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 200 | DEF_HELPER_2(fork, void, tl, tl) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 201 | DEF_HELPER_2(yield, tl, env, tl) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 202 | |
| 203 | /* CP1 functions */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 204 | DEF_HELPER_2(cfc1, tl, env, i32) |
Petar Jovanovic | 736d120 | 2014-01-22 18:35:32 +0100 | [diff] [blame] | 205 | DEF_HELPER_4(ctc1, void, env, tl, i32, i32) |
ths | 5d0fc90 | 2008-06-11 15:27:54 +0000 | [diff] [blame] | 206 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 207 | DEF_HELPER_2(float_cvtd_s, i64, env, i32) |
| 208 | DEF_HELPER_2(float_cvtd_w, i64, env, i32) |
| 209 | DEF_HELPER_2(float_cvtd_l, i64, env, i64) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 210 | DEF_HELPER_2(float_cvtps_pw, i64, env, i64) |
| 211 | DEF_HELPER_2(float_cvtpw_ps, i64, env, i64) |
| 212 | DEF_HELPER_2(float_cvts_d, i32, env, i64) |
| 213 | DEF_HELPER_2(float_cvts_w, i32, env, i32) |
| 214 | DEF_HELPER_2(float_cvts_l, i32, env, i64) |
| 215 | DEF_HELPER_2(float_cvts_pl, i32, env, i32) |
| 216 | DEF_HELPER_2(float_cvts_pu, i32, env, i32) |
ths | 5d0fc90 | 2008-06-11 15:27:54 +0000 | [diff] [blame] | 217 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 218 | DEF_HELPER_3(float_addr_ps, i64, env, i64, i64) |
| 219 | DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64) |
ths | 5d0fc90 | 2008-06-11 15:27:54 +0000 | [diff] [blame] | 220 | |
Aleksandar Markovic | af39bc8 | 2016-06-10 11:57:28 +0200 | [diff] [blame] | 221 | DEF_HELPER_FLAGS_2(float_class_s, TCG_CALL_NO_RWG_SE, i32, env, i32) |
| 222 | DEF_HELPER_FLAGS_2(float_class_d, TCG_CALL_NO_RWG_SE, i64, env, i64) |
Leon Alrae | e7f16ab | 2014-06-27 08:49:07 +0100 | [diff] [blame] | 223 | |
| 224 | #define FOP_PROTO(op) \ |
| 225 | DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \ |
| 226 | DEF_HELPER_4(float_ ## op ## _d, i64, env, i64, i64, i64) |
| 227 | FOP_PROTO(maddf) |
| 228 | FOP_PROTO(msubf) |
| 229 | #undef FOP_PROTO |
| 230 | |
| 231 | #define FOP_PROTO(op) \ |
| 232 | DEF_HELPER_3(float_ ## op ## _s, i32, env, i32, i32) \ |
| 233 | DEF_HELPER_3(float_ ## op ## _d, i64, env, i64, i64) |
| 234 | FOP_PROTO(max) |
| 235 | FOP_PROTO(maxa) |
| 236 | FOP_PROTO(min) |
| 237 | FOP_PROTO(mina) |
| 238 | #undef FOP_PROTO |
| 239 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 240 | #define FOP_PROTO(op) \ |
Aleksandar Markovic | 8755208 | 2016-06-10 11:57:35 +0200 | [diff] [blame] | 241 | DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \ |
| 242 | DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \ |
| 243 | DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \ |
| 244 | DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64) |
| 245 | FOP_PROTO(cvt) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 246 | FOP_PROTO(round) |
| 247 | FOP_PROTO(trunc) |
| 248 | FOP_PROTO(ceil) |
| 249 | FOP_PROTO(floor) |
Aleksandar Markovic | 8755208 | 2016-06-10 11:57:35 +0200 | [diff] [blame] | 250 | FOP_PROTO(cvt_2008) |
| 251 | FOP_PROTO(round_2008) |
| 252 | FOP_PROTO(trunc_2008) |
| 253 | FOP_PROTO(ceil_2008) |
| 254 | FOP_PROTO(floor_2008) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 255 | #undef FOP_PROTO |
| 256 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 257 | #define FOP_PROTO(op) \ |
| 258 | DEF_HELPER_2(float_ ## op ## _s, i32, env, i32) \ |
| 259 | DEF_HELPER_2(float_ ## op ## _d, i64, env, i64) |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 260 | FOP_PROTO(sqrt) |
ths | 5d0fc90 | 2008-06-11 15:27:54 +0000 | [diff] [blame] | 261 | FOP_PROTO(rsqrt) |
| 262 | FOP_PROTO(recip) |
Leon Alrae | e7f16ab | 2014-06-27 08:49:07 +0100 | [diff] [blame] | 263 | FOP_PROTO(rint) |
ths | 5d0fc90 | 2008-06-11 15:27:54 +0000 | [diff] [blame] | 264 | #undef FOP_PROTO |
| 265 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 266 | #define FOP_PROTO(op) \ |
| 267 | DEF_HELPER_1(float_ ## op ## _s, i32, i32) \ |
| 268 | DEF_HELPER_1(float_ ## op ## _d, i64, i64) \ |
| 269 | DEF_HELPER_1(float_ ## op ## _ps, i64, i64) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 270 | FOP_PROTO(abs) |
| 271 | FOP_PROTO(chs) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 272 | #undef FOP_PROTO |
| 273 | |
| 274 | #define FOP_PROTO(op) \ |
| 275 | DEF_HELPER_2(float_ ## op ## _s, i32, env, i32) \ |
| 276 | DEF_HELPER_2(float_ ## op ## _d, i64, env, i64) \ |
| 277 | DEF_HELPER_2(float_ ## op ## _ps, i64, env, i64) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 278 | FOP_PROTO(recip1) |
| 279 | FOP_PROTO(rsqrt1) |
| 280 | #undef FOP_PROTO |
| 281 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 282 | #define FOP_PROTO(op) \ |
| 283 | DEF_HELPER_3(float_ ## op ## _s, i32, env, i32, i32) \ |
| 284 | DEF_HELPER_3(float_ ## op ## _d, i64, env, i64, i64) \ |
| 285 | DEF_HELPER_3(float_ ## op ## _ps, i64, env, i64, i64) |
ths | 5d0fc90 | 2008-06-11 15:27:54 +0000 | [diff] [blame] | 286 | FOP_PROTO(add) |
| 287 | FOP_PROTO(sub) |
| 288 | FOP_PROTO(mul) |
| 289 | FOP_PROTO(div) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 290 | FOP_PROTO(recip2) |
| 291 | FOP_PROTO(rsqrt2) |
| 292 | #undef FOP_PROTO |
| 293 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 294 | #define FOP_PROTO(op) \ |
| 295 | DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \ |
| 296 | DEF_HELPER_4(float_ ## op ## _d, i64, env, i64, i64, i64) \ |
| 297 | DEF_HELPER_4(float_ ## op ## _ps, i64, env, i64, i64, i64) |
Aurelien Jarno | b3d6cd4 | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 298 | FOP_PROTO(madd) |
| 299 | FOP_PROTO(msub) |
| 300 | FOP_PROTO(nmadd) |
| 301 | FOP_PROTO(nmsub) |
ths | 5d0fc90 | 2008-06-11 15:27:54 +0000 | [diff] [blame] | 302 | #undef FOP_PROTO |
| 303 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 304 | #define FOP_PROTO(op) \ |
| 305 | DEF_HELPER_4(cmp_d_ ## op, void, env, i64, i64, int) \ |
| 306 | DEF_HELPER_4(cmpabs_d_ ## op, void, env, i64, i64, int) \ |
| 307 | DEF_HELPER_4(cmp_s_ ## op, void, env, i32, i32, int) \ |
| 308 | DEF_HELPER_4(cmpabs_s_ ## op, void, env, i32, i32, int) \ |
| 309 | DEF_HELPER_4(cmp_ps_ ## op, void, env, i64, i64, int) \ |
| 310 | DEF_HELPER_4(cmpabs_ps_ ## op, void, env, i64, i64, int) |
ths | 5d0fc90 | 2008-06-11 15:27:54 +0000 | [diff] [blame] | 311 | FOP_PROTO(f) |
| 312 | FOP_PROTO(un) |
| 313 | FOP_PROTO(eq) |
| 314 | FOP_PROTO(ueq) |
| 315 | FOP_PROTO(olt) |
| 316 | FOP_PROTO(ult) |
| 317 | FOP_PROTO(ole) |
| 318 | FOP_PROTO(ule) |
| 319 | FOP_PROTO(sf) |
| 320 | FOP_PROTO(ngle) |
| 321 | FOP_PROTO(seq) |
| 322 | FOP_PROTO(ngl) |
| 323 | FOP_PROTO(lt) |
| 324 | FOP_PROTO(nge) |
| 325 | FOP_PROTO(le) |
| 326 | FOP_PROTO(ngt) |
| 327 | #undef FOP_PROTO |
ths | 08ba796 | 2008-06-12 03:15:13 +0000 | [diff] [blame] | 328 | |
Yongbok Kim | 3f49388 | 2014-06-27 08:49:07 +0100 | [diff] [blame] | 329 | #define FOP_PROTO(op) \ |
| 330 | DEF_HELPER_3(r6_cmp_d_ ## op, i64, env, i64, i64) \ |
| 331 | DEF_HELPER_3(r6_cmp_s_ ## op, i32, env, i32, i32) |
| 332 | FOP_PROTO(af) |
| 333 | FOP_PROTO(un) |
| 334 | FOP_PROTO(eq) |
| 335 | FOP_PROTO(ueq) |
| 336 | FOP_PROTO(lt) |
| 337 | FOP_PROTO(ult) |
| 338 | FOP_PROTO(le) |
| 339 | FOP_PROTO(ule) |
| 340 | FOP_PROTO(saf) |
| 341 | FOP_PROTO(sun) |
| 342 | FOP_PROTO(seq) |
| 343 | FOP_PROTO(sueq) |
| 344 | FOP_PROTO(slt) |
| 345 | FOP_PROTO(sult) |
| 346 | FOP_PROTO(sle) |
| 347 | FOP_PROTO(sule) |
| 348 | FOP_PROTO(or) |
| 349 | FOP_PROTO(une) |
| 350 | FOP_PROTO(ne) |
| 351 | FOP_PROTO(sor) |
| 352 | FOP_PROTO(sune) |
| 353 | FOP_PROTO(sne) |
| 354 | #undef FOP_PROTO |
| 355 | |
ths | 08ba796 | 2008-06-12 03:15:13 +0000 | [diff] [blame] | 356 | /* Special functions */ |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 357 | #ifndef CONFIG_USER_ONLY |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 358 | DEF_HELPER_1(tlbwi, void, env) |
| 359 | DEF_HELPER_1(tlbwr, void, env) |
| 360 | DEF_HELPER_1(tlbp, void, env) |
| 361 | DEF_HELPER_1(tlbr, void, env) |
Leon Alrae | 9456c2f | 2014-07-07 11:24:00 +0100 | [diff] [blame] | 362 | DEF_HELPER_1(tlbinv, void, env) |
| 363 | DEF_HELPER_1(tlbinvf, void, env) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 364 | DEF_HELPER_1(di, tl, env) |
| 365 | DEF_HELPER_1(ei, tl, env) |
| 366 | DEF_HELPER_1(eret, void, env) |
Leon Alrae | ce9782f | 2015-06-04 17:00:31 +0100 | [diff] [blame] | 367 | DEF_HELPER_1(eretnc, void, env) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 368 | DEF_HELPER_1(deret, void, env) |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 369 | #endif /* !CONFIG_USER_ONLY */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 370 | DEF_HELPER_1(rdhwr_cpunum, tl, env) |
| 371 | DEF_HELPER_1(rdhwr_synci_step, tl, env) |
| 372 | DEF_HELPER_1(rdhwr_cc, tl, env) |
| 373 | DEF_HELPER_1(rdhwr_ccres, tl, env) |
Yongbok Kim | b00c721 | 2015-10-29 15:18:39 +0000 | [diff] [blame] | 374 | DEF_HELPER_1(rdhwr_performance, tl, env) |
| 375 | DEF_HELPER_1(rdhwr_xnp, tl, env) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 376 | DEF_HELPER_2(pmon, void, env, int) |
| 377 | DEF_HELPER_1(wait, void, env) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 378 | |
Richard Henderson | bd277fa | 2012-09-18 21:59:44 -0700 | [diff] [blame] | 379 | /* Loongson multimedia functions. */ |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 380 | DEF_HELPER_FLAGS_2(paddsh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 381 | DEF_HELPER_FLAGS_2(paddush, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 382 | DEF_HELPER_FLAGS_2(paddh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 383 | DEF_HELPER_FLAGS_2(paddw, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 384 | DEF_HELPER_FLAGS_2(paddsb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 385 | DEF_HELPER_FLAGS_2(paddusb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 386 | DEF_HELPER_FLAGS_2(paddb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
Richard Henderson | bd277fa | 2012-09-18 21:59:44 -0700 | [diff] [blame] | 387 | |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 388 | DEF_HELPER_FLAGS_2(psubsh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 389 | DEF_HELPER_FLAGS_2(psubush, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 390 | DEF_HELPER_FLAGS_2(psubh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 391 | DEF_HELPER_FLAGS_2(psubw, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 392 | DEF_HELPER_FLAGS_2(psubsb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 393 | DEF_HELPER_FLAGS_2(psubusb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 394 | DEF_HELPER_FLAGS_2(psubb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
Richard Henderson | bd277fa | 2012-09-18 21:59:44 -0700 | [diff] [blame] | 395 | |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 396 | DEF_HELPER_FLAGS_2(pshufh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 397 | DEF_HELPER_FLAGS_2(packsswh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 398 | DEF_HELPER_FLAGS_2(packsshb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 399 | DEF_HELPER_FLAGS_2(packushb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
Richard Henderson | bd277fa | 2012-09-18 21:59:44 -0700 | [diff] [blame] | 400 | |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 401 | DEF_HELPER_FLAGS_2(punpcklhw, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 402 | DEF_HELPER_FLAGS_2(punpckhhw, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 403 | DEF_HELPER_FLAGS_2(punpcklbh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 404 | DEF_HELPER_FLAGS_2(punpckhbh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 405 | DEF_HELPER_FLAGS_2(punpcklwd, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 406 | DEF_HELPER_FLAGS_2(punpckhwd, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
Richard Henderson | bd277fa | 2012-09-18 21:59:44 -0700 | [diff] [blame] | 407 | |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 408 | DEF_HELPER_FLAGS_2(pavgh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 409 | DEF_HELPER_FLAGS_2(pavgb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 410 | DEF_HELPER_FLAGS_2(pmaxsh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 411 | DEF_HELPER_FLAGS_2(pminsh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 412 | DEF_HELPER_FLAGS_2(pmaxub, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 413 | DEF_HELPER_FLAGS_2(pminub, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
Richard Henderson | bd277fa | 2012-09-18 21:59:44 -0700 | [diff] [blame] | 414 | |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 415 | DEF_HELPER_FLAGS_2(pcmpeqw, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 416 | DEF_HELPER_FLAGS_2(pcmpgtw, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 417 | DEF_HELPER_FLAGS_2(pcmpeqh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 418 | DEF_HELPER_FLAGS_2(pcmpgth, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 419 | DEF_HELPER_FLAGS_2(pcmpeqb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 420 | DEF_HELPER_FLAGS_2(pcmpgtb, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
Richard Henderson | bd277fa | 2012-09-18 21:59:44 -0700 | [diff] [blame] | 421 | |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 422 | DEF_HELPER_FLAGS_2(psllw, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 423 | DEF_HELPER_FLAGS_2(psllh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 424 | DEF_HELPER_FLAGS_2(psrlw, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 425 | DEF_HELPER_FLAGS_2(psrlh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 426 | DEF_HELPER_FLAGS_2(psraw, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 427 | DEF_HELPER_FLAGS_2(psrah, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
Richard Henderson | bd277fa | 2012-09-18 21:59:44 -0700 | [diff] [blame] | 428 | |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 429 | DEF_HELPER_FLAGS_2(pmullh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 430 | DEF_HELPER_FLAGS_2(pmulhh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 431 | DEF_HELPER_FLAGS_2(pmulhuh, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 432 | DEF_HELPER_FLAGS_2(pmaddhw, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
Richard Henderson | bd277fa | 2012-09-18 21:59:44 -0700 | [diff] [blame] | 433 | |
Aurelien Jarno | 95bf787 | 2012-10-09 21:53:09 +0200 | [diff] [blame] | 434 | DEF_HELPER_FLAGS_2(pasubub, TCG_CALL_NO_RWG_SE, i64, i64, i64) |
| 435 | DEF_HELPER_FLAGS_1(biadd, TCG_CALL_NO_RWG_SE, i64, i64) |
| 436 | DEF_HELPER_FLAGS_1(pmovmskb, TCG_CALL_NO_RWG_SE, i64, i64) |
Richard Henderson | bd277fa | 2012-09-18 21:59:44 -0700 | [diff] [blame] | 437 | |
Jia Liu | 461c08d | 2012-10-24 22:17:06 +0800 | [diff] [blame] | 438 | /*** MIPS DSP ***/ |
| 439 | /* DSP Arithmetic Sub-class insns */ |
| 440 | DEF_HELPER_FLAGS_3(addq_ph, 0, tl, tl, tl, env) |
| 441 | DEF_HELPER_FLAGS_3(addq_s_ph, 0, tl, tl, tl, env) |
| 442 | #if defined(TARGET_MIPS64) |
| 443 | DEF_HELPER_FLAGS_3(addq_qh, 0, tl, tl, tl, env) |
| 444 | DEF_HELPER_FLAGS_3(addq_s_qh, 0, tl, tl, tl, env) |
| 445 | #endif |
| 446 | DEF_HELPER_FLAGS_3(addq_s_w, 0, tl, tl, tl, env) |
| 447 | #if defined(TARGET_MIPS64) |
| 448 | DEF_HELPER_FLAGS_3(addq_pw, 0, tl, tl, tl, env) |
| 449 | DEF_HELPER_FLAGS_3(addq_s_pw, 0, tl, tl, tl, env) |
| 450 | #endif |
| 451 | DEF_HELPER_FLAGS_3(addu_qb, 0, tl, tl, tl, env) |
| 452 | DEF_HELPER_FLAGS_3(addu_s_qb, 0, tl, tl, tl, env) |
| 453 | DEF_HELPER_FLAGS_2(adduh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 454 | DEF_HELPER_FLAGS_2(adduh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 455 | DEF_HELPER_FLAGS_3(addu_ph, 0, tl, tl, tl, env) |
| 456 | DEF_HELPER_FLAGS_3(addu_s_ph, 0, tl, tl, tl, env) |
| 457 | DEF_HELPER_FLAGS_2(addqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 458 | DEF_HELPER_FLAGS_2(addqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 459 | DEF_HELPER_FLAGS_2(addqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 460 | DEF_HELPER_FLAGS_2(addqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 461 | #if defined(TARGET_MIPS64) |
| 462 | DEF_HELPER_FLAGS_3(addu_ob, 0, tl, tl, tl, env) |
| 463 | DEF_HELPER_FLAGS_3(addu_s_ob, 0, tl, tl, tl, env) |
| 464 | DEF_HELPER_FLAGS_2(adduh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 465 | DEF_HELPER_FLAGS_2(adduh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 466 | DEF_HELPER_FLAGS_3(addu_qh, 0, tl, tl, tl, env) |
| 467 | DEF_HELPER_FLAGS_3(addu_s_qh, 0, tl, tl, tl, env) |
| 468 | #endif |
| 469 | DEF_HELPER_FLAGS_3(subq_ph, 0, tl, tl, tl, env) |
| 470 | DEF_HELPER_FLAGS_3(subq_s_ph, 0, tl, tl, tl, env) |
| 471 | #if defined(TARGET_MIPS64) |
| 472 | DEF_HELPER_FLAGS_3(subq_qh, 0, tl, tl, tl, env) |
| 473 | DEF_HELPER_FLAGS_3(subq_s_qh, 0, tl, tl, tl, env) |
| 474 | #endif |
| 475 | DEF_HELPER_FLAGS_3(subq_s_w, 0, tl, tl, tl, env) |
| 476 | #if defined(TARGET_MIPS64) |
| 477 | DEF_HELPER_FLAGS_3(subq_pw, 0, tl, tl, tl, env) |
| 478 | DEF_HELPER_FLAGS_3(subq_s_pw, 0, tl, tl, tl, env) |
| 479 | #endif |
| 480 | DEF_HELPER_FLAGS_3(subu_qb, 0, tl, tl, tl, env) |
| 481 | DEF_HELPER_FLAGS_3(subu_s_qb, 0, tl, tl, tl, env) |
| 482 | DEF_HELPER_FLAGS_2(subuh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 483 | DEF_HELPER_FLAGS_2(subuh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 484 | DEF_HELPER_FLAGS_3(subu_ph, 0, tl, tl, tl, env) |
| 485 | DEF_HELPER_FLAGS_3(subu_s_ph, 0, tl, tl, tl, env) |
| 486 | DEF_HELPER_FLAGS_2(subqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 487 | DEF_HELPER_FLAGS_2(subqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 488 | DEF_HELPER_FLAGS_2(subqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 489 | DEF_HELPER_FLAGS_2(subqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 490 | #if defined(TARGET_MIPS64) |
| 491 | DEF_HELPER_FLAGS_3(subu_ob, 0, tl, tl, tl, env) |
| 492 | DEF_HELPER_FLAGS_3(subu_s_ob, 0, tl, tl, tl, env) |
| 493 | DEF_HELPER_FLAGS_2(subuh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 494 | DEF_HELPER_FLAGS_2(subuh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 495 | DEF_HELPER_FLAGS_3(subu_qh, 0, tl, tl, tl, env) |
| 496 | DEF_HELPER_FLAGS_3(subu_s_qh, 0, tl, tl, tl, env) |
| 497 | #endif |
| 498 | DEF_HELPER_FLAGS_3(addsc, 0, tl, tl, tl, env) |
| 499 | DEF_HELPER_FLAGS_3(addwc, 0, tl, tl, tl, env) |
| 500 | DEF_HELPER_FLAGS_2(modsub, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 501 | DEF_HELPER_FLAGS_1(raddu_w_qb, TCG_CALL_NO_RWG_SE, tl, tl) |
| 502 | #if defined(TARGET_MIPS64) |
| 503 | DEF_HELPER_FLAGS_1(raddu_l_ob, TCG_CALL_NO_RWG_SE, tl, tl) |
| 504 | #endif |
| 505 | DEF_HELPER_FLAGS_2(absq_s_qb, 0, tl, tl, env) |
| 506 | DEF_HELPER_FLAGS_2(absq_s_ph, 0, tl, tl, env) |
| 507 | DEF_HELPER_FLAGS_2(absq_s_w, 0, tl, tl, env) |
| 508 | #if defined(TARGET_MIPS64) |
| 509 | DEF_HELPER_FLAGS_2(absq_s_ob, 0, tl, tl, env) |
| 510 | DEF_HELPER_FLAGS_2(absq_s_qh, 0, tl, tl, env) |
| 511 | DEF_HELPER_FLAGS_2(absq_s_pw, 0, tl, tl, env) |
| 512 | #endif |
| 513 | DEF_HELPER_FLAGS_2(precr_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 514 | DEF_HELPER_FLAGS_2(precrq_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 515 | DEF_HELPER_FLAGS_3(precr_sra_ph_w, TCG_CALL_NO_RWG_SE, |
| 516 | tl, i32, tl, tl) |
| 517 | DEF_HELPER_FLAGS_3(precr_sra_r_ph_w, TCG_CALL_NO_RWG_SE, |
| 518 | tl, i32, tl, tl) |
| 519 | DEF_HELPER_FLAGS_2(precrq_ph_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 520 | DEF_HELPER_FLAGS_3(precrq_rs_ph_w, 0, tl, tl, tl, env) |
| 521 | #if defined(TARGET_MIPS64) |
| 522 | DEF_HELPER_FLAGS_2(precr_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 523 | DEF_HELPER_FLAGS_3(precr_sra_qh_pw, |
| 524 | TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) |
| 525 | DEF_HELPER_FLAGS_3(precr_sra_r_qh_pw, |
| 526 | TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) |
| 527 | DEF_HELPER_FLAGS_2(precrq_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 528 | DEF_HELPER_FLAGS_2(precrq_qh_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 529 | DEF_HELPER_FLAGS_3(precrq_rs_qh_pw, |
| 530 | TCG_CALL_NO_RWG_SE, tl, tl, tl, env) |
| 531 | DEF_HELPER_FLAGS_2(precrq_pw_l, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 532 | #endif |
| 533 | DEF_HELPER_FLAGS_3(precrqu_s_qb_ph, 0, tl, tl, tl, env) |
| 534 | #if defined(TARGET_MIPS64) |
| 535 | DEF_HELPER_FLAGS_3(precrqu_s_ob_qh, |
| 536 | TCG_CALL_NO_RWG_SE, tl, tl, tl, env) |
| 537 | |
| 538 | DEF_HELPER_FLAGS_1(preceq_pw_qhl, TCG_CALL_NO_RWG_SE, tl, tl) |
| 539 | DEF_HELPER_FLAGS_1(preceq_pw_qhr, TCG_CALL_NO_RWG_SE, tl, tl) |
| 540 | DEF_HELPER_FLAGS_1(preceq_pw_qhla, TCG_CALL_NO_RWG_SE, tl, tl) |
| 541 | DEF_HELPER_FLAGS_1(preceq_pw_qhra, TCG_CALL_NO_RWG_SE, tl, tl) |
| 542 | #endif |
| 543 | DEF_HELPER_FLAGS_1(precequ_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl) |
| 544 | DEF_HELPER_FLAGS_1(precequ_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl) |
| 545 | DEF_HELPER_FLAGS_1(precequ_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl) |
| 546 | DEF_HELPER_FLAGS_1(precequ_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl) |
| 547 | #if defined(TARGET_MIPS64) |
| 548 | DEF_HELPER_FLAGS_1(precequ_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl) |
| 549 | DEF_HELPER_FLAGS_1(precequ_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl) |
| 550 | DEF_HELPER_FLAGS_1(precequ_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl) |
| 551 | DEF_HELPER_FLAGS_1(precequ_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl) |
| 552 | #endif |
| 553 | DEF_HELPER_FLAGS_1(preceu_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl) |
| 554 | DEF_HELPER_FLAGS_1(preceu_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl) |
| 555 | DEF_HELPER_FLAGS_1(preceu_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl) |
| 556 | DEF_HELPER_FLAGS_1(preceu_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl) |
| 557 | #if defined(TARGET_MIPS64) |
| 558 | DEF_HELPER_FLAGS_1(preceu_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl) |
| 559 | DEF_HELPER_FLAGS_1(preceu_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl) |
| 560 | DEF_HELPER_FLAGS_1(preceu_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl) |
| 561 | DEF_HELPER_FLAGS_1(preceu_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl) |
| 562 | #endif |
| 563 | |
Jia Liu | 77c5fa8 | 2012-10-24 22:17:07 +0800 | [diff] [blame] | 564 | /* DSP GPR-Based Shift Sub-class insns */ |
| 565 | DEF_HELPER_FLAGS_3(shll_qb, 0, tl, tl, tl, env) |
| 566 | #if defined(TARGET_MIPS64) |
| 567 | DEF_HELPER_FLAGS_3(shll_ob, 0, tl, tl, tl, env) |
| 568 | #endif |
| 569 | DEF_HELPER_FLAGS_3(shll_ph, 0, tl, tl, tl, env) |
| 570 | DEF_HELPER_FLAGS_3(shll_s_ph, 0, tl, tl, tl, env) |
| 571 | #if defined(TARGET_MIPS64) |
| 572 | DEF_HELPER_FLAGS_3(shll_qh, 0, tl, tl, tl, env) |
| 573 | DEF_HELPER_FLAGS_3(shll_s_qh, 0, tl, tl, tl, env) |
| 574 | #endif |
| 575 | DEF_HELPER_FLAGS_3(shll_s_w, 0, tl, tl, tl, env) |
| 576 | #if defined(TARGET_MIPS64) |
| 577 | DEF_HELPER_FLAGS_3(shll_pw, 0, tl, tl, tl, env) |
| 578 | DEF_HELPER_FLAGS_3(shll_s_pw, 0, tl, tl, tl, env) |
| 579 | #endif |
| 580 | DEF_HELPER_FLAGS_2(shrl_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 581 | DEF_HELPER_FLAGS_2(shrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 582 | #if defined(TARGET_MIPS64) |
| 583 | DEF_HELPER_FLAGS_2(shrl_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 584 | DEF_HELPER_FLAGS_2(shrl_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 585 | #endif |
| 586 | DEF_HELPER_FLAGS_2(shra_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 587 | DEF_HELPER_FLAGS_2(shra_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 588 | #if defined(TARGET_MIPS64) |
| 589 | DEF_HELPER_FLAGS_2(shra_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 590 | DEF_HELPER_FLAGS_2(shra_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 591 | #endif |
| 592 | DEF_HELPER_FLAGS_2(shra_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 593 | DEF_HELPER_FLAGS_2(shra_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 594 | DEF_HELPER_FLAGS_2(shra_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 595 | #if defined(TARGET_MIPS64) |
| 596 | DEF_HELPER_FLAGS_2(shra_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 597 | DEF_HELPER_FLAGS_2(shra_r_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 598 | DEF_HELPER_FLAGS_2(shra_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 599 | DEF_HELPER_FLAGS_2(shra_r_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 600 | #endif |
| 601 | |
Jia Liu | a22260a | 2012-10-24 22:17:08 +0800 | [diff] [blame] | 602 | /* DSP Multiply Sub-class insns */ |
| 603 | DEF_HELPER_FLAGS_3(muleu_s_ph_qbl, 0, tl, tl, tl, env) |
| 604 | DEF_HELPER_FLAGS_3(muleu_s_ph_qbr, 0, tl, tl, tl, env) |
| 605 | #if defined(TARGET_MIPS64) |
| 606 | DEF_HELPER_FLAGS_3(muleu_s_qh_obl, 0, tl, tl, tl, env) |
| 607 | DEF_HELPER_FLAGS_3(muleu_s_qh_obr, 0, tl, tl, tl, env) |
| 608 | #endif |
| 609 | DEF_HELPER_FLAGS_3(mulq_rs_ph, 0, tl, tl, tl, env) |
| 610 | #if defined(TARGET_MIPS64) |
| 611 | DEF_HELPER_FLAGS_3(mulq_rs_qh, 0, tl, tl, tl, env) |
| 612 | #endif |
| 613 | DEF_HELPER_FLAGS_3(muleq_s_w_phl, 0, tl, tl, tl, env) |
| 614 | DEF_HELPER_FLAGS_3(muleq_s_w_phr, 0, tl, tl, tl, env) |
| 615 | #if defined(TARGET_MIPS64) |
| 616 | DEF_HELPER_FLAGS_3(muleq_s_pw_qhl, 0, tl, tl, tl, env) |
| 617 | DEF_HELPER_FLAGS_3(muleq_s_pw_qhr, 0, tl, tl, tl, env) |
| 618 | #endif |
| 619 | DEF_HELPER_FLAGS_4(dpau_h_qbl, 0, void, i32, tl, tl, env) |
| 620 | DEF_HELPER_FLAGS_4(dpau_h_qbr, 0, void, i32, tl, tl, env) |
| 621 | #if defined(TARGET_MIPS64) |
| 622 | DEF_HELPER_FLAGS_4(dpau_h_obl, 0, void, tl, tl, i32, env) |
| 623 | DEF_HELPER_FLAGS_4(dpau_h_obr, 0, void, tl, tl, i32, env) |
| 624 | #endif |
| 625 | DEF_HELPER_FLAGS_4(dpsu_h_qbl, 0, void, i32, tl, tl, env) |
| 626 | DEF_HELPER_FLAGS_4(dpsu_h_qbr, 0, void, i32, tl, tl, env) |
| 627 | #if defined(TARGET_MIPS64) |
| 628 | DEF_HELPER_FLAGS_4(dpsu_h_obl, 0, void, tl, tl, i32, env) |
| 629 | DEF_HELPER_FLAGS_4(dpsu_h_obr, 0, void, tl, tl, i32, env) |
| 630 | #endif |
| 631 | DEF_HELPER_FLAGS_4(dpa_w_ph, 0, void, i32, tl, tl, env) |
| 632 | #if defined(TARGET_MIPS64) |
| 633 | DEF_HELPER_FLAGS_4(dpa_w_qh, 0, void, tl, tl, i32, env) |
| 634 | #endif |
| 635 | DEF_HELPER_FLAGS_4(dpax_w_ph, 0, void, i32, tl, tl, env) |
| 636 | DEF_HELPER_FLAGS_4(dpaq_s_w_ph, 0, void, i32, tl, tl, env) |
| 637 | #if defined(TARGET_MIPS64) |
| 638 | DEF_HELPER_FLAGS_4(dpaq_s_w_qh, 0, void, tl, tl, i32, env) |
| 639 | #endif |
| 640 | DEF_HELPER_FLAGS_4(dpaqx_s_w_ph, 0, void, i32, tl, tl, env) |
| 641 | DEF_HELPER_FLAGS_4(dpaqx_sa_w_ph, 0, void, i32, tl, tl, env) |
| 642 | DEF_HELPER_FLAGS_4(dps_w_ph, 0, void, i32, tl, tl, env) |
| 643 | #if defined(TARGET_MIPS64) |
| 644 | DEF_HELPER_FLAGS_4(dps_w_qh, 0, void, tl, tl, i32, env) |
| 645 | #endif |
| 646 | DEF_HELPER_FLAGS_4(dpsx_w_ph, 0, void, i32, tl, tl, env) |
| 647 | DEF_HELPER_FLAGS_4(dpsq_s_w_ph, 0, void, i32, tl, tl, env) |
| 648 | #if defined(TARGET_MIPS64) |
| 649 | DEF_HELPER_FLAGS_4(dpsq_s_w_qh, 0, void, tl, tl, i32, env) |
| 650 | #endif |
| 651 | DEF_HELPER_FLAGS_4(dpsqx_s_w_ph, 0, void, i32, tl, tl, env) |
| 652 | DEF_HELPER_FLAGS_4(dpsqx_sa_w_ph, 0, void, i32, tl, tl, env) |
| 653 | DEF_HELPER_FLAGS_4(mulsaq_s_w_ph, 0, void, i32, tl, tl, env) |
| 654 | #if defined(TARGET_MIPS64) |
| 655 | DEF_HELPER_FLAGS_4(mulsaq_s_w_qh, 0, void, tl, tl, i32, env) |
| 656 | #endif |
| 657 | DEF_HELPER_FLAGS_4(dpaq_sa_l_w, 0, void, i32, tl, tl, env) |
| 658 | #if defined(TARGET_MIPS64) |
| 659 | DEF_HELPER_FLAGS_4(dpaq_sa_l_pw, 0, void, tl, tl, i32, env) |
| 660 | #endif |
| 661 | DEF_HELPER_FLAGS_4(dpsq_sa_l_w, 0, void, i32, tl, tl, env) |
| 662 | #if defined(TARGET_MIPS64) |
| 663 | DEF_HELPER_FLAGS_4(dpsq_sa_l_pw, 0, void, tl, tl, i32, env) |
| 664 | DEF_HELPER_FLAGS_4(mulsaq_s_l_pw, 0, void, tl, tl, i32, env) |
| 665 | #endif |
| 666 | DEF_HELPER_FLAGS_4(maq_s_w_phl, 0, void, i32, tl, tl, env) |
| 667 | DEF_HELPER_FLAGS_4(maq_s_w_phr, 0, void, i32, tl, tl, env) |
| 668 | DEF_HELPER_FLAGS_4(maq_sa_w_phl, 0, void, i32, tl, tl, env) |
| 669 | DEF_HELPER_FLAGS_4(maq_sa_w_phr, 0, void, i32, tl, tl, env) |
| 670 | DEF_HELPER_FLAGS_3(mul_ph, 0, tl, tl, tl, env) |
| 671 | DEF_HELPER_FLAGS_3(mul_s_ph, 0, tl, tl, tl, env) |
| 672 | DEF_HELPER_FLAGS_3(mulq_s_ph, 0, tl, tl, tl, env) |
| 673 | DEF_HELPER_FLAGS_3(mulq_s_w, 0, tl, tl, tl, env) |
| 674 | DEF_HELPER_FLAGS_3(mulq_rs_w, 0, tl, tl, tl, env) |
| 675 | DEF_HELPER_FLAGS_4(mulsa_w_ph, 0, void, i32, tl, tl, env) |
| 676 | #if defined(TARGET_MIPS64) |
| 677 | DEF_HELPER_FLAGS_4(maq_s_w_qhll, 0, void, tl, tl, i32, env) |
| 678 | DEF_HELPER_FLAGS_4(maq_s_w_qhlr, 0, void, tl, tl, i32, env) |
| 679 | DEF_HELPER_FLAGS_4(maq_s_w_qhrl, 0, void, tl, tl, i32, env) |
| 680 | DEF_HELPER_FLAGS_4(maq_s_w_qhrr, 0, void, tl, tl, i32, env) |
| 681 | DEF_HELPER_FLAGS_4(maq_sa_w_qhll, 0, void, tl, tl, i32, env) |
| 682 | DEF_HELPER_FLAGS_4(maq_sa_w_qhlr, 0, void, tl, tl, i32, env) |
| 683 | DEF_HELPER_FLAGS_4(maq_sa_w_qhrl, 0, void, tl, tl, i32, env) |
| 684 | DEF_HELPER_FLAGS_4(maq_sa_w_qhrr, 0, void, tl, tl, i32, env) |
| 685 | DEF_HELPER_FLAGS_4(maq_s_l_pwl, 0, void, tl, tl, i32, env) |
| 686 | DEF_HELPER_FLAGS_4(maq_s_l_pwr, 0, void, tl, tl, i32, env) |
| 687 | DEF_HELPER_FLAGS_4(dmadd, 0, void, tl, tl, i32, env) |
| 688 | DEF_HELPER_FLAGS_4(dmaddu, 0, void, tl, tl, i32, env) |
| 689 | DEF_HELPER_FLAGS_4(dmsub, 0, void, tl, tl, i32, env) |
| 690 | DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env) |
| 691 | #endif |
| 692 | |
Jia Liu | 1cb6686 | 2012-10-24 22:17:09 +0800 | [diff] [blame] | 693 | /* DSP Bit/Manipulation Sub-class insns */ |
| 694 | DEF_HELPER_FLAGS_1(bitrev, TCG_CALL_NO_RWG_SE, tl, tl) |
| 695 | DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl) |
| 696 | #if defined(TARGET_MIPS64) |
Richard Henderson | f5daeec | 2013-09-14 15:38:30 -0700 | [diff] [blame] | 697 | DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl) |
Jia Liu | 1cb6686 | 2012-10-24 22:17:09 +0800 | [diff] [blame] | 698 | #endif |
| 699 | |
Jia Liu | 2669056 | 2012-10-24 22:17:10 +0800 | [diff] [blame] | 700 | /* DSP Compare-Pick Sub-class insns */ |
| 701 | DEF_HELPER_FLAGS_3(cmpu_eq_qb, 0, void, tl, tl, env) |
| 702 | DEF_HELPER_FLAGS_3(cmpu_lt_qb, 0, void, tl, tl, env) |
| 703 | DEF_HELPER_FLAGS_3(cmpu_le_qb, 0, void, tl, tl, env) |
| 704 | DEF_HELPER_FLAGS_2(cmpgu_eq_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 705 | DEF_HELPER_FLAGS_2(cmpgu_lt_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 706 | DEF_HELPER_FLAGS_2(cmpgu_le_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 707 | DEF_HELPER_FLAGS_3(cmp_eq_ph, 0, void, tl, tl, env) |
| 708 | DEF_HELPER_FLAGS_3(cmp_lt_ph, 0, void, tl, tl, env) |
| 709 | DEF_HELPER_FLAGS_3(cmp_le_ph, 0, void, tl, tl, env) |
| 710 | #if defined(TARGET_MIPS64) |
| 711 | DEF_HELPER_FLAGS_3(cmpu_eq_ob, 0, void, tl, tl, env) |
| 712 | DEF_HELPER_FLAGS_3(cmpu_lt_ob, 0, void, tl, tl, env) |
| 713 | DEF_HELPER_FLAGS_3(cmpu_le_ob, 0, void, tl, tl, env) |
| 714 | DEF_HELPER_FLAGS_3(cmpgdu_eq_ob, 0, tl, tl, tl, env) |
| 715 | DEF_HELPER_FLAGS_3(cmpgdu_lt_ob, 0, tl, tl, tl, env) |
| 716 | DEF_HELPER_FLAGS_3(cmpgdu_le_ob, 0, tl, tl, tl, env) |
| 717 | DEF_HELPER_FLAGS_2(cmpgu_eq_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 718 | DEF_HELPER_FLAGS_2(cmpgu_lt_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 719 | DEF_HELPER_FLAGS_2(cmpgu_le_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 720 | DEF_HELPER_FLAGS_3(cmp_eq_qh, 0, void, tl, tl, env) |
| 721 | DEF_HELPER_FLAGS_3(cmp_lt_qh, 0, void, tl, tl, env) |
| 722 | DEF_HELPER_FLAGS_3(cmp_le_qh, 0, void, tl, tl, env) |
| 723 | DEF_HELPER_FLAGS_3(cmp_eq_pw, 0, void, tl, tl, env) |
| 724 | DEF_HELPER_FLAGS_3(cmp_lt_pw, 0, void, tl, tl, env) |
| 725 | DEF_HELPER_FLAGS_3(cmp_le_pw, 0, void, tl, tl, env) |
| 726 | #endif |
| 727 | DEF_HELPER_FLAGS_3(pick_qb, 0, tl, tl, tl, env) |
| 728 | DEF_HELPER_FLAGS_3(pick_ph, 0, tl, tl, tl, env) |
| 729 | #if defined(TARGET_MIPS64) |
| 730 | DEF_HELPER_FLAGS_3(pick_ob, 0, tl, tl, tl, env) |
| 731 | DEF_HELPER_FLAGS_3(pick_qh, 0, tl, tl, tl, env) |
| 732 | DEF_HELPER_FLAGS_3(pick_pw, 0, tl, tl, tl, env) |
| 733 | #endif |
Jia Liu | 2669056 | 2012-10-24 22:17:10 +0800 | [diff] [blame] | 734 | DEF_HELPER_FLAGS_2(packrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 735 | #if defined(TARGET_MIPS64) |
| 736 | DEF_HELPER_FLAGS_2(packrl_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) |
| 737 | #endif |
| 738 | |
Jia Liu | b53371e | 2012-10-24 22:17:11 +0800 | [diff] [blame] | 739 | /* DSP Accumulator and DSPControl Access Sub-class insns */ |
| 740 | DEF_HELPER_FLAGS_3(extr_w, 0, tl, tl, tl, env) |
| 741 | DEF_HELPER_FLAGS_3(extr_r_w, 0, tl, tl, tl, env) |
| 742 | DEF_HELPER_FLAGS_3(extr_rs_w, 0, tl, tl, tl, env) |
| 743 | #if defined(TARGET_MIPS64) |
| 744 | DEF_HELPER_FLAGS_3(dextr_w, 0, tl, tl, tl, env) |
| 745 | DEF_HELPER_FLAGS_3(dextr_r_w, 0, tl, tl, tl, env) |
| 746 | DEF_HELPER_FLAGS_3(dextr_rs_w, 0, tl, tl, tl, env) |
| 747 | DEF_HELPER_FLAGS_3(dextr_l, 0, tl, tl, tl, env) |
| 748 | DEF_HELPER_FLAGS_3(dextr_r_l, 0, tl, tl, tl, env) |
| 749 | DEF_HELPER_FLAGS_3(dextr_rs_l, 0, tl, tl, tl, env) |
| 750 | #endif |
| 751 | DEF_HELPER_FLAGS_3(extr_s_h, 0, tl, tl, tl, env) |
| 752 | #if defined(TARGET_MIPS64) |
| 753 | DEF_HELPER_FLAGS_3(dextr_s_h, 0, tl, tl, tl, env) |
| 754 | #endif |
| 755 | DEF_HELPER_FLAGS_3(extp, 0, tl, tl, tl, env) |
| 756 | DEF_HELPER_FLAGS_3(extpdp, 0, tl, tl, tl, env) |
| 757 | #if defined(TARGET_MIPS64) |
| 758 | DEF_HELPER_FLAGS_3(dextp, 0, tl, tl, tl, env) |
| 759 | DEF_HELPER_FLAGS_3(dextpdp, 0, tl, tl, tl, env) |
| 760 | #endif |
| 761 | DEF_HELPER_FLAGS_3(shilo, 0, void, tl, tl, env) |
| 762 | #if defined(TARGET_MIPS64) |
| 763 | DEF_HELPER_FLAGS_3(dshilo, 0, void, tl, tl, env) |
| 764 | #endif |
| 765 | DEF_HELPER_FLAGS_3(mthlip, 0, void, tl, tl, env) |
| 766 | #if defined(TARGET_MIPS64) |
| 767 | DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) |
| 768 | #endif |
| 769 | DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) |
| 770 | DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) |
Yongbok Kim | 4c78954 | 2014-11-01 05:28:43 +0000 | [diff] [blame] | 771 | |
| 772 | /* MIPS SIMD Architecture */ |
| 773 | DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) |
| 774 | DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) |
| 775 | DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) |
| 776 | DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32) |
| 777 | DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32) |
| 778 | DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32) |
| 779 | DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32) |
| 780 | DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32) |
Yongbok Kim | 80e7159 | 2014-11-01 05:28:44 +0000 | [diff] [blame] | 781 | |
| 782 | DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32) |
| 783 | DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32) |
| 784 | DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32) |
| 785 | DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32) |
| 786 | DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32) |
| 787 | DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32) |
| 788 | DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32) |
| 789 | DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32) |
| 790 | DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32) |
| 791 | DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32) |
| 792 | DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32) |
| 793 | DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32) |
Yongbok Kim | d4cf28d | 2014-11-01 05:28:45 +0000 | [diff] [blame] | 794 | |
| 795 | DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32) |
| 796 | DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32) |
| 797 | DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32) |
| 798 | DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32) |
| 799 | DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32) |
| 800 | DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32) |
| 801 | DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32) |
| 802 | DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32) |
| 803 | DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32) |
| 804 | DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32) |
| 805 | DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32) |
| 806 | DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32) |
Yongbok Kim | 28f99f0 | 2014-11-01 05:28:46 +0000 | [diff] [blame] | 807 | |
| 808 | DEF_HELPER_5(msa_sll_df, void, env, i32, i32, i32, i32) |
| 809 | DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32) |
| 810 | DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32) |
| 811 | DEF_HELPER_5(msa_bclr_df, void, env, i32, i32, i32, i32) |
| 812 | DEF_HELPER_5(msa_bset_df, void, env, i32, i32, i32, i32) |
| 813 | DEF_HELPER_5(msa_bneg_df, void, env, i32, i32, i32, i32) |
| 814 | DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) |
| 815 | DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) |
| 816 | DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32) |
| 817 | DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32) |
| 818 | DEF_HELPER_5(msa_max_s_df, void, env, i32, i32, i32, i32) |
| 819 | DEF_HELPER_5(msa_max_u_df, void, env, i32, i32, i32, i32) |
| 820 | DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32) |
| 821 | DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32) |
| 822 | DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32) |
| 823 | DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32) |
| 824 | DEF_HELPER_5(msa_ceq_df, void, env, i32, i32, i32, i32) |
| 825 | DEF_HELPER_5(msa_clt_s_df, void, env, i32, i32, i32, i32) |
| 826 | DEF_HELPER_5(msa_clt_u_df, void, env, i32, i32, i32, i32) |
| 827 | DEF_HELPER_5(msa_cle_s_df, void, env, i32, i32, i32, i32) |
| 828 | DEF_HELPER_5(msa_cle_u_df, void, env, i32, i32, i32, i32) |
| 829 | DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32) |
| 830 | DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) |
| 831 | DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) |
| 832 | DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32) |
| 833 | DEF_HELPER_5(msa_ave_s_df, void, env, i32, i32, i32, i32) |
| 834 | DEF_HELPER_5(msa_ave_u_df, void, env, i32, i32, i32, i32) |
| 835 | DEF_HELPER_5(msa_aver_s_df, void, env, i32, i32, i32, i32) |
| 836 | DEF_HELPER_5(msa_aver_u_df, void, env, i32, i32, i32, i32) |
| 837 | DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32) |
| 838 | DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32) |
| 839 | DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32) |
| 840 | DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32) |
| 841 | DEF_HELPER_5(msa_asub_s_df, void, env, i32, i32, i32, i32) |
| 842 | DEF_HELPER_5(msa_asub_u_df, void, env, i32, i32, i32, i32) |
| 843 | DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32) |
| 844 | DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32) |
| 845 | DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32) |
| 846 | DEF_HELPER_5(msa_div_s_df, void, env, i32, i32, i32, i32) |
| 847 | DEF_HELPER_5(msa_div_u_df, void, env, i32, i32, i32, i32) |
| 848 | DEF_HELPER_5(msa_mod_s_df, void, env, i32, i32, i32, i32) |
| 849 | DEF_HELPER_5(msa_mod_u_df, void, env, i32, i32, i32, i32) |
| 850 | DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32) |
| 851 | DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32) |
| 852 | DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32) |
| 853 | DEF_HELPER_5(msa_dpadd_u_df, void, env, i32, i32, i32, i32) |
| 854 | DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32, i32) |
| 855 | DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32) |
| 856 | DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32) |
| 857 | DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) |
| 858 | DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32) |
| 859 | DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32) |
| 860 | DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32) |
| 861 | DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32) |
| 862 | DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32) |
| 863 | DEF_HELPER_5(msa_ilvod_df, void, env, i32, i32, i32, i32) |
| 864 | DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) |
| 865 | DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32) |
| 866 | DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32) |
| 867 | DEF_HELPER_5(msa_hadd_s_df, void, env, i32, i32, i32, i32) |
| 868 | DEF_HELPER_5(msa_hadd_u_df, void, env, i32, i32, i32, i32) |
| 869 | DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32) |
| 870 | DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32) |
Yongbok Kim | 1e608ec | 2014-11-01 05:28:47 +0000 | [diff] [blame] | 871 | |
| 872 | DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) |
| 873 | DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) |
| 874 | DEF_HELPER_5(msa_copy_s_df, void, env, i32, i32, i32, i32) |
| 875 | DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32) |
| 876 | DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) |
| 877 | DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) |
| 878 | DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) |
| 879 | DEF_HELPER_2(msa_cfcmsa, tl, env, i32) |
| 880 | DEF_HELPER_3(msa_move_v, void, env, i32, i32) |
Yongbok Kim | 7d05b9c | 2014-11-01 05:28:48 +0000 | [diff] [blame] | 881 | |
| 882 | DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32) |
| 883 | DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32) |
| 884 | DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32) |
| 885 | DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32) |
| 886 | DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32) |
| 887 | DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32) |
| 888 | DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32) |
| 889 | DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32) |
| 890 | DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32) |
| 891 | DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32) |
| 892 | DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32) |
| 893 | DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32) |
| 894 | DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32) |
| 895 | DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32) |
| 896 | DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32) |
| 897 | DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32) |
| 898 | DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32) |
| 899 | DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32) |
| 900 | DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32) |
| 901 | DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32) |
| 902 | DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32) |
| 903 | DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32) |
| 904 | DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32) |
| 905 | DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32) |
| 906 | DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32) |
| 907 | DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32) |
| 908 | DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32) |
| 909 | DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32) |
| 910 | DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32) |
| 911 | DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32) |
| 912 | DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32) |
| 913 | DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32) |
| 914 | DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32) |
| 915 | DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32) |
| 916 | DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32) |
| 917 | DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32) |
| 918 | DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32) |
| 919 | DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32) |
| 920 | DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32) |
| 921 | DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32) |
| 922 | DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32) |
Yongbok Kim | cbe50b9 | 2014-11-01 05:28:49 +0000 | [diff] [blame] | 923 | |
| 924 | DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) |
| 925 | DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) |
| 926 | DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) |
| 927 | DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) |
| 928 | DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) |
| 929 | DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) |
| 930 | DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) |
| 931 | DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) |
| 932 | DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32) |
| 933 | DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32) |
| 934 | DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32) |
Yongbok Kim | 3bdeb68 | 2014-11-01 05:28:50 +0000 | [diff] [blame] | 935 | |
| 936 | DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) |
| 937 | DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) |
| 938 | DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32) |
| 939 | DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32) |
| 940 | DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32) |
| 941 | DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32) |
| 942 | DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32) |
| 943 | DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32) |
| 944 | DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32) |
| 945 | DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32) |
| 946 | DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32) |
| 947 | DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32) |
| 948 | DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32) |
| 949 | DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32) |
| 950 | DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32) |
| 951 | DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) |
Yongbok Kim | f768587 | 2014-11-01 05:28:51 +0000 | [diff] [blame] | 952 | |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 953 | #define MSALDST_PROTO(type) \ |
| 954 | DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ |
| 955 | DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) |
| 956 | MSALDST_PROTO(b) |
| 957 | MSALDST_PROTO(h) |
| 958 | MSALDST_PROTO(w) |
| 959 | MSALDST_PROTO(d) |
| 960 | #undef MSALDST_PROTO |
Leon Alrae | 0d74a22 | 2016-03-25 13:49:36 +0000 | [diff] [blame] | 961 | |
| 962 | DEF_HELPER_3(cache, void, env, tl, i32) |