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Blue Swirl5918fff2012-04-29 12:21:21 +00001/*
2 * x86 condition code helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "cpu.h"
Blue Swirl5918fff2012-04-29 12:21:21 +000021#include "helper.h"
22
23const uint8_t parity_table[256] = {
24 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
25 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
26 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
27 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
28 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
29 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
30 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
31 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
32 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
33 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
34 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
35 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
36 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
37 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
38 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
39 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
40 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
41 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
42 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
43 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
44 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
45 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
46 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
47 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
48 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
49 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
50 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
53 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
54 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
55 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
56};
57
58#define SHIFT 0
59#include "cc_helper_template.h"
60#undef SHIFT
61
62#define SHIFT 1
63#include "cc_helper_template.h"
64#undef SHIFT
65
66#define SHIFT 2
67#include "cc_helper_template.h"
68#undef SHIFT
69
70#ifdef TARGET_X86_64
71
72#define SHIFT 3
73#include "cc_helper_template.h"
74#undef SHIFT
75
76#endif
77
Richard Henderson988c3eb2013-01-23 16:03:16 -080078target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
79 target_ulong src2, int op)
Blue Swirl5918fff2012-04-29 12:21:21 +000080{
81 switch (op) {
82 default: /* should never happen */
83 return 0;
84
85 case CC_OP_EFLAGS:
Richard Henderson8601c0b2013-01-23 16:06:38 -080086 return src1;
Blue Swirl5918fff2012-04-29 12:21:21 +000087
88 case CC_OP_MULB:
Richard Henderson8601c0b2013-01-23 16:06:38 -080089 return compute_all_mulb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +000090 case CC_OP_MULW:
Richard Henderson8601c0b2013-01-23 16:06:38 -080091 return compute_all_mulw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +000092 case CC_OP_MULL:
Richard Henderson8601c0b2013-01-23 16:06:38 -080093 return compute_all_mull(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +000094
95 case CC_OP_ADDB:
Richard Henderson8601c0b2013-01-23 16:06:38 -080096 return compute_all_addb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +000097 case CC_OP_ADDW:
Richard Henderson8601c0b2013-01-23 16:06:38 -080098 return compute_all_addw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +000099 case CC_OP_ADDL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800100 return compute_all_addl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000101
102 case CC_OP_ADCB:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800103 return compute_all_adcb(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000104 case CC_OP_ADCW:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800105 return compute_all_adcw(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000106 case CC_OP_ADCL:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800107 return compute_all_adcl(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000108
109 case CC_OP_SUBB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800110 return compute_all_subb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000111 case CC_OP_SUBW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800112 return compute_all_subw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000113 case CC_OP_SUBL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800114 return compute_all_subl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000115
116 case CC_OP_SBBB:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800117 return compute_all_sbbb(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000118 case CC_OP_SBBW:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800119 return compute_all_sbbw(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000120 case CC_OP_SBBL:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800121 return compute_all_sbbl(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000122
123 case CC_OP_LOGICB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800124 return compute_all_logicb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000125 case CC_OP_LOGICW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800126 return compute_all_logicw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000127 case CC_OP_LOGICL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800128 return compute_all_logicl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000129
130 case CC_OP_INCB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800131 return compute_all_incb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000132 case CC_OP_INCW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800133 return compute_all_incw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000134 case CC_OP_INCL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800135 return compute_all_incl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000136
137 case CC_OP_DECB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800138 return compute_all_decb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000139 case CC_OP_DECW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800140 return compute_all_decw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000141 case CC_OP_DECL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800142 return compute_all_decl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000143
144 case CC_OP_SHLB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800145 return compute_all_shlb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000146 case CC_OP_SHLW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800147 return compute_all_shlw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000148 case CC_OP_SHLL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800149 return compute_all_shll(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000150
151 case CC_OP_SARB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800152 return compute_all_sarb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000153 case CC_OP_SARW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800154 return compute_all_sarw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000155 case CC_OP_SARL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800156 return compute_all_sarl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000157
Richard Hendersonbc4b43d2013-01-23 16:44:37 -0800158 case CC_OP_BMILGB:
159 return compute_all_bmilgb(dst, src1);
160 case CC_OP_BMILGW:
161 return compute_all_bmilgw(dst, src1);
162 case CC_OP_BMILGL:
163 return compute_all_bmilgl(dst, src1);
164
Blue Swirl5918fff2012-04-29 12:21:21 +0000165#ifdef TARGET_X86_64
166 case CC_OP_MULQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800167 return compute_all_mulq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000168 case CC_OP_ADDQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800169 return compute_all_addq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000170 case CC_OP_ADCQ:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800171 return compute_all_adcq(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000172 case CC_OP_SUBQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800173 return compute_all_subq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000174 case CC_OP_SBBQ:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800175 return compute_all_sbbq(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000176 case CC_OP_LOGICQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800177 return compute_all_logicq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000178 case CC_OP_INCQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800179 return compute_all_incq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000180 case CC_OP_DECQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800181 return compute_all_decq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000182 case CC_OP_SHLQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800183 return compute_all_shlq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000184 case CC_OP_SARQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800185 return compute_all_sarq(dst, src1);
Richard Hendersonbc4b43d2013-01-23 16:44:37 -0800186 case CC_OP_BMILGQ:
187 return compute_all_bmilgq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000188#endif
189 }
190}
191
Blue Swirlf0967a12012-04-29 12:45:34 +0000192uint32_t cpu_cc_compute_all(CPUX86State *env, int op)
Blue Swirl5918fff2012-04-29 12:21:21 +0000193{
Richard Henderson988c3eb2013-01-23 16:03:16 -0800194 return helper_cc_compute_all(CC_DST, CC_SRC, CC_SRC2, op);
Blue Swirl5918fff2012-04-29 12:21:21 +0000195}
196
Richard Henderson988c3eb2013-01-23 16:03:16 -0800197target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
198 target_ulong src2, int op)
Blue Swirl5918fff2012-04-29 12:21:21 +0000199{
200 switch (op) {
201 default: /* should never happen */
Richard Henderson8601c0b2013-01-23 16:06:38 -0800202 case CC_OP_LOGICB:
203 case CC_OP_LOGICW:
204 case CC_OP_LOGICL:
205 case CC_OP_LOGICQ:
Blue Swirl5918fff2012-04-29 12:21:21 +0000206 return 0;
207
208 case CC_OP_EFLAGS:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800209 case CC_OP_SARB:
210 case CC_OP_SARW:
211 case CC_OP_SARL:
212 case CC_OP_SARQ:
213 return src1 & 1;
Blue Swirl5918fff2012-04-29 12:21:21 +0000214
215 case CC_OP_INCB:
Blue Swirl5918fff2012-04-29 12:21:21 +0000216 case CC_OP_INCW:
Blue Swirl5918fff2012-04-29 12:21:21 +0000217 case CC_OP_INCL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800218 case CC_OP_INCQ:
Blue Swirl5918fff2012-04-29 12:21:21 +0000219 case CC_OP_DECB:
Blue Swirl5918fff2012-04-29 12:21:21 +0000220 case CC_OP_DECW:
Blue Swirl5918fff2012-04-29 12:21:21 +0000221 case CC_OP_DECL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800222 case CC_OP_DECQ:
223 return src1;
224
225 case CC_OP_MULB:
226 case CC_OP_MULW:
227 case CC_OP_MULL:
228 case CC_OP_MULQ:
229 return src1 != 0;
230
231 case CC_OP_ADDB:
232 return compute_c_addb(dst, src1);
233 case CC_OP_ADDW:
234 return compute_c_addw(dst, src1);
235 case CC_OP_ADDL:
236 return compute_c_addl(dst, src1);
237
238 case CC_OP_ADCB:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800239 return compute_c_adcb(dst, src1, src2);
Richard Henderson8601c0b2013-01-23 16:06:38 -0800240 case CC_OP_ADCW:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800241 return compute_c_adcw(dst, src1, src2);
Richard Henderson8601c0b2013-01-23 16:06:38 -0800242 case CC_OP_ADCL:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800243 return compute_c_adcl(dst, src1, src2);
Richard Henderson8601c0b2013-01-23 16:06:38 -0800244
245 case CC_OP_SUBB:
246 return compute_c_subb(dst, src1);
247 case CC_OP_SUBW:
248 return compute_c_subw(dst, src1);
249 case CC_OP_SUBL:
250 return compute_c_subl(dst, src1);
251
252 case CC_OP_SBBB:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800253 return compute_c_sbbb(dst, src1, src2);
Richard Henderson8601c0b2013-01-23 16:06:38 -0800254 case CC_OP_SBBW:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800255 return compute_c_sbbw(dst, src1, src2);
Richard Henderson8601c0b2013-01-23 16:06:38 -0800256 case CC_OP_SBBL:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800257 return compute_c_sbbl(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000258
259 case CC_OP_SHLB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800260 return compute_c_shlb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000261 case CC_OP_SHLW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800262 return compute_c_shlw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000263 case CC_OP_SHLL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800264 return compute_c_shll(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000265
Richard Hendersonbc4b43d2013-01-23 16:44:37 -0800266 case CC_OP_BMILGB:
267 return compute_c_bmilgb(dst, src1);
268 case CC_OP_BMILGW:
269 return compute_c_bmilgw(dst, src1);
270 case CC_OP_BMILGL:
271 return compute_c_bmilgl(dst, src1);
272
Blue Swirl5918fff2012-04-29 12:21:21 +0000273#ifdef TARGET_X86_64
Blue Swirl5918fff2012-04-29 12:21:21 +0000274 case CC_OP_ADDQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800275 return compute_c_addq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000276 case CC_OP_ADCQ:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800277 return compute_c_adcq(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000278 case CC_OP_SUBQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800279 return compute_c_subq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000280 case CC_OP_SBBQ:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800281 return compute_c_sbbq(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000282 case CC_OP_SHLQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800283 return compute_c_shlq(dst, src1);
Richard Hendersonbc4b43d2013-01-23 16:44:37 -0800284 case CC_OP_BMILGQ:
285 return compute_c_bmilgq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000286#endif
287 }
288}
289
Blue Swirlf0967a12012-04-29 12:45:34 +0000290void helper_write_eflags(CPUX86State *env, target_ulong t0,
291 uint32_t update_mask)
Blue Swirl5918fff2012-04-29 12:21:21 +0000292{
293 cpu_load_eflags(env, t0, update_mask);
294}
295
Blue Swirlf0967a12012-04-29 12:45:34 +0000296target_ulong helper_read_eflags(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000297{
298 uint32_t eflags;
299
Richard Hendersondb9f2592013-01-23 16:10:49 -0800300 eflags = cpu_cc_compute_all(env, CC_OP);
Blue Swirl5918fff2012-04-29 12:21:21 +0000301 eflags |= (DF & DF_MASK);
302 eflags |= env->eflags & ~(VM_MASK | RF_MASK);
303 return eflags;
304}
305
Blue Swirlf0967a12012-04-29 12:45:34 +0000306void helper_clts(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000307{
308 env->cr[0] &= ~CR0_TS_MASK;
309 env->hflags &= ~HF_TS_MASK;
310}
311
Blue Swirlf0967a12012-04-29 12:45:34 +0000312void helper_reset_rf(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000313{
314 env->eflags &= ~RF_MASK;
315}
316
Blue Swirlf0967a12012-04-29 12:45:34 +0000317void helper_cli(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000318{
319 env->eflags &= ~IF_MASK;
320}
321
Blue Swirlf0967a12012-04-29 12:45:34 +0000322void helper_sti(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000323{
324 env->eflags |= IF_MASK;
325}
326
H. Peter Anvina9321a42012-09-26 13:18:43 -0700327void helper_clac(CPUX86State *env)
328{
329 env->eflags &= ~AC_MASK;
330}
331
332void helper_stac(CPUX86State *env)
333{
334 env->eflags |= AC_MASK;
335}
336
Blue Swirl5918fff2012-04-29 12:21:21 +0000337#if 0
338/* vm86plus instructions */
Blue Swirlf0967a12012-04-29 12:45:34 +0000339void helper_cli_vm(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000340{
341 env->eflags &= ~VIF_MASK;
342}
343
Blue Swirlf0967a12012-04-29 12:45:34 +0000344void helper_sti_vm(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000345{
346 env->eflags |= VIF_MASK;
347 if (env->eflags & VIP_MASK) {
348 raise_exception(env, EXCP0D_GPF);
349 }
350}
351#endif
352
Blue Swirlf0967a12012-04-29 12:45:34 +0000353void helper_set_inhibit_irq(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000354{
355 env->hflags |= HF_INHIBIT_IRQ_MASK;
356}
357
Blue Swirlf0967a12012-04-29 12:45:34 +0000358void helper_reset_inhibit_irq(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000359{
360 env->hflags &= ~HF_INHIBIT_IRQ_MASK;
361}