Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Raspberry Pi (BCM2835) SD Host Controller |
| 3 | * |
| 4 | * Copyright (c) 2017 Antfield SAS |
| 5 | * |
| 6 | * Authors: |
| 7 | * Clement Deschamps <clement.deschamps@antfield.fr> |
| 8 | * Luc Michel <luc.michel@antfield.fr> |
| 9 | * |
| 10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 11 | * See the COPYING file in the top-level directory. |
| 12 | */ |
| 13 | |
| 14 | #include "qemu/osdep.h" |
| 15 | #include "qemu/log.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 16 | #include "qemu/module.h" |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 17 | #include "sysemu/blockdev.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 18 | #include "hw/irq.h" |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 19 | #include "hw/sd/bcm2835_sdhost.h" |
Markus Armbruster | d645427 | 2019-08-12 07:23:45 +0200 | [diff] [blame] | 20 | #include "migration/vmstate.h" |
Peter Maydell | b318f32 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 21 | #include "trace.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 22 | #include "qom/object.h" |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 23 | |
| 24 | #define TYPE_BCM2835_SDHOST_BUS "bcm2835-sdhost-bus" |
Eduardo Habkost | fa34a3c | 2020-08-31 17:07:36 -0400 | [diff] [blame] | 25 | /* This is reusing the SDBus typedef from SD_BUS */ |
| 26 | DECLARE_INSTANCE_CHECKER(SDBus, BCM2835_SDHOST_BUS, |
| 27 | TYPE_BCM2835_SDHOST_BUS) |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 28 | |
| 29 | #define SDCMD 0x00 /* Command to SD card - 16 R/W */ |
| 30 | #define SDARG 0x04 /* Argument to SD card - 32 R/W */ |
| 31 | #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ |
| 32 | #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ |
| 33 | #define SDRSP0 0x10 /* SD card rsp (31:0) - 32 R */ |
| 34 | #define SDRSP1 0x14 /* SD card rsp (63:32) - 32 R */ |
| 35 | #define SDRSP2 0x18 /* SD card rsp (95:64) - 32 R */ |
| 36 | #define SDRSP3 0x1c /* SD card rsp (127:96) - 32 R */ |
| 37 | #define SDHSTS 0x20 /* SD host status - 11 R */ |
| 38 | #define SDVDD 0x30 /* SD card power control - 1 R/W */ |
| 39 | #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ |
| 40 | #define SDHCFG 0x38 /* Host configuration - 2 R/W */ |
| 41 | #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ |
| 42 | #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ |
| 43 | #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ |
| 44 | |
| 45 | #define SDCMD_NEW_FLAG 0x8000 |
| 46 | #define SDCMD_FAIL_FLAG 0x4000 |
| 47 | #define SDCMD_BUSYWAIT 0x800 |
| 48 | #define SDCMD_NO_RESPONSE 0x400 |
| 49 | #define SDCMD_LONG_RESPONSE 0x200 |
| 50 | #define SDCMD_WRITE_CMD 0x80 |
| 51 | #define SDCMD_READ_CMD 0x40 |
| 52 | #define SDCMD_CMD_MASK 0x3f |
| 53 | |
| 54 | #define SDCDIV_MAX_CDIV 0x7ff |
| 55 | |
| 56 | #define SDHSTS_BUSY_IRPT 0x400 |
| 57 | #define SDHSTS_BLOCK_IRPT 0x200 |
| 58 | #define SDHSTS_SDIO_IRPT 0x100 |
| 59 | #define SDHSTS_REW_TIME_OUT 0x80 |
| 60 | #define SDHSTS_CMD_TIME_OUT 0x40 |
| 61 | #define SDHSTS_CRC16_ERROR 0x20 |
| 62 | #define SDHSTS_CRC7_ERROR 0x10 |
| 63 | #define SDHSTS_FIFO_ERROR 0x08 |
| 64 | /* Reserved */ |
| 65 | /* Reserved */ |
| 66 | #define SDHSTS_DATA_FLAG 0x01 |
| 67 | |
| 68 | #define SDHCFG_BUSY_IRPT_EN (1 << 10) |
| 69 | #define SDHCFG_BLOCK_IRPT_EN (1 << 8) |
| 70 | #define SDHCFG_SDIO_IRPT_EN (1 << 5) |
| 71 | #define SDHCFG_DATA_IRPT_EN (1 << 4) |
| 72 | #define SDHCFG_SLOW_CARD (1 << 3) |
| 73 | #define SDHCFG_WIDE_EXT_BUS (1 << 2) |
| 74 | #define SDHCFG_WIDE_INT_BUS (1 << 1) |
| 75 | #define SDHCFG_REL_CMD_LINE (1 << 0) |
| 76 | |
| 77 | #define SDEDM_FORCE_DATA_MODE (1 << 19) |
| 78 | #define SDEDM_CLOCK_PULSE (1 << 20) |
| 79 | #define SDEDM_BYPASS (1 << 21) |
| 80 | |
| 81 | #define SDEDM_WRITE_THRESHOLD_SHIFT 9 |
| 82 | #define SDEDM_READ_THRESHOLD_SHIFT 14 |
| 83 | #define SDEDM_THRESHOLD_MASK 0x1f |
| 84 | |
| 85 | #define SDEDM_FSM_MASK 0xf |
| 86 | #define SDEDM_FSM_IDENTMODE 0x0 |
| 87 | #define SDEDM_FSM_DATAMODE 0x1 |
| 88 | #define SDEDM_FSM_READDATA 0x2 |
| 89 | #define SDEDM_FSM_WRITEDATA 0x3 |
| 90 | #define SDEDM_FSM_READWAIT 0x4 |
| 91 | #define SDEDM_FSM_READCRC 0x5 |
| 92 | #define SDEDM_FSM_WRITECRC 0x6 |
| 93 | #define SDEDM_FSM_WRITEWAIT1 0x7 |
| 94 | #define SDEDM_FSM_POWERDOWN 0x8 |
| 95 | #define SDEDM_FSM_POWERUP 0x9 |
| 96 | #define SDEDM_FSM_WRITESTART1 0xa |
| 97 | #define SDEDM_FSM_WRITESTART2 0xb |
| 98 | #define SDEDM_FSM_GENPULSES 0xc |
| 99 | #define SDEDM_FSM_WRITEWAIT2 0xd |
| 100 | #define SDEDM_FSM_STARTPOWDOWN 0xf |
| 101 | |
| 102 | #define SDDATA_FIFO_WORDS 16 |
| 103 | |
| 104 | static void bcm2835_sdhost_update_irq(BCM2835SDHostState *s) |
| 105 | { |
| 106 | uint32_t irq = s->status & |
| 107 | (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | SDHSTS_SDIO_IRPT); |
Peter Maydell | b318f32 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 108 | trace_bcm2835_sdhost_update_irq(irq); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 109 | qemu_set_irq(s->irq, !!irq); |
| 110 | } |
| 111 | |
| 112 | static void bcm2835_sdhost_send_command(BCM2835SDHostState *s) |
| 113 | { |
| 114 | SDRequest request; |
| 115 | uint8_t rsp[16]; |
| 116 | int rlen; |
| 117 | |
| 118 | request.cmd = s->cmd & SDCMD_CMD_MASK; |
| 119 | request.arg = s->cmdarg; |
| 120 | |
| 121 | rlen = sdbus_do_command(&s->sdbus, &request, rsp); |
| 122 | if (rlen < 0) { |
| 123 | goto error; |
| 124 | } |
| 125 | if (!(s->cmd & SDCMD_NO_RESPONSE)) { |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 126 | if (rlen == 0 || (rlen == 4 && (s->cmd & SDCMD_LONG_RESPONSE))) { |
| 127 | goto error; |
| 128 | } |
| 129 | if (rlen != 4 && rlen != 16) { |
| 130 | goto error; |
| 131 | } |
| 132 | if (rlen == 4) { |
Philippe Mathieu-Daudé | b3141c0 | 2018-06-29 15:11:20 +0100 | [diff] [blame] | 133 | s->rsp[0] = ldl_be_p(&rsp[0]); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 134 | s->rsp[1] = s->rsp[2] = s->rsp[3] = 0; |
| 135 | } else { |
Philippe Mathieu-Daudé | b3141c0 | 2018-06-29 15:11:20 +0100 | [diff] [blame] | 136 | s->rsp[0] = ldl_be_p(&rsp[12]); |
| 137 | s->rsp[1] = ldl_be_p(&rsp[8]); |
| 138 | s->rsp[2] = ldl_be_p(&rsp[4]); |
| 139 | s->rsp[3] = ldl_be_p(&rsp[0]); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 140 | } |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 141 | } |
Peter Maydell | f3d9fe8 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 142 | /* We never really delay commands, so if this was a 'busywait' command |
| 143 | * then we've completed it now and can raise the interrupt. |
| 144 | */ |
| 145 | if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) { |
| 146 | s->status |= SDHSTS_BUSY_IRPT; |
| 147 | } |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 148 | return; |
| 149 | |
| 150 | error: |
| 151 | s->cmd |= SDCMD_FAIL_FLAG; |
| 152 | s->status |= SDHSTS_CMD_TIME_OUT; |
| 153 | } |
| 154 | |
| 155 | static void bcm2835_sdhost_fifo_push(BCM2835SDHostState *s, uint32_t value) |
| 156 | { |
| 157 | int n; |
| 158 | |
| 159 | if (s->fifo_len == BCM2835_SDHOST_FIFO_LEN) { |
| 160 | /* FIFO overflow */ |
| 161 | return; |
| 162 | } |
| 163 | n = (s->fifo_pos + s->fifo_len) & (BCM2835_SDHOST_FIFO_LEN - 1); |
| 164 | s->fifo_len++; |
| 165 | s->fifo[n] = value; |
| 166 | } |
| 167 | |
| 168 | static uint32_t bcm2835_sdhost_fifo_pop(BCM2835SDHostState *s) |
| 169 | { |
| 170 | uint32_t value; |
| 171 | |
| 172 | if (s->fifo_len == 0) { |
| 173 | /* FIFO underflow */ |
| 174 | return 0; |
| 175 | } |
| 176 | value = s->fifo[s->fifo_pos]; |
| 177 | s->fifo_len--; |
| 178 | s->fifo_pos = (s->fifo_pos + 1) & (BCM2835_SDHOST_FIFO_LEN - 1); |
| 179 | return value; |
| 180 | } |
| 181 | |
| 182 | static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s) |
| 183 | { |
| 184 | uint32_t value = 0; |
| 185 | int n; |
| 186 | int is_read; |
Guenter Roeck | 03a3177 | 2018-07-23 15:21:26 +0100 | [diff] [blame] | 187 | int is_write; |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 188 | |
| 189 | is_read = (s->cmd & SDCMD_READ_CMD) != 0; |
Guenter Roeck | 03a3177 | 2018-07-23 15:21:26 +0100 | [diff] [blame] | 190 | is_write = (s->cmd & SDCMD_WRITE_CMD) != 0; |
| 191 | if (s->datacnt != 0 && (is_write || sdbus_data_ready(&s->sdbus))) { |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 192 | if (is_read) { |
| 193 | n = 0; |
| 194 | while (s->datacnt && s->fifo_len < BCM2835_SDHOST_FIFO_LEN) { |
Philippe Mathieu-Daudé | 8467f62 | 2020-08-14 11:23:42 +0200 | [diff] [blame] | 195 | value |= (uint32_t)sdbus_read_byte(&s->sdbus) << (n * 8); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 196 | s->datacnt--; |
| 197 | n++; |
| 198 | if (n == 4) { |
| 199 | bcm2835_sdhost_fifo_push(s, value); |
Peter Maydell | f3d9fe8 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 200 | s->status |= SDHSTS_DATA_FLAG; |
| 201 | if (s->config & SDHCFG_DATA_IRPT_EN) { |
| 202 | s->status |= SDHSTS_SDIO_IRPT; |
| 203 | } |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 204 | n = 0; |
| 205 | value = 0; |
| 206 | } |
| 207 | } |
| 208 | if (n != 0) { |
| 209 | bcm2835_sdhost_fifo_push(s, value); |
Peter Maydell | f3d9fe8 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 210 | s->status |= SDHSTS_DATA_FLAG; |
Guenter Roeck | 03a3177 | 2018-07-23 15:21:26 +0100 | [diff] [blame] | 211 | if (s->config & SDHCFG_DATA_IRPT_EN) { |
| 212 | s->status |= SDHSTS_SDIO_IRPT; |
| 213 | } |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 214 | } |
Guenter Roeck | 03a3177 | 2018-07-23 15:21:26 +0100 | [diff] [blame] | 215 | } else if (is_write) { /* write */ |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 216 | n = 0; |
| 217 | while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) { |
| 218 | if (n == 0) { |
| 219 | value = bcm2835_sdhost_fifo_pop(s); |
Peter Maydell | f3d9fe8 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 220 | s->status |= SDHSTS_DATA_FLAG; |
| 221 | if (s->config & SDHCFG_DATA_IRPT_EN) { |
| 222 | s->status |= SDHSTS_SDIO_IRPT; |
| 223 | } |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 224 | n = 4; |
| 225 | } |
| 226 | n--; |
| 227 | s->datacnt--; |
Philippe Mathieu-Daudé | 3901714 | 2020-08-14 11:23:41 +0200 | [diff] [blame] | 228 | sdbus_write_byte(&s->sdbus, value & 0xff); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 229 | value >>= 8; |
| 230 | } |
| 231 | } |
Peter Maydell | f3d9fe8 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 232 | if (s->datacnt == 0) { |
| 233 | s->edm &= ~SDEDM_FSM_MASK; |
| 234 | s->edm |= SDEDM_FSM_DATAMODE; |
| 235 | trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm); |
Guenter Roeck | 03a3177 | 2018-07-23 15:21:26 +0100 | [diff] [blame] | 236 | } |
| 237 | if (is_write) { |
| 238 | /* set block interrupt at end of each block transfer */ |
| 239 | if (s->hbct && s->datacnt % s->hbct == 0 && |
Peter Maydell | f3d9fe8 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 240 | (s->config & SDHCFG_BLOCK_IRPT_EN)) { |
| 241 | s->status |= SDHSTS_BLOCK_IRPT; |
| 242 | } |
Guenter Roeck | 03a3177 | 2018-07-23 15:21:26 +0100 | [diff] [blame] | 243 | /* set data interrupt after each transfer */ |
| 244 | s->status |= SDHSTS_DATA_FLAG; |
| 245 | if (s->config & SDHCFG_DATA_IRPT_EN) { |
| 246 | s->status |= SDHSTS_SDIO_IRPT; |
| 247 | } |
Peter Maydell | f3d9fe8 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 248 | } |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 249 | } |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 250 | |
Peter Maydell | f3d9fe8 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 251 | bcm2835_sdhost_update_irq(s); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 252 | |
| 253 | s->edm &= ~(0x1f << 4); |
| 254 | s->edm |= ((s->fifo_len & 0x1f) << 4); |
Peter Maydell | b318f32 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 255 | trace_bcm2835_sdhost_edm_change("fifo run", s->edm); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset, |
| 259 | unsigned size) |
| 260 | { |
| 261 | BCM2835SDHostState *s = (BCM2835SDHostState *)opaque; |
| 262 | uint32_t res = 0; |
| 263 | |
| 264 | switch (offset) { |
| 265 | case SDCMD: |
| 266 | res = s->cmd; |
| 267 | break; |
| 268 | case SDHSTS: |
| 269 | res = s->status; |
| 270 | break; |
| 271 | case SDRSP0: |
| 272 | res = s->rsp[0]; |
| 273 | break; |
| 274 | case SDRSP1: |
| 275 | res = s->rsp[1]; |
| 276 | break; |
| 277 | case SDRSP2: |
| 278 | res = s->rsp[2]; |
| 279 | break; |
| 280 | case SDRSP3: |
| 281 | res = s->rsp[3]; |
| 282 | break; |
| 283 | case SDEDM: |
| 284 | res = s->edm; |
| 285 | break; |
| 286 | case SDVDD: |
| 287 | res = s->vdd; |
| 288 | break; |
| 289 | case SDDATA: |
| 290 | res = bcm2835_sdhost_fifo_pop(s); |
| 291 | bcm2835_sdhost_fifo_run(s); |
| 292 | break; |
| 293 | case SDHBCT: |
| 294 | res = s->hbct; |
| 295 | break; |
| 296 | case SDHBLC: |
| 297 | res = s->hblc; |
| 298 | break; |
| 299 | |
| 300 | default: |
| 301 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", |
| 302 | __func__, offset); |
| 303 | res = 0; |
| 304 | break; |
| 305 | } |
| 306 | |
Peter Maydell | b318f32 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 307 | trace_bcm2835_sdhost_read(offset, res, size); |
| 308 | |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 309 | return res; |
| 310 | } |
| 311 | |
| 312 | static void bcm2835_sdhost_write(void *opaque, hwaddr offset, |
| 313 | uint64_t value, unsigned size) |
| 314 | { |
| 315 | BCM2835SDHostState *s = (BCM2835SDHostState *)opaque; |
| 316 | |
Peter Maydell | b318f32 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 317 | trace_bcm2835_sdhost_write(offset, value, size); |
| 318 | |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 319 | switch (offset) { |
| 320 | case SDCMD: |
| 321 | s->cmd = value; |
| 322 | if (value & SDCMD_NEW_FLAG) { |
| 323 | bcm2835_sdhost_send_command(s); |
| 324 | bcm2835_sdhost_fifo_run(s); |
| 325 | s->cmd &= ~SDCMD_NEW_FLAG; |
| 326 | } |
| 327 | break; |
| 328 | case SDTOUT: |
| 329 | break; |
| 330 | case SDCDIV: |
| 331 | break; |
| 332 | case SDHSTS: |
| 333 | s->status &= ~value; |
| 334 | bcm2835_sdhost_update_irq(s); |
| 335 | break; |
| 336 | case SDARG: |
| 337 | s->cmdarg = value; |
| 338 | break; |
| 339 | case SDEDM: |
| 340 | if ((value & 0xf) == 0xf) { |
| 341 | /* power down */ |
| 342 | value &= ~0xf; |
| 343 | } |
| 344 | s->edm = value; |
Peter Maydell | b318f32 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 345 | trace_bcm2835_sdhost_edm_change("guest register write", s->edm); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 346 | break; |
| 347 | case SDHCFG: |
| 348 | s->config = value; |
| 349 | bcm2835_sdhost_fifo_run(s); |
| 350 | break; |
| 351 | case SDVDD: |
| 352 | s->vdd = value; |
| 353 | break; |
| 354 | case SDDATA: |
| 355 | bcm2835_sdhost_fifo_push(s, value); |
| 356 | bcm2835_sdhost_fifo_run(s); |
| 357 | break; |
| 358 | case SDHBCT: |
| 359 | s->hbct = value; |
| 360 | break; |
| 361 | case SDHBLC: |
| 362 | s->hblc = value; |
| 363 | s->datacnt = s->hblc * s->hbct; |
| 364 | bcm2835_sdhost_fifo_run(s); |
| 365 | break; |
| 366 | |
| 367 | default: |
| 368 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", |
| 369 | __func__, offset); |
| 370 | break; |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | static const MemoryRegionOps bcm2835_sdhost_ops = { |
| 375 | .read = bcm2835_sdhost_read, |
| 376 | .write = bcm2835_sdhost_write, |
| 377 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 378 | }; |
| 379 | |
| 380 | static const VMStateDescription vmstate_bcm2835_sdhost = { |
| 381 | .name = TYPE_BCM2835_SDHOST, |
| 382 | .version_id = 1, |
| 383 | .minimum_version_id = 1, |
Richard Henderson | 307119b | 2023-12-21 14:16:33 +1100 | [diff] [blame] | 384 | .fields = (const VMStateField[]) { |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 385 | VMSTATE_UINT32(cmd, BCM2835SDHostState), |
| 386 | VMSTATE_UINT32(cmdarg, BCM2835SDHostState), |
| 387 | VMSTATE_UINT32(status, BCM2835SDHostState), |
| 388 | VMSTATE_UINT32_ARRAY(rsp, BCM2835SDHostState, 4), |
| 389 | VMSTATE_UINT32(config, BCM2835SDHostState), |
| 390 | VMSTATE_UINT32(edm, BCM2835SDHostState), |
| 391 | VMSTATE_UINT32(vdd, BCM2835SDHostState), |
| 392 | VMSTATE_UINT32(hbct, BCM2835SDHostState), |
| 393 | VMSTATE_UINT32(hblc, BCM2835SDHostState), |
| 394 | VMSTATE_INT32(fifo_pos, BCM2835SDHostState), |
| 395 | VMSTATE_INT32(fifo_len, BCM2835SDHostState), |
| 396 | VMSTATE_UINT32_ARRAY(fifo, BCM2835SDHostState, BCM2835_SDHOST_FIFO_LEN), |
| 397 | VMSTATE_UINT32(datacnt, BCM2835SDHostState), |
| 398 | VMSTATE_END_OF_LIST() |
| 399 | } |
| 400 | }; |
| 401 | |
| 402 | static void bcm2835_sdhost_init(Object *obj) |
| 403 | { |
| 404 | BCM2835SDHostState *s = BCM2835_SDHOST(obj); |
| 405 | |
Peter Maydell | d637e1d | 2021-09-23 13:11:51 +0100 | [diff] [blame] | 406 | qbus_init(&s->sdbus, sizeof(s->sdbus), |
| 407 | TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus"); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 408 | |
| 409 | memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s, |
| 410 | TYPE_BCM2835_SDHOST, 0x1000); |
| 411 | sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); |
| 412 | sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); |
| 413 | } |
| 414 | |
| 415 | static void bcm2835_sdhost_reset(DeviceState *dev) |
| 416 | { |
| 417 | BCM2835SDHostState *s = BCM2835_SDHOST(dev); |
| 418 | |
| 419 | s->cmd = 0; |
| 420 | s->cmdarg = 0; |
| 421 | s->edm = 0x0000c60f; |
Peter Maydell | b318f32 | 2018-04-10 13:02:25 +0100 | [diff] [blame] | 422 | trace_bcm2835_sdhost_edm_change("device reset", s->edm); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 423 | s->config = 0; |
| 424 | s->hbct = 0; |
| 425 | s->hblc = 0; |
| 426 | s->datacnt = 0; |
| 427 | s->fifo_pos = 0; |
| 428 | s->fifo_len = 0; |
| 429 | } |
| 430 | |
| 431 | static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data) |
| 432 | { |
| 433 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 434 | |
Peter Maydell | e3d0814 | 2024-09-13 15:31:44 +0100 | [diff] [blame] | 435 | device_class_set_legacy_reset(dc, bcm2835_sdhost_reset); |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 436 | dc->vmsd = &vmstate_bcm2835_sdhost; |
| 437 | } |
| 438 | |
Philippe Mathieu-Daudé | 88d2198 | 2023-10-31 06:55:39 +0100 | [diff] [blame] | 439 | static const TypeInfo bcm2835_sdhost_types[] = { |
| 440 | { |
| 441 | .name = TYPE_BCM2835_SDHOST, |
| 442 | .parent = TYPE_SYS_BUS_DEVICE, |
| 443 | .instance_size = sizeof(BCM2835SDHostState), |
| 444 | .class_init = bcm2835_sdhost_class_init, |
| 445 | .instance_init = bcm2835_sdhost_init, |
| 446 | }, |
| 447 | { |
| 448 | .name = TYPE_BCM2835_SDHOST_BUS, |
| 449 | .parent = TYPE_SD_BUS, |
| 450 | .instance_size = sizeof(SDBus), |
| 451 | }, |
Clement Deschamps | 43ddc18 | 2017-02-28 12:08:19 +0000 | [diff] [blame] | 452 | }; |
| 453 | |
Philippe Mathieu-Daudé | 88d2198 | 2023-10-31 06:55:39 +0100 | [diff] [blame] | 454 | DEFINE_TYPES(bcm2835_sdhost_types) |