ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1 | /* |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 2 | * ARM PrimeCell Timer modules. |
| 3 | * |
| 4 | * Copyright (c) 2005-2006 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
Matthew Fernandez | 8e31bf3 | 2011-06-26 12:21:35 +1000 | [diff] [blame] | 7 | * This code is licensed under the GPL. |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
Peter Maydell | 8ef94f0 | 2016-01-26 18:17:05 +0000 | [diff] [blame] | 10 | #include "qemu/osdep.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 11 | #include "hw/sysbus.h" |
Markus Armbruster | d645427 | 2019-08-12 07:23:45 +0200 | [diff] [blame] | 12 | #include "migration/vmstate.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 13 | #include "qemu/timer.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 14 | #include "hw/irq.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 15 | #include "hw/ptimer.h" |
Markus Armbruster | a27bd6c | 2019-08-12 07:23:51 +0200 | [diff] [blame] | 16 | #include "hw/qdev-properties.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 17 | #include "qemu/module.h" |
Paolo Bonzini | 03dd024 | 2015-12-15 13:16:16 +0100 | [diff] [blame] | 18 | #include "qemu/log.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 19 | #include "qom/object.h" |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 20 | |
| 21 | /* Common timer implementation. */ |
| 22 | |
| 23 | #define TIMER_CTRL_ONESHOT (1 << 0) |
| 24 | #define TIMER_CTRL_32BIT (1 << 1) |
| 25 | #define TIMER_CTRL_DIV1 (0 << 2) |
| 26 | #define TIMER_CTRL_DIV16 (1 << 2) |
| 27 | #define TIMER_CTRL_DIV256 (2 << 2) |
| 28 | #define TIMER_CTRL_IE (1 << 5) |
| 29 | #define TIMER_CTRL_PERIODIC (1 << 6) |
| 30 | #define TIMER_CTRL_ENABLE (1 << 7) |
| 31 | |
| 32 | typedef struct { |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 33 | ptimer_state *timer; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 34 | uint32_t control; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 35 | uint32_t limit; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 36 | int freq; |
| 37 | int int_level; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 38 | qemu_irq irq; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 39 | } arm_timer_state; |
| 40 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 41 | /* Check all active timers, and schedule the next timer interrupt. */ |
| 42 | |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 43 | static void arm_timer_update(arm_timer_state *s) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 44 | { |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 45 | /* Update interrupts. */ |
| 46 | if (s->int_level && (s->control & TIMER_CTRL_IE)) { |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 47 | qemu_irq_raise(s->irq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 48 | } else { |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 49 | qemu_irq_lower(s->irq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 50 | } |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 51 | } |
| 52 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 53 | static uint32_t arm_timer_read(void *opaque, hwaddr offset) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 54 | { |
| 55 | arm_timer_state *s = (arm_timer_state *)opaque; |
| 56 | |
| 57 | switch (offset >> 2) { |
| 58 | case 0: /* TimerLoad */ |
| 59 | case 6: /* TimerBGLoad */ |
| 60 | return s->limit; |
| 61 | case 1: /* TimerValue */ |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 62 | return ptimer_get_count(s->timer); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 63 | case 2: /* TimerControl */ |
| 64 | return s->control; |
| 65 | case 4: /* TimerRIS */ |
| 66 | return s->int_level; |
| 67 | case 5: /* TimerMIS */ |
| 68 | if ((s->control & TIMER_CTRL_IE) == 0) |
| 69 | return 0; |
| 70 | return s->int_level; |
| 71 | default: |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 72 | qemu_log_mask(LOG_GUEST_ERROR, |
| 73 | "%s: Bad offset %x\n", __func__, (int)offset); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 74 | return 0; |
| 75 | } |
| 76 | } |
| 77 | |
Peter Maydell | 5a65f7b | 2019-10-08 18:17:23 +0100 | [diff] [blame] | 78 | /* |
| 79 | * Reset the timer limit after settings have changed. |
| 80 | * May only be called from inside a ptimer transaction block. |
| 81 | */ |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 82 | static void arm_timer_recalibrate(arm_timer_state *s, int reload) |
| 83 | { |
| 84 | uint32_t limit; |
| 85 | |
Rabin Vincent | a9cf98d | 2010-05-02 15:20:52 +0530 | [diff] [blame] | 86 | if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 87 | /* Free running. */ |
| 88 | if (s->control & TIMER_CTRL_32BIT) |
| 89 | limit = 0xffffffff; |
| 90 | else |
| 91 | limit = 0xffff; |
| 92 | } else { |
| 93 | /* Periodic. */ |
| 94 | limit = s->limit; |
| 95 | } |
| 96 | ptimer_set_limit(s->timer, limit, reload); |
| 97 | } |
| 98 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 99 | static void arm_timer_write(void *opaque, hwaddr offset, |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 100 | uint32_t value) |
| 101 | { |
| 102 | arm_timer_state *s = (arm_timer_state *)opaque; |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 103 | int freq; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 104 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 105 | switch (offset >> 2) { |
| 106 | case 0: /* TimerLoad */ |
| 107 | s->limit = value; |
Peter Maydell | 5a65f7b | 2019-10-08 18:17:23 +0100 | [diff] [blame] | 108 | ptimer_transaction_begin(s->timer); |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 109 | arm_timer_recalibrate(s, 1); |
Peter Maydell | 5a65f7b | 2019-10-08 18:17:23 +0100 | [diff] [blame] | 110 | ptimer_transaction_commit(s->timer); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 111 | break; |
| 112 | case 1: /* TimerValue */ |
| 113 | /* ??? Linux seems to want to write to this readonly register. |
| 114 | Ignore it. */ |
| 115 | break; |
| 116 | case 2: /* TimerControl */ |
Peter Maydell | 5a65f7b | 2019-10-08 18:17:23 +0100 | [diff] [blame] | 117 | ptimer_transaction_begin(s->timer); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 118 | if (s->control & TIMER_CTRL_ENABLE) { |
| 119 | /* Pause the timer if it is running. This may cause some |
| 120 | inaccuracy dure to rounding, but avoids a whole lot of other |
| 121 | messyness. */ |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 122 | ptimer_stop(s->timer); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 123 | } |
| 124 | s->control = value; |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 125 | freq = s->freq; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 126 | /* ??? Need to recalculate expiry time after changing divisor. */ |
| 127 | switch ((value >> 2) & 3) { |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 128 | case 1: freq >>= 4; break; |
| 129 | case 2: freq >>= 8; break; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 130 | } |
Rabin Vincent | d675990 | 2010-05-02 15:20:51 +0530 | [diff] [blame] | 131 | arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 132 | ptimer_set_freq(s->timer, freq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 133 | if (s->control & TIMER_CTRL_ENABLE) { |
| 134 | /* Restart the timer if still enabled. */ |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 135 | ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 136 | } |
Peter Maydell | 5a65f7b | 2019-10-08 18:17:23 +0100 | [diff] [blame] | 137 | ptimer_transaction_commit(s->timer); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 138 | break; |
| 139 | case 3: /* TimerIntClr */ |
| 140 | s->int_level = 0; |
| 141 | break; |
| 142 | case 6: /* TimerBGLoad */ |
| 143 | s->limit = value; |
Peter Maydell | 5a65f7b | 2019-10-08 18:17:23 +0100 | [diff] [blame] | 144 | ptimer_transaction_begin(s->timer); |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 145 | arm_timer_recalibrate(s, 0); |
Peter Maydell | 5a65f7b | 2019-10-08 18:17:23 +0100 | [diff] [blame] | 146 | ptimer_transaction_commit(s->timer); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 147 | break; |
| 148 | default: |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 149 | qemu_log_mask(LOG_GUEST_ERROR, |
| 150 | "%s: Bad offset %x\n", __func__, (int)offset); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 151 | } |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 152 | arm_timer_update(s); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | static void arm_timer_tick(void *opaque) |
| 156 | { |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 157 | arm_timer_state *s = (arm_timer_state *)opaque; |
| 158 | s->int_level = 1; |
| 159 | arm_timer_update(s); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 160 | } |
| 161 | |
Juan Quintela | eecd33a | 2010-12-01 23:15:41 +0100 | [diff] [blame] | 162 | static const VMStateDescription vmstate_arm_timer = { |
| 163 | .name = "arm_timer", |
| 164 | .version_id = 1, |
| 165 | .minimum_version_id = 1, |
Juan Quintela | 8f1e884 | 2014-05-13 16:09:35 +0100 | [diff] [blame] | 166 | .fields = (VMStateField[]) { |
Juan Quintela | eecd33a | 2010-12-01 23:15:41 +0100 | [diff] [blame] | 167 | VMSTATE_UINT32(control, arm_timer_state), |
| 168 | VMSTATE_UINT32(limit, arm_timer_state), |
| 169 | VMSTATE_INT32(int_level, arm_timer_state), |
| 170 | VMSTATE_PTIMER(timer, arm_timer_state), |
| 171 | VMSTATE_END_OF_LIST() |
| 172 | } |
| 173 | }; |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 174 | |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 175 | static arm_timer_state *arm_timer_init(uint32_t freq) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 176 | { |
| 177 | arm_timer_state *s; |
| 178 | |
Markus Armbruster | b21e238 | 2022-03-15 15:41:56 +0100 | [diff] [blame] | 179 | s = g_new0(arm_timer_state, 1); |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 180 | s->freq = freq; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 181 | s->control = TIMER_CTRL_IE; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 182 | |
Peter Maydell | 9598c1b | 2022-05-16 11:30:58 +0100 | [diff] [blame] | 183 | s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_LEGACY); |
Peter Xu | 1df2c9a | 2019-10-16 10:29:30 +0800 | [diff] [blame] | 184 | vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 185 | return s; |
| 186 | } |
| 187 | |
Peter Maydell | 932a8d1 | 2021-02-05 17:14:56 +0000 | [diff] [blame] | 188 | /* |
| 189 | * ARM PrimeCell SP804 dual timer module. |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 190 | * Docs at |
Peter Maydell | 932a8d1 | 2021-02-05 17:14:56 +0000 | [diff] [blame] | 191 | * https://developer.arm.com/documentation/ddi0271/latest/ |
| 192 | */ |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 193 | |
Andreas Färber | 0c88dea | 2013-07-27 14:17:41 +0200 | [diff] [blame] | 194 | #define TYPE_SP804 "sp804" |
Eduardo Habkost | 8063396 | 2020-09-16 14:25:19 -0400 | [diff] [blame] | 195 | OBJECT_DECLARE_SIMPLE_TYPE(SP804State, SP804) |
Andreas Färber | 0c88dea | 2013-07-27 14:17:41 +0200 | [diff] [blame] | 196 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 197 | struct SP804State { |
Andreas Färber | 0c88dea | 2013-07-27 14:17:41 +0200 | [diff] [blame] | 198 | SysBusDevice parent_obj; |
| 199 | |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 200 | MemoryRegion iomem; |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 201 | arm_timer_state *timer[2]; |
Mark Langsdorf | 104a26a | 2011-12-29 06:19:51 +0000 | [diff] [blame] | 202 | uint32_t freq0, freq1; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 203 | int level[2]; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 204 | qemu_irq irq; |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 205 | }; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 206 | |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 207 | static const uint8_t sp804_ids[] = { |
| 208 | /* Timer ID */ |
| 209 | 0x04, 0x18, 0x14, 0, |
| 210 | /* PrimeCell ID */ |
| 211 | 0xd, 0xf0, 0x05, 0xb1 |
| 212 | }; |
| 213 | |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 214 | /* Merge the IRQs from the two component devices. */ |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 215 | static void sp804_set_irq(void *opaque, int irq, int level) |
| 216 | { |
Andreas Färber | 1024d7f | 2013-07-27 14:15:46 +0200 | [diff] [blame] | 217 | SP804State *s = (SP804State *)opaque; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 218 | |
| 219 | s->level[irq] = level; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 220 | qemu_set_irq(s->irq, s->level[0] || s->level[1]); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 221 | } |
| 222 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 223 | static uint64_t sp804_read(void *opaque, hwaddr offset, |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 224 | unsigned size) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 225 | { |
Andreas Färber | 1024d7f | 2013-07-27 14:15:46 +0200 | [diff] [blame] | 226 | SP804State *s = (SP804State *)opaque; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 227 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 228 | if (offset < 0x20) { |
| 229 | return arm_timer_read(s->timer[0], offset); |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 230 | } |
| 231 | if (offset < 0x40) { |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 232 | return arm_timer_read(s->timer[1], offset - 0x20); |
| 233 | } |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 234 | |
| 235 | /* TimerPeriphID */ |
| 236 | if (offset >= 0xfe0 && offset <= 0xffc) { |
| 237 | return sp804_ids[(offset - 0xfe0) >> 2]; |
| 238 | } |
| 239 | |
| 240 | switch (offset) { |
| 241 | /* Integration Test control registers, which we won't support */ |
| 242 | case 0xf00: /* TimerITCR */ |
| 243 | case 0xf04: /* TimerITOP (strictly write only but..) */ |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 244 | qemu_log_mask(LOG_UNIMP, |
| 245 | "%s: integration test registers unimplemented\n", |
| 246 | __func__); |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 247 | return 0; |
| 248 | } |
| 249 | |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 250 | qemu_log_mask(LOG_GUEST_ERROR, |
| 251 | "%s: Bad offset %x\n", __func__, (int)offset); |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 252 | return 0; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 253 | } |
| 254 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 255 | static void sp804_write(void *opaque, hwaddr offset, |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 256 | uint64_t value, unsigned size) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 257 | { |
Andreas Färber | 1024d7f | 2013-07-27 14:15:46 +0200 | [diff] [blame] | 258 | SP804State *s = (SP804State *)opaque; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 259 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 260 | if (offset < 0x20) { |
| 261 | arm_timer_write(s->timer[0], offset, value); |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 262 | return; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 263 | } |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 264 | |
| 265 | if (offset < 0x40) { |
| 266 | arm_timer_write(s->timer[1], offset - 0x20, value); |
| 267 | return; |
| 268 | } |
| 269 | |
| 270 | /* Technically we could be writing to the Test Registers, but not likely */ |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 271 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", |
| 272 | __func__, (int)offset); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 273 | } |
| 274 | |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 275 | static const MemoryRegionOps sp804_ops = { |
| 276 | .read = sp804_read, |
| 277 | .write = sp804_write, |
| 278 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 279 | }; |
| 280 | |
Juan Quintela | 81986ac | 2010-12-01 23:12:32 +0100 | [diff] [blame] | 281 | static const VMStateDescription vmstate_sp804 = { |
| 282 | .name = "sp804", |
| 283 | .version_id = 1, |
| 284 | .minimum_version_id = 1, |
Juan Quintela | 8f1e884 | 2014-05-13 16:09:35 +0100 | [diff] [blame] | 285 | .fields = (VMStateField[]) { |
Andreas Färber | 1024d7f | 2013-07-27 14:15:46 +0200 | [diff] [blame] | 286 | VMSTATE_INT32_ARRAY(level, SP804State, 2), |
Juan Quintela | 81986ac | 2010-12-01 23:12:32 +0100 | [diff] [blame] | 287 | VMSTATE_END_OF_LIST() |
| 288 | } |
| 289 | }; |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 290 | |
xiaoqiang.zhao | 0d175e7 | 2016-02-18 14:16:20 +0000 | [diff] [blame] | 291 | static void sp804_init(Object *obj) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 292 | { |
xiaoqiang.zhao | 0d175e7 | 2016-02-18 14:16:20 +0000 | [diff] [blame] | 293 | SP804State *s = SP804(obj); |
| 294 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 295 | |
Andreas Färber | 0c88dea | 2013-07-27 14:17:41 +0200 | [diff] [blame] | 296 | sysbus_init_irq(sbd, &s->irq); |
xiaoqiang.zhao | 0d175e7 | 2016-02-18 14:16:20 +0000 | [diff] [blame] | 297 | memory_region_init_io(&s->iomem, obj, &sp804_ops, s, |
| 298 | "sp804", 0x1000); |
| 299 | sysbus_init_mmio(sbd, &s->iomem); |
| 300 | } |
| 301 | |
| 302 | static void sp804_realize(DeviceState *dev, Error **errp) |
| 303 | { |
| 304 | SP804State *s = SP804(dev); |
| 305 | |
Mark Langsdorf | 104a26a | 2011-12-29 06:19:51 +0000 | [diff] [blame] | 306 | s->timer[0] = arm_timer_init(s->freq0); |
| 307 | s->timer[1] = arm_timer_init(s->freq1); |
Shannon Zhao | b641272 | 2015-05-29 13:27:02 +0800 | [diff] [blame] | 308 | s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); |
| 309 | s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 310 | } |
| 311 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 312 | /* Integrator/CP timer module. */ |
| 313 | |
Andreas Färber | e2051b4 | 2013-07-27 14:20:25 +0200 | [diff] [blame] | 314 | #define TYPE_INTEGRATOR_PIT "integrator_pit" |
Eduardo Habkost | 8063396 | 2020-09-16 14:25:19 -0400 | [diff] [blame] | 315 | OBJECT_DECLARE_SIMPLE_TYPE(icp_pit_state, INTEGRATOR_PIT) |
Andreas Färber | e2051b4 | 2013-07-27 14:20:25 +0200 | [diff] [blame] | 316 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 317 | struct icp_pit_state { |
Andreas Färber | e2051b4 | 2013-07-27 14:20:25 +0200 | [diff] [blame] | 318 | SysBusDevice parent_obj; |
| 319 | |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 320 | MemoryRegion iomem; |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 321 | arm_timer_state *timer[3]; |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 322 | }; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 323 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 324 | static uint64_t icp_pit_read(void *opaque, hwaddr offset, |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 325 | unsigned size) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 326 | { |
| 327 | icp_pit_state *s = (icp_pit_state *)opaque; |
| 328 | int n; |
| 329 | |
| 330 | /* ??? Don't know the PrimeCell ID for this device. */ |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 331 | n = offset >> 8; |
Peter Maydell | ee71c98 | 2011-11-11 13:30:15 +0000 | [diff] [blame] | 332 | if (n > 2) { |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 333 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); |
Peter Maydell | cba933b | 2014-02-26 17:19:58 +0000 | [diff] [blame] | 334 | return 0; |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 335 | } |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 336 | |
| 337 | return arm_timer_read(s->timer[n], offset & 0xff); |
| 338 | } |
| 339 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 340 | static void icp_pit_write(void *opaque, hwaddr offset, |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 341 | uint64_t value, unsigned size) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 342 | { |
| 343 | icp_pit_state *s = (icp_pit_state *)opaque; |
| 344 | int n; |
| 345 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 346 | n = offset >> 8; |
Peter Maydell | ee71c98 | 2011-11-11 13:30:15 +0000 | [diff] [blame] | 347 | if (n > 2) { |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 348 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); |
Peter Maydell | cba933b | 2014-02-26 17:19:58 +0000 | [diff] [blame] | 349 | return; |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 350 | } |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 351 | |
| 352 | arm_timer_write(s->timer[n], offset & 0xff, value); |
| 353 | } |
| 354 | |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 355 | static const MemoryRegionOps icp_pit_ops = { |
| 356 | .read = icp_pit_read, |
| 357 | .write = icp_pit_write, |
| 358 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 359 | }; |
| 360 | |
xiaoqiang.zhao | 0d175e7 | 2016-02-18 14:16:20 +0000 | [diff] [blame] | 361 | static void icp_pit_init(Object *obj) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 362 | { |
xiaoqiang.zhao | 0d175e7 | 2016-02-18 14:16:20 +0000 | [diff] [blame] | 363 | icp_pit_state *s = INTEGRATOR_PIT(obj); |
| 364 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 365 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 366 | /* Timer 0 runs at the system clock speed (40MHz). */ |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 367 | s->timer[0] = arm_timer_init(40000000); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 368 | /* The other two timers run at 1MHz. */ |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 369 | s->timer[1] = arm_timer_init(1000000); |
| 370 | s->timer[2] = arm_timer_init(1000000); |
| 371 | |
| 372 | sysbus_init_irq(dev, &s->timer[0]->irq); |
| 373 | sysbus_init_irq(dev, &s->timer[1]->irq); |
| 374 | sysbus_init_irq(dev, &s->timer[2]->irq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 375 | |
xiaoqiang.zhao | 0d175e7 | 2016-02-18 14:16:20 +0000 | [diff] [blame] | 376 | memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, |
Paolo Bonzini | 853dca1 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 377 | "icp_pit", 0x1000); |
Avi Kivity | 750ecd4 | 2011-11-27 11:38:10 +0200 | [diff] [blame] | 378 | sysbus_init_mmio(dev, &s->iomem); |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 379 | /* This device has no state to save/restore. The component timers will |
| 380 | save themselves. */ |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 381 | } |
| 382 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 383 | static const TypeInfo icp_pit_info = { |
Andreas Färber | e2051b4 | 2013-07-27 14:20:25 +0200 | [diff] [blame] | 384 | .name = TYPE_INTEGRATOR_PIT, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 385 | .parent = TYPE_SYS_BUS_DEVICE, |
| 386 | .instance_size = sizeof(icp_pit_state), |
xiaoqiang.zhao | 0d175e7 | 2016-02-18 14:16:20 +0000 | [diff] [blame] | 387 | .instance_init = icp_pit_init, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 388 | }; |
| 389 | |
| 390 | static Property sp804_properties[] = { |
Andreas Färber | 1024d7f | 2013-07-27 14:15:46 +0200 | [diff] [blame] | 391 | DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), |
| 392 | DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 393 | DEFINE_PROP_END_OF_LIST(), |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 394 | }; |
| 395 | |
| 396 | static void sp804_class_init(ObjectClass *klass, void *data) |
| 397 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 398 | DeviceClass *k = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 399 | |
xiaoqiang.zhao | 0d175e7 | 2016-02-18 14:16:20 +0000 | [diff] [blame] | 400 | k->realize = sp804_realize; |
Marc-André Lureau | 4f67d30 | 2020-01-10 19:30:32 +0400 | [diff] [blame] | 401 | device_class_set_props(k, sp804_properties); |
xiaoqiang.zhao | d712a5a | 2016-02-18 14:16:20 +0000 | [diff] [blame] | 402 | k->vmsd = &vmstate_sp804; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 403 | } |
| 404 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 405 | static const TypeInfo sp804_info = { |
Andreas Färber | 0c88dea | 2013-07-27 14:17:41 +0200 | [diff] [blame] | 406 | .name = TYPE_SP804, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 407 | .parent = TYPE_SYS_BUS_DEVICE, |
Andreas Färber | 1024d7f | 2013-07-27 14:15:46 +0200 | [diff] [blame] | 408 | .instance_size = sizeof(SP804State), |
xiaoqiang.zhao | 0d175e7 | 2016-02-18 14:16:20 +0000 | [diff] [blame] | 409 | .instance_init = sp804_init, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 410 | .class_init = sp804_class_init, |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 411 | }; |
| 412 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 413 | static void arm_timer_register_types(void) |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 414 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 415 | type_register_static(&icp_pit_info); |
| 416 | type_register_static(&sp804_info); |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 417 | } |
| 418 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 419 | type_init(arm_timer_register_types) |