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bellard79aceca2003-11-23 14:55:54 +00001/*
bellard3fc6c082005-07-02 20:59:34 +00002 * PowerPC emulation for qemu: main translation routines.
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer76a66252007-03-07 08:32:30 +00004 * Copyright (c) 2003-2007 Jocelyn Mayer
bellard79aceca2003-11-23 14:55:54 +00005 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
bellardc6a1c222004-05-20 13:10:49 +000020#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
bellard79aceca2003-11-23 14:55:54 +000026#include "cpu.h"
bellardc6a1c222004-05-20 13:10:49 +000027#include "exec-all.h"
bellard79aceca2003-11-23 14:55:54 +000028#include "disas.h"
aurel32f10dc082008-08-28 21:01:45 +000029#include "helper.h"
bellard57fec1f2008-02-01 10:50:11 +000030#include "tcg-op.h"
aurel32ca10f862008-04-11 21:35:42 +000031#include "qemu-common.h"
bellard79aceca2003-11-23 14:55:54 +000032
aurel328cbcb4f2008-05-10 23:28:14 +000033#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
j_mayera750fc02007-09-26 23:54:22 +000037/* Include definitions for instructions classes and implementations flags */
bellard79aceca2003-11-23 14:55:54 +000038//#define DO_SINGLE_STEP
bellard9fddaa02004-05-21 12:59:32 +000039//#define PPC_DEBUG_DISAS
j_mayer76a66252007-03-07 08:32:30 +000040//#define DO_PPC_STATISTICS
j_mayer7c580442007-10-27 17:54:30 +000041//#define OPTIMIZE_FPRF_UPDATE
bellard79aceca2003-11-23 14:55:54 +000042
j_mayera750fc02007-09-26 23:54:22 +000043/*****************************************************************************/
44/* Code translation helpers */
bellardc53be332005-10-30 21:39:19 +000045
aurel32f78fb442008-09-04 05:25:47 +000046/* global register indexes */
47static TCGv cpu_env;
aurel321d542692008-09-04 14:43:45 +000048static char cpu_reg_names[10*3 + 22*4 /* GPR */
aurel32f78fb442008-09-04 05:25:47 +000049#if !defined(TARGET_PPC64)
aurel321d542692008-09-04 14:43:45 +000050 + 10*4 + 22*5 /* SPE GPRh */
aurel32f78fb442008-09-04 05:25:47 +000051#endif
aurel32a5e26af2008-09-04 14:43:54 +000052 + 10*4 + 22*5 /* FPR */
aurel3247e46612008-09-04 17:06:47 +000053 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
aurel32f78fb442008-09-04 05:25:47 +000055static TCGv cpu_gpr[32];
56#if !defined(TARGET_PPC64)
57static TCGv cpu_gprh[32];
58#endif
aurel32a5e26af2008-09-04 14:43:54 +000059static TCGv cpu_fpr[32];
aurel321d542692008-09-04 14:43:45 +000060static TCGv cpu_avrh[32], cpu_avrl[32];
aurel3247e46612008-09-04 17:06:47 +000061static TCGv cpu_crf[8];
aurel32bd568f12008-09-04 18:06:03 +000062static TCGv cpu_nip;
aurel32cfdcd372008-09-14 18:30:23 +000063static TCGv cpu_ctr;
64static TCGv cpu_lr;
aurel323d7b4172008-10-21 11:28:46 +000065static TCGv cpu_xer;
aurel32e1571902008-10-21 11:31:14 +000066static TCGv cpu_fpscr;
aurel32f78fb442008-09-04 05:25:47 +000067
68/* dyngen register indexes */
69static TCGv cpu_T[3];
70#if defined(TARGET_PPC64)
71#define cpu_T64 cpu_T
72#else
73static TCGv cpu_T64[3];
74#endif
aurel32a5e26af2008-09-04 14:43:54 +000075static TCGv cpu_FT[3];
aurel321d542692008-09-04 14:43:45 +000076static TCGv cpu_AVRh[3], cpu_AVRl[3];
pbrook2e70f6e2008-06-29 01:03:05 +000077
78#include "gen-icount.h"
79
80void ppc_translate_init(void)
81{
aurel32f78fb442008-09-04 05:25:47 +000082 int i;
83 char* p;
pbrookb2437bf2008-06-29 12:29:56 +000084 static int done_init = 0;
aurel32f78fb442008-09-04 05:25:47 +000085
pbrook2e70f6e2008-06-29 01:03:05 +000086 if (done_init)
87 return;
aurel32f78fb442008-09-04 05:25:47 +000088
pbrook2e70f6e2008-06-29 01:03:05 +000089 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
aurel321c73fe52008-08-28 21:01:36 +000090#if TARGET_LONG_BITS > HOST_LONG_BITS
91 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
92 TCG_AREG0, offsetof(CPUState, t0), "T0");
93 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
94 TCG_AREG0, offsetof(CPUState, t1), "T1");
95 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
96 TCG_AREG0, offsetof(CPUState, t2), "T2");
97#else
98 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
99 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
100 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
101#endif
aurel32f78fb442008-09-04 05:25:47 +0000102#if !defined(TARGET_PPC64)
103 cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
aurel32bd7d9a62008-09-04 05:26:09 +0000104 TCG_AREG0, offsetof(CPUState, t0_64),
aurel32f78fb442008-09-04 05:25:47 +0000105 "T0_64");
106 cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
aurel32bd7d9a62008-09-04 05:26:09 +0000107 TCG_AREG0, offsetof(CPUState, t1_64),
aurel32f78fb442008-09-04 05:25:47 +0000108 "T1_64");
109 cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
aurel32bd7d9a62008-09-04 05:26:09 +0000110 TCG_AREG0, offsetof(CPUState, t2_64),
aurel32f78fb442008-09-04 05:25:47 +0000111 "T2_64");
112#endif
aurel32a5e26af2008-09-04 14:43:54 +0000113
114 cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
115 offsetof(CPUState, ft0), "FT0");
116 cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
117 offsetof(CPUState, ft1), "FT1");
118 cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
119 offsetof(CPUState, ft2), "FT2");
120
aurel321d542692008-09-04 14:43:45 +0000121 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
122 offsetof(CPUState, avr0.u64[0]), "AVR0H");
123 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
124 offsetof(CPUState, avr0.u64[1]), "AVR0L");
125 cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
126 offsetof(CPUState, avr1.u64[0]), "AVR1H");
127 cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
128 offsetof(CPUState, avr1.u64[1]), "AVR1L");
129 cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
130 offsetof(CPUState, avr2.u64[0]), "AVR2H");
131 cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
132 offsetof(CPUState, avr2.u64[1]), "AVR2L");
133
aurel32f78fb442008-09-04 05:25:47 +0000134 p = cpu_reg_names;
aurel3247e46612008-09-04 17:06:47 +0000135
136 for (i = 0; i < 8; i++) {
137 sprintf(p, "crf%d", i);
138 cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
139 offsetof(CPUState, crf[i]), p);
140 p += 5;
141 }
142
aurel32f78fb442008-09-04 05:25:47 +0000143 for (i = 0; i < 32; i++) {
144 sprintf(p, "r%d", i);
145 cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
146 offsetof(CPUState, gpr[i]), p);
147 p += (i < 10) ? 3 : 4;
148#if !defined(TARGET_PPC64)
149 sprintf(p, "r%dH", i);
150 cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
151 offsetof(CPUState, gprh[i]), p);
152 p += (i < 10) ? 4 : 5;
153#endif
aurel321d542692008-09-04 14:43:45 +0000154
aurel32a5e26af2008-09-04 14:43:54 +0000155 sprintf(p, "fp%d", i);
156 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
157 offsetof(CPUState, fpr[i]), p);
aurel32ec1ac722008-09-04 15:49:12 +0000158 p += (i < 10) ? 4 : 5;
aurel32a5e26af2008-09-04 14:43:54 +0000159
aurel321d542692008-09-04 14:43:45 +0000160 sprintf(p, "avr%dH", i);
161 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
162 offsetof(CPUState, avr[i].u64[0]), p);
163 p += (i < 10) ? 6 : 7;
aurel32ec1ac722008-09-04 15:49:12 +0000164
aurel321d542692008-09-04 14:43:45 +0000165 sprintf(p, "avr%dL", i);
166 cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
167 offsetof(CPUState, avr[i].u64[1]), p);
168 p += (i < 10) ? 6 : 7;
aurel32f78fb442008-09-04 05:25:47 +0000169 }
aurel32f10dc082008-08-28 21:01:45 +0000170
aurel32bd568f12008-09-04 18:06:03 +0000171 cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
172 offsetof(CPUState, nip), "nip");
173
aurel32cfdcd372008-09-14 18:30:23 +0000174 cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
175 offsetof(CPUState, ctr), "ctr");
176
177 cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
178 offsetof(CPUState, lr), "lr");
179
aurel323d7b4172008-10-21 11:28:46 +0000180 cpu_xer = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
181 offsetof(CPUState, xer), "xer");
182
aurel32e1571902008-10-21 11:31:14 +0000183 cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
184 offsetof(CPUState, fpscr), "fpscr");
185
aurel32f10dc082008-08-28 21:01:45 +0000186 /* register helpers */
187#undef DEF_HELPER
188#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
189#include "helper.h"
190
pbrook2e70f6e2008-06-29 01:03:05 +0000191 done_init = 1;
192}
193
j_mayer7c580442007-10-27 17:54:30 +0000194#if defined(OPTIMIZE_FPRF_UPDATE)
195static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
196static uint16_t **gen_fprf_ptr;
197#endif
bellard79aceca2003-11-23 14:55:54 +0000198
bellard79aceca2003-11-23 14:55:54 +0000199/* internal defines */
200typedef struct DisasContext {
201 struct TranslationBlock *tb;
bellard0fa85d42005-01-03 23:43:32 +0000202 target_ulong nip;
bellard79aceca2003-11-23 14:55:54 +0000203 uint32_t opcode;
bellard9a64fbe2004-01-04 22:58:38 +0000204 uint32_t exception;
bellard3cc62372005-02-15 23:06:19 +0000205 /* Routine used to access memory */
206 int mem_idx;
207 /* Translation flags */
bellard9a64fbe2004-01-04 22:58:38 +0000208#if !defined(CONFIG_USER_ONLY)
bellard79aceca2003-11-23 14:55:54 +0000209 int supervisor;
bellard9a64fbe2004-01-04 22:58:38 +0000210#endif
j_mayerd9bce9d2007-03-17 14:02:15 +0000211#if defined(TARGET_PPC64)
212 int sf_mode;
213#endif
bellard3cc62372005-02-15 23:06:19 +0000214 int fpu_enabled;
j_mayera9d9eb82007-10-07 18:19:26 +0000215 int altivec_enabled;
j_mayer0487d6a2007-03-20 22:11:31 +0000216 int spe_enabled;
bellard3fc6c082005-07-02 20:59:34 +0000217 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
bellardea4e7542006-05-22 21:50:20 +0000218 int singlestep_enabled;
j_mayerd63001d2007-10-04 00:51:58 +0000219 int dcache_line_size;
bellard79aceca2003-11-23 14:55:54 +0000220} DisasContext;
221
bellard3fc6c082005-07-02 20:59:34 +0000222struct opc_handler_t {
bellard79aceca2003-11-23 14:55:54 +0000223 /* invalid bits */
224 uint32_t inval;
bellard9a64fbe2004-01-04 22:58:38 +0000225 /* instruction type */
j_mayer0487d6a2007-03-20 22:11:31 +0000226 uint64_t type;
bellard79aceca2003-11-23 14:55:54 +0000227 /* handler */
228 void (*handler)(DisasContext *ctx);
j_mayera750fc02007-09-26 23:54:22 +0000229#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
blueswir1b55266b2008-09-20 08:07:15 +0000230 const char *oname;
j_mayera750fc02007-09-26 23:54:22 +0000231#endif
232#if defined(DO_PPC_STATISTICS)
j_mayer76a66252007-03-07 08:32:30 +0000233 uint64_t count;
234#endif
bellard3fc6c082005-07-02 20:59:34 +0000235};
bellard79aceca2003-11-23 14:55:54 +0000236
j_mayer7c580442007-10-27 17:54:30 +0000237static always_inline void gen_reset_fpstatus (void)
238{
239#ifdef CONFIG_SOFTFLOAT
240 gen_op_reset_fpstatus();
241#endif
242}
243
244static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
245{
246 if (set_fprf != 0) {
247 /* This case might be optimized later */
248#if defined(OPTIMIZE_FPRF_UPDATE)
249 *gen_fprf_ptr++ = gen_opc_ptr;
250#endif
251 gen_op_compute_fprf(1);
252 if (unlikely(set_rc))
aurel3247e46612008-09-04 17:06:47 +0000253 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
j_mayer7c580442007-10-27 17:54:30 +0000254 gen_op_float_check_status();
255 } else if (unlikely(set_rc)) {
256 /* We always need to compute fpcc */
257 gen_op_compute_fprf(0);
aurel3247e46612008-09-04 17:06:47 +0000258 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
j_mayer7c580442007-10-27 17:54:30 +0000259 if (set_fprf)
260 gen_op_float_check_status();
261 }
262}
263
264static always_inline void gen_optimize_fprf (void)
265{
266#if defined(OPTIMIZE_FPRF_UPDATE)
267 uint16_t **ptr;
268
269 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
270 *ptr = INDEX_op_nop1;
271 gen_fprf_ptr = gen_fprf_buf;
272#endif
273}
274
j_mayerb068d6a2007-10-07 17:13:44 +0000275static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
j_mayerd9bce9d2007-03-17 14:02:15 +0000276{
277#if defined(TARGET_PPC64)
278 if (ctx->sf_mode)
aurel32bd568f12008-09-04 18:06:03 +0000279 tcg_gen_movi_tl(cpu_nip, nip);
j_mayerd9bce9d2007-03-17 14:02:15 +0000280 else
281#endif
aurel32bd568f12008-09-04 18:06:03 +0000282 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
j_mayerd9bce9d2007-03-17 14:02:15 +0000283}
284
j_mayere1833e12007-09-29 13:06:16 +0000285#define GEN_EXCP(ctx, excp, error) \
bellard79aceca2003-11-23 14:55:54 +0000286do { \
j_mayere1833e12007-09-29 13:06:16 +0000287 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
j_mayerd9bce9d2007-03-17 14:02:15 +0000288 gen_update_nip(ctx, (ctx)->nip); \
bellard9fddaa02004-05-21 12:59:32 +0000289 } \
290 gen_op_raise_exception_err((excp), (error)); \
291 ctx->exception = (excp); \
bellard79aceca2003-11-23 14:55:54 +0000292} while (0)
293
j_mayere1833e12007-09-29 13:06:16 +0000294#define GEN_EXCP_INVAL(ctx) \
295GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
296 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
bellard9a64fbe2004-01-04 22:58:38 +0000297
j_mayere1833e12007-09-29 13:06:16 +0000298#define GEN_EXCP_PRIVOPC(ctx) \
299GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
300 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
bellard9a64fbe2004-01-04 22:58:38 +0000301
j_mayere1833e12007-09-29 13:06:16 +0000302#define GEN_EXCP_PRIVREG(ctx) \
303GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
304 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
305
306#define GEN_EXCP_NO_FP(ctx) \
307GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
308
309#define GEN_EXCP_NO_AP(ctx) \
310GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
bellard9fddaa02004-05-21 12:59:32 +0000311
j_mayera9d9eb82007-10-07 18:19:26 +0000312#define GEN_EXCP_NO_VR(ctx) \
313GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
314
bellardf24e5692005-11-23 21:36:30 +0000315/* Stop translation */
j_mayerb068d6a2007-10-07 17:13:44 +0000316static always_inline void GEN_STOP (DisasContext *ctx)
bellard3fc6c082005-07-02 20:59:34 +0000317{
j_mayerd9bce9d2007-03-17 14:02:15 +0000318 gen_update_nip(ctx, ctx->nip);
j_mayere1833e12007-09-29 13:06:16 +0000319 ctx->exception = POWERPC_EXCP_STOP;
bellard3fc6c082005-07-02 20:59:34 +0000320}
321
bellardf24e5692005-11-23 21:36:30 +0000322/* No need to update nip here, as execution flow will change */
j_mayerb068d6a2007-10-07 17:13:44 +0000323static always_inline void GEN_SYNC (DisasContext *ctx)
bellard2be00712005-07-02 22:09:27 +0000324{
j_mayere1833e12007-09-29 13:06:16 +0000325 ctx->exception = POWERPC_EXCP_SYNC;
bellard2be00712005-07-02 22:09:27 +0000326}
327
bellard79aceca2003-11-23 14:55:54 +0000328#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329static void gen_##name (DisasContext *ctx); \
330GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
331static void gen_##name (DisasContext *ctx)
332
j_mayerc7697e12007-10-26 00:46:07 +0000333#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
334static void gen_##name (DisasContext *ctx); \
335GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
336static void gen_##name (DisasContext *ctx)
337
bellard79aceca2003-11-23 14:55:54 +0000338typedef struct opcode_t {
339 unsigned char opc1, opc2, opc3;
ths1235fc02008-06-03 19:51:57 +0000340#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
bellard18fba282005-02-08 21:24:36 +0000341 unsigned char pad[5];
342#else
343 unsigned char pad[1];
344#endif
bellard79aceca2003-11-23 14:55:54 +0000345 opc_handler_t handler;
blueswir1b55266b2008-09-20 08:07:15 +0000346 const char *oname;
bellard79aceca2003-11-23 14:55:54 +0000347} opcode_t;
348
j_mayera750fc02007-09-26 23:54:22 +0000349/*****************************************************************************/
bellard79aceca2003-11-23 14:55:54 +0000350/*** Instruction decoding ***/
351#define EXTRACT_HELPER(name, shift, nb) \
j_mayerb068d6a2007-10-07 17:13:44 +0000352static always_inline uint32_t name (uint32_t opcode) \
bellard79aceca2003-11-23 14:55:54 +0000353{ \
354 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
355}
356
357#define EXTRACT_SHELPER(name, shift, nb) \
j_mayerb068d6a2007-10-07 17:13:44 +0000358static always_inline int32_t name (uint32_t opcode) \
bellard79aceca2003-11-23 14:55:54 +0000359{ \
bellard18fba282005-02-08 21:24:36 +0000360 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
bellard79aceca2003-11-23 14:55:54 +0000361}
362
363/* Opcode part 1 */
364EXTRACT_HELPER(opc1, 26, 6);
365/* Opcode part 2 */
366EXTRACT_HELPER(opc2, 1, 5);
367/* Opcode part 3 */
368EXTRACT_HELPER(opc3, 6, 5);
369/* Update Cr0 flags */
370EXTRACT_HELPER(Rc, 0, 1);
371/* Destination */
372EXTRACT_HELPER(rD, 21, 5);
373/* Source */
374EXTRACT_HELPER(rS, 21, 5);
375/* First operand */
376EXTRACT_HELPER(rA, 16, 5);
377/* Second operand */
378EXTRACT_HELPER(rB, 11, 5);
379/* Third operand */
380EXTRACT_HELPER(rC, 6, 5);
381/*** Get CRn ***/
382EXTRACT_HELPER(crfD, 23, 3);
383EXTRACT_HELPER(crfS, 18, 3);
384EXTRACT_HELPER(crbD, 21, 5);
385EXTRACT_HELPER(crbA, 16, 5);
386EXTRACT_HELPER(crbB, 11, 5);
387/* SPR / TBL */
bellard3fc6c082005-07-02 20:59:34 +0000388EXTRACT_HELPER(_SPR, 11, 10);
j_mayerb068d6a2007-10-07 17:13:44 +0000389static always_inline uint32_t SPR (uint32_t opcode)
bellard3fc6c082005-07-02 20:59:34 +0000390{
391 uint32_t sprn = _SPR(opcode);
392
393 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
394}
bellard79aceca2003-11-23 14:55:54 +0000395/*** Get constants ***/
396EXTRACT_HELPER(IMM, 12, 8);
397/* 16 bits signed immediate value */
398EXTRACT_SHELPER(SIMM, 0, 16);
399/* 16 bits unsigned immediate value */
400EXTRACT_HELPER(UIMM, 0, 16);
401/* Bit count */
402EXTRACT_HELPER(NB, 11, 5);
403/* Shift count */
404EXTRACT_HELPER(SH, 11, 5);
405/* Mask start */
406EXTRACT_HELPER(MB, 6, 5);
407/* Mask end */
408EXTRACT_HELPER(ME, 1, 5);
bellardfb0eaff2004-01-04 14:57:11 +0000409/* Trap operand */
410EXTRACT_HELPER(TO, 21, 5);
bellard79aceca2003-11-23 14:55:54 +0000411
412EXTRACT_HELPER(CRM, 12, 8);
413EXTRACT_HELPER(FM, 17, 8);
414EXTRACT_HELPER(SR, 16, 4);
aurel32e4bb9972008-06-18 22:10:12 +0000415EXTRACT_HELPER(FPIMM, 12, 4);
bellardfb0eaff2004-01-04 14:57:11 +0000416
bellard79aceca2003-11-23 14:55:54 +0000417/*** Jump target decoding ***/
418/* Displacement */
419EXTRACT_SHELPER(d, 0, 16);
420/* Immediate address */
j_mayerb068d6a2007-10-07 17:13:44 +0000421static always_inline target_ulong LI (uint32_t opcode)
bellard79aceca2003-11-23 14:55:54 +0000422{
423 return (opcode >> 0) & 0x03FFFFFC;
424}
425
j_mayerb068d6a2007-10-07 17:13:44 +0000426static always_inline uint32_t BD (uint32_t opcode)
bellard79aceca2003-11-23 14:55:54 +0000427{
428 return (opcode >> 0) & 0xFFFC;
429}
430
431EXTRACT_HELPER(BO, 21, 5);
432EXTRACT_HELPER(BI, 16, 5);
433/* Absolute/relative address */
434EXTRACT_HELPER(AA, 1, 1);
435/* Link */
436EXTRACT_HELPER(LK, 0, 1);
437
438/* Create a mask between <start> and <end> bits */
j_mayerb068d6a2007-10-07 17:13:44 +0000439static always_inline target_ulong MASK (uint32_t start, uint32_t end)
bellard79aceca2003-11-23 14:55:54 +0000440{
j_mayer76a66252007-03-07 08:32:30 +0000441 target_ulong ret;
bellard79aceca2003-11-23 14:55:54 +0000442
j_mayer76a66252007-03-07 08:32:30 +0000443#if defined(TARGET_PPC64)
444 if (likely(start == 0)) {
j_mayer6f2d8972007-11-12 00:04:48 +0000445 ret = UINT64_MAX << (63 - end);
j_mayer76a66252007-03-07 08:32:30 +0000446 } else if (likely(end == 63)) {
j_mayer6f2d8972007-11-12 00:04:48 +0000447 ret = UINT64_MAX >> start;
j_mayer76a66252007-03-07 08:32:30 +0000448 }
449#else
450 if (likely(start == 0)) {
j_mayer6f2d8972007-11-12 00:04:48 +0000451 ret = UINT32_MAX << (31 - end);
j_mayer76a66252007-03-07 08:32:30 +0000452 } else if (likely(end == 31)) {
j_mayer6f2d8972007-11-12 00:04:48 +0000453 ret = UINT32_MAX >> start;
j_mayer76a66252007-03-07 08:32:30 +0000454 }
455#endif
456 else {
457 ret = (((target_ulong)(-1ULL)) >> (start)) ^
458 (((target_ulong)(-1ULL) >> (end)) >> 1);
459 if (unlikely(start > end))
460 return ~ret;
461 }
bellard79aceca2003-11-23 14:55:54 +0000462
463 return ret;
464}
465
j_mayera750fc02007-09-26 23:54:22 +0000466/*****************************************************************************/
467/* PowerPC Instructions types definitions */
468enum {
j_mayer1b413d52007-11-14 01:08:45 +0000469 PPC_NONE = 0x0000000000000000ULL,
j_mayer12de9a32007-10-05 22:06:02 +0000470 /* PowerPC base instructions set */
j_mayer1b413d52007-11-14 01:08:45 +0000471 PPC_INSNS_BASE = 0x0000000000000001ULL,
472 /* integer operations instructions */
j_mayera750fc02007-09-26 23:54:22 +0000473#define PPC_INTEGER PPC_INSNS_BASE
j_mayer1b413d52007-11-14 01:08:45 +0000474 /* flow control instructions */
j_mayera750fc02007-09-26 23:54:22 +0000475#define PPC_FLOW PPC_INSNS_BASE
j_mayer1b413d52007-11-14 01:08:45 +0000476 /* virtual memory instructions */
j_mayera750fc02007-09-26 23:54:22 +0000477#define PPC_MEM PPC_INSNS_BASE
j_mayer1b413d52007-11-14 01:08:45 +0000478 /* ld/st with reservation instructions */
j_mayera750fc02007-09-26 23:54:22 +0000479#define PPC_RES PPC_INSNS_BASE
j_mayer1b413d52007-11-14 01:08:45 +0000480 /* spr/msr access instructions */
j_mayera750fc02007-09-26 23:54:22 +0000481#define PPC_MISC PPC_INSNS_BASE
j_mayer1b413d52007-11-14 01:08:45 +0000482 /* Deprecated instruction sets */
483 /* Original POWER instruction set */
j_mayerf6103492007-11-17 12:01:45 +0000484 PPC_POWER = 0x0000000000000002ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000485 /* POWER2 instruction set extension */
j_mayerf6103492007-11-17 12:01:45 +0000486 PPC_POWER2 = 0x0000000000000004ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000487 /* Power RTC support */
j_mayerf6103492007-11-17 12:01:45 +0000488 PPC_POWER_RTC = 0x0000000000000008ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000489 /* Power-to-PowerPC bridge (601) */
j_mayerf6103492007-11-17 12:01:45 +0000490 PPC_POWER_BR = 0x0000000000000010ULL,
j_mayer12de9a32007-10-05 22:06:02 +0000491 /* 64 bits PowerPC instruction set */
j_mayerf6103492007-11-17 12:01:45 +0000492 PPC_64B = 0x0000000000000020ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000493 /* New 64 bits extensions (PowerPC 2.0x) */
j_mayerf6103492007-11-17 12:01:45 +0000494 PPC_64BX = 0x0000000000000040ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000495 /* 64 bits hypervisor extensions */
j_mayerf6103492007-11-17 12:01:45 +0000496 PPC_64H = 0x0000000000000080ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000497 /* New wait instruction (PowerPC 2.0x) */
j_mayerf6103492007-11-17 12:01:45 +0000498 PPC_WAIT = 0x0000000000000100ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000499 /* Time base mftb instruction */
j_mayerf6103492007-11-17 12:01:45 +0000500 PPC_MFTB = 0x0000000000000200ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000501
502 /* Fixed-point unit extensions */
503 /* PowerPC 602 specific */
j_mayerf6103492007-11-17 12:01:45 +0000504 PPC_602_SPEC = 0x0000000000000400ULL,
j_mayer05332d72007-11-17 22:26:51 +0000505 /* isel instruction */
506 PPC_ISEL = 0x0000000000000800ULL,
507 /* popcntb instruction */
508 PPC_POPCNTB = 0x0000000000001000ULL,
509 /* string load / store */
510 PPC_STRING = 0x0000000000002000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000511
512 /* Floating-point unit extensions */
513 /* Optional floating point instructions */
514 PPC_FLOAT = 0x0000000000010000ULL,
j_mayer12de9a32007-10-05 22:06:02 +0000515 /* New floating-point extensions (PowerPC 2.0x) */
j_mayer1b413d52007-11-14 01:08:45 +0000516 PPC_FLOAT_EXT = 0x0000000000020000ULL,
517 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
518 PPC_FLOAT_FRES = 0x0000000000080000ULL,
519 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
520 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
521 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
522 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
523
524 /* Vector/SIMD extensions */
525 /* Altivec support */
526 PPC_ALTIVEC = 0x0000000001000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000527 /* PowerPC 2.03 SPE extension */
j_mayer05332d72007-11-17 22:26:51 +0000528 PPC_SPE = 0x0000000002000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000529 /* PowerPC 2.03 SPE floating-point extension */
j_mayer05332d72007-11-17 22:26:51 +0000530 PPC_SPEFPU = 0x0000000004000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000531
532 /* Optional memory control instructions */
533 PPC_MEM_TLBIA = 0x0000000010000000ULL,
534 PPC_MEM_TLBIE = 0x0000000020000000ULL,
535 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
536 /* sync instruction */
537 PPC_MEM_SYNC = 0x0000000080000000ULL,
538 /* eieio instruction */
539 PPC_MEM_EIEIO = 0x0000000100000000ULL,
540
541 /* Cache control instructions */
j_mayerc8623f22007-11-19 01:48:51 +0000542 PPC_CACHE = 0x0000000200000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000543 /* icbi instruction */
j_mayer05332d72007-11-17 22:26:51 +0000544 PPC_CACHE_ICBI = 0x0000000400000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000545 /* dcbz instruction with fixed cache line size */
j_mayer05332d72007-11-17 22:26:51 +0000546 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000547 /* dcbz instruction with tunable cache line size */
j_mayer05332d72007-11-17 22:26:51 +0000548 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000549 /* dcba instruction */
j_mayer05332d72007-11-17 22:26:51 +0000550 PPC_CACHE_DCBA = 0x0000002000000000ULL,
551 /* Freescale cache locking instructions */
552 PPC_CACHE_LOCK = 0x0000004000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000553
554 /* MMU related extensions */
555 /* external control instructions */
j_mayer05332d72007-11-17 22:26:51 +0000556 PPC_EXTERN = 0x0000010000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000557 /* segment register access instructions */
j_mayer05332d72007-11-17 22:26:51 +0000558 PPC_SEGMENT = 0x0000020000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000559 /* PowerPC 6xx TLB management instructions */
j_mayer05332d72007-11-17 22:26:51 +0000560 PPC_6xx_TLB = 0x0000040000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000561 /* PowerPC 74xx TLB management instructions */
j_mayer05332d72007-11-17 22:26:51 +0000562 PPC_74xx_TLB = 0x0000080000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000563 /* PowerPC 40x TLB management instructions */
j_mayer05332d72007-11-17 22:26:51 +0000564 PPC_40x_TLB = 0x0000100000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000565 /* segment register access instructions for PowerPC 64 "bridge" */
j_mayer05332d72007-11-17 22:26:51 +0000566 PPC_SEGMENT_64B = 0x0000200000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000567 /* SLB management */
j_mayer05332d72007-11-17 22:26:51 +0000568 PPC_SLBI = 0x0000400000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000569
570 /* Embedded PowerPC dedicated instructions */
j_mayer05332d72007-11-17 22:26:51 +0000571 PPC_WRTEE = 0x0001000000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000572 /* PowerPC 40x exception model */
j_mayer05332d72007-11-17 22:26:51 +0000573 PPC_40x_EXCP = 0x0002000000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000574 /* PowerPC 405 Mac instructions */
j_mayer05332d72007-11-17 22:26:51 +0000575 PPC_405_MAC = 0x0004000000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000576 /* PowerPC 440 specific instructions */
j_mayer05332d72007-11-17 22:26:51 +0000577 PPC_440_SPEC = 0x0008000000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000578 /* BookE (embedded) PowerPC specification */
j_mayer05332d72007-11-17 22:26:51 +0000579 PPC_BOOKE = 0x0010000000000000ULL,
580 /* mfapidi instruction */
581 PPC_MFAPIDI = 0x0020000000000000ULL,
582 /* tlbiva instruction */
583 PPC_TLBIVA = 0x0040000000000000ULL,
584 /* tlbivax instruction */
585 PPC_TLBIVAX = 0x0080000000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000586 /* PowerPC 4xx dedicated instructions */
j_mayer05332d72007-11-17 22:26:51 +0000587 PPC_4xx_COMMON = 0x0100000000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000588 /* PowerPC 40x ibct instructions */
j_mayer05332d72007-11-17 22:26:51 +0000589 PPC_40x_ICBT = 0x0200000000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000590 /* rfmci is not implemented in all BookE PowerPC */
j_mayer05332d72007-11-17 22:26:51 +0000591 PPC_RFMCI = 0x0400000000000000ULL,
592 /* rfdi instruction */
593 PPC_RFDI = 0x0800000000000000ULL,
594 /* DCR accesses */
595 PPC_DCR = 0x1000000000000000ULL,
596 /* DCR extended accesse */
597 PPC_DCRX = 0x2000000000000000ULL,
j_mayer1b413d52007-11-14 01:08:45 +0000598 /* user-mode DCR access, implemented in PowerPC 460 */
j_mayer05332d72007-11-17 22:26:51 +0000599 PPC_DCRUX = 0x4000000000000000ULL,
j_mayera750fc02007-09-26 23:54:22 +0000600};
601
602/*****************************************************************************/
603/* PowerPC instructions table */
bellard3fc6c082005-07-02 20:59:34 +0000604#if HOST_LONG_BITS == 64
605#define OPC_ALIGN 8
606#else
607#define OPC_ALIGN 4
608#endif
bellard1b039c02004-07-12 18:39:45 +0000609#if defined(__APPLE__)
j_mayerd9bce9d2007-03-17 14:02:15 +0000610#define OPCODES_SECTION \
bellard3fc6c082005-07-02 20:59:34 +0000611 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
bellard1b039c02004-07-12 18:39:45 +0000612#else
j_mayerd9bce9d2007-03-17 14:02:15 +0000613#define OPCODES_SECTION \
bellard3fc6c082005-07-02 20:59:34 +0000614 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
bellard933dc6e2004-07-10 15:33:29 +0000615#endif
616
j_mayer76a66252007-03-07 08:32:30 +0000617#if defined(DO_PPC_STATISTICS)
618#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
619OPCODES_SECTION opcode_t opc_##name = { \
620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
623 .pad = { 0, }, \
624 .handler = { \
625 .inval = invl, \
626 .type = _typ, \
627 .handler = &gen_##name, \
628 .oname = stringify(name), \
629 }, \
630 .oname = stringify(name), \
631}
j_mayerc7697e12007-10-26 00:46:07 +0000632#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
633OPCODES_SECTION opcode_t opc_##name = { \
634 .opc1 = op1, \
635 .opc2 = op2, \
636 .opc3 = op3, \
637 .pad = { 0, }, \
638 .handler = { \
639 .inval = invl, \
640 .type = _typ, \
641 .handler = &gen_##name, \
642 .oname = onam, \
643 }, \
644 .oname = onam, \
645}
j_mayer76a66252007-03-07 08:32:30 +0000646#else
bellard79aceca2003-11-23 14:55:54 +0000647#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
bellard18fba282005-02-08 21:24:36 +0000648OPCODES_SECTION opcode_t opc_##name = { \
bellard79aceca2003-11-23 14:55:54 +0000649 .opc1 = op1, \
650 .opc2 = op2, \
651 .opc3 = op3, \
bellard18fba282005-02-08 21:24:36 +0000652 .pad = { 0, }, \
bellard79aceca2003-11-23 14:55:54 +0000653 .handler = { \
654 .inval = invl, \
bellard9a64fbe2004-01-04 22:58:38 +0000655 .type = _typ, \
bellard79aceca2003-11-23 14:55:54 +0000656 .handler = &gen_##name, \
657 }, \
bellard3fc6c082005-07-02 20:59:34 +0000658 .oname = stringify(name), \
bellard79aceca2003-11-23 14:55:54 +0000659}
j_mayerc7697e12007-10-26 00:46:07 +0000660#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
661OPCODES_SECTION opcode_t opc_##name = { \
662 .opc1 = op1, \
663 .opc2 = op2, \
664 .opc3 = op3, \
665 .pad = { 0, }, \
666 .handler = { \
667 .inval = invl, \
668 .type = _typ, \
669 .handler = &gen_##name, \
670 }, \
671 .oname = onam, \
672}
j_mayer76a66252007-03-07 08:32:30 +0000673#endif
bellard79aceca2003-11-23 14:55:54 +0000674
675#define GEN_OPCODE_MARK(name) \
bellard18fba282005-02-08 21:24:36 +0000676OPCODES_SECTION opcode_t opc_##name = { \
bellard79aceca2003-11-23 14:55:54 +0000677 .opc1 = 0xFF, \
678 .opc2 = 0xFF, \
679 .opc3 = 0xFF, \
bellard18fba282005-02-08 21:24:36 +0000680 .pad = { 0, }, \
bellard79aceca2003-11-23 14:55:54 +0000681 .handler = { \
682 .inval = 0x00000000, \
bellard9a64fbe2004-01-04 22:58:38 +0000683 .type = 0x00, \
bellard79aceca2003-11-23 14:55:54 +0000684 .handler = NULL, \
685 }, \
bellard3fc6c082005-07-02 20:59:34 +0000686 .oname = stringify(name), \
bellard79aceca2003-11-23 14:55:54 +0000687}
688
689/* Start opcode list */
690GEN_OPCODE_MARK(start);
691
692/* Invalid instruction */
bellard9a64fbe2004-01-04 22:58:38 +0000693GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
bellard79aceca2003-11-23 14:55:54 +0000694{
j_mayere1833e12007-09-29 13:06:16 +0000695 GEN_EXCP_INVAL(ctx);
bellard9a64fbe2004-01-04 22:58:38 +0000696}
697
bellard79aceca2003-11-23 14:55:54 +0000698static opc_handler_t invalid_handler = {
699 .inval = 0xFFFFFFFF,
bellard9a64fbe2004-01-04 22:58:38 +0000700 .type = PPC_NONE,
bellard79aceca2003-11-23 14:55:54 +0000701 .handler = gen_invalid,
702};
703
aurel32e1571902008-10-21 11:31:14 +0000704/*** Integer comparison ***/
705
aurel32ea363692008-10-27 22:50:39 +0000706static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
aurel32e1571902008-10-21 11:31:14 +0000707{
708 int l1, l2, l3;
709
aurel32269f3e92008-11-01 00:53:48 +0000710 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
711 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
aurel32e1571902008-10-21 11:31:14 +0000712 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
713
714 l1 = gen_new_label();
715 l2 = gen_new_label();
716 l3 = gen_new_label();
717 if (s) {
aurel32ea363692008-10-27 22:50:39 +0000718 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
719 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
aurel32e1571902008-10-21 11:31:14 +0000720 } else {
aurel32ea363692008-10-27 22:50:39 +0000721 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
aurel32e1571902008-10-21 11:31:14 +0000723 }
724 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
725 tcg_gen_br(l3);
726 gen_set_label(l1);
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
728 tcg_gen_br(l3);
729 gen_set_label(l2);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
731 gen_set_label(l3);
732}
733
aurel32ea363692008-10-27 22:50:39 +0000734static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
aurel32e1571902008-10-21 11:31:14 +0000735{
aurel32ea363692008-10-27 22:50:39 +0000736 TCGv t0 = tcg_const_local_tl(arg1);
737 gen_op_cmp(arg0, t0, s, crf);
738 tcg_temp_free(t0);
aurel32e1571902008-10-21 11:31:14 +0000739}
740
741#if defined(TARGET_PPC64)
aurel32ea363692008-10-27 22:50:39 +0000742static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
aurel32e1571902008-10-21 11:31:14 +0000743{
aurel32ea363692008-10-27 22:50:39 +0000744 TCGv t0, t1;
745 t0 = tcg_temp_local_new(TCG_TYPE_TL);
746 t1 = tcg_temp_local_new(TCG_TYPE_TL);
aurel32e1571902008-10-21 11:31:14 +0000747 if (s) {
aurel32ea363692008-10-27 22:50:39 +0000748 tcg_gen_ext32s_tl(t0, arg0);
749 tcg_gen_ext32s_tl(t1, arg1);
aurel32e1571902008-10-21 11:31:14 +0000750 } else {
aurel32ea363692008-10-27 22:50:39 +0000751 tcg_gen_ext32u_tl(t0, arg0);
752 tcg_gen_ext32u_tl(t1, arg1);
aurel32e1571902008-10-21 11:31:14 +0000753 }
aurel32ea363692008-10-27 22:50:39 +0000754 gen_op_cmp(t0, t1, s, crf);
755 tcg_temp_free(t1);
756 tcg_temp_free(t0);
aurel32e1571902008-10-21 11:31:14 +0000757}
758
aurel32ea363692008-10-27 22:50:39 +0000759static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
aurel32e1571902008-10-21 11:31:14 +0000760{
aurel32ea363692008-10-27 22:50:39 +0000761 TCGv t0 = tcg_const_local_tl(arg1);
762 gen_op_cmp32(arg0, t0, s, crf);
763 tcg_temp_free(t0);
aurel32e1571902008-10-21 11:31:14 +0000764}
765#endif
766
767static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
768{
769#if defined(TARGET_PPC64)
770 if (!(ctx->sf_mode))
771 gen_op_cmpi32(reg, 0, 1, 0);
772 else
773#endif
774 gen_op_cmpi(reg, 0, 1, 0);
775}
776
777/* cmp */
778GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
779{
780#if defined(TARGET_PPC64)
781 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
782 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
783 1, crfD(ctx->opcode));
784 else
785#endif
786 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
787 1, crfD(ctx->opcode));
788}
789
790/* cmpi */
791GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
792{
793#if defined(TARGET_PPC64)
794 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
795 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
796 1, crfD(ctx->opcode));
797 else
798#endif
799 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
800 1, crfD(ctx->opcode));
801}
802
803/* cmpl */
804GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
805{
806#if defined(TARGET_PPC64)
807 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
808 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
809 0, crfD(ctx->opcode));
810 else
811#endif
812 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
813 0, crfD(ctx->opcode));
814}
815
816/* cmpli */
817GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
818{
819#if defined(TARGET_PPC64)
820 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
821 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
822 0, crfD(ctx->opcode));
823 else
824#endif
825 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
826 0, crfD(ctx->opcode));
827}
828
829/* isel (PowerPC 2.03 specification) */
830GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
831{
832 int l1, l2;
833 uint32_t bi = rC(ctx->opcode);
834 uint32_t mask;
835 TCGv temp;
836
837 l1 = gen_new_label();
838 l2 = gen_new_label();
839
840 mask = 1 << (3 - (bi & 0x03));
841 temp = tcg_temp_new(TCG_TYPE_I32);
842 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
843 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
844 if (rA(ctx->opcode) == 0)
845 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
846 else
847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
848 tcg_gen_br(l2);
849 gen_set_label(l1);
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
851 gen_set_label(l2);
852}
853
bellard79aceca2003-11-23 14:55:54 +0000854/*** Integer arithmetic ***/
j_mayerd9bce9d2007-03-17 14:02:15 +0000855#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
856GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
bellard79aceca2003-11-23 14:55:54 +0000857{ \
aurel32f78fb442008-09-04 05:25:47 +0000858 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
859 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
bellard79aceca2003-11-23 14:55:54 +0000860 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +0000861 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
j_mayer76a66252007-03-07 08:32:30 +0000862 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel32e1571902008-10-21 11:31:14 +0000863 gen_set_Rc0(ctx, cpu_T[0]); \
bellard79aceca2003-11-23 14:55:54 +0000864}
865
j_mayerd9bce9d2007-03-17 14:02:15 +0000866#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
867GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
bellard79aceca2003-11-23 14:55:54 +0000868{ \
aurel32f78fb442008-09-04 05:25:47 +0000869 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
870 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
bellard79aceca2003-11-23 14:55:54 +0000871 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +0000872 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
j_mayer76a66252007-03-07 08:32:30 +0000873 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel32e1571902008-10-21 11:31:14 +0000874 gen_set_Rc0(ctx, cpu_T[0]); \
bellard79aceca2003-11-23 14:55:54 +0000875}
876
j_mayerd9bce9d2007-03-17 14:02:15 +0000877#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
878GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
bellard79aceca2003-11-23 14:55:54 +0000879{ \
aurel32f78fb442008-09-04 05:25:47 +0000880 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
bellard79aceca2003-11-23 14:55:54 +0000881 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +0000882 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
j_mayer76a66252007-03-07 08:32:30 +0000883 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel32e1571902008-10-21 11:31:14 +0000884 gen_set_Rc0(ctx, cpu_T[0]); \
bellard79aceca2003-11-23 14:55:54 +0000885}
j_mayerd9bce9d2007-03-17 14:02:15 +0000886#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
887GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
bellard79aceca2003-11-23 14:55:54 +0000888{ \
aurel32f78fb442008-09-04 05:25:47 +0000889 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
bellard79aceca2003-11-23 14:55:54 +0000890 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +0000891 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
j_mayer76a66252007-03-07 08:32:30 +0000892 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel32e1571902008-10-21 11:31:14 +0000893 gen_set_Rc0(ctx, cpu_T[0]); \
bellard79aceca2003-11-23 14:55:54 +0000894}
895
896/* Two operands arithmetic functions */
j_mayerd9bce9d2007-03-17 14:02:15 +0000897#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
898__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
899__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
bellard79aceca2003-11-23 14:55:54 +0000900
901/* Two operands arithmetic functions with no overflow allowed */
j_mayerd9bce9d2007-03-17 14:02:15 +0000902#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
903__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
bellard79aceca2003-11-23 14:55:54 +0000904
905/* One operand arithmetic functions */
j_mayerd9bce9d2007-03-17 14:02:15 +0000906#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
907__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
908__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
909
910#if defined(TARGET_PPC64)
911#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
912GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
913{ \
aurel32f78fb442008-09-04 05:25:47 +0000914 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
915 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000916 if (ctx->sf_mode) \
917 gen_op_##name##_64(); \
918 else \
919 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +0000920 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000921 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel32e1571902008-10-21 11:31:14 +0000922 gen_set_Rc0(ctx, cpu_T[0]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000923}
924
925#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
926GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
927{ \
aurel32f78fb442008-09-04 05:25:47 +0000928 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
929 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000930 if (ctx->sf_mode) \
931 gen_op_##name##_64(); \
932 else \
933 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +0000934 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000935 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel32e1571902008-10-21 11:31:14 +0000936 gen_set_Rc0(ctx, cpu_T[0]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000937}
938
939#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
940GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
941{ \
aurel32f78fb442008-09-04 05:25:47 +0000942 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000943 if (ctx->sf_mode) \
944 gen_op_##name##_64(); \
945 else \
946 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +0000947 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000948 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel32e1571902008-10-21 11:31:14 +0000949 gen_set_Rc0(ctx, cpu_T[0]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000950}
951#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
952GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
953{ \
aurel32f78fb442008-09-04 05:25:47 +0000954 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000955 if (ctx->sf_mode) \
956 gen_op_##name##_64(); \
957 else \
958 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +0000959 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000960 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel32e1571902008-10-21 11:31:14 +0000961 gen_set_Rc0(ctx, cpu_T[0]); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000962}
963
964/* Two operands arithmetic functions */
965#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
966__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
967__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
968
969/* Two operands arithmetic functions with no overflow allowed */
970#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
971__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
972
973/* One operand arithmetic functions */
974#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
975__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
976__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
977#else
978#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
979#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
980#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
981#endif
bellard79aceca2003-11-23 14:55:54 +0000982
983/* add add. addo addo. */
aurel3239dd32e2008-09-05 14:19:43 +0000984static always_inline void gen_op_add (void)
985{
986 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
987}
j_mayerb068d6a2007-10-07 17:13:44 +0000988static always_inline void gen_op_addo (void)
j_mayerd9bce9d2007-03-17 14:02:15 +0000989{
aurel32e55fd932008-09-02 16:19:05 +0000990 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
aurel3239dd32e2008-09-05 14:19:43 +0000991 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
j_mayerd9bce9d2007-03-17 14:02:15 +0000992 gen_op_check_addo();
993}
994#if defined(TARGET_PPC64)
995#define gen_op_add_64 gen_op_add
j_mayerb068d6a2007-10-07 17:13:44 +0000996static always_inline void gen_op_addo_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +0000997{
aurel32e55fd932008-09-02 16:19:05 +0000998 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
aurel3239dd32e2008-09-05 14:19:43 +0000999 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001000 gen_op_check_addo_64();
1001}
1002#endif
1003GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001004/* addc addc. addco addco. */
j_mayerb068d6a2007-10-07 17:13:44 +00001005static always_inline void gen_op_addc (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001006{
aurel32e55fd932008-09-02 16:19:05 +00001007 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
aurel3239dd32e2008-09-05 14:19:43 +00001008 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001009 gen_op_check_addc();
1010}
j_mayerb068d6a2007-10-07 17:13:44 +00001011static always_inline void gen_op_addco (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001012{
aurel32e55fd932008-09-02 16:19:05 +00001013 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
aurel3239dd32e2008-09-05 14:19:43 +00001014 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001015 gen_op_check_addc();
1016 gen_op_check_addo();
1017}
1018#if defined(TARGET_PPC64)
j_mayerb068d6a2007-10-07 17:13:44 +00001019static always_inline void gen_op_addc_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001020{
aurel32e55fd932008-09-02 16:19:05 +00001021 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
aurel3239dd32e2008-09-05 14:19:43 +00001022 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001023 gen_op_check_addc_64();
1024}
j_mayerb068d6a2007-10-07 17:13:44 +00001025static always_inline void gen_op_addco_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001026{
aurel32e55fd932008-09-02 16:19:05 +00001027 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
aurel3239dd32e2008-09-05 14:19:43 +00001028 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001029 gen_op_check_addc_64();
1030 gen_op_check_addo_64();
1031}
1032#endif
1033GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001034/* adde adde. addeo addeo. */
j_mayerb068d6a2007-10-07 17:13:44 +00001035static always_inline void gen_op_addeo (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001036{
aurel32e55fd932008-09-02 16:19:05 +00001037 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001038 gen_op_adde();
1039 gen_op_check_addo();
1040}
1041#if defined(TARGET_PPC64)
j_mayerb068d6a2007-10-07 17:13:44 +00001042static always_inline void gen_op_addeo_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001043{
aurel32e55fd932008-09-02 16:19:05 +00001044 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001045 gen_op_adde_64();
1046 gen_op_check_addo_64();
1047}
1048#endif
1049GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001050/* addme addme. addmeo addmeo. */
j_mayerb068d6a2007-10-07 17:13:44 +00001051static always_inline void gen_op_addme (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001052{
aurel32e55fd932008-09-02 16:19:05 +00001053 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001054 gen_op_add_me();
1055}
1056#if defined(TARGET_PPC64)
j_mayerb068d6a2007-10-07 17:13:44 +00001057static always_inline void gen_op_addme_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001058{
aurel32e55fd932008-09-02 16:19:05 +00001059 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001060 gen_op_add_me_64();
1061}
1062#endif
1063GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001064/* addze addze. addzeo addzeo. */
j_mayerb068d6a2007-10-07 17:13:44 +00001065static always_inline void gen_op_addze (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001066{
aurel32e55fd932008-09-02 16:19:05 +00001067 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001068 gen_op_add_ze();
1069 gen_op_check_addc();
1070}
j_mayerb068d6a2007-10-07 17:13:44 +00001071static always_inline void gen_op_addzeo (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001072{
aurel32e55fd932008-09-02 16:19:05 +00001073 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001074 gen_op_add_ze();
1075 gen_op_check_addc();
1076 gen_op_check_addo();
1077}
1078#if defined(TARGET_PPC64)
j_mayerb068d6a2007-10-07 17:13:44 +00001079static always_inline void gen_op_addze_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001080{
aurel32e55fd932008-09-02 16:19:05 +00001081 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001082 gen_op_add_ze();
1083 gen_op_check_addc_64();
1084}
j_mayerb068d6a2007-10-07 17:13:44 +00001085static always_inline void gen_op_addzeo_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001086{
aurel32e55fd932008-09-02 16:19:05 +00001087 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001088 gen_op_add_ze();
1089 gen_op_check_addc_64();
1090 gen_op_check_addo_64();
1091}
1092#endif
1093GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001094/* divw divw. divwo divwo. */
j_mayerd9bce9d2007-03-17 14:02:15 +00001095GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001096/* divwu divwu. divwuo divwuo. */
j_mayerd9bce9d2007-03-17 14:02:15 +00001097GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001098/* mulhw mulhw. */
j_mayerd9bce9d2007-03-17 14:02:15 +00001099GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001100/* mulhwu mulhwu. */
j_mayerd9bce9d2007-03-17 14:02:15 +00001101GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001102/* mullw mullw. mullwo mullwo. */
j_mayerd9bce9d2007-03-17 14:02:15 +00001103GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001104/* neg neg. nego nego. */
j_mayerd9bce9d2007-03-17 14:02:15 +00001105GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001106/* subf subf. subfo subfo. */
aurel327c417962008-09-05 14:19:51 +00001107static always_inline void gen_op_subf (void)
1108{
1109 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1110}
j_mayerb068d6a2007-10-07 17:13:44 +00001111static always_inline void gen_op_subfo (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001112{
aurel32f0413472008-09-02 23:26:40 +00001113 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
aurel327c417962008-09-05 14:19:51 +00001114 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
j_mayerc3e10c72007-11-11 00:18:34 +00001115 gen_op_check_addo();
j_mayerd9bce9d2007-03-17 14:02:15 +00001116}
1117#if defined(TARGET_PPC64)
1118#define gen_op_subf_64 gen_op_subf
j_mayerb068d6a2007-10-07 17:13:44 +00001119static always_inline void gen_op_subfo_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001120{
aurel32f0413472008-09-02 23:26:40 +00001121 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
aurel327c417962008-09-05 14:19:51 +00001122 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
j_mayerc3e10c72007-11-11 00:18:34 +00001123 gen_op_check_addo_64();
j_mayerd9bce9d2007-03-17 14:02:15 +00001124}
1125#endif
1126GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001127/* subfc subfc. subfco subfco. */
j_mayerb068d6a2007-10-07 17:13:44 +00001128static always_inline void gen_op_subfc (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001129{
aurel327c417962008-09-05 14:19:51 +00001130 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001131 gen_op_check_subfc();
1132}
j_mayerb068d6a2007-10-07 17:13:44 +00001133static always_inline void gen_op_subfco (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001134{
aurel32f0413472008-09-02 23:26:40 +00001135 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
aurel327c417962008-09-05 14:19:51 +00001136 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001137 gen_op_check_subfc();
j_mayerc3e10c72007-11-11 00:18:34 +00001138 gen_op_check_addo();
j_mayerd9bce9d2007-03-17 14:02:15 +00001139}
1140#if defined(TARGET_PPC64)
j_mayerb068d6a2007-10-07 17:13:44 +00001141static always_inline void gen_op_subfc_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001142{
aurel327c417962008-09-05 14:19:51 +00001143 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001144 gen_op_check_subfc_64();
1145}
j_mayerb068d6a2007-10-07 17:13:44 +00001146static always_inline void gen_op_subfco_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001147{
aurel32f0413472008-09-02 23:26:40 +00001148 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
aurel327c417962008-09-05 14:19:51 +00001149 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001150 gen_op_check_subfc_64();
j_mayerc3e10c72007-11-11 00:18:34 +00001151 gen_op_check_addo_64();
j_mayerd9bce9d2007-03-17 14:02:15 +00001152}
1153#endif
1154GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001155/* subfe subfe. subfeo subfeo. */
j_mayerb068d6a2007-10-07 17:13:44 +00001156static always_inline void gen_op_subfeo (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001157{
aurel32f0413472008-09-02 23:26:40 +00001158 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001159 gen_op_subfe();
j_mayerc3e10c72007-11-11 00:18:34 +00001160 gen_op_check_addo();
j_mayerd9bce9d2007-03-17 14:02:15 +00001161}
1162#if defined(TARGET_PPC64)
1163#define gen_op_subfe_64 gen_op_subfe
j_mayerb068d6a2007-10-07 17:13:44 +00001164static always_inline void gen_op_subfeo_64 (void)
j_mayerd9bce9d2007-03-17 14:02:15 +00001165{
aurel32f0413472008-09-02 23:26:40 +00001166 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001167 gen_op_subfe_64();
j_mayerc3e10c72007-11-11 00:18:34 +00001168 gen_op_check_addo_64();
j_mayerd9bce9d2007-03-17 14:02:15 +00001169}
1170#endif
1171GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001172/* subfme subfme. subfmeo subfmeo. */
j_mayerd9bce9d2007-03-17 14:02:15 +00001173GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001174/* subfze subfze. subfzeo subfzeo. */
j_mayerd9bce9d2007-03-17 14:02:15 +00001175GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001176/* addi */
1177GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1178{
j_mayer76a66252007-03-07 08:32:30 +00001179 target_long simm = SIMM(ctx->opcode);
bellard79aceca2003-11-23 14:55:54 +00001180
1181 if (rA(ctx->opcode) == 0) {
j_mayer76a66252007-03-07 08:32:30 +00001182 /* li case */
aurel3202f4f6c2008-09-02 16:18:55 +00001183 tcg_gen_movi_tl(cpu_T[0], simm);
bellard79aceca2003-11-23 14:55:54 +00001184 } else {
aurel32f78fb442008-09-04 05:25:47 +00001185 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00001186 if (likely(simm != 0))
aurel3239dd32e2008-09-05 14:19:43 +00001187 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
bellard79aceca2003-11-23 14:55:54 +00001188 }
aurel32f78fb442008-09-04 05:25:47 +00001189 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
bellard79aceca2003-11-23 14:55:54 +00001190}
1191/* addic */
1192GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1193{
j_mayer76a66252007-03-07 08:32:30 +00001194 target_long simm = SIMM(ctx->opcode);
1195
aurel32f78fb442008-09-04 05:25:47 +00001196 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001197 if (likely(simm != 0)) {
aurel32e55fd932008-09-02 16:19:05 +00001198 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
aurel3239dd32e2008-09-05 14:19:43 +00001199 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
j_mayerd9bce9d2007-03-17 14:02:15 +00001200#if defined(TARGET_PPC64)
1201 if (ctx->sf_mode)
1202 gen_op_check_addc_64();
1203 else
1204#endif
1205 gen_op_check_addc();
j_mayere864cab2007-03-22 22:17:08 +00001206 } else {
aurel323d7b4172008-10-21 11:28:46 +00001207 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
j_mayerd9bce9d2007-03-17 14:02:15 +00001208 }
aurel32f78fb442008-09-04 05:25:47 +00001209 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
bellard79aceca2003-11-23 14:55:54 +00001210}
1211/* addic. */
j_mayerc7697e12007-10-26 00:46:07 +00001212GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
bellard79aceca2003-11-23 14:55:54 +00001213{
j_mayer76a66252007-03-07 08:32:30 +00001214 target_long simm = SIMM(ctx->opcode);
1215
aurel32f78fb442008-09-04 05:25:47 +00001216 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001217 if (likely(simm != 0)) {
aurel32e55fd932008-09-02 16:19:05 +00001218 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
aurel3239dd32e2008-09-05 14:19:43 +00001219 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
j_mayerd9bce9d2007-03-17 14:02:15 +00001220#if defined(TARGET_PPC64)
1221 if (ctx->sf_mode)
1222 gen_op_check_addc_64();
1223 else
1224#endif
1225 gen_op_check_addc();
j_mayer966439a2007-09-17 09:51:40 +00001226 } else {
aurel323d7b4172008-10-21 11:28:46 +00001227 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
j_mayerd9bce9d2007-03-17 14:02:15 +00001228 }
aurel32f78fb442008-09-04 05:25:47 +00001229 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
aurel32e1571902008-10-21 11:31:14 +00001230 gen_set_Rc0(ctx, cpu_T[0]);
bellard79aceca2003-11-23 14:55:54 +00001231}
1232/* addis */
1233GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1234{
j_mayer76a66252007-03-07 08:32:30 +00001235 target_long simm = SIMM(ctx->opcode);
bellard79aceca2003-11-23 14:55:54 +00001236
1237 if (rA(ctx->opcode) == 0) {
j_mayer76a66252007-03-07 08:32:30 +00001238 /* lis case */
aurel3202f4f6c2008-09-02 16:18:55 +00001239 tcg_gen_movi_tl(cpu_T[0], simm << 16);
bellard79aceca2003-11-23 14:55:54 +00001240 } else {
aurel32f78fb442008-09-04 05:25:47 +00001241 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00001242 if (likely(simm != 0))
aurel3239dd32e2008-09-05 14:19:43 +00001243 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16);
bellard79aceca2003-11-23 14:55:54 +00001244 }
aurel32f78fb442008-09-04 05:25:47 +00001245 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
bellard79aceca2003-11-23 14:55:54 +00001246}
1247/* mulli */
1248GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1249{
aurel32f78fb442008-09-04 05:25:47 +00001250 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001251 gen_op_mulli(SIMM(ctx->opcode));
aurel32f78fb442008-09-04 05:25:47 +00001252 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
bellard79aceca2003-11-23 14:55:54 +00001253}
1254/* subfic */
1255GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1256{
aurel32f78fb442008-09-04 05:25:47 +00001257 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001258#if defined(TARGET_PPC64)
1259 if (ctx->sf_mode)
1260 gen_op_subfic_64(SIMM(ctx->opcode));
1261 else
1262#endif
1263 gen_op_subfic(SIMM(ctx->opcode));
aurel32f78fb442008-09-04 05:25:47 +00001264 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
bellard79aceca2003-11-23 14:55:54 +00001265}
1266
j_mayerd9bce9d2007-03-17 14:02:15 +00001267#if defined(TARGET_PPC64)
1268/* mulhd mulhd. */
j_mayera750fc02007-09-26 23:54:22 +00001269GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00001270/* mulhdu mulhdu. */
j_mayera750fc02007-09-26 23:54:22 +00001271GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00001272/* mulld mulld. mulldo mulldo. */
j_mayera750fc02007-09-26 23:54:22 +00001273GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00001274/* divd divd. divdo divdo. */
j_mayera750fc02007-09-26 23:54:22 +00001275GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00001276/* divdu divdu. divduo divduo. */
j_mayera750fc02007-09-26 23:54:22 +00001277GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00001278#endif
1279
bellard79aceca2003-11-23 14:55:54 +00001280/*** Integer logical ***/
aurel3226d67362008-10-21 11:31:27 +00001281#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1282GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
bellard79aceca2003-11-23 14:55:54 +00001283{ \
aurel3226d67362008-10-21 11:31:27 +00001284 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1285 cpu_gpr[rB(ctx->opcode)]); \
j_mayer76a66252007-03-07 08:32:30 +00001286 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel3226d67362008-10-21 11:31:27 +00001287 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
bellard79aceca2003-11-23 14:55:54 +00001288}
bellard79aceca2003-11-23 14:55:54 +00001289
aurel3226d67362008-10-21 11:31:27 +00001290#define GEN_LOGICAL1(name, tcg_op, opc, type) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001291GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
bellard79aceca2003-11-23 14:55:54 +00001292{ \
aurel3226d67362008-10-21 11:31:27 +00001293 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
j_mayer76a66252007-03-07 08:32:30 +00001294 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel3226d67362008-10-21 11:31:27 +00001295 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
bellard79aceca2003-11-23 14:55:54 +00001296}
1297
1298/* and & and. */
aurel3226d67362008-10-21 11:31:27 +00001299GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001300/* andc & andc. */
aurel3226d67362008-10-21 11:31:27 +00001301GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001302/* andi. */
j_mayerc7697e12007-10-26 00:46:07 +00001303GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
bellard79aceca2003-11-23 14:55:54 +00001304{
aurel3226d67362008-10-21 11:31:27 +00001305 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1306 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001307}
1308/* andis. */
j_mayerc7697e12007-10-26 00:46:07 +00001309GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
bellard79aceca2003-11-23 14:55:54 +00001310{
aurel3226d67362008-10-21 11:31:27 +00001311 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1312 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001313}
bellard79aceca2003-11-23 14:55:54 +00001314/* cntlzw */
aurel3226d67362008-10-21 11:31:27 +00001315GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1316{
1317 tcg_gen_helper_1_1(helper_cntlzw, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1318 if (unlikely(Rc(ctx->opcode) != 0))
pbrook2e31f5d2008-10-24 12:03:16 +00001319 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
aurel3226d67362008-10-21 11:31:27 +00001320}
bellard79aceca2003-11-23 14:55:54 +00001321/* eqv & eqv. */
aurel3226d67362008-10-21 11:31:27 +00001322GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001323/* extsb & extsb. */
aurel3226d67362008-10-21 11:31:27 +00001324GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001325/* extsh & extsh. */
aurel3226d67362008-10-21 11:31:27 +00001326GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001327/* nand & nand. */
aurel3226d67362008-10-21 11:31:27 +00001328GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001329/* nor & nor. */
aurel3226d67362008-10-21 11:31:27 +00001330GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001331/* or & or. */
bellard9a64fbe2004-01-04 22:58:38 +00001332GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1333{
j_mayer76a66252007-03-07 08:32:30 +00001334 int rs, ra, rb;
1335
1336 rs = rS(ctx->opcode);
1337 ra = rA(ctx->opcode);
1338 rb = rB(ctx->opcode);
1339 /* Optimisation for mr. ri case */
1340 if (rs != ra || rs != rb) {
aurel3226d67362008-10-21 11:31:27 +00001341 if (rs != rb)
1342 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1343 else
1344 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
j_mayer76a66252007-03-07 08:32:30 +00001345 if (unlikely(Rc(ctx->opcode) != 0))
aurel3226d67362008-10-21 11:31:27 +00001346 gen_set_Rc0(ctx, cpu_gpr[ra]);
j_mayer76a66252007-03-07 08:32:30 +00001347 } else if (unlikely(Rc(ctx->opcode) != 0)) {
aurel3226d67362008-10-21 11:31:27 +00001348 gen_set_Rc0(ctx, cpu_gpr[rs]);
j_mayerc80f84e2007-09-30 01:18:26 +00001349#if defined(TARGET_PPC64)
1350 } else {
aurel3226d67362008-10-21 11:31:27 +00001351 int prio = 0;
1352
j_mayerc80f84e2007-09-30 01:18:26 +00001353 switch (rs) {
1354 case 1:
1355 /* Set process priority to low */
aurel3226d67362008-10-21 11:31:27 +00001356 prio = 2;
j_mayerc80f84e2007-09-30 01:18:26 +00001357 break;
1358 case 6:
1359 /* Set process priority to medium-low */
aurel3226d67362008-10-21 11:31:27 +00001360 prio = 3;
j_mayerc80f84e2007-09-30 01:18:26 +00001361 break;
1362 case 2:
1363 /* Set process priority to normal */
aurel3226d67362008-10-21 11:31:27 +00001364 prio = 4;
j_mayerc80f84e2007-09-30 01:18:26 +00001365 break;
j_mayerbe147d02007-09-30 13:03:23 +00001366#if !defined(CONFIG_USER_ONLY)
1367 case 31:
1368 if (ctx->supervisor > 0) {
1369 /* Set process priority to very low */
aurel3226d67362008-10-21 11:31:27 +00001370 prio = 1;
j_mayerbe147d02007-09-30 13:03:23 +00001371 }
1372 break;
1373 case 5:
1374 if (ctx->supervisor > 0) {
1375 /* Set process priority to medium-hight */
aurel3226d67362008-10-21 11:31:27 +00001376 prio = 5;
j_mayerbe147d02007-09-30 13:03:23 +00001377 }
1378 break;
1379 case 3:
1380 if (ctx->supervisor > 0) {
1381 /* Set process priority to high */
aurel3226d67362008-10-21 11:31:27 +00001382 prio = 6;
j_mayerbe147d02007-09-30 13:03:23 +00001383 }
1384 break;
j_mayerbe147d02007-09-30 13:03:23 +00001385 case 7:
1386 if (ctx->supervisor > 1) {
1387 /* Set process priority to very high */
aurel3226d67362008-10-21 11:31:27 +00001388 prio = 7;
j_mayerbe147d02007-09-30 13:03:23 +00001389 }
1390 break;
1391#endif
j_mayerc80f84e2007-09-30 01:18:26 +00001392 default:
1393 /* nop */
1394 break;
1395 }
aurel3226d67362008-10-21 11:31:27 +00001396 if (prio) {
aurel32ea363692008-10-27 22:50:39 +00001397 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1398 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1399 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1400 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1401 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1402 tcg_temp_free(t0);
aurel3226d67362008-10-21 11:31:27 +00001403 }
j_mayerc80f84e2007-09-30 01:18:26 +00001404#endif
bellard9a64fbe2004-01-04 22:58:38 +00001405 }
bellard9a64fbe2004-01-04 22:58:38 +00001406}
bellard79aceca2003-11-23 14:55:54 +00001407/* orc & orc. */
aurel3226d67362008-10-21 11:31:27 +00001408GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001409/* xor & xor. */
bellard9a64fbe2004-01-04 22:58:38 +00001410GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1411{
bellard9a64fbe2004-01-04 22:58:38 +00001412 /* Optimisation for "set to zero" case */
aurel3226d67362008-10-21 11:31:27 +00001413 if (rS(ctx->opcode) != rB(ctx->opcode))
aurel32312179c2008-10-27 22:50:31 +00001414 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
aurel3226d67362008-10-21 11:31:27 +00001415 else
1416 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
j_mayer76a66252007-03-07 08:32:30 +00001417 if (unlikely(Rc(ctx->opcode) != 0))
aurel3226d67362008-10-21 11:31:27 +00001418 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard9a64fbe2004-01-04 22:58:38 +00001419}
bellard79aceca2003-11-23 14:55:54 +00001420/* ori */
1421GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1422{
j_mayer76a66252007-03-07 08:32:30 +00001423 target_ulong uimm = UIMM(ctx->opcode);
bellard79aceca2003-11-23 14:55:54 +00001424
bellard9a64fbe2004-01-04 22:58:38 +00001425 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1426 /* NOP */
j_mayer76a66252007-03-07 08:32:30 +00001427 /* XXX: should handle special NOPs for POWER series */
bellard9a64fbe2004-01-04 22:58:38 +00001428 return;
j_mayer76a66252007-03-07 08:32:30 +00001429 }
aurel3226d67362008-10-21 11:31:27 +00001430 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
bellard79aceca2003-11-23 14:55:54 +00001431}
1432/* oris */
1433GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1434{
j_mayer76a66252007-03-07 08:32:30 +00001435 target_ulong uimm = UIMM(ctx->opcode);
bellard9a64fbe2004-01-04 22:58:38 +00001436
1437 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1438 /* NOP */
1439 return;
1440 }
aurel3226d67362008-10-21 11:31:27 +00001441 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
j_mayer76a66252007-03-07 08:32:30 +00001442}
1443/* xori */
1444GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1445{
1446 target_ulong uimm = UIMM(ctx->opcode);
1447
1448 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1449 /* NOP */
1450 return;
1451 }
aurel3226d67362008-10-21 11:31:27 +00001452 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
bellard79aceca2003-11-23 14:55:54 +00001453}
bellard79aceca2003-11-23 14:55:54 +00001454/* xoris */
1455GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1456{
j_mayer76a66252007-03-07 08:32:30 +00001457 target_ulong uimm = UIMM(ctx->opcode);
bellard9a64fbe2004-01-04 22:58:38 +00001458
1459 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1460 /* NOP */
1461 return;
1462 }
aurel3226d67362008-10-21 11:31:27 +00001463 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
bellard79aceca2003-11-23 14:55:54 +00001464}
j_mayerd9bce9d2007-03-17 14:02:15 +00001465/* popcntb : PowerPC 2.03 specification */
j_mayer05332d72007-11-17 22:26:51 +00001466GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
j_mayerd9bce9d2007-03-17 14:02:15 +00001467{
j_mayerd9bce9d2007-03-17 14:02:15 +00001468#if defined(TARGET_PPC64)
1469 if (ctx->sf_mode)
aurel3226d67362008-10-21 11:31:27 +00001470 tcg_gen_helper_1_1(helper_popcntb_64, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001471 else
1472#endif
aurel3226d67362008-10-21 11:31:27 +00001473 tcg_gen_helper_1_1(helper_popcntb, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001474}
1475
1476#if defined(TARGET_PPC64)
1477/* extsw & extsw. */
aurel3226d67362008-10-21 11:31:27 +00001478GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00001479/* cntlzd */
aurel3226d67362008-10-21 11:31:27 +00001480GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1481{
1482 tcg_gen_helper_1_1(helper_cntlzd, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1483 if (unlikely(Rc(ctx->opcode) != 0))
1484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1485}
j_mayerd9bce9d2007-03-17 14:02:15 +00001486#endif
1487
bellard79aceca2003-11-23 14:55:54 +00001488/*** Integer rotate ***/
1489/* rlwimi & rlwimi. */
1490GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1491{
j_mayer76a66252007-03-07 08:32:30 +00001492 uint32_t mb, me, sh;
bellard79aceca2003-11-23 14:55:54 +00001493
1494 mb = MB(ctx->opcode);
1495 me = ME(ctx->opcode);
j_mayer76a66252007-03-07 08:32:30 +00001496 sh = SH(ctx->opcode);
aurel32d03ef512008-10-27 22:50:22 +00001497 if (likely(sh == 0 && mb == 0 && me == 31)) {
1498 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1499 } else {
1500 TCGv t0, t1;
1501 target_ulong mask;
1502
1503 t0 = tcg_temp_new(TCG_TYPE_TL);
1504 t1 = tcg_temp_new(TCG_TYPE_TL);
1505 if (likely(sh == 0)) {
1506 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1507 } else {
1508 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1509 tcg_gen_shli_tl(t0, t1, sh);
1510 tcg_gen_shri_tl(t1, t1, 32 - sh);
1511 tcg_gen_or_tl(t0, t0, t1);
j_mayer76a66252007-03-07 08:32:30 +00001512 }
j_mayer76a66252007-03-07 08:32:30 +00001513#if defined(TARGET_PPC64)
aurel32d03ef512008-10-27 22:50:22 +00001514 mb += 32;
1515 me += 32;
j_mayer76a66252007-03-07 08:32:30 +00001516#endif
aurel32d03ef512008-10-27 22:50:22 +00001517 mask = MASK(mb, me);
1518 tcg_gen_andi_tl(t0, t0, mask);
1519 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1520 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1521 tcg_temp_free(t0);
1522 tcg_temp_free(t1);
1523 }
j_mayer76a66252007-03-07 08:32:30 +00001524 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001525 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001526}
1527/* rlwinm & rlwinm. */
1528GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1529{
1530 uint32_t mb, me, sh;
ths3b46e622007-09-17 08:09:54 +00001531
bellard79aceca2003-11-23 14:55:54 +00001532 sh = SH(ctx->opcode);
1533 mb = MB(ctx->opcode);
1534 me = ME(ctx->opcode);
aurel32d03ef512008-10-27 22:50:22 +00001535
1536 if (likely(mb == 0 && me == (31 - sh))) {
1537 if (likely(sh == 0)) {
1538 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1539 } else {
1540 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1541 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1542 tcg_gen_shli_tl(t0, t0, sh);
1543 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1544 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00001545 }
aurel32d03ef512008-10-27 22:50:22 +00001546 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1547 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1548 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1549 tcg_gen_shri_tl(t0, t0, mb);
1550 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1551 tcg_temp_free(t0);
1552 } else {
1553 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1554 if (likely(sh != 0)) {
1555 TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
1556 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1557 tcg_gen_shli_tl(t1, t0, sh);
1558 tcg_gen_shri_tl(t0, t0, 32 - sh);
1559 tcg_gen_or_tl(t0, t0, t1);
1560 tcg_temp_free(t1);
1561 } else {
1562 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001563 }
j_mayer76a66252007-03-07 08:32:30 +00001564#if defined(TARGET_PPC64)
aurel32d03ef512008-10-27 22:50:22 +00001565 mb += 32;
1566 me += 32;
j_mayer76a66252007-03-07 08:32:30 +00001567#endif
aurel32d03ef512008-10-27 22:50:22 +00001568 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1569 tcg_temp_free(t0);
1570 }
j_mayer76a66252007-03-07 08:32:30 +00001571 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001572 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001573}
1574/* rlwnm & rlwnm. */
1575GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1576{
1577 uint32_t mb, me;
aurel32d03ef512008-10-27 22:50:22 +00001578 TCGv t0, t1, t2, t3;
bellard79aceca2003-11-23 14:55:54 +00001579
1580 mb = MB(ctx->opcode);
1581 me = ME(ctx->opcode);
aurel32d03ef512008-10-27 22:50:22 +00001582 t0 = tcg_temp_new(TCG_TYPE_TL);
1583 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1584 t1 = tcg_temp_new(TCG_TYPE_TL);
1585 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1586 t2 = tcg_temp_new(TCG_TYPE_TL);
1587 tcg_gen_shl_tl(t2, t1, t0);
1588 t3 = tcg_const_tl(32);
1589 tcg_gen_sub_tl(t0, t3, t0);
1590 tcg_temp_free(t3);
1591 tcg_gen_shr_tl(t1, t1, t0);
1592 tcg_temp_free(t0);
1593 tcg_gen_or_tl(t2, t2, t1);
1594 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00001595 if (unlikely(mb != 0 || me != 31)) {
1596#if defined(TARGET_PPC64)
1597 mb += 32;
1598 me += 32;
1599#endif
aurel32d03ef512008-10-27 22:50:22 +00001600 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t2, MASK(mb, me));
1601 } else {
1602 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t2);
bellard79aceca2003-11-23 14:55:54 +00001603 }
aurel32d03ef512008-10-27 22:50:22 +00001604 tcg_temp_free(t2);
j_mayer76a66252007-03-07 08:32:30 +00001605 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001606 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001607}
1608
j_mayerd9bce9d2007-03-17 14:02:15 +00001609#if defined(TARGET_PPC64)
1610#define GEN_PPC64_R2(name, opc1, opc2) \
j_mayerc7697e12007-10-26 00:46:07 +00001611GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001612{ \
1613 gen_##name(ctx, 0); \
1614} \
j_mayerc7697e12007-10-26 00:46:07 +00001615GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1616 PPC_64B) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001617{ \
1618 gen_##name(ctx, 1); \
1619}
1620#define GEN_PPC64_R4(name, opc1, opc2) \
j_mayerc7697e12007-10-26 00:46:07 +00001621GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001622{ \
1623 gen_##name(ctx, 0, 0); \
1624} \
j_mayerc7697e12007-10-26 00:46:07 +00001625GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1626 PPC_64B) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001627{ \
1628 gen_##name(ctx, 0, 1); \
1629} \
j_mayerc7697e12007-10-26 00:46:07 +00001630GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1631 PPC_64B) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001632{ \
1633 gen_##name(ctx, 1, 0); \
1634} \
j_mayerc7697e12007-10-26 00:46:07 +00001635GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1636 PPC_64B) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001637{ \
1638 gen_##name(ctx, 1, 1); \
1639}
j_mayer51789c42007-03-22 22:41:50 +00001640
j_mayerb068d6a2007-10-07 17:13:44 +00001641static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1642 uint32_t me, uint32_t sh)
j_mayer51789c42007-03-22 22:41:50 +00001643{
aurel32d03ef512008-10-27 22:50:22 +00001644 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1645 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1646 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1647 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1648 } else {
1649 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1650 if (likely(sh != 0)) {
1651 TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
1652 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1653 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);
1654 tcg_gen_or_tl(t0, t0, t1);
1655 tcg_temp_free(t1);
1656 } else {
1657 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
j_mayer51789c42007-03-22 22:41:50 +00001658 }
aurel32d03ef512008-10-27 22:50:22 +00001659 if (likely(mb == 0 && me == 63)) {
1660 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1661 } else {
1662 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
j_mayer51789c42007-03-22 22:41:50 +00001663 }
aurel32d03ef512008-10-27 22:50:22 +00001664 tcg_temp_free(t0);
j_mayer51789c42007-03-22 22:41:50 +00001665 }
j_mayer51789c42007-03-22 22:41:50 +00001666 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001667 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer51789c42007-03-22 22:41:50 +00001668}
j_mayerd9bce9d2007-03-17 14:02:15 +00001669/* rldicl - rldicl. */
j_mayerb068d6a2007-10-07 17:13:44 +00001670static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
j_mayerd9bce9d2007-03-17 14:02:15 +00001671{
j_mayer51789c42007-03-22 22:41:50 +00001672 uint32_t sh, mb;
j_mayerd9bce9d2007-03-17 14:02:15 +00001673
j_mayer9d53c752007-04-06 07:59:47 +00001674 sh = SH(ctx->opcode) | (shn << 5);
1675 mb = MB(ctx->opcode) | (mbn << 5);
j_mayer51789c42007-03-22 22:41:50 +00001676 gen_rldinm(ctx, mb, 63, sh);
j_mayerd9bce9d2007-03-17 14:02:15 +00001677}
j_mayer51789c42007-03-22 22:41:50 +00001678GEN_PPC64_R4(rldicl, 0x1E, 0x00);
j_mayerd9bce9d2007-03-17 14:02:15 +00001679/* rldicr - rldicr. */
j_mayerb068d6a2007-10-07 17:13:44 +00001680static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
j_mayerd9bce9d2007-03-17 14:02:15 +00001681{
j_mayer51789c42007-03-22 22:41:50 +00001682 uint32_t sh, me;
j_mayerd9bce9d2007-03-17 14:02:15 +00001683
j_mayer9d53c752007-04-06 07:59:47 +00001684 sh = SH(ctx->opcode) | (shn << 5);
1685 me = MB(ctx->opcode) | (men << 5);
j_mayer51789c42007-03-22 22:41:50 +00001686 gen_rldinm(ctx, 0, me, sh);
j_mayerd9bce9d2007-03-17 14:02:15 +00001687}
j_mayer51789c42007-03-22 22:41:50 +00001688GEN_PPC64_R4(rldicr, 0x1E, 0x02);
j_mayerd9bce9d2007-03-17 14:02:15 +00001689/* rldic - rldic. */
j_mayerb068d6a2007-10-07 17:13:44 +00001690static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
j_mayerd9bce9d2007-03-17 14:02:15 +00001691{
j_mayer51789c42007-03-22 22:41:50 +00001692 uint32_t sh, mb;
j_mayerd9bce9d2007-03-17 14:02:15 +00001693
j_mayer9d53c752007-04-06 07:59:47 +00001694 sh = SH(ctx->opcode) | (shn << 5);
1695 mb = MB(ctx->opcode) | (mbn << 5);
j_mayer51789c42007-03-22 22:41:50 +00001696 gen_rldinm(ctx, mb, 63 - sh, sh);
j_mayerd9bce9d2007-03-17 14:02:15 +00001697}
j_mayer51789c42007-03-22 22:41:50 +00001698GEN_PPC64_R4(rldic, 0x1E, 0x04);
1699
j_mayerb068d6a2007-10-07 17:13:44 +00001700static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1701 uint32_t me)
j_mayer51789c42007-03-22 22:41:50 +00001702{
aurel32d03ef512008-10-27 22:50:22 +00001703 TCGv t0, t1, t2;
1704
1705 mb = MB(ctx->opcode);
1706 me = ME(ctx->opcode);
1707 t0 = tcg_temp_new(TCG_TYPE_TL);
1708 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1709 t1 = tcg_temp_new(TCG_TYPE_TL);
1710 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t0);
1711 t2 = tcg_const_tl(32);
1712 tcg_gen_sub_tl(t0, t2, t0);
1713 tcg_temp_free(t2);
1714 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1715 tcg_gen_or_tl(t1, t1, t0);
1716 tcg_temp_free(t0);
j_mayer51789c42007-03-22 22:41:50 +00001717 if (unlikely(mb != 0 || me != 63)) {
aurel32d03ef512008-10-27 22:50:22 +00001718 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t1, MASK(mb, me));
1719 } else
1720 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
1721 tcg_temp_free(t1);
j_mayer51789c42007-03-22 22:41:50 +00001722 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001723 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer51789c42007-03-22 22:41:50 +00001724}
1725
j_mayerd9bce9d2007-03-17 14:02:15 +00001726/* rldcl - rldcl. */
j_mayerb068d6a2007-10-07 17:13:44 +00001727static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
j_mayerd9bce9d2007-03-17 14:02:15 +00001728{
j_mayer51789c42007-03-22 22:41:50 +00001729 uint32_t mb;
j_mayerd9bce9d2007-03-17 14:02:15 +00001730
j_mayer9d53c752007-04-06 07:59:47 +00001731 mb = MB(ctx->opcode) | (mbn << 5);
j_mayer51789c42007-03-22 22:41:50 +00001732 gen_rldnm(ctx, mb, 63);
j_mayerd9bce9d2007-03-17 14:02:15 +00001733}
j_mayer36081602007-09-17 08:21:54 +00001734GEN_PPC64_R2(rldcl, 0x1E, 0x08);
j_mayerd9bce9d2007-03-17 14:02:15 +00001735/* rldcr - rldcr. */
j_mayerb068d6a2007-10-07 17:13:44 +00001736static always_inline void gen_rldcr (DisasContext *ctx, int men)
j_mayerd9bce9d2007-03-17 14:02:15 +00001737{
j_mayer51789c42007-03-22 22:41:50 +00001738 uint32_t me;
j_mayerd9bce9d2007-03-17 14:02:15 +00001739
j_mayer9d53c752007-04-06 07:59:47 +00001740 me = MB(ctx->opcode) | (men << 5);
j_mayer51789c42007-03-22 22:41:50 +00001741 gen_rldnm(ctx, 0, me);
j_mayerd9bce9d2007-03-17 14:02:15 +00001742}
j_mayer36081602007-09-17 08:21:54 +00001743GEN_PPC64_R2(rldcr, 0x1E, 0x09);
j_mayerd9bce9d2007-03-17 14:02:15 +00001744/* rldimi - rldimi. */
j_mayerb068d6a2007-10-07 17:13:44 +00001745static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
j_mayerd9bce9d2007-03-17 14:02:15 +00001746{
j_mayer271a9162007-11-14 05:26:46 +00001747 uint32_t sh, mb, me;
j_mayerd9bce9d2007-03-17 14:02:15 +00001748
j_mayer9d53c752007-04-06 07:59:47 +00001749 sh = SH(ctx->opcode) | (shn << 5);
1750 mb = MB(ctx->opcode) | (mbn << 5);
j_mayer271a9162007-11-14 05:26:46 +00001751 me = 63 - sh;
aurel32d03ef512008-10-27 22:50:22 +00001752 if (unlikely(sh == 0 && mb == 0)) {
1753 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1754 } else {
1755 TCGv t0, t1;
1756 target_ulong mask;
1757
1758 t0 = tcg_temp_new(TCG_TYPE_TL);
1759 t1 = tcg_temp_new(TCG_TYPE_TL);
1760 if (likely(sh == 0)) {
1761 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1762 } else {
1763 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1764 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);
1765 tcg_gen_or_tl(t0, t0, t1);
j_mayer51789c42007-03-22 22:41:50 +00001766 }
aurel32d03ef512008-10-27 22:50:22 +00001767 mask = MASK(mb, me);
1768 tcg_gen_andi_tl(t0, t0, mask);
1769 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1770 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1771 tcg_temp_free(t0);
1772 tcg_temp_free(t1);
j_mayer51789c42007-03-22 22:41:50 +00001773 }
j_mayer51789c42007-03-22 22:41:50 +00001774 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001775 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001776}
j_mayer36081602007-09-17 08:21:54 +00001777GEN_PPC64_R4(rldimi, 0x1E, 0x06);
j_mayerd9bce9d2007-03-17 14:02:15 +00001778#endif
1779
bellard79aceca2003-11-23 14:55:54 +00001780/*** Integer shift ***/
1781/* slw & slw. */
aurel3226d67362008-10-21 11:31:27 +00001782GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1783{
1784 TCGv temp;
1785 int l1, l2;
1786 l1 = gen_new_label();
1787 l2 = gen_new_label();
1788
1789 temp = tcg_temp_local_new(TCG_TYPE_TL);
1790 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);
1791 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1792 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1793 tcg_gen_br(l2);
1794 gen_set_label(l1);
1795 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
1796 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1797 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1798 gen_set_label(l2);
1799 tcg_temp_free(temp);
1800 if (unlikely(Rc(ctx->opcode) != 0))
1801 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1802}
bellard79aceca2003-11-23 14:55:54 +00001803/* sraw & sraw. */
aurel3226d67362008-10-21 11:31:27 +00001804GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1805{
1806 tcg_gen_helper_1_2(helper_sraw, cpu_gpr[rA(ctx->opcode)],
1807 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1808 if (unlikely(Rc(ctx->opcode) != 0))
1809 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1810}
bellard79aceca2003-11-23 14:55:54 +00001811/* srawi & srawi. */
1812GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1813{
aurel3226d67362008-10-21 11:31:27 +00001814 int sh = SH(ctx->opcode);
1815 if (sh != 0) {
1816 int l1, l2;
1817 TCGv temp;
1818 l1 = gen_new_label();
1819 l2 = gen_new_label();
1820 temp = tcg_temp_local_new(TCG_TYPE_TL);
1821 tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
1822 tcg_gen_brcondi_tl(TCG_COND_GE, temp, 0, l1);
1823 tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1824 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
aurel32269f3e92008-11-01 00:53:48 +00001825 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
aurel3226d67362008-10-21 11:31:27 +00001826 tcg_gen_br(l2);
1827 gen_set_label(l1);
aurel32269f3e92008-11-01 00:53:48 +00001828 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
aurel3226d67362008-10-21 11:31:27 +00001829 gen_set_label(l2);
1830 tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
1831 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], temp, sh);
1832 tcg_temp_free(temp);
1833 } else {
1834 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
aurel32269f3e92008-11-01 00:53:48 +00001835 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
j_mayerd9bce9d2007-03-17 14:02:15 +00001836 }
j_mayer76a66252007-03-07 08:32:30 +00001837 if (unlikely(Rc(ctx->opcode) != 0))
aurel3226d67362008-10-21 11:31:27 +00001838 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001839}
1840/* srw & srw. */
aurel3226d67362008-10-21 11:31:27 +00001841GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1842{
1843 TCGv temp;
1844 int l1, l2;
1845 l1 = gen_new_label();
1846 l2 = gen_new_label();
j_mayerd9bce9d2007-03-17 14:02:15 +00001847
aurel3226d67362008-10-21 11:31:27 +00001848 temp = tcg_temp_local_new(TCG_TYPE_TL);
1849 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);
1850 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1851 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1852 tcg_gen_br(l2);
1853 gen_set_label(l1);
1854 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
1855 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1856 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1857 gen_set_label(l2);
1858 tcg_temp_free(temp);
1859 if (unlikely(Rc(ctx->opcode) != 0))
1860 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1861}
j_mayerd9bce9d2007-03-17 14:02:15 +00001862#if defined(TARGET_PPC64)
1863/* sld & sld. */
aurel3226d67362008-10-21 11:31:27 +00001864GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1865{
1866 TCGv temp;
1867 int l1, l2;
1868 l1 = gen_new_label();
1869 l2 = gen_new_label();
1870
1871 temp = tcg_temp_local_new(TCG_TYPE_TL);
1872 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);
1873 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1874 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1875 tcg_gen_br(l2);
1876 gen_set_label(l1);
1877 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);
1878 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1879 gen_set_label(l2);
1880 tcg_temp_free(temp);
1881 if (unlikely(Rc(ctx->opcode) != 0))
1882 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1883}
j_mayerd9bce9d2007-03-17 14:02:15 +00001884/* srad & srad. */
aurel3226d67362008-10-21 11:31:27 +00001885GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
1886{
1887 tcg_gen_helper_1_2(helper_srad, cpu_gpr[rA(ctx->opcode)],
1888 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1889 if (unlikely(Rc(ctx->opcode) != 0))
1890 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1891}
j_mayerd9bce9d2007-03-17 14:02:15 +00001892/* sradi & sradi. */
j_mayerb068d6a2007-10-07 17:13:44 +00001893static always_inline void gen_sradi (DisasContext *ctx, int n)
j_mayerd9bce9d2007-03-17 14:02:15 +00001894{
aurel3226d67362008-10-21 11:31:27 +00001895 int sh = SH(ctx->opcode) + (n << 5);
j_mayerd9bce9d2007-03-17 14:02:15 +00001896 if (sh != 0) {
aurel3226d67362008-10-21 11:31:27 +00001897 int l1, l2;
1898 TCGv temp;
1899 l1 = gen_new_label();
1900 l2 = gen_new_label();
1901 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1902 temp = tcg_temp_new(TCG_TYPE_TL);
1903 tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1904 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
aurel32269f3e92008-11-01 00:53:48 +00001905 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
aurel3226d67362008-10-21 11:31:27 +00001906 tcg_gen_br(l2);
1907 gen_set_label(l1);
aurel32269f3e92008-11-01 00:53:48 +00001908 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
aurel3226d67362008-10-21 11:31:27 +00001909 gen_set_label(l2);
1910 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1911 } else {
1912 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
aurel32269f3e92008-11-01 00:53:48 +00001913 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
j_mayerd9bce9d2007-03-17 14:02:15 +00001914 }
j_mayerd9bce9d2007-03-17 14:02:15 +00001915 if (unlikely(Rc(ctx->opcode) != 0))
aurel3226d67362008-10-21 11:31:27 +00001916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001917}
j_mayerc7697e12007-10-26 00:46:07 +00001918GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
j_mayerd9bce9d2007-03-17 14:02:15 +00001919{
1920 gen_sradi(ctx, 0);
1921}
j_mayerc7697e12007-10-26 00:46:07 +00001922GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
j_mayerd9bce9d2007-03-17 14:02:15 +00001923{
1924 gen_sradi(ctx, 1);
1925}
1926/* srd & srd. */
aurel3226d67362008-10-21 11:31:27 +00001927GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
1928{
1929 TCGv temp;
1930 int l1, l2;
1931 l1 = gen_new_label();
1932 l2 = gen_new_label();
1933
1934 temp = tcg_temp_local_new(TCG_TYPE_TL);
1935 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);
1936 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1937 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1938 tcg_gen_br(l2);
1939 gen_set_label(l1);
1940 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);
1941 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1942 gen_set_label(l2);
1943 tcg_temp_free(temp);
1944 if (unlikely(Rc(ctx->opcode) != 0))
1945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1946}
j_mayerd9bce9d2007-03-17 14:02:15 +00001947#endif
bellard79aceca2003-11-23 14:55:54 +00001948
1949/*** Floating-Point arithmetic ***/
j_mayer7c580442007-10-27 17:54:30 +00001950#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
j_mayera750fc02007-09-26 23:54:22 +00001951GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
bellard9a64fbe2004-01-04 22:58:38 +00001952{ \
j_mayer76a66252007-03-07 08:32:30 +00001953 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00001954 GEN_EXCP_NO_FP(ctx); \
bellard3cc62372005-02-15 23:06:19 +00001955 return; \
1956 } \
aurel32a5e26af2008-09-04 14:43:54 +00001957 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1958 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
1959 tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
j_mayer7c580442007-10-27 17:54:30 +00001960 gen_reset_fpstatus(); \
bellard4ecc3192005-03-13 17:01:22 +00001961 gen_op_f##op(); \
1962 if (isfloat) { \
1963 gen_op_frsp(); \
1964 } \
aurel32a5e26af2008-09-04 14:43:54 +00001965 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
j_mayer7c580442007-10-27 17:54:30 +00001966 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
bellard79aceca2003-11-23 14:55:54 +00001967}
1968
j_mayer7c580442007-10-27 17:54:30 +00001969#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1970_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1971_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
bellard9a64fbe2004-01-04 22:58:38 +00001972
j_mayer7c580442007-10-27 17:54:30 +00001973#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1974GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
bellard9a64fbe2004-01-04 22:58:38 +00001975{ \
j_mayer76a66252007-03-07 08:32:30 +00001976 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00001977 GEN_EXCP_NO_FP(ctx); \
bellard3cc62372005-02-15 23:06:19 +00001978 return; \
1979 } \
aurel32a5e26af2008-09-04 14:43:54 +00001980 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1981 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
j_mayer7c580442007-10-27 17:54:30 +00001982 gen_reset_fpstatus(); \
bellard4ecc3192005-03-13 17:01:22 +00001983 gen_op_f##op(); \
1984 if (isfloat) { \
1985 gen_op_frsp(); \
1986 } \
aurel32a5e26af2008-09-04 14:43:54 +00001987 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
j_mayer7c580442007-10-27 17:54:30 +00001988 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
bellard9a64fbe2004-01-04 22:58:38 +00001989}
j_mayer7c580442007-10-27 17:54:30 +00001990#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1991_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1992_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
bellard9a64fbe2004-01-04 22:58:38 +00001993
j_mayer7c580442007-10-27 17:54:30 +00001994#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1995GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
bellard9a64fbe2004-01-04 22:58:38 +00001996{ \
j_mayer76a66252007-03-07 08:32:30 +00001997 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00001998 GEN_EXCP_NO_FP(ctx); \
bellard3cc62372005-02-15 23:06:19 +00001999 return; \
2000 } \
aurel32a5e26af2008-09-04 14:43:54 +00002001 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2002 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
j_mayer7c580442007-10-27 17:54:30 +00002003 gen_reset_fpstatus(); \
bellard4ecc3192005-03-13 17:01:22 +00002004 gen_op_f##op(); \
2005 if (isfloat) { \
2006 gen_op_frsp(); \
2007 } \
aurel32a5e26af2008-09-04 14:43:54 +00002008 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
j_mayer7c580442007-10-27 17:54:30 +00002009 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
bellard9a64fbe2004-01-04 22:58:38 +00002010}
j_mayer7c580442007-10-27 17:54:30 +00002011#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2012_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2013_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
bellard9a64fbe2004-01-04 22:58:38 +00002014
j_mayer7c580442007-10-27 17:54:30 +00002015#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
j_mayera750fc02007-09-26 23:54:22 +00002016GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
bellard9a64fbe2004-01-04 22:58:38 +00002017{ \
j_mayer76a66252007-03-07 08:32:30 +00002018 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00002019 GEN_EXCP_NO_FP(ctx); \
bellard3cc62372005-02-15 23:06:19 +00002020 return; \
2021 } \
aurel32a5e26af2008-09-04 14:43:54 +00002022 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
j_mayer7c580442007-10-27 17:54:30 +00002023 gen_reset_fpstatus(); \
bellard9a64fbe2004-01-04 22:58:38 +00002024 gen_op_f##name(); \
aurel32a5e26af2008-09-04 14:43:54 +00002025 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
j_mayer7c580442007-10-27 17:54:30 +00002026 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
bellard79aceca2003-11-23 14:55:54 +00002027}
2028
j_mayer7c580442007-10-27 17:54:30 +00002029#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
j_mayera750fc02007-09-26 23:54:22 +00002030GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
bellard9a64fbe2004-01-04 22:58:38 +00002031{ \
j_mayer76a66252007-03-07 08:32:30 +00002032 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00002033 GEN_EXCP_NO_FP(ctx); \
bellard3cc62372005-02-15 23:06:19 +00002034 return; \
2035 } \
aurel32a5e26af2008-09-04 14:43:54 +00002036 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
j_mayer7c580442007-10-27 17:54:30 +00002037 gen_reset_fpstatus(); \
bellard9a64fbe2004-01-04 22:58:38 +00002038 gen_op_f##name(); \
aurel32a5e26af2008-09-04 14:43:54 +00002039 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
j_mayer7c580442007-10-27 17:54:30 +00002040 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
bellard9a64fbe2004-01-04 22:58:38 +00002041}
2042
2043/* fadd - fadds */
j_mayer7c580442007-10-27 17:54:30 +00002044GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
bellard4ecc3192005-03-13 17:01:22 +00002045/* fdiv - fdivs */
j_mayer7c580442007-10-27 17:54:30 +00002046GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
bellard4ecc3192005-03-13 17:01:22 +00002047/* fmul - fmuls */
j_mayer7c580442007-10-27 17:54:30 +00002048GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00002049
j_mayerd7e4b872007-09-30 01:11:48 +00002050/* fre */
j_mayer7c580442007-10-27 17:54:30 +00002051GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
j_mayerd7e4b872007-09-30 01:11:48 +00002052
j_mayera750fc02007-09-26 23:54:22 +00002053/* fres */
j_mayer7c580442007-10-27 17:54:30 +00002054GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
bellard79aceca2003-11-23 14:55:54 +00002055
j_mayera750fc02007-09-26 23:54:22 +00002056/* frsqrte */
j_mayer7c580442007-10-27 17:54:30 +00002057GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2058
2059/* frsqrtes */
2060static always_inline void gen_op_frsqrtes (void)
2061{
2062 gen_op_frsqrte();
2063 gen_op_frsp();
2064}
j_mayer1b413d52007-11-14 01:08:45 +00002065GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
bellard79aceca2003-11-23 14:55:54 +00002066
j_mayera750fc02007-09-26 23:54:22 +00002067/* fsel */
j_mayer7c580442007-10-27 17:54:30 +00002068_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
bellard4ecc3192005-03-13 17:01:22 +00002069/* fsub - fsubs */
j_mayer7c580442007-10-27 17:54:30 +00002070GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00002071/* Optional: */
2072/* fsqrt */
j_mayera750fc02007-09-26 23:54:22 +00002073GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
bellardc7d344a2005-04-23 18:05:46 +00002074{
j_mayer76a66252007-03-07 08:32:30 +00002075 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002076 GEN_EXCP_NO_FP(ctx);
bellardc7d344a2005-04-23 18:05:46 +00002077 return;
2078 }
aurel32a5e26af2008-09-04 14:43:54 +00002079 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
j_mayer7c580442007-10-27 17:54:30 +00002080 gen_reset_fpstatus();
bellardc7d344a2005-04-23 18:05:46 +00002081 gen_op_fsqrt();
aurel32a5e26af2008-09-04 14:43:54 +00002082 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
j_mayer7c580442007-10-27 17:54:30 +00002083 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
bellardc7d344a2005-04-23 18:05:46 +00002084}
bellard79aceca2003-11-23 14:55:54 +00002085
j_mayera750fc02007-09-26 23:54:22 +00002086GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
bellard79aceca2003-11-23 14:55:54 +00002087{
j_mayer76a66252007-03-07 08:32:30 +00002088 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002089 GEN_EXCP_NO_FP(ctx);
bellard3cc62372005-02-15 23:06:19 +00002090 return;
2091 }
aurel32a5e26af2008-09-04 14:43:54 +00002092 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
j_mayer7c580442007-10-27 17:54:30 +00002093 gen_reset_fpstatus();
bellard4ecc3192005-03-13 17:01:22 +00002094 gen_op_fsqrt();
2095 gen_op_frsp();
aurel32a5e26af2008-09-04 14:43:54 +00002096 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
j_mayer7c580442007-10-27 17:54:30 +00002097 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
bellard79aceca2003-11-23 14:55:54 +00002098}
2099
2100/*** Floating-Point multiply-and-add ***/
bellard4ecc3192005-03-13 17:01:22 +00002101/* fmadd - fmadds */
j_mayer7c580442007-10-27 17:54:30 +00002102GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
bellard4ecc3192005-03-13 17:01:22 +00002103/* fmsub - fmsubs */
j_mayer7c580442007-10-27 17:54:30 +00002104GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
bellard4ecc3192005-03-13 17:01:22 +00002105/* fnmadd - fnmadds */
j_mayer7c580442007-10-27 17:54:30 +00002106GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
bellard4ecc3192005-03-13 17:01:22 +00002107/* fnmsub - fnmsubs */
j_mayer7c580442007-10-27 17:54:30 +00002108GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00002109
2110/*** Floating-Point round & convert ***/
2111/* fctiw */
j_mayer7c580442007-10-27 17:54:30 +00002112GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00002113/* fctiwz */
j_mayer7c580442007-10-27 17:54:30 +00002114GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00002115/* frsp */
j_mayer7c580442007-10-27 17:54:30 +00002116GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
j_mayer426613d2007-03-23 09:45:27 +00002117#if defined(TARGET_PPC64)
2118/* fcfid */
j_mayer7c580442007-10-27 17:54:30 +00002119GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
j_mayer426613d2007-03-23 09:45:27 +00002120/* fctid */
j_mayer7c580442007-10-27 17:54:30 +00002121GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
j_mayer426613d2007-03-23 09:45:27 +00002122/* fctidz */
j_mayer7c580442007-10-27 17:54:30 +00002123GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
j_mayer426613d2007-03-23 09:45:27 +00002124#endif
bellard79aceca2003-11-23 14:55:54 +00002125
j_mayerd7e4b872007-09-30 01:11:48 +00002126/* frin */
j_mayer7c580442007-10-27 17:54:30 +00002127GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
j_mayerd7e4b872007-09-30 01:11:48 +00002128/* friz */
j_mayer7c580442007-10-27 17:54:30 +00002129GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
j_mayerd7e4b872007-09-30 01:11:48 +00002130/* frip */
j_mayer7c580442007-10-27 17:54:30 +00002131GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
j_mayerd7e4b872007-09-30 01:11:48 +00002132/* frim */
j_mayer7c580442007-10-27 17:54:30 +00002133GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
j_mayerd7e4b872007-09-30 01:11:48 +00002134
bellard79aceca2003-11-23 14:55:54 +00002135/*** Floating-Point compare ***/
2136/* fcmpo */
j_mayer76a66252007-03-07 08:32:30 +00002137GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
bellard79aceca2003-11-23 14:55:54 +00002138{
j_mayer76a66252007-03-07 08:32:30 +00002139 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002140 GEN_EXCP_NO_FP(ctx);
bellard3cc62372005-02-15 23:06:19 +00002141 return;
2142 }
aurel32a5e26af2008-09-04 14:43:54 +00002143 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2144 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
j_mayer7c580442007-10-27 17:54:30 +00002145 gen_reset_fpstatus();
aurel32e1571902008-10-21 11:31:14 +00002146 tcg_gen_helper_1_0(helper_fcmpo, cpu_crf[crfD(ctx->opcode)]);
j_mayer7c580442007-10-27 17:54:30 +00002147 gen_op_float_check_status();
bellard79aceca2003-11-23 14:55:54 +00002148}
2149
2150/* fcmpu */
j_mayer76a66252007-03-07 08:32:30 +00002151GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
bellard79aceca2003-11-23 14:55:54 +00002152{
j_mayer76a66252007-03-07 08:32:30 +00002153 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002154 GEN_EXCP_NO_FP(ctx);
bellard3cc62372005-02-15 23:06:19 +00002155 return;
2156 }
aurel32a5e26af2008-09-04 14:43:54 +00002157 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2158 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
j_mayer7c580442007-10-27 17:54:30 +00002159 gen_reset_fpstatus();
aurel32e1571902008-10-21 11:31:14 +00002160 tcg_gen_helper_1_0(helper_fcmpu, cpu_crf[crfD(ctx->opcode)]);
j_mayer7c580442007-10-27 17:54:30 +00002161 gen_op_float_check_status();
bellard79aceca2003-11-23 14:55:54 +00002162}
2163
bellard9a64fbe2004-01-04 22:58:38 +00002164/*** Floating-point move ***/
2165/* fabs */
j_mayer7c580442007-10-27 17:54:30 +00002166/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2167GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
bellard9a64fbe2004-01-04 22:58:38 +00002168
2169/* fmr - fmr. */
j_mayer7c580442007-10-27 17:54:30 +00002170/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
bellard9a64fbe2004-01-04 22:58:38 +00002171GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2172{
j_mayer76a66252007-03-07 08:32:30 +00002173 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002174 GEN_EXCP_NO_FP(ctx);
bellard3cc62372005-02-15 23:06:19 +00002175 return;
2176 }
aurel32a5e26af2008-09-04 14:43:54 +00002177 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2178 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
j_mayer7c580442007-10-27 17:54:30 +00002179 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
bellard9a64fbe2004-01-04 22:58:38 +00002180}
2181
2182/* fnabs */
j_mayer7c580442007-10-27 17:54:30 +00002183/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2184GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
bellard9a64fbe2004-01-04 22:58:38 +00002185/* fneg */
j_mayer7c580442007-10-27 17:54:30 +00002186/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2187GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
bellard9a64fbe2004-01-04 22:58:38 +00002188
bellard79aceca2003-11-23 14:55:54 +00002189/*** Floating-Point status & ctrl register ***/
2190/* mcrfs */
2191GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2192{
j_mayer7c580442007-10-27 17:54:30 +00002193 int bfa;
2194
j_mayer76a66252007-03-07 08:32:30 +00002195 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002196 GEN_EXCP_NO_FP(ctx);
bellard3cc62372005-02-15 23:06:19 +00002197 return;
2198 }
j_mayer7c580442007-10-27 17:54:30 +00002199 gen_optimize_fprf();
2200 bfa = 4 * (7 - crfS(ctx->opcode));
aurel32e1571902008-10-21 11:31:14 +00002201 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2202 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
j_mayer7c580442007-10-27 17:54:30 +00002203 gen_op_fpscr_resetbit(~(0xF << bfa));
bellard79aceca2003-11-23 14:55:54 +00002204}
2205
2206/* mffs */
2207GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2208{
j_mayer76a66252007-03-07 08:32:30 +00002209 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002210 GEN_EXCP_NO_FP(ctx);
bellard3cc62372005-02-15 23:06:19 +00002211 return;
2212 }
j_mayer7c580442007-10-27 17:54:30 +00002213 gen_optimize_fprf();
2214 gen_reset_fpstatus();
2215 gen_op_load_fpscr_FT0();
aurel32a5e26af2008-09-04 14:43:54 +00002216 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
j_mayer7c580442007-10-27 17:54:30 +00002217 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
bellard79aceca2003-11-23 14:55:54 +00002218}
2219
2220/* mtfsb0 */
2221GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2222{
bellardfb0eaff2004-01-04 14:57:11 +00002223 uint8_t crb;
ths3b46e622007-09-17 08:09:54 +00002224
j_mayer76a66252007-03-07 08:32:30 +00002225 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002226 GEN_EXCP_NO_FP(ctx);
bellard3cc62372005-02-15 23:06:19 +00002227 return;
2228 }
j_mayer7c580442007-10-27 17:54:30 +00002229 crb = 32 - (crbD(ctx->opcode) >> 2);
2230 gen_optimize_fprf();
2231 gen_reset_fpstatus();
2232 if (likely(crb != 30 && crb != 29))
2233 gen_op_fpscr_resetbit(~(1 << crb));
2234 if (unlikely(Rc(ctx->opcode) != 0)) {
aurel32e1571902008-10-21 11:31:14 +00002235 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
j_mayer7c580442007-10-27 17:54:30 +00002236 }
bellard79aceca2003-11-23 14:55:54 +00002237}
2238
2239/* mtfsb1 */
2240GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2241{
bellardfb0eaff2004-01-04 14:57:11 +00002242 uint8_t crb;
ths3b46e622007-09-17 08:09:54 +00002243
j_mayer76a66252007-03-07 08:32:30 +00002244 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002245 GEN_EXCP_NO_FP(ctx);
bellard3cc62372005-02-15 23:06:19 +00002246 return;
2247 }
j_mayer7c580442007-10-27 17:54:30 +00002248 crb = 32 - (crbD(ctx->opcode) >> 2);
2249 gen_optimize_fprf();
2250 gen_reset_fpstatus();
2251 /* XXX: we pretend we can only do IEEE floating-point computations */
2252 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2253 gen_op_fpscr_setbit(crb);
2254 if (unlikely(Rc(ctx->opcode) != 0)) {
aurel32e1571902008-10-21 11:31:14 +00002255 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
j_mayer7c580442007-10-27 17:54:30 +00002256 }
2257 /* We can raise a differed exception */
2258 gen_op_float_check_status();
bellard79aceca2003-11-23 14:55:54 +00002259}
2260
2261/* mtfsf */
2262GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2263{
j_mayer76a66252007-03-07 08:32:30 +00002264 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002265 GEN_EXCP_NO_FP(ctx);
bellard3cc62372005-02-15 23:06:19 +00002266 return;
2267 }
j_mayer7c580442007-10-27 17:54:30 +00002268 gen_optimize_fprf();
aurel32a5e26af2008-09-04 14:43:54 +00002269 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
j_mayer7c580442007-10-27 17:54:30 +00002270 gen_reset_fpstatus();
bellard28b67512003-11-23 16:58:08 +00002271 gen_op_store_fpscr(FM(ctx->opcode));
j_mayer7c580442007-10-27 17:54:30 +00002272 if (unlikely(Rc(ctx->opcode) != 0)) {
aurel32e1571902008-10-21 11:31:14 +00002273 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
j_mayer7c580442007-10-27 17:54:30 +00002274 }
2275 /* We can raise a differed exception */
2276 gen_op_float_check_status();
bellard79aceca2003-11-23 14:55:54 +00002277}
2278
2279/* mtfsfi */
2280GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2281{
j_mayer7c580442007-10-27 17:54:30 +00002282 int bf, sh;
2283
j_mayer76a66252007-03-07 08:32:30 +00002284 if (unlikely(!ctx->fpu_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00002285 GEN_EXCP_NO_FP(ctx);
bellard3cc62372005-02-15 23:06:19 +00002286 return;
2287 }
j_mayer7c580442007-10-27 17:54:30 +00002288 bf = crbD(ctx->opcode) >> 2;
2289 sh = 7 - bf;
2290 gen_optimize_fprf();
aurel32489251f2008-09-04 20:34:31 +00002291 tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
j_mayer7c580442007-10-27 17:54:30 +00002292 gen_reset_fpstatus();
2293 gen_op_store_fpscr(1 << sh);
2294 if (unlikely(Rc(ctx->opcode) != 0)) {
aurel32e1571902008-10-21 11:31:14 +00002295 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
j_mayer7c580442007-10-27 17:54:30 +00002296 }
2297 /* We can raise a differed exception */
2298 gen_op_float_check_status();
bellard79aceca2003-11-23 14:55:54 +00002299}
2300
j_mayer76a66252007-03-07 08:32:30 +00002301/*** Addressing modes ***/
2302/* Register indirect with immediate index : EA = (rA|0) + SIMM */
aurel32e2be8d82008-10-14 19:55:54 +00002303static always_inline void gen_addr_imm_index (TCGv EA,
2304 DisasContext *ctx,
j_mayerb068d6a2007-10-07 17:13:44 +00002305 target_long maskl)
j_mayer76a66252007-03-07 08:32:30 +00002306{
2307 target_long simm = SIMM(ctx->opcode);
2308
j_mayerbe147d02007-09-30 13:03:23 +00002309 simm &= ~maskl;
aurel32e2be8d82008-10-14 19:55:54 +00002310 if (rA(ctx->opcode) == 0)
2311 tcg_gen_movi_tl(EA, simm);
2312 else if (likely(simm != 0))
2313 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2314 else
2315 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00002316}
2317
aurel32e2be8d82008-10-14 19:55:54 +00002318static always_inline void gen_addr_reg_index (TCGv EA,
2319 DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00002320{
aurel32e2be8d82008-10-14 19:55:54 +00002321 if (rA(ctx->opcode) == 0)
2322 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2323 else
2324 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00002325}
2326
aurel32e2be8d82008-10-14 19:55:54 +00002327static always_inline void gen_addr_register (TCGv EA,
2328 DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00002329{
aurel32e2be8d82008-10-14 19:55:54 +00002330 if (rA(ctx->opcode) == 0)
2331 tcg_gen_movi_tl(EA, 0);
2332 else
2333 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00002334}
2335
j_mayer78636672007-11-16 14:11:28 +00002336#if defined(TARGET_PPC64)
2337#define _GEN_MEM_FUNCS(name, mode) \
2338 &gen_op_##name##_##mode, \
2339 &gen_op_##name##_le_##mode, \
2340 &gen_op_##name##_64_##mode, \
2341 &gen_op_##name##_le_64_##mode
2342#else
2343#define _GEN_MEM_FUNCS(name, mode) \
2344 &gen_op_##name##_##mode, \
2345 &gen_op_##name##_le_##mode
2346#endif
bellard111bfab2005-04-23 18:16:07 +00002347#if defined(CONFIG_USER_ONLY)
j_mayerd9bce9d2007-03-17 14:02:15 +00002348#if defined(TARGET_PPC64)
j_mayer78636672007-11-16 14:11:28 +00002349#define NB_MEM_FUNCS 4
j_mayerd9bce9d2007-03-17 14:02:15 +00002350#else
j_mayer78636672007-11-16 14:11:28 +00002351#define NB_MEM_FUNCS 2
j_mayerd9bce9d2007-03-17 14:02:15 +00002352#endif
j_mayer78636672007-11-16 14:11:28 +00002353#define GEN_MEM_FUNCS(name) \
2354 _GEN_MEM_FUNCS(name, raw)
bellard111bfab2005-04-23 18:16:07 +00002355#else
j_mayerd9bce9d2007-03-17 14:02:15 +00002356#if defined(TARGET_PPC64)
j_mayer78636672007-11-16 14:11:28 +00002357#define NB_MEM_FUNCS 12
j_mayer28570682007-10-02 10:11:50 +00002358#else
j_mayer78636672007-11-16 14:11:28 +00002359#define NB_MEM_FUNCS 6
j_mayer28570682007-10-02 10:11:50 +00002360#endif
j_mayer78636672007-11-16 14:11:28 +00002361#define GEN_MEM_FUNCS(name) \
2362 _GEN_MEM_FUNCS(name, user), \
2363 _GEN_MEM_FUNCS(name, kernel), \
2364 _GEN_MEM_FUNCS(name, hypv)
2365#endif
2366
2367/*** Integer load ***/
2368#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
bellard9a64fbe2004-01-04 22:58:38 +00002369#define OP_LD_TABLE(width) \
j_mayer78636672007-11-16 14:11:28 +00002370static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2371 GEN_MEM_FUNCS(l##width), \
bellard111bfab2005-04-23 18:16:07 +00002372};
bellard9a64fbe2004-01-04 22:58:38 +00002373#define OP_ST_TABLE(width) \
j_mayer78636672007-11-16 14:11:28 +00002374static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2375 GEN_MEM_FUNCS(st##width), \
bellard111bfab2005-04-23 18:16:07 +00002376};
bellard9a64fbe2004-01-04 22:58:38 +00002377
aurel32b61f2752008-10-15 17:00:37 +00002378
2379#if defined(TARGET_PPC64)
2380#define GEN_QEMU_LD_PPC64(width) \
2381static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2382{ \
2383 if (likely(flags & 2)) \
2384 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2385 else { \
2386 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2387 tcg_gen_ext32u_tl(addr, t1); \
2388 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2389 tcg_temp_free(addr); \
2390 } \
2391}
2392GEN_QEMU_LD_PPC64(8u)
2393GEN_QEMU_LD_PPC64(8s)
2394GEN_QEMU_LD_PPC64(16u)
2395GEN_QEMU_LD_PPC64(16s)
2396GEN_QEMU_LD_PPC64(32u)
2397GEN_QEMU_LD_PPC64(32s)
2398GEN_QEMU_LD_PPC64(64)
2399
2400#define GEN_QEMU_ST_PPC64(width) \
2401static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2402{ \
2403 if (likely(flags & 2)) \
2404 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2405 else { \
2406 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2407 tcg_gen_ext32u_tl(addr, t1); \
2408 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2409 tcg_temp_free(addr); \
2410 } \
2411}
2412GEN_QEMU_ST_PPC64(8)
2413GEN_QEMU_ST_PPC64(16)
2414GEN_QEMU_ST_PPC64(32)
2415GEN_QEMU_ST_PPC64(64)
2416
aurel32ea363692008-10-27 22:50:39 +00002417static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002418{
aurel32ea363692008-10-27 22:50:39 +00002419 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002420}
2421
aurel32ea363692008-10-27 22:50:39 +00002422static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002423{
aurel32ea363692008-10-27 22:50:39 +00002424 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002425}
2426
aurel32ea363692008-10-27 22:50:39 +00002427static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002428{
2429 if (unlikely(flags & 1)) {
aurel32ea363692008-10-27 22:50:39 +00002430 TCGv t0;
2431 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2432 t0 = tcg_temp_new(TCG_TYPE_I32);
2433 tcg_gen_trunc_tl_i32(t0, arg0);
2434 tcg_gen_bswap16_i32(t0, t0);
2435 tcg_gen_extu_i32_tl(arg0, t0);
2436 tcg_temp_free(t0);
aurel32b61f2752008-10-15 17:00:37 +00002437 } else
aurel32ea363692008-10-27 22:50:39 +00002438 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002439}
2440
aurel32ea363692008-10-27 22:50:39 +00002441static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002442{
2443 if (unlikely(flags & 1)) {
aurel32ea363692008-10-27 22:50:39 +00002444 TCGv t0;
2445 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2446 t0 = tcg_temp_new(TCG_TYPE_I32);
2447 tcg_gen_trunc_tl_i32(t0, arg0);
2448 tcg_gen_bswap16_i32(t0, t0);
2449 tcg_gen_extu_i32_tl(arg0, t0);
2450 tcg_gen_ext16s_tl(arg0, arg0);
2451 tcg_temp_free(t0);
aurel32b61f2752008-10-15 17:00:37 +00002452 } else
aurel32ea363692008-10-27 22:50:39 +00002453 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002454}
2455
aurel32ea363692008-10-27 22:50:39 +00002456static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002457{
2458 if (unlikely(flags & 1)) {
aurel32ea363692008-10-27 22:50:39 +00002459 TCGv t0;
2460 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2461 t0 = tcg_temp_new(TCG_TYPE_I32);
2462 tcg_gen_trunc_tl_i32(t0, arg0);
2463 tcg_gen_bswap_i32(t0, t0);
2464 tcg_gen_extu_i32_tl(arg0, t0);
2465 tcg_temp_free(t0);
aurel32b61f2752008-10-15 17:00:37 +00002466 } else
aurel32ea363692008-10-27 22:50:39 +00002467 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002468}
2469
aurel32ea363692008-10-27 22:50:39 +00002470static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002471{
2472 if (unlikely(flags & 1)) {
aurel32ea363692008-10-27 22:50:39 +00002473 TCGv t0;
2474 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2475 t0 = tcg_temp_new(TCG_TYPE_I32);
2476 tcg_gen_trunc_tl_i32(t0, arg0);
2477 tcg_gen_bswap_i32(t0, t0);
2478 tcg_gen_ext_i32_tl(arg0, t0);
2479 tcg_temp_free(t0);
aurel32b61f2752008-10-15 17:00:37 +00002480 } else
aurel32ea363692008-10-27 22:50:39 +00002481 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002482}
2483
aurel32ea363692008-10-27 22:50:39 +00002484static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002485{
aurel32ea363692008-10-27 22:50:39 +00002486 gen_qemu_ld64_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002487 if (unlikely(flags & 1))
aurel32ea363692008-10-27 22:50:39 +00002488 tcg_gen_bswap_i64(arg0, arg0);
aurel32b61f2752008-10-15 17:00:37 +00002489}
2490
aurel32ea363692008-10-27 22:50:39 +00002491static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002492{
aurel32ea363692008-10-27 22:50:39 +00002493 gen_qemu_st8_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002494}
2495
aurel32ea363692008-10-27 22:50:39 +00002496static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002497{
2498 if (unlikely(flags & 1)) {
aurel32ea363692008-10-27 22:50:39 +00002499 TCGv t0, t1;
2500 t0 = tcg_temp_new(TCG_TYPE_I32);
2501 tcg_gen_trunc_tl_i32(t0, arg0);
2502 tcg_gen_ext16u_i32(t0, t0);
2503 tcg_gen_bswap16_i32(t0, t0);
2504 t1 = tcg_temp_new(TCG_TYPE_I64);
2505 tcg_gen_extu_i32_tl(t1, t0);
2506 tcg_temp_free(t0);
2507 gen_qemu_st16_ppc64(t1, arg1, flags);
2508 tcg_temp_free(t1);
aurel32b61f2752008-10-15 17:00:37 +00002509 } else
aurel32ea363692008-10-27 22:50:39 +00002510 gen_qemu_st16_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002511}
2512
aurel32ea363692008-10-27 22:50:39 +00002513static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002514{
2515 if (unlikely(flags & 1)) {
aurel32ea363692008-10-27 22:50:39 +00002516 TCGv t0, t1;
2517 t0 = tcg_temp_new(TCG_TYPE_I32);
2518 tcg_gen_trunc_tl_i32(t0, arg0);
2519 tcg_gen_bswap_i32(t0, t0);
2520 t1 = tcg_temp_new(TCG_TYPE_I64);
2521 tcg_gen_extu_i32_tl(t1, t0);
2522 tcg_temp_free(t0);
2523 gen_qemu_st32_ppc64(t1, arg1, flags);
2524 tcg_temp_free(t1);
aurel32b61f2752008-10-15 17:00:37 +00002525 } else
aurel32ea363692008-10-27 22:50:39 +00002526 gen_qemu_st32_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002527}
2528
aurel32ea363692008-10-27 22:50:39 +00002529static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002530{
2531 if (unlikely(flags & 1)) {
aurel32ea363692008-10-27 22:50:39 +00002532 TCGv t0 = tcg_temp_new(TCG_TYPE_I64);
2533 tcg_gen_bswap_i64(t0, arg0);
2534 gen_qemu_st64_ppc64(t0, arg1, flags);
2535 tcg_temp_free(t0);
aurel32b61f2752008-10-15 17:00:37 +00002536 } else
aurel32ea363692008-10-27 22:50:39 +00002537 gen_qemu_st64_ppc64(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002538}
2539
2540
2541#else /* defined(TARGET_PPC64) */
2542#define GEN_QEMU_LD_PPC32(width) \
aurel32ea363692008-10-27 22:50:39 +00002543static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
aurel32b61f2752008-10-15 17:00:37 +00002544{ \
aurel32ea363692008-10-27 22:50:39 +00002545 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
aurel32b61f2752008-10-15 17:00:37 +00002546}
2547GEN_QEMU_LD_PPC32(8u)
2548GEN_QEMU_LD_PPC32(8s)
2549GEN_QEMU_LD_PPC32(16u)
2550GEN_QEMU_LD_PPC32(16s)
2551GEN_QEMU_LD_PPC32(32u)
2552GEN_QEMU_LD_PPC32(32s)
2553GEN_QEMU_LD_PPC32(64)
2554
2555#define GEN_QEMU_ST_PPC32(width) \
aurel32ea363692008-10-27 22:50:39 +00002556static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
aurel32b61f2752008-10-15 17:00:37 +00002557{ \
aurel32ea363692008-10-27 22:50:39 +00002558 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
aurel32b61f2752008-10-15 17:00:37 +00002559}
2560GEN_QEMU_ST_PPC32(8)
2561GEN_QEMU_ST_PPC32(16)
2562GEN_QEMU_ST_PPC32(32)
2563GEN_QEMU_ST_PPC32(64)
2564
aurel32ea363692008-10-27 22:50:39 +00002565static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002566{
aurel32ea363692008-10-27 22:50:39 +00002567 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
aurel32b61f2752008-10-15 17:00:37 +00002568}
2569
aurel32ea363692008-10-27 22:50:39 +00002570static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002571{
aurel32ea363692008-10-27 22:50:39 +00002572 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
aurel32b61f2752008-10-15 17:00:37 +00002573}
2574
aurel32ea363692008-10-27 22:50:39 +00002575static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002576{
aurel32ea363692008-10-27 22:50:39 +00002577 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
aurel32b61f2752008-10-15 17:00:37 +00002578 if (unlikely(flags & 1))
aurel32ea363692008-10-27 22:50:39 +00002579 tcg_gen_bswap16_i32(arg0, arg0);
aurel32b61f2752008-10-15 17:00:37 +00002580}
2581
aurel32ea363692008-10-27 22:50:39 +00002582static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002583{
2584 if (unlikely(flags & 1)) {
aurel32ea363692008-10-27 22:50:39 +00002585 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2586 tcg_gen_bswap16_i32(arg0, arg0);
2587 tcg_gen_ext16s_i32(arg0, arg0);
aurel32b61f2752008-10-15 17:00:37 +00002588 } else
aurel32ea363692008-10-27 22:50:39 +00002589 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002590}
2591
aurel32ea363692008-10-27 22:50:39 +00002592static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002593{
aurel32ea363692008-10-27 22:50:39 +00002594 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002595 if (unlikely(flags & 1))
aurel32ea363692008-10-27 22:50:39 +00002596 tcg_gen_bswap_i32(arg0, arg0);
aurel32b61f2752008-10-15 17:00:37 +00002597}
2598
aurel32ea363692008-10-27 22:50:39 +00002599static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002600{
aurel32ea363692008-10-27 22:50:39 +00002601 gen_qemu_ld64_ppc32(arg0, arg1, flags);
aurel32b61f2752008-10-15 17:00:37 +00002602 if (unlikely(flags & 1))
aurel32ea363692008-10-27 22:50:39 +00002603 tcg_gen_bswap_i64(arg0, arg0);
aurel32b61f2752008-10-15 17:00:37 +00002604}
2605
aurel32ea363692008-10-27 22:50:39 +00002606static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002607{
aurel32ea363692008-10-27 22:50:39 +00002608 gen_qemu_st8_ppc32(arg0, arg1, flags >> 1);
aurel32b61f2752008-10-15 17:00:37 +00002609}
2610
aurel32ea363692008-10-27 22:50:39 +00002611static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002612{
2613 if (unlikely(flags & 1)) {
2614 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
aurel32ea363692008-10-27 22:50:39 +00002615 tcg_gen_ext16u_i32(temp, arg0);
aurel32b61f2752008-10-15 17:00:37 +00002616 tcg_gen_bswap16_i32(temp, temp);
aurel32ea363692008-10-27 22:50:39 +00002617 gen_qemu_st16_ppc32(temp, arg1, flags >> 1);
aurel32312179c2008-10-27 22:50:31 +00002618 tcg_temp_free(temp);
aurel32b61f2752008-10-15 17:00:37 +00002619 } else
aurel32ea363692008-10-27 22:50:39 +00002620 gen_qemu_st16_ppc32(arg0, arg1, flags >> 1);
aurel32b61f2752008-10-15 17:00:37 +00002621}
2622
aurel32ea363692008-10-27 22:50:39 +00002623static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002624{
2625 if (unlikely(flags & 1)) {
2626 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
aurel32ea363692008-10-27 22:50:39 +00002627 tcg_gen_bswap_i32(temp, arg0);
2628 gen_qemu_st32_ppc32(temp, arg1, flags >> 1);
aurel32312179c2008-10-27 22:50:31 +00002629 tcg_temp_free(temp);
aurel32b61f2752008-10-15 17:00:37 +00002630 } else
aurel32ea363692008-10-27 22:50:39 +00002631 gen_qemu_st32_ppc32(arg0, arg1, flags >> 1);
aurel32b61f2752008-10-15 17:00:37 +00002632}
2633
aurel32ea363692008-10-27 22:50:39 +00002634static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
aurel32b61f2752008-10-15 17:00:37 +00002635{
2636 if (unlikely(flags & 1)) {
2637 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
aurel32ea363692008-10-27 22:50:39 +00002638 tcg_gen_bswap_i64(temp, arg0);
2639 gen_qemu_st64_ppc32(temp, arg1, flags >> 1);
aurel32312179c2008-10-27 22:50:31 +00002640 tcg_temp_free(temp);
aurel32b61f2752008-10-15 17:00:37 +00002641 } else
aurel32ea363692008-10-27 22:50:39 +00002642 gen_qemu_st64_ppc32(arg0, arg1, flags >> 1);
aurel32b61f2752008-10-15 17:00:37 +00002643}
2644
2645#endif
2646
j_mayerd9bce9d2007-03-17 14:02:15 +00002647#define GEN_LD(width, opc, type) \
2648GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
bellard79aceca2003-11-23 14:55:54 +00002649{ \
aurel32b61f2752008-10-15 17:00:37 +00002650 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2651 gen_addr_imm_index(EA, ctx, 0); \
2652 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2653 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002654}
2655
j_mayerd9bce9d2007-03-17 14:02:15 +00002656#define GEN_LDU(width, opc, type) \
2657GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
bellard79aceca2003-11-23 14:55:54 +00002658{ \
aurel32b61f2752008-10-15 17:00:37 +00002659 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00002660 if (unlikely(rA(ctx->opcode) == 0 || \
2661 rA(ctx->opcode) == rD(ctx->opcode))) { \
j_mayere1833e12007-09-29 13:06:16 +00002662 GEN_EXCP_INVAL(ctx); \
bellard9fddaa02004-05-21 12:59:32 +00002663 return; \
bellard9a64fbe2004-01-04 22:58:38 +00002664 } \
aurel32b61f2752008-10-15 17:00:37 +00002665 EA = tcg_temp_new(TCG_TYPE_TL); \
j_mayer9d53c752007-04-06 07:59:47 +00002666 if (type == PPC_64B) \
aurel32b61f2752008-10-15 17:00:37 +00002667 gen_addr_imm_index(EA, ctx, 0x03); \
j_mayer9d53c752007-04-06 07:59:47 +00002668 else \
aurel32b61f2752008-10-15 17:00:37 +00002669 gen_addr_imm_index(EA, ctx, 0); \
2670 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2671 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2672 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002673}
2674
j_mayerd9bce9d2007-03-17 14:02:15 +00002675#define GEN_LDUX(width, opc2, opc3, type) \
2676GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
bellard79aceca2003-11-23 14:55:54 +00002677{ \
aurel32b61f2752008-10-15 17:00:37 +00002678 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00002679 if (unlikely(rA(ctx->opcode) == 0 || \
2680 rA(ctx->opcode) == rD(ctx->opcode))) { \
j_mayere1833e12007-09-29 13:06:16 +00002681 GEN_EXCP_INVAL(ctx); \
bellard9fddaa02004-05-21 12:59:32 +00002682 return; \
bellard9a64fbe2004-01-04 22:58:38 +00002683 } \
aurel32b61f2752008-10-15 17:00:37 +00002684 EA = tcg_temp_new(TCG_TYPE_TL); \
2685 gen_addr_reg_index(EA, ctx); \
2686 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2687 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2688 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002689}
2690
j_mayerd9bce9d2007-03-17 14:02:15 +00002691#define GEN_LDX(width, opc2, opc3, type) \
2692GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
bellard79aceca2003-11-23 14:55:54 +00002693{ \
aurel32b61f2752008-10-15 17:00:37 +00002694 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2695 gen_addr_reg_index(EA, ctx); \
2696 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2697 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002698}
2699
j_mayerd9bce9d2007-03-17 14:02:15 +00002700#define GEN_LDS(width, op, type) \
j_mayerd9bce9d2007-03-17 14:02:15 +00002701GEN_LD(width, op | 0x20, type); \
2702GEN_LDU(width, op | 0x21, type); \
2703GEN_LDUX(width, 0x17, op | 0x01, type); \
2704GEN_LDX(width, 0x17, op | 0x00, type)
bellard79aceca2003-11-23 14:55:54 +00002705
2706/* lbz lbzu lbzux lbzx */
aurel32b61f2752008-10-15 17:00:37 +00002707GEN_LDS(8u, 0x02, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002708/* lha lhau lhaux lhax */
aurel32b61f2752008-10-15 17:00:37 +00002709GEN_LDS(16s, 0x0A, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002710/* lhz lhzu lhzux lhzx */
aurel32b61f2752008-10-15 17:00:37 +00002711GEN_LDS(16u, 0x08, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002712/* lwz lwzu lwzux lwzx */
aurel32b61f2752008-10-15 17:00:37 +00002713GEN_LDS(32u, 0x00, PPC_INTEGER);
j_mayerd9bce9d2007-03-17 14:02:15 +00002714#if defined(TARGET_PPC64)
j_mayerd9bce9d2007-03-17 14:02:15 +00002715/* lwaux */
aurel32b61f2752008-10-15 17:00:37 +00002716GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00002717/* lwax */
aurel32b61f2752008-10-15 17:00:37 +00002718GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00002719/* ldux */
aurel32b61f2752008-10-15 17:00:37 +00002720GEN_LDUX(64, 0x15, 0x01, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00002721/* ldx */
aurel32b61f2752008-10-15 17:00:37 +00002722GEN_LDX(64, 0x15, 0x00, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00002723GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2724{
aurel32b61f2752008-10-15 17:00:37 +00002725 TCGv EA;
j_mayerd9bce9d2007-03-17 14:02:15 +00002726 if (Rc(ctx->opcode)) {
2727 if (unlikely(rA(ctx->opcode) == 0 ||
2728 rA(ctx->opcode) == rD(ctx->opcode))) {
j_mayere1833e12007-09-29 13:06:16 +00002729 GEN_EXCP_INVAL(ctx);
j_mayerd9bce9d2007-03-17 14:02:15 +00002730 return;
2731 }
2732 }
aurel32b61f2752008-10-15 17:00:37 +00002733 EA = tcg_temp_new(TCG_TYPE_TL);
2734 gen_addr_imm_index(EA, ctx, 0x03);
j_mayerd9bce9d2007-03-17 14:02:15 +00002735 if (ctx->opcode & 0x02) {
2736 /* lwa (lwau is undefined) */
aurel32b61f2752008-10-15 17:00:37 +00002737 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
j_mayerd9bce9d2007-03-17 14:02:15 +00002738 } else {
2739 /* ld - ldu */
aurel32b61f2752008-10-15 17:00:37 +00002740 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
j_mayerd9bce9d2007-03-17 14:02:15 +00002741 }
j_mayerd9bce9d2007-03-17 14:02:15 +00002742 if (Rc(ctx->opcode))
aurel32b61f2752008-10-15 17:00:37 +00002743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2744 tcg_temp_free(EA);
j_mayerd9bce9d2007-03-17 14:02:15 +00002745}
j_mayerbe147d02007-09-30 13:03:23 +00002746/* lq */
2747GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2748{
2749#if defined(CONFIG_USER_ONLY)
2750 GEN_EXCP_PRIVOPC(ctx);
2751#else
2752 int ra, rd;
aurel32b61f2752008-10-15 17:00:37 +00002753 TCGv EA;
j_mayerbe147d02007-09-30 13:03:23 +00002754
2755 /* Restore CPU state */
2756 if (unlikely(ctx->supervisor == 0)) {
2757 GEN_EXCP_PRIVOPC(ctx);
2758 return;
2759 }
2760 ra = rA(ctx->opcode);
2761 rd = rD(ctx->opcode);
2762 if (unlikely((rd & 1) || rd == ra)) {
2763 GEN_EXCP_INVAL(ctx);
2764 return;
2765 }
2766 if (unlikely(ctx->mem_idx & 1)) {
2767 /* Little-endian mode is not handled */
2768 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2769 return;
2770 }
aurel32b61f2752008-10-15 17:00:37 +00002771 EA = tcg_temp_new(TCG_TYPE_TL);
2772 gen_addr_imm_index(EA, ctx, 0x0F);
2773 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2774 tcg_gen_addi_tl(EA, EA, 8);
2775 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2776 tcg_temp_free(EA);
j_mayerbe147d02007-09-30 13:03:23 +00002777#endif
2778}
j_mayerd9bce9d2007-03-17 14:02:15 +00002779#endif
bellard79aceca2003-11-23 14:55:54 +00002780
2781/*** Integer store ***/
j_mayerd9bce9d2007-03-17 14:02:15 +00002782#define GEN_ST(width, opc, type) \
2783GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
bellard79aceca2003-11-23 14:55:54 +00002784{ \
aurel32b61f2752008-10-15 17:00:37 +00002785 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2786 gen_addr_imm_index(EA, ctx, 0); \
2787 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2788 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002789}
2790
j_mayerd9bce9d2007-03-17 14:02:15 +00002791#define GEN_STU(width, opc, type) \
2792GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
bellard79aceca2003-11-23 14:55:54 +00002793{ \
aurel32b61f2752008-10-15 17:00:37 +00002794 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00002795 if (unlikely(rA(ctx->opcode) == 0)) { \
j_mayere1833e12007-09-29 13:06:16 +00002796 GEN_EXCP_INVAL(ctx); \
bellard9fddaa02004-05-21 12:59:32 +00002797 return; \
bellard9a64fbe2004-01-04 22:58:38 +00002798 } \
aurel32b61f2752008-10-15 17:00:37 +00002799 EA = tcg_temp_new(TCG_TYPE_TL); \
j_mayer9d53c752007-04-06 07:59:47 +00002800 if (type == PPC_64B) \
aurel32b61f2752008-10-15 17:00:37 +00002801 gen_addr_imm_index(EA, ctx, 0x03); \
j_mayer9d53c752007-04-06 07:59:47 +00002802 else \
aurel32b61f2752008-10-15 17:00:37 +00002803 gen_addr_imm_index(EA, ctx, 0); \
2804 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2806 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002807}
2808
j_mayerd9bce9d2007-03-17 14:02:15 +00002809#define GEN_STUX(width, opc2, opc3, type) \
2810GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
bellard79aceca2003-11-23 14:55:54 +00002811{ \
aurel32b61f2752008-10-15 17:00:37 +00002812 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00002813 if (unlikely(rA(ctx->opcode) == 0)) { \
j_mayere1833e12007-09-29 13:06:16 +00002814 GEN_EXCP_INVAL(ctx); \
bellard9fddaa02004-05-21 12:59:32 +00002815 return; \
bellard9a64fbe2004-01-04 22:58:38 +00002816 } \
aurel32b61f2752008-10-15 17:00:37 +00002817 EA = tcg_temp_new(TCG_TYPE_TL); \
2818 gen_addr_reg_index(EA, ctx); \
2819 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2820 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2821 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002822}
2823
j_mayerd9bce9d2007-03-17 14:02:15 +00002824#define GEN_STX(width, opc2, opc3, type) \
2825GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
bellard79aceca2003-11-23 14:55:54 +00002826{ \
aurel32b61f2752008-10-15 17:00:37 +00002827 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2828 gen_addr_reg_index(EA, ctx); \
2829 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2830 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002831}
2832
j_mayerd9bce9d2007-03-17 14:02:15 +00002833#define GEN_STS(width, op, type) \
j_mayerd9bce9d2007-03-17 14:02:15 +00002834GEN_ST(width, op | 0x20, type); \
2835GEN_STU(width, op | 0x21, type); \
2836GEN_STUX(width, 0x17, op | 0x01, type); \
2837GEN_STX(width, 0x17, op | 0x00, type)
bellard79aceca2003-11-23 14:55:54 +00002838
2839/* stb stbu stbux stbx */
aurel32b61f2752008-10-15 17:00:37 +00002840GEN_STS(8, 0x06, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002841/* sth sthu sthux sthx */
aurel32b61f2752008-10-15 17:00:37 +00002842GEN_STS(16, 0x0C, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002843/* stw stwu stwux stwx */
aurel32b61f2752008-10-15 17:00:37 +00002844GEN_STS(32, 0x04, PPC_INTEGER);
j_mayerd9bce9d2007-03-17 14:02:15 +00002845#if defined(TARGET_PPC64)
aurel32b61f2752008-10-15 17:00:37 +00002846GEN_STUX(64, 0x15, 0x05, PPC_64B);
2847GEN_STX(64, 0x15, 0x04, PPC_64B);
j_mayerbe147d02007-09-30 13:03:23 +00002848GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
j_mayerd9bce9d2007-03-17 14:02:15 +00002849{
j_mayerbe147d02007-09-30 13:03:23 +00002850 int rs;
aurel32b61f2752008-10-15 17:00:37 +00002851 TCGv EA;
j_mayerbe147d02007-09-30 13:03:23 +00002852
2853 rs = rS(ctx->opcode);
2854 if ((ctx->opcode & 0x3) == 0x2) {
2855#if defined(CONFIG_USER_ONLY)
2856 GEN_EXCP_PRIVOPC(ctx);
2857#else
2858 /* stq */
2859 if (unlikely(ctx->supervisor == 0)) {
2860 GEN_EXCP_PRIVOPC(ctx);
2861 return;
2862 }
2863 if (unlikely(rs & 1)) {
j_mayere1833e12007-09-29 13:06:16 +00002864 GEN_EXCP_INVAL(ctx);
j_mayerd9bce9d2007-03-17 14:02:15 +00002865 return;
2866 }
j_mayerbe147d02007-09-30 13:03:23 +00002867 if (unlikely(ctx->mem_idx & 1)) {
2868 /* Little-endian mode is not handled */
2869 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2870 return;
2871 }
aurel32b61f2752008-10-15 17:00:37 +00002872 EA = tcg_temp_new(TCG_TYPE_TL);
2873 gen_addr_imm_index(EA, ctx, 0x03);
2874 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
2875 tcg_gen_addi_tl(EA, EA, 8);
2876 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
2877 tcg_temp_free(EA);
j_mayerbe147d02007-09-30 13:03:23 +00002878#endif
2879 } else {
2880 /* std / stdu */
2881 if (Rc(ctx->opcode)) {
2882 if (unlikely(rA(ctx->opcode) == 0)) {
2883 GEN_EXCP_INVAL(ctx);
2884 return;
2885 }
2886 }
aurel32b61f2752008-10-15 17:00:37 +00002887 EA = tcg_temp_new(TCG_TYPE_TL);
2888 gen_addr_imm_index(EA, ctx, 0x03);
2889 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
j_mayerbe147d02007-09-30 13:03:23 +00002890 if (Rc(ctx->opcode))
aurel32b61f2752008-10-15 17:00:37 +00002891 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2892 tcg_temp_free(EA);
j_mayerd9bce9d2007-03-17 14:02:15 +00002893 }
j_mayerd9bce9d2007-03-17 14:02:15 +00002894}
2895#endif
bellard79aceca2003-11-23 14:55:54 +00002896/*** Integer load and store with byte reverse ***/
2897/* lhbrx */
aurel32b61f2752008-10-15 17:00:37 +00002898void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
2899{
2900 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2901 gen_qemu_ld16u(temp, t1, flags);
2902 tcg_gen_bswap16_i32(temp, temp);
2903 tcg_gen_extu_i32_tl(t0, temp);
2904 tcg_temp_free(temp);
2905}
2906GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
2907
bellard79aceca2003-11-23 14:55:54 +00002908/* lwbrx */
aurel32b61f2752008-10-15 17:00:37 +00002909void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
2910{
2911 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2912 gen_qemu_ld32u(temp, t1, flags);
2913 tcg_gen_bswap_i32(temp, temp);
2914 tcg_gen_extu_i32_tl(t0, temp);
2915 tcg_temp_free(temp);
2916}
2917GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
2918
bellard79aceca2003-11-23 14:55:54 +00002919/* sthbrx */
aurel32b61f2752008-10-15 17:00:37 +00002920void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
2921{
2922 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2923 tcg_gen_trunc_tl_i32(temp, t0);
2924 tcg_gen_ext16u_i32(temp, temp);
2925 tcg_gen_bswap16_i32(temp, temp);
2926 gen_qemu_st16(temp, t1, flags);
2927 tcg_temp_free(temp);
2928}
2929GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
2930
bellard79aceca2003-11-23 14:55:54 +00002931/* stwbrx */
aurel32b61f2752008-10-15 17:00:37 +00002932void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
2933{
2934 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2935 tcg_gen_trunc_tl_i32(temp, t0);
2936 tcg_gen_bswap_i32(temp, temp);
2937 gen_qemu_st32(temp, t1, flags);
2938 tcg_temp_free(temp);
2939}
2940GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002941
2942/*** Integer load and store multiple ***/
bellard9a64fbe2004-01-04 22:58:38 +00002943#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
j_mayer78636672007-11-16 14:11:28 +00002944static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2945 GEN_MEM_FUNCS(lmw),
bellard111bfab2005-04-23 18:16:07 +00002946};
j_mayer78636672007-11-16 14:11:28 +00002947static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2948 GEN_MEM_FUNCS(stmw),
bellard111bfab2005-04-23 18:16:07 +00002949};
bellard9a64fbe2004-01-04 22:58:38 +00002950
bellard79aceca2003-11-23 14:55:54 +00002951/* lmw */
2952GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2953{
j_mayer76a66252007-03-07 08:32:30 +00002954 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00002955 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00002956 gen_addr_imm_index(cpu_T[0], ctx, 0);
bellard9a64fbe2004-01-04 22:58:38 +00002957 op_ldstm(lmw, rD(ctx->opcode));
bellard79aceca2003-11-23 14:55:54 +00002958}
2959
2960/* stmw */
2961GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2962{
j_mayer76a66252007-03-07 08:32:30 +00002963 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00002964 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00002965 gen_addr_imm_index(cpu_T[0], ctx, 0);
bellard9a64fbe2004-01-04 22:58:38 +00002966 op_ldstm(stmw, rS(ctx->opcode));
bellard79aceca2003-11-23 14:55:54 +00002967}
2968
2969/*** Integer load and store strings ***/
bellard9a64fbe2004-01-04 22:58:38 +00002970#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2971#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
j_mayere7c24002007-11-22 11:00:46 +00002972/* string load & stores are by definition endian-safe */
2973#define gen_op_lswi_le_raw gen_op_lswi_raw
2974#define gen_op_lswi_le_user gen_op_lswi_user
2975#define gen_op_lswi_le_kernel gen_op_lswi_kernel
2976#define gen_op_lswi_le_hypv gen_op_lswi_hypv
2977#define gen_op_lswi_le_64_raw gen_op_lswi_raw
2978#define gen_op_lswi_le_64_user gen_op_lswi_user
2979#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2980#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
j_mayer78636672007-11-16 14:11:28 +00002981static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2982 GEN_MEM_FUNCS(lswi),
j_mayerd9bce9d2007-03-17 14:02:15 +00002983};
j_mayere7c24002007-11-22 11:00:46 +00002984#define gen_op_lswx_le_raw gen_op_lswx_raw
2985#define gen_op_lswx_le_user gen_op_lswx_user
2986#define gen_op_lswx_le_kernel gen_op_lswx_kernel
2987#define gen_op_lswx_le_hypv gen_op_lswx_hypv
2988#define gen_op_lswx_le_64_raw gen_op_lswx_raw
2989#define gen_op_lswx_le_64_user gen_op_lswx_user
2990#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2991#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
j_mayer78636672007-11-16 14:11:28 +00002992static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2993 GEN_MEM_FUNCS(lswx),
j_mayerd9bce9d2007-03-17 14:02:15 +00002994};
j_mayere7c24002007-11-22 11:00:46 +00002995#define gen_op_stsw_le_raw gen_op_stsw_raw
2996#define gen_op_stsw_le_user gen_op_stsw_user
2997#define gen_op_stsw_le_kernel gen_op_stsw_kernel
2998#define gen_op_stsw_le_hypv gen_op_stsw_hypv
2999#define gen_op_stsw_le_64_raw gen_op_stsw_raw
3000#define gen_op_stsw_le_64_user gen_op_stsw_user
3001#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
3002#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
j_mayer78636672007-11-16 14:11:28 +00003003static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
3004 GEN_MEM_FUNCS(stsw),
j_mayerd9bce9d2007-03-17 14:02:15 +00003005};
bellard9a64fbe2004-01-04 22:58:38 +00003006
bellard79aceca2003-11-23 14:55:54 +00003007/* lswi */
bellard3fc6c082005-07-02 20:59:34 +00003008/* PowerPC32 specification says we must generate an exception if
bellard9a64fbe2004-01-04 22:58:38 +00003009 * rA is in the range of registers to be loaded.
3010 * In an other hand, IBM says this is valid, but rA won't be loaded.
3011 * For now, I'll follow the spec...
3012 */
j_mayer05332d72007-11-17 22:26:51 +00003013GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
bellard79aceca2003-11-23 14:55:54 +00003014{
3015 int nb = NB(ctx->opcode);
3016 int start = rD(ctx->opcode);
bellard9a64fbe2004-01-04 22:58:38 +00003017 int ra = rA(ctx->opcode);
bellard79aceca2003-11-23 14:55:54 +00003018 int nr;
3019
3020 if (nb == 0)
3021 nb = 32;
3022 nr = nb / 4;
j_mayer76a66252007-03-07 08:32:30 +00003023 if (unlikely(((start + nr) > 32 &&
3024 start <= ra && (start + nr - 32) > ra) ||
3025 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
j_mayere1833e12007-09-29 13:06:16 +00003026 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3027 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
bellard9fddaa02004-05-21 12:59:32 +00003028 return;
bellard297d8e62004-02-21 14:11:27 +00003029 }
bellard8dd49832005-06-04 22:22:27 +00003030 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00003031 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00003032 gen_addr_register(cpu_T[0], ctx);
aurel3286c581d2008-09-02 23:26:32 +00003033 tcg_gen_movi_tl(cpu_T[1], nb);
bellard9a64fbe2004-01-04 22:58:38 +00003034 op_ldsts(lswi, start);
bellard79aceca2003-11-23 14:55:54 +00003035}
3036
3037/* lswx */
j_mayer05332d72007-11-17 22:26:51 +00003038GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
bellard79aceca2003-11-23 14:55:54 +00003039{
bellard9a64fbe2004-01-04 22:58:38 +00003040 int ra = rA(ctx->opcode);
3041 int rb = rB(ctx->opcode);
3042
j_mayer76a66252007-03-07 08:32:30 +00003043 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00003044 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00003045 gen_addr_reg_index(cpu_T[0], ctx);
bellard9a64fbe2004-01-04 22:58:38 +00003046 if (ra == 0) {
bellard9a64fbe2004-01-04 22:58:38 +00003047 ra = rb;
bellard79aceca2003-11-23 14:55:54 +00003048 }
aurel323d7b4172008-10-21 11:28:46 +00003049 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
bellard9a64fbe2004-01-04 22:58:38 +00003050 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
bellard79aceca2003-11-23 14:55:54 +00003051}
3052
3053/* stswi */
j_mayer05332d72007-11-17 22:26:51 +00003054GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
bellard79aceca2003-11-23 14:55:54 +00003055{
bellard4b3686f2004-05-23 22:18:12 +00003056 int nb = NB(ctx->opcode);
3057
j_mayer76a66252007-03-07 08:32:30 +00003058 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00003059 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00003060 gen_addr_register(cpu_T[0], ctx);
bellard4b3686f2004-05-23 22:18:12 +00003061 if (nb == 0)
3062 nb = 32;
aurel3286c581d2008-09-02 23:26:32 +00003063 tcg_gen_movi_tl(cpu_T[1], nb);
bellard9a64fbe2004-01-04 22:58:38 +00003064 op_ldsts(stsw, rS(ctx->opcode));
bellard79aceca2003-11-23 14:55:54 +00003065}
3066
3067/* stswx */
j_mayer05332d72007-11-17 22:26:51 +00003068GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
bellard79aceca2003-11-23 14:55:54 +00003069{
bellard8dd49832005-06-04 22:22:27 +00003070 /* NIP cannot be restored if the memory exception comes from an helper */
ths5fafdf22007-09-16 21:08:06 +00003071 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00003072 gen_addr_reg_index(cpu_T[0], ctx);
aurel323d7b4172008-10-21 11:28:46 +00003073 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
bellard9a64fbe2004-01-04 22:58:38 +00003074 op_ldsts(stsw, rS(ctx->opcode));
bellard79aceca2003-11-23 14:55:54 +00003075}
3076
3077/*** Memory synchronisation ***/
3078/* eieio */
j_mayer0db1b202007-09-30 03:46:38 +00003079GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
bellard79aceca2003-11-23 14:55:54 +00003080{
bellard79aceca2003-11-23 14:55:54 +00003081}
3082
3083/* isync */
j_mayer0db1b202007-09-30 03:46:38 +00003084GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
bellard79aceca2003-11-23 14:55:54 +00003085{
j_mayere1833e12007-09-29 13:06:16 +00003086 GEN_STOP(ctx);
bellard79aceca2003-11-23 14:55:54 +00003087}
3088
bellard985a19d2004-01-18 22:49:57 +00003089#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
bellard111bfab2005-04-23 18:16:07 +00003090#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
j_mayer78636672007-11-16 14:11:28 +00003091static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3092 GEN_MEM_FUNCS(lwarx),
j_mayerd9bce9d2007-03-17 14:02:15 +00003093};
j_mayer78636672007-11-16 14:11:28 +00003094static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3095 GEN_MEM_FUNCS(stwcx),
j_mayerd9bce9d2007-03-17 14:02:15 +00003096};
bellard9a64fbe2004-01-04 22:58:38 +00003097
bellard111bfab2005-04-23 18:16:07 +00003098/* lwarx */
j_mayer76a66252007-03-07 08:32:30 +00003099GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
bellard79aceca2003-11-23 14:55:54 +00003100{
j_mayer30032c92007-10-01 05:22:17 +00003101 /* NIP cannot be restored if the memory exception comes from an helper */
3102 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00003103 gen_addr_reg_index(cpu_T[0], ctx);
bellard985a19d2004-01-18 22:49:57 +00003104 op_lwarx();
aurel32f78fb442008-09-04 05:25:47 +00003105 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
bellard79aceca2003-11-23 14:55:54 +00003106}
3107
3108/* stwcx. */
j_mayerc7697e12007-10-26 00:46:07 +00003109GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
bellard79aceca2003-11-23 14:55:54 +00003110{
j_mayer30032c92007-10-01 05:22:17 +00003111 /* NIP cannot be restored if the memory exception comes from an helper */
3112 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00003113 gen_addr_reg_index(cpu_T[0], ctx);
aurel32f78fb442008-09-04 05:25:47 +00003114 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
bellard9a64fbe2004-01-04 22:58:38 +00003115 op_stwcx();
bellard79aceca2003-11-23 14:55:54 +00003116}
3117
j_mayer426613d2007-03-23 09:45:27 +00003118#if defined(TARGET_PPC64)
3119#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3120#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
j_mayer78636672007-11-16 14:11:28 +00003121static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3122 GEN_MEM_FUNCS(ldarx),
j_mayer426613d2007-03-23 09:45:27 +00003123};
j_mayer78636672007-11-16 14:11:28 +00003124static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3125 GEN_MEM_FUNCS(stdcx),
j_mayer426613d2007-03-23 09:45:27 +00003126};
j_mayer426613d2007-03-23 09:45:27 +00003127
3128/* ldarx */
j_mayera750fc02007-09-26 23:54:22 +00003129GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
j_mayer426613d2007-03-23 09:45:27 +00003130{
j_mayer30032c92007-10-01 05:22:17 +00003131 /* NIP cannot be restored if the memory exception comes from an helper */
3132 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00003133 gen_addr_reg_index(cpu_T[0], ctx);
j_mayer426613d2007-03-23 09:45:27 +00003134 op_ldarx();
aurel32f78fb442008-09-04 05:25:47 +00003135 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
j_mayer426613d2007-03-23 09:45:27 +00003136}
3137
3138/* stdcx. */
j_mayerc7697e12007-10-26 00:46:07 +00003139GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
j_mayer426613d2007-03-23 09:45:27 +00003140{
j_mayer30032c92007-10-01 05:22:17 +00003141 /* NIP cannot be restored if the memory exception comes from an helper */
3142 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00003143 gen_addr_reg_index(cpu_T[0], ctx);
aurel32f78fb442008-09-04 05:25:47 +00003144 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
j_mayer426613d2007-03-23 09:45:27 +00003145 op_stdcx();
3146}
3147#endif /* defined(TARGET_PPC64) */
3148
bellard79aceca2003-11-23 14:55:54 +00003149/* sync */
j_mayera902d882007-09-30 15:21:15 +00003150GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
bellard79aceca2003-11-23 14:55:54 +00003151{
bellard79aceca2003-11-23 14:55:54 +00003152}
3153
j_mayer0db1b202007-09-30 03:46:38 +00003154/* wait */
3155GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3156{
3157 /* Stop translation, as the CPU is supposed to sleep from now */
j_mayerbe147d02007-09-30 13:03:23 +00003158 gen_op_wait();
3159 GEN_EXCP(ctx, EXCP_HLT, 1);
j_mayer0db1b202007-09-30 03:46:38 +00003160}
3161
bellard79aceca2003-11-23 14:55:54 +00003162/*** Floating-point load ***/
j_mayer477023a2007-09-30 01:01:08 +00003163#define GEN_LDF(width, opc, type) \
3164GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
bellard79aceca2003-11-23 14:55:54 +00003165{ \
j_mayer76a66252007-03-07 08:32:30 +00003166 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00003167 GEN_EXCP_NO_FP(ctx); \
bellard4ecc3192005-03-13 17:01:22 +00003168 return; \
3169 } \
aurel32e2be8d82008-10-14 19:55:54 +00003170 gen_addr_imm_index(cpu_T[0], ctx, 0); \
bellard9a64fbe2004-01-04 22:58:38 +00003171 op_ldst(l##width); \
aurel32a5e26af2008-09-04 14:43:54 +00003172 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
bellard79aceca2003-11-23 14:55:54 +00003173}
3174
j_mayer477023a2007-09-30 01:01:08 +00003175#define GEN_LDUF(width, opc, type) \
3176GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
bellard79aceca2003-11-23 14:55:54 +00003177{ \
j_mayer76a66252007-03-07 08:32:30 +00003178 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00003179 GEN_EXCP_NO_FP(ctx); \
bellard4ecc3192005-03-13 17:01:22 +00003180 return; \
3181 } \
j_mayer76a66252007-03-07 08:32:30 +00003182 if (unlikely(rA(ctx->opcode) == 0)) { \
j_mayere1833e12007-09-29 13:06:16 +00003183 GEN_EXCP_INVAL(ctx); \
bellard9fddaa02004-05-21 12:59:32 +00003184 return; \
bellard9a64fbe2004-01-04 22:58:38 +00003185 } \
aurel32e2be8d82008-10-14 19:55:54 +00003186 gen_addr_imm_index(cpu_T[0], ctx, 0); \
bellard9a64fbe2004-01-04 22:58:38 +00003187 op_ldst(l##width); \
aurel32a5e26af2008-09-04 14:43:54 +00003188 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
aurel32f78fb442008-09-04 05:25:47 +00003189 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
bellard79aceca2003-11-23 14:55:54 +00003190}
3191
j_mayer477023a2007-09-30 01:01:08 +00003192#define GEN_LDUXF(width, opc, type) \
3193GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
bellard79aceca2003-11-23 14:55:54 +00003194{ \
j_mayer76a66252007-03-07 08:32:30 +00003195 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00003196 GEN_EXCP_NO_FP(ctx); \
bellard4ecc3192005-03-13 17:01:22 +00003197 return; \
3198 } \
j_mayer76a66252007-03-07 08:32:30 +00003199 if (unlikely(rA(ctx->opcode) == 0)) { \
j_mayere1833e12007-09-29 13:06:16 +00003200 GEN_EXCP_INVAL(ctx); \
bellard9fddaa02004-05-21 12:59:32 +00003201 return; \
bellard9a64fbe2004-01-04 22:58:38 +00003202 } \
aurel32e2be8d82008-10-14 19:55:54 +00003203 gen_addr_reg_index(cpu_T[0], ctx); \
bellard9a64fbe2004-01-04 22:58:38 +00003204 op_ldst(l##width); \
aurel32a5e26af2008-09-04 14:43:54 +00003205 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
aurel32f78fb442008-09-04 05:25:47 +00003206 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
bellard79aceca2003-11-23 14:55:54 +00003207}
3208
j_mayer477023a2007-09-30 01:01:08 +00003209#define GEN_LDXF(width, opc2, opc3, type) \
3210GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
bellard79aceca2003-11-23 14:55:54 +00003211{ \
j_mayer76a66252007-03-07 08:32:30 +00003212 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00003213 GEN_EXCP_NO_FP(ctx); \
bellard4ecc3192005-03-13 17:01:22 +00003214 return; \
3215 } \
aurel32e2be8d82008-10-14 19:55:54 +00003216 gen_addr_reg_index(cpu_T[0], ctx); \
bellard9a64fbe2004-01-04 22:58:38 +00003217 op_ldst(l##width); \
aurel32a5e26af2008-09-04 14:43:54 +00003218 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
bellard79aceca2003-11-23 14:55:54 +00003219}
3220
j_mayer477023a2007-09-30 01:01:08 +00003221#define GEN_LDFS(width, op, type) \
bellard9a64fbe2004-01-04 22:58:38 +00003222OP_LD_TABLE(width); \
j_mayer477023a2007-09-30 01:01:08 +00003223GEN_LDF(width, op | 0x20, type); \
3224GEN_LDUF(width, op | 0x21, type); \
3225GEN_LDUXF(width, op | 0x01, type); \
3226GEN_LDXF(width, 0x17, op | 0x00, type)
bellard79aceca2003-11-23 14:55:54 +00003227
3228/* lfd lfdu lfdux lfdx */
j_mayer477023a2007-09-30 01:01:08 +00003229GEN_LDFS(fd, 0x12, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00003230/* lfs lfsu lfsux lfsx */
j_mayer477023a2007-09-30 01:01:08 +00003231GEN_LDFS(fs, 0x10, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00003232
3233/*** Floating-point store ***/
j_mayer477023a2007-09-30 01:01:08 +00003234#define GEN_STF(width, opc, type) \
3235GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
bellard79aceca2003-11-23 14:55:54 +00003236{ \
j_mayer76a66252007-03-07 08:32:30 +00003237 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00003238 GEN_EXCP_NO_FP(ctx); \
bellard4ecc3192005-03-13 17:01:22 +00003239 return; \
3240 } \
aurel32e2be8d82008-10-14 19:55:54 +00003241 gen_addr_imm_index(cpu_T[0], ctx, 0); \
aurel32a5e26af2008-09-04 14:43:54 +00003242 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
bellard9a64fbe2004-01-04 22:58:38 +00003243 op_ldst(st##width); \
bellard79aceca2003-11-23 14:55:54 +00003244}
3245
j_mayer477023a2007-09-30 01:01:08 +00003246#define GEN_STUF(width, opc, type) \
3247GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
bellard79aceca2003-11-23 14:55:54 +00003248{ \
j_mayer76a66252007-03-07 08:32:30 +00003249 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00003250 GEN_EXCP_NO_FP(ctx); \
bellard4ecc3192005-03-13 17:01:22 +00003251 return; \
3252 } \
j_mayer76a66252007-03-07 08:32:30 +00003253 if (unlikely(rA(ctx->opcode) == 0)) { \
j_mayere1833e12007-09-29 13:06:16 +00003254 GEN_EXCP_INVAL(ctx); \
bellard9fddaa02004-05-21 12:59:32 +00003255 return; \
bellard9a64fbe2004-01-04 22:58:38 +00003256 } \
aurel32e2be8d82008-10-14 19:55:54 +00003257 gen_addr_imm_index(cpu_T[0], ctx, 0); \
aurel32a5e26af2008-09-04 14:43:54 +00003258 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
bellard9a64fbe2004-01-04 22:58:38 +00003259 op_ldst(st##width); \
aurel32f78fb442008-09-04 05:25:47 +00003260 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
bellard79aceca2003-11-23 14:55:54 +00003261}
3262
j_mayer477023a2007-09-30 01:01:08 +00003263#define GEN_STUXF(width, opc, type) \
3264GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
bellard79aceca2003-11-23 14:55:54 +00003265{ \
j_mayer76a66252007-03-07 08:32:30 +00003266 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00003267 GEN_EXCP_NO_FP(ctx); \
bellard4ecc3192005-03-13 17:01:22 +00003268 return; \
3269 } \
j_mayer76a66252007-03-07 08:32:30 +00003270 if (unlikely(rA(ctx->opcode) == 0)) { \
j_mayere1833e12007-09-29 13:06:16 +00003271 GEN_EXCP_INVAL(ctx); \
bellard9fddaa02004-05-21 12:59:32 +00003272 return; \
bellard9a64fbe2004-01-04 22:58:38 +00003273 } \
aurel32e2be8d82008-10-14 19:55:54 +00003274 gen_addr_reg_index(cpu_T[0], ctx); \
aurel32a5e26af2008-09-04 14:43:54 +00003275 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
bellard9a64fbe2004-01-04 22:58:38 +00003276 op_ldst(st##width); \
aurel32f78fb442008-09-04 05:25:47 +00003277 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
bellard79aceca2003-11-23 14:55:54 +00003278}
3279
j_mayer477023a2007-09-30 01:01:08 +00003280#define GEN_STXF(width, opc2, opc3, type) \
3281GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
bellard79aceca2003-11-23 14:55:54 +00003282{ \
j_mayer76a66252007-03-07 08:32:30 +00003283 if (unlikely(!ctx->fpu_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00003284 GEN_EXCP_NO_FP(ctx); \
bellard4ecc3192005-03-13 17:01:22 +00003285 return; \
3286 } \
aurel32e2be8d82008-10-14 19:55:54 +00003287 gen_addr_reg_index(cpu_T[0], ctx); \
aurel32a5e26af2008-09-04 14:43:54 +00003288 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
bellard9a64fbe2004-01-04 22:58:38 +00003289 op_ldst(st##width); \
bellard79aceca2003-11-23 14:55:54 +00003290}
3291
j_mayer477023a2007-09-30 01:01:08 +00003292#define GEN_STFS(width, op, type) \
bellard9a64fbe2004-01-04 22:58:38 +00003293OP_ST_TABLE(width); \
j_mayer477023a2007-09-30 01:01:08 +00003294GEN_STF(width, op | 0x20, type); \
3295GEN_STUF(width, op | 0x21, type); \
3296GEN_STUXF(width, op | 0x01, type); \
3297GEN_STXF(width, 0x17, op | 0x00, type)
bellard79aceca2003-11-23 14:55:54 +00003298
3299/* stfd stfdu stfdux stfdx */
j_mayer477023a2007-09-30 01:01:08 +00003300GEN_STFS(fd, 0x16, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00003301/* stfs stfsu stfsux stfsx */
j_mayer477023a2007-09-30 01:01:08 +00003302GEN_STFS(fs, 0x14, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00003303
3304/* Optional: */
3305/* stfiwx */
j_mayer5b8105f2007-11-19 11:39:29 +00003306OP_ST_TABLE(fiw);
3307GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
bellard79aceca2003-11-23 14:55:54 +00003308
3309/*** Branch ***/
j_mayerb068d6a2007-10-07 17:13:44 +00003310static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3311 target_ulong dest)
bellardc53be332005-10-30 21:39:19 +00003312{
bellardc1942362005-11-20 10:31:08 +00003313 TranslationBlock *tb;
3314 tb = ctx->tb;
aurel32a2ffb812008-10-21 16:31:31 +00003315#if defined(TARGET_PPC64)
3316 if (!ctx->sf_mode)
3317 dest = (uint32_t) dest;
3318#endif
bellard57fec1f2008-02-01 10:50:11 +00003319 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
aurel328cbcb4f2008-05-10 23:28:14 +00003320 likely(!ctx->singlestep_enabled)) {
bellard57fec1f2008-02-01 10:50:11 +00003321 tcg_gen_goto_tb(n);
aurel32a2ffb812008-10-21 16:31:31 +00003322 tcg_gen_movi_tl(cpu_nip, dest & ~3);
bellard57fec1f2008-02-01 10:50:11 +00003323 tcg_gen_exit_tb((long)tb + n);
bellardc1942362005-11-20 10:31:08 +00003324 } else {
aurel32a2ffb812008-10-21 16:31:31 +00003325 tcg_gen_movi_tl(cpu_nip, dest & ~3);
aurel328cbcb4f2008-05-10 23:28:14 +00003326 if (unlikely(ctx->singlestep_enabled)) {
3327 if ((ctx->singlestep_enabled &
3328 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3329 ctx->exception == POWERPC_EXCP_BRANCH) {
3330 target_ulong tmp = ctx->nip;
3331 ctx->nip = dest;
3332 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3333 ctx->nip = tmp;
3334 }
3335 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3336 gen_update_nip(ctx, dest);
3337 gen_op_debug();
3338 }
3339 }
bellard57fec1f2008-02-01 10:50:11 +00003340 tcg_gen_exit_tb(0);
bellardc1942362005-11-20 10:31:08 +00003341 }
bellardc53be332005-10-30 21:39:19 +00003342}
3343
j_mayerb068d6a2007-10-07 17:13:44 +00003344static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
j_mayere1833e12007-09-29 13:06:16 +00003345{
3346#if defined(TARGET_PPC64)
aurel32a2ffb812008-10-21 16:31:31 +00003347 if (ctx->sf_mode == 0)
3348 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
j_mayere1833e12007-09-29 13:06:16 +00003349 else
3350#endif
aurel32a2ffb812008-10-21 16:31:31 +00003351 tcg_gen_movi_tl(cpu_lr, nip);
j_mayere1833e12007-09-29 13:06:16 +00003352}
3353
bellard79aceca2003-11-23 14:55:54 +00003354/* b ba bl bla */
3355GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3356{
j_mayer76a66252007-03-07 08:32:30 +00003357 target_ulong li, target;
bellard38a64f92004-07-07 22:06:01 +00003358
aurel328cbcb4f2008-05-10 23:28:14 +00003359 ctx->exception = POWERPC_EXCP_BRANCH;
bellard38a64f92004-07-07 22:06:01 +00003360 /* sign extend LI */
j_mayer76a66252007-03-07 08:32:30 +00003361#if defined(TARGET_PPC64)
j_mayerd9bce9d2007-03-17 14:02:15 +00003362 if (ctx->sf_mode)
3363 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3364 else
j_mayer76a66252007-03-07 08:32:30 +00003365#endif
j_mayerd9bce9d2007-03-17 14:02:15 +00003366 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
j_mayer76a66252007-03-07 08:32:30 +00003367 if (likely(AA(ctx->opcode) == 0))
bellard046d6672004-04-25 21:15:35 +00003368 target = ctx->nip + li - 4;
bellard79aceca2003-11-23 14:55:54 +00003369 else
bellard9a64fbe2004-01-04 22:58:38 +00003370 target = li;
j_mayere1833e12007-09-29 13:06:16 +00003371 if (LK(ctx->opcode))
3372 gen_setlr(ctx, ctx->nip);
bellardc1942362005-11-20 10:31:08 +00003373 gen_goto_tb(ctx, 0, target);
bellard79aceca2003-11-23 14:55:54 +00003374}
3375
bellarde98a6e42004-02-21 15:35:00 +00003376#define BCOND_IM 0
3377#define BCOND_LR 1
3378#define BCOND_CTR 2
bellard79aceca2003-11-23 14:55:54 +00003379
j_mayerb068d6a2007-10-07 17:13:44 +00003380static always_inline void gen_bcond (DisasContext *ctx, int type)
j_mayerd9bce9d2007-03-17 14:02:15 +00003381{
j_mayerd9bce9d2007-03-17 14:02:15 +00003382 uint32_t bo = BO(ctx->opcode);
aurel32a2ffb812008-10-21 16:31:31 +00003383 int l1 = gen_new_label();
3384 TCGv target;
bellard79aceca2003-11-23 14:55:54 +00003385
aurel328cbcb4f2008-05-10 23:28:14 +00003386 ctx->exception = POWERPC_EXCP_BRANCH;
aurel32a2ffb812008-10-21 16:31:31 +00003387 if (type == BCOND_LR || type == BCOND_CTR) {
3388 target = tcg_temp_local_new(TCG_TYPE_TL);
3389 if (type == BCOND_CTR)
3390 tcg_gen_mov_tl(target, cpu_ctr);
3391 else
3392 tcg_gen_mov_tl(target, cpu_lr);
bellarde98a6e42004-02-21 15:35:00 +00003393 }
j_mayere1833e12007-09-29 13:06:16 +00003394 if (LK(ctx->opcode))
3395 gen_setlr(ctx, ctx->nip);
aurel32a2ffb812008-10-21 16:31:31 +00003396 l1 = gen_new_label();
3397 if ((bo & 0x4) == 0) {
3398 /* Decrement and test CTR */
3399 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3400 if (unlikely(type == BCOND_CTR)) {
3401 GEN_EXCP_INVAL(ctx);
3402 return;
bellarde98a6e42004-02-21 15:35:00 +00003403 }
aurel32a2ffb812008-10-21 16:31:31 +00003404 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
j_mayerd9bce9d2007-03-17 14:02:15 +00003405#if defined(TARGET_PPC64)
aurel32a2ffb812008-10-21 16:31:31 +00003406 if (!ctx->sf_mode)
3407 tcg_gen_ext32u_tl(temp, cpu_ctr);
3408 else
j_mayerd9bce9d2007-03-17 14:02:15 +00003409#endif
aurel32a2ffb812008-10-21 16:31:31 +00003410 tcg_gen_mov_tl(temp, cpu_ctr);
3411 if (bo & 0x2) {
3412 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
j_mayerd9bce9d2007-03-17 14:02:15 +00003413 } else {
aurel32a2ffb812008-10-21 16:31:31 +00003414 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3415 }
3416 }
3417 if ((bo & 0x10) == 0) {
3418 /* Test CR */
3419 uint32_t bi = BI(ctx->opcode);
3420 uint32_t mask = 1 << (3 - (bi & 0x03));
3421 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3422
3423 if (bo & 0x8) {
3424 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3425 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3426 } else {
3427 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3428 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
j_mayerd9bce9d2007-03-17 14:02:15 +00003429 }
3430 }
bellarde98a6e42004-02-21 15:35:00 +00003431 if (type == BCOND_IM) {
aurel32a2ffb812008-10-21 16:31:31 +00003432
3433 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3434 if (likely(AA(ctx->opcode) == 0)) {
3435 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3436 } else {
3437 gen_goto_tb(ctx, 0, li);
3438 }
bellardc53be332005-10-30 21:39:19 +00003439 gen_set_label(l1);
bellardc1942362005-11-20 10:31:08 +00003440 gen_goto_tb(ctx, 1, ctx->nip);
bellarde98a6e42004-02-21 15:35:00 +00003441 } else {
j_mayerd9bce9d2007-03-17 14:02:15 +00003442#if defined(TARGET_PPC64)
aurel32a2ffb812008-10-21 16:31:31 +00003443 if (!(ctx->sf_mode))
3444 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
j_mayerd9bce9d2007-03-17 14:02:15 +00003445 else
3446#endif
aurel32a2ffb812008-10-21 16:31:31 +00003447 tcg_gen_andi_tl(cpu_nip, target, ~3);
3448 tcg_gen_exit_tb(0);
3449 gen_set_label(l1);
3450#if defined(TARGET_PPC64)
3451 if (!(ctx->sf_mode))
3452 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3453 else
3454#endif
3455 tcg_gen_movi_tl(cpu_nip, ctx->nip);
bellard57fec1f2008-02-01 10:50:11 +00003456 tcg_gen_exit_tb(0);
j_mayer08e46e52007-04-16 07:18:42 +00003457 }
bellarde98a6e42004-02-21 15:35:00 +00003458}
3459
3460GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
ths3b46e622007-09-17 08:09:54 +00003461{
bellarde98a6e42004-02-21 15:35:00 +00003462 gen_bcond(ctx, BCOND_IM);
3463}
3464
3465GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
ths3b46e622007-09-17 08:09:54 +00003466{
bellarde98a6e42004-02-21 15:35:00 +00003467 gen_bcond(ctx, BCOND_CTR);
3468}
3469
3470GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
ths3b46e622007-09-17 08:09:54 +00003471{
bellarde98a6e42004-02-21 15:35:00 +00003472 gen_bcond(ctx, BCOND_LR);
3473}
bellard79aceca2003-11-23 14:55:54 +00003474
3475/*** Condition register logical ***/
aurel32e1571902008-10-21 11:31:14 +00003476#define GEN_CRLOGIC(name, tcg_op, opc) \
3477GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
bellard79aceca2003-11-23 14:55:54 +00003478{ \
j_mayerfc0d4412007-10-31 22:02:17 +00003479 uint8_t bitmask; \
3480 int sh; \
aurel32e1571902008-10-21 11:31:14 +00003481 TCGv temp1, temp2; \
j_mayerfc0d4412007-10-31 22:02:17 +00003482 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
aurel32e1571902008-10-21 11:31:14 +00003483 temp1 = tcg_temp_new(TCG_TYPE_I32); \
j_mayerfc0d4412007-10-31 22:02:17 +00003484 if (sh > 0) \
aurel32e1571902008-10-21 11:31:14 +00003485 tcg_gen_shri_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
j_mayerfc0d4412007-10-31 22:02:17 +00003486 else if (sh < 0) \
aurel32e1571902008-10-21 11:31:14 +00003487 tcg_gen_shli_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3488 else \
pbrook2e31f5d2008-10-24 12:03:16 +00003489 tcg_gen_mov_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2]); \
aurel32e1571902008-10-21 11:31:14 +00003490 temp2 = tcg_temp_new(TCG_TYPE_I32); \
j_mayerfc0d4412007-10-31 22:02:17 +00003491 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3492 if (sh > 0) \
aurel32e1571902008-10-21 11:31:14 +00003493 tcg_gen_shri_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
j_mayerfc0d4412007-10-31 22:02:17 +00003494 else if (sh < 0) \
aurel32e1571902008-10-21 11:31:14 +00003495 tcg_gen_shli_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3496 else \
3497 tcg_gen_mov_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2]); \
3498 tcg_op(temp1, temp1, temp2); \
j_mayerfc0d4412007-10-31 22:02:17 +00003499 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
aurel32e1571902008-10-21 11:31:14 +00003500 tcg_gen_andi_i32(temp1, temp1, bitmask); \
3501 tcg_gen_andi_i32(temp2, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3502 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], temp1, temp2); \
3503 tcg_temp_free(temp1); \
3504 tcg_temp_free(temp2); \
bellard79aceca2003-11-23 14:55:54 +00003505}
3506
3507/* crand */
aurel32e1571902008-10-21 11:31:14 +00003508GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
bellard79aceca2003-11-23 14:55:54 +00003509/* crandc */
aurel32e1571902008-10-21 11:31:14 +00003510GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
bellard79aceca2003-11-23 14:55:54 +00003511/* creqv */
aurel32e1571902008-10-21 11:31:14 +00003512GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
bellard79aceca2003-11-23 14:55:54 +00003513/* crnand */
aurel32e1571902008-10-21 11:31:14 +00003514GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
bellard79aceca2003-11-23 14:55:54 +00003515/* crnor */
aurel32e1571902008-10-21 11:31:14 +00003516GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
bellard79aceca2003-11-23 14:55:54 +00003517/* cror */
aurel32e1571902008-10-21 11:31:14 +00003518GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
bellard79aceca2003-11-23 14:55:54 +00003519/* crorc */
aurel32e1571902008-10-21 11:31:14 +00003520GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
bellard79aceca2003-11-23 14:55:54 +00003521/* crxor */
aurel32e1571902008-10-21 11:31:14 +00003522GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
bellard79aceca2003-11-23 14:55:54 +00003523/* mcrf */
3524GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3525{
aurel3247e46612008-09-04 17:06:47 +00003526 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00003527}
3528
3529/*** System linkage ***/
3530/* rfi (supervisor only) */
j_mayer76a66252007-03-07 08:32:30 +00003531GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
bellard79aceca2003-11-23 14:55:54 +00003532{
bellard9a64fbe2004-01-04 22:58:38 +00003533#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00003534 GEN_EXCP_PRIVOPC(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00003535#else
3536 /* Restore CPU state */
j_mayer76a66252007-03-07 08:32:30 +00003537 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00003538 GEN_EXCP_PRIVOPC(ctx);
bellard9fddaa02004-05-21 12:59:32 +00003539 return;
bellard9a64fbe2004-01-04 22:58:38 +00003540 }
j_mayera42bd6c2007-03-30 10:22:46 +00003541 gen_op_rfi();
j_mayere1833e12007-09-29 13:06:16 +00003542 GEN_SYNC(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00003543#endif
bellard79aceca2003-11-23 14:55:54 +00003544}
3545
j_mayer426613d2007-03-23 09:45:27 +00003546#if defined(TARGET_PPC64)
j_mayera750fc02007-09-26 23:54:22 +00003547GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
j_mayer426613d2007-03-23 09:45:27 +00003548{
3549#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00003550 GEN_EXCP_PRIVOPC(ctx);
j_mayer426613d2007-03-23 09:45:27 +00003551#else
3552 /* Restore CPU state */
3553 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00003554 GEN_EXCP_PRIVOPC(ctx);
j_mayer426613d2007-03-23 09:45:27 +00003555 return;
3556 }
j_mayera42bd6c2007-03-30 10:22:46 +00003557 gen_op_rfid();
j_mayere1833e12007-09-29 13:06:16 +00003558 GEN_SYNC(ctx);
j_mayer426613d2007-03-23 09:45:27 +00003559#endif
3560}
j_mayer426613d2007-03-23 09:45:27 +00003561
j_mayer5b8105f2007-11-19 11:39:29 +00003562GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
j_mayerbe147d02007-09-30 13:03:23 +00003563{
3564#if defined(CONFIG_USER_ONLY)
3565 GEN_EXCP_PRIVOPC(ctx);
3566#else
3567 /* Restore CPU state */
3568 if (unlikely(ctx->supervisor <= 1)) {
3569 GEN_EXCP_PRIVOPC(ctx);
3570 return;
3571 }
3572 gen_op_hrfid();
3573 GEN_SYNC(ctx);
3574#endif
3575}
3576#endif
3577
bellard79aceca2003-11-23 14:55:54 +00003578/* sc */
j_mayer417bf012007-10-07 23:10:08 +00003579#if defined(CONFIG_USER_ONLY)
3580#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3581#else
3582#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3583#endif
j_mayere1833e12007-09-29 13:06:16 +00003584GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
bellard79aceca2003-11-23 14:55:54 +00003585{
j_mayere1833e12007-09-29 13:06:16 +00003586 uint32_t lev;
3587
3588 lev = (ctx->opcode >> 5) & 0x7F;
j_mayer417bf012007-10-07 23:10:08 +00003589 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
bellard79aceca2003-11-23 14:55:54 +00003590}
3591
3592/*** Trap ***/
3593/* tw */
j_mayer76a66252007-03-07 08:32:30 +00003594GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
bellard79aceca2003-11-23 14:55:54 +00003595{
aurel32f78fb442008-09-04 05:25:47 +00003596 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3597 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
thsa0ae05a2007-01-05 16:54:16 +00003598 /* Update the nip since this might generate a trap exception */
j_mayerd9bce9d2007-03-17 14:02:15 +00003599 gen_update_nip(ctx, ctx->nip);
bellard9a64fbe2004-01-04 22:58:38 +00003600 gen_op_tw(TO(ctx->opcode));
bellard79aceca2003-11-23 14:55:54 +00003601}
3602
3603/* twi */
3604GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3605{
aurel32f78fb442008-09-04 05:25:47 +00003606 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
aurel3202f4f6c2008-09-02 16:18:55 +00003607 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
j_mayerd9bce9d2007-03-17 14:02:15 +00003608 /* Update the nip since this might generate a trap exception */
3609 gen_update_nip(ctx, ctx->nip);
j_mayer76a66252007-03-07 08:32:30 +00003610 gen_op_tw(TO(ctx->opcode));
bellard79aceca2003-11-23 14:55:54 +00003611}
3612
j_mayerd9bce9d2007-03-17 14:02:15 +00003613#if defined(TARGET_PPC64)
3614/* td */
3615GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3616{
aurel32f78fb442008-09-04 05:25:47 +00003617 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3618 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00003619 /* Update the nip since this might generate a trap exception */
3620 gen_update_nip(ctx, ctx->nip);
3621 gen_op_td(TO(ctx->opcode));
3622}
3623
3624/* tdi */
3625GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3626{
aurel32f78fb442008-09-04 05:25:47 +00003627 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
aurel3202f4f6c2008-09-02 16:18:55 +00003628 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
j_mayerd9bce9d2007-03-17 14:02:15 +00003629 /* Update the nip since this might generate a trap exception */
3630 gen_update_nip(ctx, ctx->nip);
3631 gen_op_td(TO(ctx->opcode));
3632}
3633#endif
3634
bellard79aceca2003-11-23 14:55:54 +00003635/*** Processor control ***/
bellard79aceca2003-11-23 14:55:54 +00003636/* mcrxr */
3637GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3638{
aurel323d7b4172008-10-21 11:28:46 +00003639 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3640 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
aurel32269f3e92008-11-01 00:53:48 +00003641 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
bellard79aceca2003-11-23 14:55:54 +00003642}
3643
3644/* mfcr */
j_mayer76a66252007-03-07 08:32:30 +00003645GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
bellard79aceca2003-11-23 14:55:54 +00003646{
j_mayer76a66252007-03-07 08:32:30 +00003647 uint32_t crm, crn;
ths3b46e622007-09-17 08:09:54 +00003648
j_mayer76a66252007-03-07 08:32:30 +00003649 if (likely(ctx->opcode & 0x00100000)) {
3650 crm = CRM(ctx->opcode);
3651 if (likely((crm ^ (crm - 1)) == 0)) {
3652 crn = ffs(crm);
aurel32e1571902008-10-21 11:31:14 +00003653 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
j_mayer76a66252007-03-07 08:32:30 +00003654 }
j_mayerd9bce9d2007-03-17 14:02:15 +00003655 } else {
aurel32e1571902008-10-21 11:31:14 +00003656 tcg_gen_helper_1_0(helper_load_cr, cpu_gpr[rD(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00003657 }
bellard79aceca2003-11-23 14:55:54 +00003658}
3659
3660/* mfmsr */
3661GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3662{
bellard9a64fbe2004-01-04 22:58:38 +00003663#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00003664 GEN_EXCP_PRIVREG(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00003665#else
j_mayer76a66252007-03-07 08:32:30 +00003666 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00003667 GEN_EXCP_PRIVREG(ctx);
bellard9fddaa02004-05-21 12:59:32 +00003668 return;
bellard9a64fbe2004-01-04 22:58:38 +00003669 }
aurel326676f422008-08-24 23:16:35 +00003670 gen_op_load_msr();
aurel32f78fb442008-09-04 05:25:47 +00003671 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
bellard9a64fbe2004-01-04 22:58:38 +00003672#endif
bellard79aceca2003-11-23 14:55:54 +00003673}
3674
j_mayera11b8152007-10-28 00:55:05 +00003675#if 1
j_mayer6f2d8972007-11-12 00:04:48 +00003676#define SPR_NOACCESS ((void *)(-1UL))
bellard3fc6c082005-07-02 20:59:34 +00003677#else
3678static void spr_noaccess (void *opaque, int sprn)
bellard79aceca2003-11-23 14:55:54 +00003679{
bellard3fc6c082005-07-02 20:59:34 +00003680 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3681 printf("ERROR: try to access SPR %d !\n", sprn);
3682}
3683#define SPR_NOACCESS (&spr_noaccess)
3684#endif
3685
3686/* mfspr */
j_mayerb068d6a2007-10-07 17:13:44 +00003687static always_inline void gen_op_mfspr (DisasContext *ctx)
bellard3fc6c082005-07-02 20:59:34 +00003688{
3689 void (*read_cb)(void *opaque, int sprn);
bellard79aceca2003-11-23 14:55:54 +00003690 uint32_t sprn = SPR(ctx->opcode);
3691
bellard3fc6c082005-07-02 20:59:34 +00003692#if !defined(CONFIG_USER_ONLY)
j_mayerbe147d02007-09-30 13:03:23 +00003693 if (ctx->supervisor == 2)
3694 read_cb = ctx->spr_cb[sprn].hea_read;
j_mayer78636672007-11-16 14:11:28 +00003695 else if (ctx->supervisor)
bellard3fc6c082005-07-02 20:59:34 +00003696 read_cb = ctx->spr_cb[sprn].oea_read;
3697 else
bellard9a64fbe2004-01-04 22:58:38 +00003698#endif
bellard3fc6c082005-07-02 20:59:34 +00003699 read_cb = ctx->spr_cb[sprn].uea_read;
j_mayer76a66252007-03-07 08:32:30 +00003700 if (likely(read_cb != NULL)) {
3701 if (likely(read_cb != SPR_NOACCESS)) {
bellard3fc6c082005-07-02 20:59:34 +00003702 (*read_cb)(ctx, sprn);
aurel32f78fb442008-09-04 05:25:47 +00003703 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
bellard3fc6c082005-07-02 20:59:34 +00003704 } else {
3705 /* Privilege exception */
j_mayer9fceefa2007-11-02 22:47:50 +00003706 /* This is a hack to avoid warnings when running Linux:
3707 * this OS breaks the PowerPC virtualisation model,
3708 * allowing userland application to read the PVR
3709 */
3710 if (sprn != SPR_PVR) {
3711 if (loglevel != 0) {
j_mayer6b542af2007-11-24 02:03:55 +00003712 fprintf(logfile, "Trying to read privileged spr %d %03x at "
j_mayer077fc202007-11-04 01:57:29 +00003713 ADDRX "\n", sprn, sprn, ctx->nip);
j_mayer9fceefa2007-11-02 22:47:50 +00003714 }
j_mayer077fc202007-11-04 01:57:29 +00003715 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3716 sprn, sprn, ctx->nip);
bellardf24e5692005-11-23 21:36:30 +00003717 }
j_mayere1833e12007-09-29 13:06:16 +00003718 GEN_EXCP_PRIVREG(ctx);
bellard79aceca2003-11-23 14:55:54 +00003719 }
bellard3fc6c082005-07-02 20:59:34 +00003720 } else {
3721 /* Not defined */
j_mayer4a057712007-04-19 08:42:21 +00003722 if (loglevel != 0) {
j_mayer077fc202007-11-04 01:57:29 +00003723 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3724 ADDRX "\n", sprn, sprn, ctx->nip);
bellardf24e5692005-11-23 21:36:30 +00003725 }
j_mayer077fc202007-11-04 01:57:29 +00003726 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3727 sprn, sprn, ctx->nip);
j_mayere1833e12007-09-29 13:06:16 +00003728 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3729 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
bellard79aceca2003-11-23 14:55:54 +00003730 }
bellard79aceca2003-11-23 14:55:54 +00003731}
3732
bellard3fc6c082005-07-02 20:59:34 +00003733GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
bellard79aceca2003-11-23 14:55:54 +00003734{
bellard3fc6c082005-07-02 20:59:34 +00003735 gen_op_mfspr(ctx);
j_mayer76a66252007-03-07 08:32:30 +00003736}
bellard3fc6c082005-07-02 20:59:34 +00003737
3738/* mftb */
j_mayera750fc02007-09-26 23:54:22 +00003739GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
bellard3fc6c082005-07-02 20:59:34 +00003740{
3741 gen_op_mfspr(ctx);
bellard79aceca2003-11-23 14:55:54 +00003742}
3743
3744/* mtcrf */
bellard8dd49832005-06-04 22:22:27 +00003745GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
bellard79aceca2003-11-23 14:55:54 +00003746{
j_mayer76a66252007-03-07 08:32:30 +00003747 uint32_t crm, crn;
ths3b46e622007-09-17 08:09:54 +00003748
j_mayer76a66252007-03-07 08:32:30 +00003749 crm = CRM(ctx->opcode);
3750 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3751 crn = ffs(crm);
aurel32e1571902008-10-21 11:31:14 +00003752 tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
3753 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
j_mayer76a66252007-03-07 08:32:30 +00003754 } else {
aurel32e1571902008-10-21 11:31:14 +00003755 TCGv temp = tcg_const_tl(crm);
3756 tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], temp);
3757 tcg_temp_free(temp);
j_mayer76a66252007-03-07 08:32:30 +00003758 }
bellard79aceca2003-11-23 14:55:54 +00003759}
3760
3761/* mtmsr */
j_mayer426613d2007-03-23 09:45:27 +00003762#if defined(TARGET_PPC64)
j_mayerbe147d02007-09-30 13:03:23 +00003763GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
j_mayer426613d2007-03-23 09:45:27 +00003764{
3765#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00003766 GEN_EXCP_PRIVREG(ctx);
j_mayer426613d2007-03-23 09:45:27 +00003767#else
3768 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00003769 GEN_EXCP_PRIVREG(ctx);
j_mayer426613d2007-03-23 09:45:27 +00003770 return;
3771 }
aurel32f78fb442008-09-04 05:25:47 +00003772 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
j_mayerbe147d02007-09-30 13:03:23 +00003773 if (ctx->opcode & 0x00010000) {
3774 /* Special form that does not need any synchronisation */
3775 gen_op_update_riee();
3776 } else {
j_mayer056b05f2007-10-01 03:03:51 +00003777 /* XXX: we need to update nip before the store
3778 * if we enter power saving mode, we will exit the loop
3779 * directly from ppc_store_msr
3780 */
j_mayerbe147d02007-09-30 13:03:23 +00003781 gen_update_nip(ctx, ctx->nip);
aurel326676f422008-08-24 23:16:35 +00003782 gen_op_store_msr();
j_mayerbe147d02007-09-30 13:03:23 +00003783 /* Must stop the translation as machine state (may have) changed */
3784 /* Note that mtmsr is not always defined as context-synchronizing */
j_mayer056b05f2007-10-01 03:03:51 +00003785 ctx->exception = POWERPC_EXCP_STOP;
j_mayerbe147d02007-09-30 13:03:23 +00003786 }
j_mayer426613d2007-03-23 09:45:27 +00003787#endif
3788}
3789#endif
3790
bellard79aceca2003-11-23 14:55:54 +00003791GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3792{
bellard9a64fbe2004-01-04 22:58:38 +00003793#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00003794 GEN_EXCP_PRIVREG(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00003795#else
j_mayer76a66252007-03-07 08:32:30 +00003796 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00003797 GEN_EXCP_PRIVREG(ctx);
bellard9fddaa02004-05-21 12:59:32 +00003798 return;
bellard9a64fbe2004-01-04 22:58:38 +00003799 }
aurel32f78fb442008-09-04 05:25:47 +00003800 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
j_mayerbe147d02007-09-30 13:03:23 +00003801 if (ctx->opcode & 0x00010000) {
3802 /* Special form that does not need any synchronisation */
3803 gen_op_update_riee();
3804 } else {
j_mayer056b05f2007-10-01 03:03:51 +00003805 /* XXX: we need to update nip before the store
3806 * if we enter power saving mode, we will exit the loop
3807 * directly from ppc_store_msr
3808 */
j_mayerbe147d02007-09-30 13:03:23 +00003809 gen_update_nip(ctx, ctx->nip);
j_mayerd9bce9d2007-03-17 14:02:15 +00003810#if defined(TARGET_PPC64)
j_mayerbe147d02007-09-30 13:03:23 +00003811 if (!ctx->sf_mode)
aurel326676f422008-08-24 23:16:35 +00003812 gen_op_store_msr_32();
j_mayerbe147d02007-09-30 13:03:23 +00003813 else
j_mayerd9bce9d2007-03-17 14:02:15 +00003814#endif
aurel326676f422008-08-24 23:16:35 +00003815 gen_op_store_msr();
j_mayerbe147d02007-09-30 13:03:23 +00003816 /* Must stop the translation as machine state (may have) changed */
3817 /* Note that mtmsrd is not always defined as context-synchronizing */
j_mayer056b05f2007-10-01 03:03:51 +00003818 ctx->exception = POWERPC_EXCP_STOP;
j_mayerbe147d02007-09-30 13:03:23 +00003819 }
bellard9a64fbe2004-01-04 22:58:38 +00003820#endif
bellard79aceca2003-11-23 14:55:54 +00003821}
3822
3823/* mtspr */
3824GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3825{
bellard3fc6c082005-07-02 20:59:34 +00003826 void (*write_cb)(void *opaque, int sprn);
bellard79aceca2003-11-23 14:55:54 +00003827 uint32_t sprn = SPR(ctx->opcode);
3828
bellard3fc6c082005-07-02 20:59:34 +00003829#if !defined(CONFIG_USER_ONLY)
j_mayerbe147d02007-09-30 13:03:23 +00003830 if (ctx->supervisor == 2)
3831 write_cb = ctx->spr_cb[sprn].hea_write;
j_mayer78636672007-11-16 14:11:28 +00003832 else if (ctx->supervisor)
bellard3fc6c082005-07-02 20:59:34 +00003833 write_cb = ctx->spr_cb[sprn].oea_write;
3834 else
bellard9a64fbe2004-01-04 22:58:38 +00003835#endif
bellard3fc6c082005-07-02 20:59:34 +00003836 write_cb = ctx->spr_cb[sprn].uea_write;
j_mayer76a66252007-03-07 08:32:30 +00003837 if (likely(write_cb != NULL)) {
3838 if (likely(write_cb != SPR_NOACCESS)) {
aurel32f78fb442008-09-04 05:25:47 +00003839 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
bellard3fc6c082005-07-02 20:59:34 +00003840 (*write_cb)(ctx, sprn);
3841 } else {
3842 /* Privilege exception */
j_mayer4a057712007-04-19 08:42:21 +00003843 if (loglevel != 0) {
j_mayer077fc202007-11-04 01:57:29 +00003844 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3845 ADDRX "\n", sprn, sprn, ctx->nip);
bellardf24e5692005-11-23 21:36:30 +00003846 }
j_mayer077fc202007-11-04 01:57:29 +00003847 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3848 sprn, sprn, ctx->nip);
j_mayere1833e12007-09-29 13:06:16 +00003849 GEN_EXCP_PRIVREG(ctx);
j_mayer76a66252007-03-07 08:32:30 +00003850 }
bellard3fc6c082005-07-02 20:59:34 +00003851 } else {
3852 /* Not defined */
j_mayer4a057712007-04-19 08:42:21 +00003853 if (loglevel != 0) {
j_mayer077fc202007-11-04 01:57:29 +00003854 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3855 ADDRX "\n", sprn, sprn, ctx->nip);
bellardf24e5692005-11-23 21:36:30 +00003856 }
j_mayer077fc202007-11-04 01:57:29 +00003857 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3858 sprn, sprn, ctx->nip);
j_mayere1833e12007-09-29 13:06:16 +00003859 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3860 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
bellard9a64fbe2004-01-04 22:58:38 +00003861 }
bellard79aceca2003-11-23 14:55:54 +00003862}
3863
3864/*** Cache management ***/
bellard79aceca2003-11-23 14:55:54 +00003865/* dcbf */
j_mayer0db1b202007-09-30 03:46:38 +00003866GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
bellard79aceca2003-11-23 14:55:54 +00003867{
j_mayerdac454a2007-10-26 00:48:00 +00003868 /* XXX: specification says this is treated as a load by the MMU */
aurel32b61f2752008-10-15 17:00:37 +00003869 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3870 gen_addr_reg_index(temp, ctx);
3871 gen_qemu_ld8u(temp, temp, ctx->mem_idx);
3872 tcg_temp_free(temp);
bellard79aceca2003-11-23 14:55:54 +00003873}
3874
3875/* dcbi (Supervisor only) */
bellard9a64fbe2004-01-04 22:58:38 +00003876GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
bellard79aceca2003-11-23 14:55:54 +00003877{
bellarda541f292004-04-12 20:39:29 +00003878#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00003879 GEN_EXCP_PRIVOPC(ctx);
bellarda541f292004-04-12 20:39:29 +00003880#else
aurel32b61f2752008-10-15 17:00:37 +00003881 TCGv EA, val;
j_mayer76a66252007-03-07 08:32:30 +00003882 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00003883 GEN_EXCP_PRIVOPC(ctx);
bellard9fddaa02004-05-21 12:59:32 +00003884 return;
bellard9a64fbe2004-01-04 22:58:38 +00003885 }
aurel32b61f2752008-10-15 17:00:37 +00003886 EA = tcg_temp_new(TCG_TYPE_TL);
3887 gen_addr_reg_index(EA, ctx);
aurel32ed695222008-10-15 22:25:21 +00003888 val = tcg_temp_new(TCG_TYPE_TL);
j_mayer76a66252007-03-07 08:32:30 +00003889 /* XXX: specification says this should be treated as a store by the MMU */
aurel32b61f2752008-10-15 17:00:37 +00003890 gen_qemu_ld8u(val, EA, ctx->mem_idx);
3891 gen_qemu_st8(val, EA, ctx->mem_idx);
3892 tcg_temp_free(val);
3893 tcg_temp_free(EA);
bellarda541f292004-04-12 20:39:29 +00003894#endif
bellard79aceca2003-11-23 14:55:54 +00003895}
3896
3897/* dcdst */
bellard9a64fbe2004-01-04 22:58:38 +00003898GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
bellard79aceca2003-11-23 14:55:54 +00003899{
j_mayer76a66252007-03-07 08:32:30 +00003900 /* XXX: specification say this is treated as a load by the MMU */
aurel32b61f2752008-10-15 17:00:37 +00003901 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3902 gen_addr_reg_index(temp, ctx);
3903 gen_qemu_ld8u(temp, temp, ctx->mem_idx);
3904 tcg_temp_free(temp);
bellard79aceca2003-11-23 14:55:54 +00003905}
3906
3907/* dcbt */
j_mayer0db1b202007-09-30 03:46:38 +00003908GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
bellard79aceca2003-11-23 14:55:54 +00003909{
j_mayer0db1b202007-09-30 03:46:38 +00003910 /* interpreted as no-op */
j_mayer76a66252007-03-07 08:32:30 +00003911 /* XXX: specification say this is treated as a load by the MMU
3912 * but does not generate any exception
3913 */
bellard79aceca2003-11-23 14:55:54 +00003914}
3915
3916/* dcbtst */
j_mayer0db1b202007-09-30 03:46:38 +00003917GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
bellard79aceca2003-11-23 14:55:54 +00003918{
j_mayer0db1b202007-09-30 03:46:38 +00003919 /* interpreted as no-op */
j_mayer76a66252007-03-07 08:32:30 +00003920 /* XXX: specification say this is treated as a load by the MMU
3921 * but does not generate any exception
3922 */
bellard79aceca2003-11-23 14:55:54 +00003923}
3924
3925/* dcbz */
j_mayerd63001d2007-10-04 00:51:58 +00003926#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
j_mayer78636672007-11-16 14:11:28 +00003927static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3928 /* 32 bytes cache line size */
j_mayerd63001d2007-10-04 00:51:58 +00003929 {
j_mayer78636672007-11-16 14:11:28 +00003930#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3931#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3932#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3933#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3934#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3935#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3936#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3937#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3938 GEN_MEM_FUNCS(dcbz_l32),
j_mayerd63001d2007-10-04 00:51:58 +00003939 },
j_mayer78636672007-11-16 14:11:28 +00003940 /* 64 bytes cache line size */
j_mayerd63001d2007-10-04 00:51:58 +00003941 {
j_mayer78636672007-11-16 14:11:28 +00003942#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3943#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3944#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3945#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3946#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3947#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3948#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3949#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3950 GEN_MEM_FUNCS(dcbz_l64),
j_mayerd63001d2007-10-04 00:51:58 +00003951 },
j_mayer78636672007-11-16 14:11:28 +00003952 /* 128 bytes cache line size */
j_mayerd63001d2007-10-04 00:51:58 +00003953 {
j_mayer78636672007-11-16 14:11:28 +00003954#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3955#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3956#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3957#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3958#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3959#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3960#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3961#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3962 GEN_MEM_FUNCS(dcbz_l128),
j_mayerd63001d2007-10-04 00:51:58 +00003963 },
j_mayer78636672007-11-16 14:11:28 +00003964 /* tunable cache line size */
j_mayerd63001d2007-10-04 00:51:58 +00003965 {
j_mayer78636672007-11-16 14:11:28 +00003966#define gen_op_dcbz_le_raw gen_op_dcbz_raw
3967#define gen_op_dcbz_le_user gen_op_dcbz_user
3968#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3969#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3970#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3971#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3972#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3973#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3974 GEN_MEM_FUNCS(dcbz),
j_mayerd63001d2007-10-04 00:51:58 +00003975 },
j_mayer76a66252007-03-07 08:32:30 +00003976};
bellard9a64fbe2004-01-04 22:58:38 +00003977
j_mayerb068d6a2007-10-07 17:13:44 +00003978static always_inline void handler_dcbz (DisasContext *ctx,
3979 int dcache_line_size)
j_mayerd63001d2007-10-04 00:51:58 +00003980{
3981 int n;
3982
3983 switch (dcache_line_size) {
3984 case 32:
3985 n = 0;
3986 break;
3987 case 64:
3988 n = 1;
3989 break;
3990 case 128:
3991 n = 2;
3992 break;
3993 default:
3994 n = 3;
3995 break;
3996 }
3997 op_dcbz(n);
3998}
3999
4000GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
bellard79aceca2003-11-23 14:55:54 +00004001{
aurel32e2be8d82008-10-14 19:55:54 +00004002 gen_addr_reg_index(cpu_T[0], ctx);
j_mayerd63001d2007-10-04 00:51:58 +00004003 handler_dcbz(ctx, ctx->dcache_line_size);
4004 gen_op_check_reservation();
4005}
4006
j_mayerc7697e12007-10-26 00:46:07 +00004007GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
j_mayerd63001d2007-10-04 00:51:58 +00004008{
aurel32e2be8d82008-10-14 19:55:54 +00004009 gen_addr_reg_index(cpu_T[0], ctx);
j_mayerd63001d2007-10-04 00:51:58 +00004010 if (ctx->opcode & 0x00200000)
4011 handler_dcbz(ctx, ctx->dcache_line_size);
4012 else
4013 handler_dcbz(ctx, -1);
bellard4b3686f2004-05-23 22:18:12 +00004014 gen_op_check_reservation();
bellard79aceca2003-11-23 14:55:54 +00004015}
4016
4017/* icbi */
j_mayer36f69652007-03-18 08:47:10 +00004018#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
j_mayer78636672007-11-16 14:11:28 +00004019#define gen_op_icbi_le_raw gen_op_icbi_raw
4020#define gen_op_icbi_le_user gen_op_icbi_user
4021#define gen_op_icbi_le_kernel gen_op_icbi_kernel
4022#define gen_op_icbi_le_hypv gen_op_icbi_hypv
4023#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
4024#define gen_op_icbi_le_64_user gen_op_icbi_64_user
4025#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
4026#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
4027static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
4028 GEN_MEM_FUNCS(icbi),
j_mayer36f69652007-03-18 08:47:10 +00004029};
j_mayere1833e12007-09-29 13:06:16 +00004030
j_mayer1b413d52007-11-14 01:08:45 +00004031GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
bellard79aceca2003-11-23 14:55:54 +00004032{
j_mayer30032c92007-10-01 05:22:17 +00004033 /* NIP cannot be restored if the memory exception comes from an helper */
4034 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00004035 gen_addr_reg_index(cpu_T[0], ctx);
j_mayer36f69652007-03-18 08:47:10 +00004036 op_icbi();
bellard79aceca2003-11-23 14:55:54 +00004037}
4038
4039/* Optional: */
4040/* dcba */
j_mayera750fc02007-09-26 23:54:22 +00004041GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
bellard79aceca2003-11-23 14:55:54 +00004042{
j_mayer0db1b202007-09-30 03:46:38 +00004043 /* interpreted as no-op */
4044 /* XXX: specification say this is treated as a store by the MMU
4045 * but does not generate any exception
4046 */
bellard79aceca2003-11-23 14:55:54 +00004047}
4048
4049/*** Segment register manipulation ***/
4050/* Supervisor only: */
4051/* mfsr */
4052GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4053{
bellard9a64fbe2004-01-04 22:58:38 +00004054#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004055 GEN_EXCP_PRIVREG(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00004056#else
j_mayer76a66252007-03-07 08:32:30 +00004057 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004058 GEN_EXCP_PRIVREG(ctx);
bellard9fddaa02004-05-21 12:59:32 +00004059 return;
bellard9a64fbe2004-01-04 22:58:38 +00004060 }
aurel3286c581d2008-09-02 23:26:32 +00004061 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
j_mayer76a66252007-03-07 08:32:30 +00004062 gen_op_load_sr();
aurel32f78fb442008-09-04 05:25:47 +00004063 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
bellard9a64fbe2004-01-04 22:58:38 +00004064#endif
bellard79aceca2003-11-23 14:55:54 +00004065}
4066
4067/* mfsrin */
bellard9a64fbe2004-01-04 22:58:38 +00004068GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
bellard79aceca2003-11-23 14:55:54 +00004069{
bellard9a64fbe2004-01-04 22:58:38 +00004070#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004071 GEN_EXCP_PRIVREG(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00004072#else
j_mayer76a66252007-03-07 08:32:30 +00004073 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004074 GEN_EXCP_PRIVREG(ctx);
bellard9fddaa02004-05-21 12:59:32 +00004075 return;
bellard9a64fbe2004-01-04 22:58:38 +00004076 }
aurel32f78fb442008-09-04 05:25:47 +00004077 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004078 gen_op_srli_T1(28);
4079 gen_op_load_sr();
aurel32f78fb442008-09-04 05:25:47 +00004080 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
bellard9a64fbe2004-01-04 22:58:38 +00004081#endif
bellard79aceca2003-11-23 14:55:54 +00004082}
4083
4084/* mtsr */
bellarde63c59c2004-05-17 21:05:06 +00004085GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
bellard79aceca2003-11-23 14:55:54 +00004086{
bellard9a64fbe2004-01-04 22:58:38 +00004087#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004088 GEN_EXCP_PRIVREG(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00004089#else
j_mayer76a66252007-03-07 08:32:30 +00004090 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004091 GEN_EXCP_PRIVREG(ctx);
bellard9fddaa02004-05-21 12:59:32 +00004092 return;
bellard9a64fbe2004-01-04 22:58:38 +00004093 }
aurel32f78fb442008-09-04 05:25:47 +00004094 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
aurel3286c581d2008-09-02 23:26:32 +00004095 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
j_mayer76a66252007-03-07 08:32:30 +00004096 gen_op_store_sr();
bellard9a64fbe2004-01-04 22:58:38 +00004097#endif
bellard79aceca2003-11-23 14:55:54 +00004098}
4099
4100/* mtsrin */
bellard9a64fbe2004-01-04 22:58:38 +00004101GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
bellard79aceca2003-11-23 14:55:54 +00004102{
bellard9a64fbe2004-01-04 22:58:38 +00004103#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004104 GEN_EXCP_PRIVREG(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00004105#else
j_mayer76a66252007-03-07 08:32:30 +00004106 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004107 GEN_EXCP_PRIVREG(ctx);
bellard9fddaa02004-05-21 12:59:32 +00004108 return;
bellard9a64fbe2004-01-04 22:58:38 +00004109 }
aurel32f78fb442008-09-04 05:25:47 +00004110 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4111 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004112 gen_op_srli_T1(28);
4113 gen_op_store_sr();
bellard9a64fbe2004-01-04 22:58:38 +00004114#endif
bellard79aceca2003-11-23 14:55:54 +00004115}
4116
j_mayer12de9a32007-10-05 22:06:02 +00004117#if defined(TARGET_PPC64)
4118/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4119/* mfsr */
j_mayerc7697e12007-10-26 00:46:07 +00004120GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
j_mayer12de9a32007-10-05 22:06:02 +00004121{
4122#if defined(CONFIG_USER_ONLY)
4123 GEN_EXCP_PRIVREG(ctx);
4124#else
4125 if (unlikely(!ctx->supervisor)) {
4126 GEN_EXCP_PRIVREG(ctx);
4127 return;
4128 }
aurel3286c581d2008-09-02 23:26:32 +00004129 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
j_mayer12de9a32007-10-05 22:06:02 +00004130 gen_op_load_slb();
aurel32f78fb442008-09-04 05:25:47 +00004131 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer12de9a32007-10-05 22:06:02 +00004132#endif
4133}
4134
4135/* mfsrin */
j_mayerc7697e12007-10-26 00:46:07 +00004136GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4137 PPC_SEGMENT_64B)
j_mayer12de9a32007-10-05 22:06:02 +00004138{
4139#if defined(CONFIG_USER_ONLY)
4140 GEN_EXCP_PRIVREG(ctx);
4141#else
4142 if (unlikely(!ctx->supervisor)) {
4143 GEN_EXCP_PRIVREG(ctx);
4144 return;
4145 }
aurel32f78fb442008-09-04 05:25:47 +00004146 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer12de9a32007-10-05 22:06:02 +00004147 gen_op_srli_T1(28);
4148 gen_op_load_slb();
aurel32f78fb442008-09-04 05:25:47 +00004149 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer12de9a32007-10-05 22:06:02 +00004150#endif
4151}
4152
4153/* mtsr */
j_mayerc7697e12007-10-26 00:46:07 +00004154GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
j_mayer12de9a32007-10-05 22:06:02 +00004155{
4156#if defined(CONFIG_USER_ONLY)
4157 GEN_EXCP_PRIVREG(ctx);
4158#else
4159 if (unlikely(!ctx->supervisor)) {
4160 GEN_EXCP_PRIVREG(ctx);
4161 return;
4162 }
aurel32f78fb442008-09-04 05:25:47 +00004163 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
aurel3286c581d2008-09-02 23:26:32 +00004164 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
j_mayer12de9a32007-10-05 22:06:02 +00004165 gen_op_store_slb();
4166#endif
4167}
4168
4169/* mtsrin */
j_mayerc7697e12007-10-26 00:46:07 +00004170GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4171 PPC_SEGMENT_64B)
j_mayer12de9a32007-10-05 22:06:02 +00004172{
4173#if defined(CONFIG_USER_ONLY)
4174 GEN_EXCP_PRIVREG(ctx);
4175#else
4176 if (unlikely(!ctx->supervisor)) {
4177 GEN_EXCP_PRIVREG(ctx);
4178 return;
4179 }
aurel32f78fb442008-09-04 05:25:47 +00004180 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4181 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer12de9a32007-10-05 22:06:02 +00004182 gen_op_srli_T1(28);
4183 gen_op_store_slb();
4184#endif
4185}
4186#endif /* defined(TARGET_PPC64) */
4187
bellard79aceca2003-11-23 14:55:54 +00004188/*** Lookaside buffer management ***/
4189/* Optional & supervisor only: */
4190/* tlbia */
bellard3fc6c082005-07-02 20:59:34 +00004191GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
bellard79aceca2003-11-23 14:55:54 +00004192{
bellard9a64fbe2004-01-04 22:58:38 +00004193#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004194 GEN_EXCP_PRIVOPC(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00004195#else
j_mayer76a66252007-03-07 08:32:30 +00004196 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004197 GEN_EXCP_PRIVOPC(ctx);
bellard9fddaa02004-05-21 12:59:32 +00004198 return;
bellard9a64fbe2004-01-04 22:58:38 +00004199 }
4200 gen_op_tlbia();
4201#endif
bellard79aceca2003-11-23 14:55:54 +00004202}
4203
4204/* tlbie */
j_mayer76a66252007-03-07 08:32:30 +00004205GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
bellard79aceca2003-11-23 14:55:54 +00004206{
bellard9a64fbe2004-01-04 22:58:38 +00004207#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004208 GEN_EXCP_PRIVOPC(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00004209#else
j_mayer76a66252007-03-07 08:32:30 +00004210 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004211 GEN_EXCP_PRIVOPC(ctx);
bellard9fddaa02004-05-21 12:59:32 +00004212 return;
bellard9a64fbe2004-01-04 22:58:38 +00004213 }
aurel32f78fb442008-09-04 05:25:47 +00004214 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00004215#if defined(TARGET_PPC64)
4216 if (ctx->sf_mode)
4217 gen_op_tlbie_64();
4218 else
4219#endif
4220 gen_op_tlbie();
bellard9a64fbe2004-01-04 22:58:38 +00004221#endif
bellard79aceca2003-11-23 14:55:54 +00004222}
4223
4224/* tlbsync */
j_mayer76a66252007-03-07 08:32:30 +00004225GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
bellard79aceca2003-11-23 14:55:54 +00004226{
bellard9a64fbe2004-01-04 22:58:38 +00004227#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004228 GEN_EXCP_PRIVOPC(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00004229#else
j_mayer76a66252007-03-07 08:32:30 +00004230 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004231 GEN_EXCP_PRIVOPC(ctx);
bellard9fddaa02004-05-21 12:59:32 +00004232 return;
bellard9a64fbe2004-01-04 22:58:38 +00004233 }
4234 /* This has no effect: it should ensure that all previous
4235 * tlbie have completed
4236 */
j_mayere1833e12007-09-29 13:06:16 +00004237 GEN_STOP(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00004238#endif
bellard79aceca2003-11-23 14:55:54 +00004239}
4240
j_mayer426613d2007-03-23 09:45:27 +00004241#if defined(TARGET_PPC64)
4242/* slbia */
4243GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4244{
4245#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004246 GEN_EXCP_PRIVOPC(ctx);
j_mayer426613d2007-03-23 09:45:27 +00004247#else
4248 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004249 GEN_EXCP_PRIVOPC(ctx);
j_mayer426613d2007-03-23 09:45:27 +00004250 return;
4251 }
4252 gen_op_slbia();
j_mayer426613d2007-03-23 09:45:27 +00004253#endif
4254}
4255
4256/* slbie */
4257GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4258{
4259#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004260 GEN_EXCP_PRIVOPC(ctx);
j_mayer426613d2007-03-23 09:45:27 +00004261#else
4262 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004263 GEN_EXCP_PRIVOPC(ctx);
j_mayer426613d2007-03-23 09:45:27 +00004264 return;
4265 }
aurel32f78fb442008-09-04 05:25:47 +00004266 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
j_mayer426613d2007-03-23 09:45:27 +00004267 gen_op_slbie();
j_mayer426613d2007-03-23 09:45:27 +00004268#endif
4269}
4270#endif
4271
bellard79aceca2003-11-23 14:55:54 +00004272/*** External control ***/
4273/* Optional: */
bellard9a64fbe2004-01-04 22:58:38 +00004274#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4275#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
j_mayer78636672007-11-16 14:11:28 +00004276static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4277 GEN_MEM_FUNCS(eciwx),
j_mayerd9bce9d2007-03-17 14:02:15 +00004278};
j_mayer78636672007-11-16 14:11:28 +00004279static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4280 GEN_MEM_FUNCS(ecowx),
j_mayerd9bce9d2007-03-17 14:02:15 +00004281};
bellard9a64fbe2004-01-04 22:58:38 +00004282
bellard111bfab2005-04-23 18:16:07 +00004283/* eciwx */
bellard79aceca2003-11-23 14:55:54 +00004284GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4285{
bellard9a64fbe2004-01-04 22:58:38 +00004286 /* Should check EAR[E] & alignment ! */
aurel32e2be8d82008-10-14 19:55:54 +00004287 gen_addr_reg_index(cpu_T[0], ctx);
bellard9a64fbe2004-01-04 22:58:38 +00004288 op_eciwx();
aurel32f78fb442008-09-04 05:25:47 +00004289 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
bellard79aceca2003-11-23 14:55:54 +00004290}
4291
4292/* ecowx */
4293GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4294{
bellard9a64fbe2004-01-04 22:58:38 +00004295 /* Should check EAR[E] & alignment ! */
aurel32e2be8d82008-10-14 19:55:54 +00004296 gen_addr_reg_index(cpu_T[0], ctx);
aurel32f78fb442008-09-04 05:25:47 +00004297 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
bellard9a64fbe2004-01-04 22:58:38 +00004298 op_ecowx();
bellard79aceca2003-11-23 14:55:54 +00004299}
4300
j_mayer76a66252007-03-07 08:32:30 +00004301/* PowerPC 601 specific instructions */
4302/* abs - abs. */
4303GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4304{
aurel32f78fb442008-09-04 05:25:47 +00004305 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004306 gen_op_POWER_abs();
aurel32f78fb442008-09-04 05:25:47 +00004307 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004308 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004309 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004310}
4311
4312/* abso - abso. */
4313GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4314{
aurel32f78fb442008-09-04 05:25:47 +00004315 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004316 gen_op_POWER_abso();
aurel32f78fb442008-09-04 05:25:47 +00004317 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004318 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004319 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004320}
4321
4322/* clcs */
j_mayera750fc02007-09-26 23:54:22 +00004323GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
j_mayer76a66252007-03-07 08:32:30 +00004324{
aurel32f78fb442008-09-04 05:25:47 +00004325 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004326 gen_op_POWER_clcs();
j_mayerc7697e12007-10-26 00:46:07 +00004327 /* Rc=1 sets CR0 to an undefined state */
aurel32f78fb442008-09-04 05:25:47 +00004328 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004329}
4330
4331/* div - div. */
4332GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4333{
aurel32f78fb442008-09-04 05:25:47 +00004334 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4335 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004336 gen_op_POWER_div();
aurel32f78fb442008-09-04 05:25:47 +00004337 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004338 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004339 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004340}
4341
4342/* divo - divo. */
4343GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4344{
aurel32f78fb442008-09-04 05:25:47 +00004345 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4346 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004347 gen_op_POWER_divo();
aurel32f78fb442008-09-04 05:25:47 +00004348 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004349 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004350 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004351}
4352
4353/* divs - divs. */
4354GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4355{
aurel32f78fb442008-09-04 05:25:47 +00004356 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4357 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004358 gen_op_POWER_divs();
aurel32f78fb442008-09-04 05:25:47 +00004359 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004360 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004361 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004362}
4363
4364/* divso - divso. */
4365GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4366{
aurel32f78fb442008-09-04 05:25:47 +00004367 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4368 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004369 gen_op_POWER_divso();
aurel32f78fb442008-09-04 05:25:47 +00004370 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004371 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004372 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004373}
4374
4375/* doz - doz. */
4376GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4377{
aurel32f78fb442008-09-04 05:25:47 +00004378 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4379 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004380 gen_op_POWER_doz();
aurel32f78fb442008-09-04 05:25:47 +00004381 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004382 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004383 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004384}
4385
4386/* dozo - dozo. */
4387GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4388{
aurel32f78fb442008-09-04 05:25:47 +00004389 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4390 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004391 gen_op_POWER_dozo();
aurel32f78fb442008-09-04 05:25:47 +00004392 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004393 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004394 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004395}
4396
4397/* dozi */
4398GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4399{
aurel32f78fb442008-09-04 05:25:47 +00004400 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
aurel3286c581d2008-09-02 23:26:32 +00004401 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
j_mayer76a66252007-03-07 08:32:30 +00004402 gen_op_POWER_doz();
aurel32f78fb442008-09-04 05:25:47 +00004403 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004404}
4405
j_mayer78636672007-11-16 14:11:28 +00004406/* As lscbx load from memory byte after byte, it's always endian safe.
4407 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4408 */
j_mayer28570682007-10-02 10:11:50 +00004409#define op_POWER_lscbx(start, ra, rb) \
j_mayer76a66252007-03-07 08:32:30 +00004410(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
j_mayer78636672007-11-16 14:11:28 +00004411#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4412#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4413#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4414#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4415#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4416#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4417#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4418#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4419#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4420#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4421#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4422#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4423static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4424 GEN_MEM_FUNCS(POWER_lscbx),
j_mayer76a66252007-03-07 08:32:30 +00004425};
j_mayer76a66252007-03-07 08:32:30 +00004426
4427/* lscbx - lscbx. */
4428GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4429{
4430 int ra = rA(ctx->opcode);
4431 int rb = rB(ctx->opcode);
4432
aurel32e2be8d82008-10-14 19:55:54 +00004433 gen_addr_reg_index(cpu_T[0], ctx);
j_mayer76a66252007-03-07 08:32:30 +00004434 if (ra == 0) {
4435 ra = rb;
4436 }
4437 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00004438 gen_update_nip(ctx, ctx->nip - 4);
aurel323d7b4172008-10-21 11:28:46 +00004439 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4440 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4441 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
j_mayer76a66252007-03-07 08:32:30 +00004442 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
aurel323d7b4172008-10-21 11:28:46 +00004443 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4444 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004445 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004446 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004447}
4448
4449/* maskg - maskg. */
4450GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4451{
aurel32f78fb442008-09-04 05:25:47 +00004452 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4453 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004454 gen_op_POWER_maskg();
aurel32f78fb442008-09-04 05:25:47 +00004455 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004456 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004457 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004458}
4459
4460/* maskir - maskir. */
4461GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4462{
aurel32f78fb442008-09-04 05:25:47 +00004463 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4464 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4465 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004466 gen_op_POWER_maskir();
aurel32f78fb442008-09-04 05:25:47 +00004467 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004468 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004469 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004470}
4471
4472/* mul - mul. */
4473GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4474{
aurel32f78fb442008-09-04 05:25:47 +00004475 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4476 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004477 gen_op_POWER_mul();
aurel32f78fb442008-09-04 05:25:47 +00004478 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004479 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004480 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004481}
4482
4483/* mulo - mulo. */
4484GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4485{
aurel32f78fb442008-09-04 05:25:47 +00004486 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4487 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004488 gen_op_POWER_mulo();
aurel32f78fb442008-09-04 05:25:47 +00004489 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004490 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004491 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004492}
4493
4494/* nabs - nabs. */
4495GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4496{
aurel32f78fb442008-09-04 05:25:47 +00004497 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004498 gen_op_POWER_nabs();
aurel32f78fb442008-09-04 05:25:47 +00004499 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004500 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004501 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004502}
4503
4504/* nabso - nabso. */
4505GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4506{
aurel32f78fb442008-09-04 05:25:47 +00004507 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004508 gen_op_POWER_nabso();
aurel32f78fb442008-09-04 05:25:47 +00004509 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004510 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004511 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004512}
4513
4514/* rlmi - rlmi. */
4515GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4516{
4517 uint32_t mb, me;
4518
4519 mb = MB(ctx->opcode);
4520 me = ME(ctx->opcode);
aurel32f78fb442008-09-04 05:25:47 +00004521 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4522 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4523 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004524 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
aurel32f78fb442008-09-04 05:25:47 +00004525 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004526 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004527 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004528}
4529
4530/* rrib - rrib. */
4531GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4532{
aurel32f78fb442008-09-04 05:25:47 +00004533 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4534 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4535 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004536 gen_op_POWER_rrib();
aurel32f78fb442008-09-04 05:25:47 +00004537 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004538 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004539 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004540}
4541
4542/* sle - sle. */
4543GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4544{
aurel32f78fb442008-09-04 05:25:47 +00004545 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4546 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004547 gen_op_POWER_sle();
aurel32f78fb442008-09-04 05:25:47 +00004548 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004549 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004550 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004551}
4552
4553/* sleq - sleq. */
4554GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4555{
aurel32f78fb442008-09-04 05:25:47 +00004556 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4557 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004558 gen_op_POWER_sleq();
aurel32f78fb442008-09-04 05:25:47 +00004559 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004560 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004561 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004562}
4563
4564/* sliq - sliq. */
4565GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4566{
aurel32f78fb442008-09-04 05:25:47 +00004567 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
aurel3286c581d2008-09-02 23:26:32 +00004568 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
j_mayer76a66252007-03-07 08:32:30 +00004569 gen_op_POWER_sle();
aurel32f78fb442008-09-04 05:25:47 +00004570 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004571 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004572 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004573}
4574
4575/* slliq - slliq. */
4576GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4577{
aurel32f78fb442008-09-04 05:25:47 +00004578 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
aurel3286c581d2008-09-02 23:26:32 +00004579 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
j_mayer76a66252007-03-07 08:32:30 +00004580 gen_op_POWER_sleq();
aurel32f78fb442008-09-04 05:25:47 +00004581 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004582 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004583 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004584}
4585
4586/* sllq - sllq. */
4587GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4588{
aurel32f78fb442008-09-04 05:25:47 +00004589 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4590 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004591 gen_op_POWER_sllq();
aurel32f78fb442008-09-04 05:25:47 +00004592 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004593 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004594 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004595}
4596
4597/* slq - slq. */
4598GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4599{
aurel32f78fb442008-09-04 05:25:47 +00004600 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4601 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004602 gen_op_POWER_slq();
aurel32f78fb442008-09-04 05:25:47 +00004603 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004604 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004605 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004606}
4607
j_mayerd9bce9d2007-03-17 14:02:15 +00004608/* sraiq - sraiq. */
j_mayer76a66252007-03-07 08:32:30 +00004609GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4610{
aurel32f78fb442008-09-04 05:25:47 +00004611 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
aurel3286c581d2008-09-02 23:26:32 +00004612 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
j_mayer76a66252007-03-07 08:32:30 +00004613 gen_op_POWER_sraq();
aurel32f78fb442008-09-04 05:25:47 +00004614 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004615 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004616 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004617}
4618
4619/* sraq - sraq. */
4620GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4621{
aurel32f78fb442008-09-04 05:25:47 +00004622 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4623 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004624 gen_op_POWER_sraq();
aurel32f78fb442008-09-04 05:25:47 +00004625 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004626 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004627 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004628}
4629
4630/* sre - sre. */
4631GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4632{
aurel32f78fb442008-09-04 05:25:47 +00004633 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4634 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004635 gen_op_POWER_sre();
aurel32f78fb442008-09-04 05:25:47 +00004636 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004637 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004638 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004639}
4640
4641/* srea - srea. */
4642GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4643{
aurel32f78fb442008-09-04 05:25:47 +00004644 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4645 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004646 gen_op_POWER_srea();
aurel32f78fb442008-09-04 05:25:47 +00004647 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004648 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004649 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004650}
4651
4652/* sreq */
4653GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4654{
aurel32f78fb442008-09-04 05:25:47 +00004655 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4656 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004657 gen_op_POWER_sreq();
aurel32f78fb442008-09-04 05:25:47 +00004658 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004659 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004660 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004661}
4662
4663/* sriq */
4664GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4665{
aurel32f78fb442008-09-04 05:25:47 +00004666 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
aurel3286c581d2008-09-02 23:26:32 +00004667 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
j_mayer76a66252007-03-07 08:32:30 +00004668 gen_op_POWER_srq();
aurel32f78fb442008-09-04 05:25:47 +00004669 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004670 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004671 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004672}
4673
4674/* srliq */
4675GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4676{
aurel32f78fb442008-09-04 05:25:47 +00004677 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4678 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
aurel3286c581d2008-09-02 23:26:32 +00004679 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
j_mayer76a66252007-03-07 08:32:30 +00004680 gen_op_POWER_srlq();
aurel32f78fb442008-09-04 05:25:47 +00004681 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004682 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004683 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004684}
4685
4686/* srlq */
4687GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4688{
aurel32f78fb442008-09-04 05:25:47 +00004689 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4690 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004691 gen_op_POWER_srlq();
aurel32f78fb442008-09-04 05:25:47 +00004692 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004693 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004694 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004695}
4696
4697/* srq */
4698GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4699{
aurel32f78fb442008-09-04 05:25:47 +00004700 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4701 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004702 gen_op_POWER_srq();
aurel32f78fb442008-09-04 05:25:47 +00004703 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004704 if (unlikely(Rc(ctx->opcode) != 0))
aurel32e1571902008-10-21 11:31:14 +00004705 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004706}
4707
4708/* PowerPC 602 specific instructions */
4709/* dsa */
4710GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4711{
4712 /* XXX: TODO */
j_mayere1833e12007-09-29 13:06:16 +00004713 GEN_EXCP_INVAL(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004714}
4715
4716/* esa */
4717GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4718{
4719 /* XXX: TODO */
j_mayere1833e12007-09-29 13:06:16 +00004720 GEN_EXCP_INVAL(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004721}
4722
4723/* mfrom */
4724GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4725{
4726#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004727 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004728#else
4729 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004730 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004731 return;
4732 }
aurel32f78fb442008-09-04 05:25:47 +00004733 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004734 gen_op_602_mfrom();
aurel32f78fb442008-09-04 05:25:47 +00004735 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004736#endif
4737}
4738
4739/* 602 - 603 - G2 TLB management */
4740/* tlbld */
j_mayerc7697e12007-10-26 00:46:07 +00004741GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
j_mayer76a66252007-03-07 08:32:30 +00004742{
4743#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004744 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004745#else
4746 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004747 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004748 return;
4749 }
aurel32f78fb442008-09-04 05:25:47 +00004750 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004751 gen_op_6xx_tlbld();
j_mayer76a66252007-03-07 08:32:30 +00004752#endif
4753}
4754
4755/* tlbli */
j_mayerc7697e12007-10-26 00:46:07 +00004756GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
j_mayer76a66252007-03-07 08:32:30 +00004757{
4758#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004759 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004760#else
4761 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004762 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004763 return;
4764 }
aurel32f78fb442008-09-04 05:25:47 +00004765 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004766 gen_op_6xx_tlbli();
j_mayer76a66252007-03-07 08:32:30 +00004767#endif
4768}
4769
j_mayer7dbe11a2007-10-01 05:16:57 +00004770/* 74xx TLB management */
4771/* tlbld */
j_mayerc7697e12007-10-26 00:46:07 +00004772GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
j_mayer7dbe11a2007-10-01 05:16:57 +00004773{
4774#if defined(CONFIG_USER_ONLY)
4775 GEN_EXCP_PRIVOPC(ctx);
4776#else
4777 if (unlikely(!ctx->supervisor)) {
4778 GEN_EXCP_PRIVOPC(ctx);
4779 return;
4780 }
aurel32f78fb442008-09-04 05:25:47 +00004781 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
j_mayer7dbe11a2007-10-01 05:16:57 +00004782 gen_op_74xx_tlbld();
4783#endif
4784}
4785
4786/* tlbli */
j_mayerc7697e12007-10-26 00:46:07 +00004787GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
j_mayer7dbe11a2007-10-01 05:16:57 +00004788{
4789#if defined(CONFIG_USER_ONLY)
4790 GEN_EXCP_PRIVOPC(ctx);
4791#else
4792 if (unlikely(!ctx->supervisor)) {
4793 GEN_EXCP_PRIVOPC(ctx);
4794 return;
4795 }
aurel32f78fb442008-09-04 05:25:47 +00004796 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
j_mayer7dbe11a2007-10-01 05:16:57 +00004797 gen_op_74xx_tlbli();
4798#endif
4799}
4800
j_mayer76a66252007-03-07 08:32:30 +00004801/* POWER instructions not in PowerPC 601 */
4802/* clf */
4803GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4804{
4805 /* Cache line flush: implemented as no-op */
4806}
4807
4808/* cli */
4809GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4810{
blueswir17f75ffd2007-05-27 19:39:27 +00004811 /* Cache line invalidate: privileged and treated as no-op */
j_mayer76a66252007-03-07 08:32:30 +00004812#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004813 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004814#else
4815 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004816 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004817 return;
4818 }
4819#endif
4820}
4821
4822/* dclst */
4823GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4824{
4825 /* Data cache line store: treated as no-op */
4826}
4827
4828GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4829{
4830#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004831 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004832#else
4833 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004834 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004835 return;
4836 }
4837 int ra = rA(ctx->opcode);
4838 int rd = rD(ctx->opcode);
4839
aurel32e2be8d82008-10-14 19:55:54 +00004840 gen_addr_reg_index(cpu_T[0], ctx);
j_mayer76a66252007-03-07 08:32:30 +00004841 gen_op_POWER_mfsri();
aurel32f78fb442008-09-04 05:25:47 +00004842 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004843 if (ra != 0 && ra != rd)
aurel32f78fb442008-09-04 05:25:47 +00004844 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
j_mayer76a66252007-03-07 08:32:30 +00004845#endif
4846}
4847
4848GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4849{
4850#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004851 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004852#else
4853 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004854 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004855 return;
4856 }
aurel32e2be8d82008-10-14 19:55:54 +00004857 gen_addr_reg_index(cpu_T[0], ctx);
j_mayer76a66252007-03-07 08:32:30 +00004858 gen_op_POWER_rac();
aurel32f78fb442008-09-04 05:25:47 +00004859 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004860#endif
4861}
4862
4863GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4864{
4865#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00004866 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004867#else
4868 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00004869 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004870 return;
4871 }
4872 gen_op_POWER_rfsvc();
j_mayere1833e12007-09-29 13:06:16 +00004873 GEN_SYNC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00004874#endif
4875}
4876
4877/* svc is not implemented for now */
4878
4879/* POWER2 specific instructions */
4880/* Quad manipulation (load/store two floats at a time) */
j_mayer78636672007-11-16 14:11:28 +00004881/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
j_mayer76a66252007-03-07 08:32:30 +00004882#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4883#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
j_mayer78636672007-11-16 14:11:28 +00004884#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4885#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4886#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4887#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4888#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4889#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4890#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4891#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4892#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4893#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4894#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4895#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4896#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4897#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4898#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4899#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4900static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4901 GEN_MEM_FUNCS(POWER2_lfq),
j_mayer76a66252007-03-07 08:32:30 +00004902};
j_mayer78636672007-11-16 14:11:28 +00004903static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4904 GEN_MEM_FUNCS(POWER2_stfq),
j_mayer76a66252007-03-07 08:32:30 +00004905};
j_mayer76a66252007-03-07 08:32:30 +00004906
4907/* lfq */
4908GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4909{
4910 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00004911 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00004912 gen_addr_imm_index(cpu_T[0], ctx, 0);
j_mayer76a66252007-03-07 08:32:30 +00004913 op_POWER2_lfq();
aurel32a5e26af2008-09-04 14:43:54 +00004914 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4915 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
j_mayer76a66252007-03-07 08:32:30 +00004916}
4917
4918/* lfqu */
4919GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4920{
4921 int ra = rA(ctx->opcode);
4922
4923 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00004924 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00004925 gen_addr_imm_index(cpu_T[0], ctx, 0);
j_mayer76a66252007-03-07 08:32:30 +00004926 op_POWER2_lfq();
aurel32a5e26af2008-09-04 14:43:54 +00004927 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4928 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
j_mayer76a66252007-03-07 08:32:30 +00004929 if (ra != 0)
aurel32f78fb442008-09-04 05:25:47 +00004930 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004931}
4932
4933/* lfqux */
4934GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4935{
4936 int ra = rA(ctx->opcode);
4937
4938 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00004939 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00004940 gen_addr_reg_index(cpu_T[0], ctx);
j_mayer76a66252007-03-07 08:32:30 +00004941 op_POWER2_lfq();
aurel32a5e26af2008-09-04 14:43:54 +00004942 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4943 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
j_mayer76a66252007-03-07 08:32:30 +00004944 if (ra != 0)
aurel32f78fb442008-09-04 05:25:47 +00004945 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004946}
4947
4948/* lfqx */
4949GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4950{
4951 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00004952 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00004953 gen_addr_reg_index(cpu_T[0], ctx);
j_mayer76a66252007-03-07 08:32:30 +00004954 op_POWER2_lfq();
aurel32a5e26af2008-09-04 14:43:54 +00004955 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4956 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
j_mayer76a66252007-03-07 08:32:30 +00004957}
4958
4959/* stfq */
4960GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4961{
4962 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00004963 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00004964 gen_addr_imm_index(cpu_T[0], ctx, 0);
aurel32a5e26af2008-09-04 14:43:54 +00004965 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4966 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
j_mayer76a66252007-03-07 08:32:30 +00004967 op_POWER2_stfq();
4968}
4969
4970/* stfqu */
4971GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4972{
4973 int ra = rA(ctx->opcode);
4974
4975 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00004976 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00004977 gen_addr_imm_index(cpu_T[0], ctx, 0);
aurel32a5e26af2008-09-04 14:43:54 +00004978 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4979 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
j_mayer76a66252007-03-07 08:32:30 +00004980 op_POWER2_stfq();
4981 if (ra != 0)
aurel32f78fb442008-09-04 05:25:47 +00004982 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004983}
4984
4985/* stfqux */
4986GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4987{
4988 int ra = rA(ctx->opcode);
4989
4990 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00004991 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00004992 gen_addr_reg_index(cpu_T[0], ctx);
aurel32a5e26af2008-09-04 14:43:54 +00004993 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4994 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
j_mayer76a66252007-03-07 08:32:30 +00004995 op_POWER2_stfq();
4996 if (ra != 0)
aurel32f78fb442008-09-04 05:25:47 +00004997 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00004998}
4999
5000/* stfqx */
5001GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5002{
5003 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00005004 gen_update_nip(ctx, ctx->nip - 4);
aurel32e2be8d82008-10-14 19:55:54 +00005005 gen_addr_reg_index(cpu_T[0], ctx);
aurel32a5e26af2008-09-04 14:43:54 +00005006 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5007 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
j_mayer76a66252007-03-07 08:32:30 +00005008 op_POWER2_stfq();
5009}
5010
5011/* BookE specific instructions */
j_mayer2662a052007-09-21 05:50:37 +00005012/* XXX: not implemented on 440 ? */
j_mayer05332d72007-11-17 22:26:51 +00005013GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
j_mayer76a66252007-03-07 08:32:30 +00005014{
5015 /* XXX: TODO */
j_mayere1833e12007-09-29 13:06:16 +00005016 GEN_EXCP_INVAL(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005017}
5018
j_mayer2662a052007-09-21 05:50:37 +00005019/* XXX: not implemented on 440 ? */
j_mayer05332d72007-11-17 22:26:51 +00005020GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
j_mayer76a66252007-03-07 08:32:30 +00005021{
5022#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005023 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005024#else
5025 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005026 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005027 return;
5028 }
aurel32e2be8d82008-10-14 19:55:54 +00005029 gen_addr_reg_index(cpu_T[0], ctx);
j_mayer76a66252007-03-07 08:32:30 +00005030 /* Use the same micro-ops as for tlbie */
j_mayerd9bce9d2007-03-17 14:02:15 +00005031#if defined(TARGET_PPC64)
5032 if (ctx->sf_mode)
5033 gen_op_tlbie_64();
5034 else
5035#endif
5036 gen_op_tlbie();
j_mayer76a66252007-03-07 08:32:30 +00005037#endif
5038}
5039
5040/* All 405 MAC instructions are translated here */
j_mayerb068d6a2007-10-07 17:13:44 +00005041static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5042 int opc2, int opc3,
5043 int ra, int rb, int rt, int Rc)
j_mayer76a66252007-03-07 08:32:30 +00005044{
aurel32f78fb442008-09-04 05:25:47 +00005045 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
5046 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
j_mayer76a66252007-03-07 08:32:30 +00005047 switch (opc3 & 0x0D) {
5048 case 0x05:
5049 /* macchw - macchw. - macchwo - macchwo. */
5050 /* macchws - macchws. - macchwso - macchwso. */
5051 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5052 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5053 /* mulchw - mulchw. */
5054 gen_op_405_mulchw();
5055 break;
5056 case 0x04:
5057 /* macchwu - macchwu. - macchwuo - macchwuo. */
5058 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5059 /* mulchwu - mulchwu. */
5060 gen_op_405_mulchwu();
5061 break;
5062 case 0x01:
5063 /* machhw - machhw. - machhwo - machhwo. */
5064 /* machhws - machhws. - machhwso - machhwso. */
5065 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5066 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5067 /* mulhhw - mulhhw. */
5068 gen_op_405_mulhhw();
5069 break;
5070 case 0x00:
5071 /* machhwu - machhwu. - machhwuo - machhwuo. */
5072 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5073 /* mulhhwu - mulhhwu. */
5074 gen_op_405_mulhhwu();
5075 break;
5076 case 0x0D:
5077 /* maclhw - maclhw. - maclhwo - maclhwo. */
5078 /* maclhws - maclhws. - maclhwso - maclhwso. */
5079 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5080 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5081 /* mullhw - mullhw. */
5082 gen_op_405_mullhw();
5083 break;
5084 case 0x0C:
5085 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5086 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5087 /* mullhwu - mullhwu. */
5088 gen_op_405_mullhwu();
5089 break;
5090 }
5091 if (opc2 & 0x02) {
5092 /* nmultiply-and-accumulate (0x0E) */
5093 gen_op_neg();
5094 }
5095 if (opc2 & 0x04) {
5096 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
aurel32f78fb442008-09-04 05:25:47 +00005097 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
aurel32e55fd932008-09-02 16:19:05 +00005098 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00005099 gen_op_405_add_T0_T2();
5100 }
5101 if (opc3 & 0x10) {
5102 /* Check overflow */
5103 if (opc3 & 0x01)
j_mayerc3e10c72007-11-11 00:18:34 +00005104 gen_op_check_addo();
j_mayer76a66252007-03-07 08:32:30 +00005105 else
5106 gen_op_405_check_ovu();
5107 }
5108 if (opc3 & 0x02) {
5109 /* Saturate */
5110 if (opc3 & 0x01)
5111 gen_op_405_check_sat();
5112 else
5113 gen_op_405_check_satu();
5114 }
aurel32f78fb442008-09-04 05:25:47 +00005115 tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00005116 if (unlikely(Rc) != 0) {
5117 /* Update Rc0 */
aurel32e1571902008-10-21 11:31:14 +00005118 gen_set_Rc0(ctx, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00005119 }
5120}
5121
j_mayera750fc02007-09-26 23:54:22 +00005122#define GEN_MAC_HANDLER(name, opc2, opc3) \
5123GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
j_mayer76a66252007-03-07 08:32:30 +00005124{ \
5125 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5126 rD(ctx->opcode), Rc(ctx->opcode)); \
5127}
5128
5129/* macchw - macchw. */
j_mayera750fc02007-09-26 23:54:22 +00005130GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
j_mayer76a66252007-03-07 08:32:30 +00005131/* macchwo - macchwo. */
j_mayera750fc02007-09-26 23:54:22 +00005132GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
j_mayer76a66252007-03-07 08:32:30 +00005133/* macchws - macchws. */
j_mayera750fc02007-09-26 23:54:22 +00005134GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
j_mayer76a66252007-03-07 08:32:30 +00005135/* macchwso - macchwso. */
j_mayera750fc02007-09-26 23:54:22 +00005136GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
j_mayer76a66252007-03-07 08:32:30 +00005137/* macchwsu - macchwsu. */
j_mayera750fc02007-09-26 23:54:22 +00005138GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
j_mayer76a66252007-03-07 08:32:30 +00005139/* macchwsuo - macchwsuo. */
j_mayera750fc02007-09-26 23:54:22 +00005140GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
j_mayer76a66252007-03-07 08:32:30 +00005141/* macchwu - macchwu. */
j_mayera750fc02007-09-26 23:54:22 +00005142GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
j_mayer76a66252007-03-07 08:32:30 +00005143/* macchwuo - macchwuo. */
j_mayera750fc02007-09-26 23:54:22 +00005144GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
j_mayer76a66252007-03-07 08:32:30 +00005145/* machhw - machhw. */
j_mayera750fc02007-09-26 23:54:22 +00005146GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
j_mayer76a66252007-03-07 08:32:30 +00005147/* machhwo - machhwo. */
j_mayera750fc02007-09-26 23:54:22 +00005148GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
j_mayer76a66252007-03-07 08:32:30 +00005149/* machhws - machhws. */
j_mayera750fc02007-09-26 23:54:22 +00005150GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
j_mayer76a66252007-03-07 08:32:30 +00005151/* machhwso - machhwso. */
j_mayera750fc02007-09-26 23:54:22 +00005152GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
j_mayer76a66252007-03-07 08:32:30 +00005153/* machhwsu - machhwsu. */
j_mayera750fc02007-09-26 23:54:22 +00005154GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
j_mayer76a66252007-03-07 08:32:30 +00005155/* machhwsuo - machhwsuo. */
j_mayera750fc02007-09-26 23:54:22 +00005156GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
j_mayer76a66252007-03-07 08:32:30 +00005157/* machhwu - machhwu. */
j_mayera750fc02007-09-26 23:54:22 +00005158GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
j_mayer76a66252007-03-07 08:32:30 +00005159/* machhwuo - machhwuo. */
j_mayera750fc02007-09-26 23:54:22 +00005160GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
j_mayer76a66252007-03-07 08:32:30 +00005161/* maclhw - maclhw. */
j_mayera750fc02007-09-26 23:54:22 +00005162GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
j_mayer76a66252007-03-07 08:32:30 +00005163/* maclhwo - maclhwo. */
j_mayera750fc02007-09-26 23:54:22 +00005164GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
j_mayer76a66252007-03-07 08:32:30 +00005165/* maclhws - maclhws. */
j_mayera750fc02007-09-26 23:54:22 +00005166GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
j_mayer76a66252007-03-07 08:32:30 +00005167/* maclhwso - maclhwso. */
j_mayera750fc02007-09-26 23:54:22 +00005168GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
j_mayer76a66252007-03-07 08:32:30 +00005169/* maclhwu - maclhwu. */
j_mayera750fc02007-09-26 23:54:22 +00005170GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
j_mayer76a66252007-03-07 08:32:30 +00005171/* maclhwuo - maclhwuo. */
j_mayera750fc02007-09-26 23:54:22 +00005172GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
j_mayer76a66252007-03-07 08:32:30 +00005173/* maclhwsu - maclhwsu. */
j_mayera750fc02007-09-26 23:54:22 +00005174GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
j_mayer76a66252007-03-07 08:32:30 +00005175/* maclhwsuo - maclhwsuo. */
j_mayera750fc02007-09-26 23:54:22 +00005176GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
j_mayer76a66252007-03-07 08:32:30 +00005177/* nmacchw - nmacchw. */
j_mayera750fc02007-09-26 23:54:22 +00005178GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
j_mayer76a66252007-03-07 08:32:30 +00005179/* nmacchwo - nmacchwo. */
j_mayera750fc02007-09-26 23:54:22 +00005180GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
j_mayer76a66252007-03-07 08:32:30 +00005181/* nmacchws - nmacchws. */
j_mayera750fc02007-09-26 23:54:22 +00005182GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
j_mayer76a66252007-03-07 08:32:30 +00005183/* nmacchwso - nmacchwso. */
j_mayera750fc02007-09-26 23:54:22 +00005184GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
j_mayer76a66252007-03-07 08:32:30 +00005185/* nmachhw - nmachhw. */
j_mayera750fc02007-09-26 23:54:22 +00005186GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
j_mayer76a66252007-03-07 08:32:30 +00005187/* nmachhwo - nmachhwo. */
j_mayera750fc02007-09-26 23:54:22 +00005188GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
j_mayer76a66252007-03-07 08:32:30 +00005189/* nmachhws - nmachhws. */
j_mayera750fc02007-09-26 23:54:22 +00005190GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
j_mayer76a66252007-03-07 08:32:30 +00005191/* nmachhwso - nmachhwso. */
j_mayera750fc02007-09-26 23:54:22 +00005192GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
j_mayer76a66252007-03-07 08:32:30 +00005193/* nmaclhw - nmaclhw. */
j_mayera750fc02007-09-26 23:54:22 +00005194GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
j_mayer76a66252007-03-07 08:32:30 +00005195/* nmaclhwo - nmaclhwo. */
j_mayera750fc02007-09-26 23:54:22 +00005196GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
j_mayer76a66252007-03-07 08:32:30 +00005197/* nmaclhws - nmaclhws. */
j_mayera750fc02007-09-26 23:54:22 +00005198GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
j_mayer76a66252007-03-07 08:32:30 +00005199/* nmaclhwso - nmaclhwso. */
j_mayera750fc02007-09-26 23:54:22 +00005200GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
j_mayer76a66252007-03-07 08:32:30 +00005201
5202/* mulchw - mulchw. */
j_mayera750fc02007-09-26 23:54:22 +00005203GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
j_mayer76a66252007-03-07 08:32:30 +00005204/* mulchwu - mulchwu. */
j_mayera750fc02007-09-26 23:54:22 +00005205GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
j_mayer76a66252007-03-07 08:32:30 +00005206/* mulhhw - mulhhw. */
j_mayera750fc02007-09-26 23:54:22 +00005207GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
j_mayer76a66252007-03-07 08:32:30 +00005208/* mulhhwu - mulhhwu. */
j_mayera750fc02007-09-26 23:54:22 +00005209GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
j_mayer76a66252007-03-07 08:32:30 +00005210/* mullhw - mullhw. */
j_mayera750fc02007-09-26 23:54:22 +00005211GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
j_mayer76a66252007-03-07 08:32:30 +00005212/* mullhwu - mullhwu. */
j_mayera750fc02007-09-26 23:54:22 +00005213GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
j_mayer76a66252007-03-07 08:32:30 +00005214
5215/* mfdcr */
j_mayer05332d72007-11-17 22:26:51 +00005216GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
j_mayer76a66252007-03-07 08:32:30 +00005217{
5218#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005219 GEN_EXCP_PRIVREG(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005220#else
5221 uint32_t dcrn = SPR(ctx->opcode);
5222
5223 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005224 GEN_EXCP_PRIVREG(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005225 return;
5226 }
aurel3286c581d2008-09-02 23:26:32 +00005227 tcg_gen_movi_tl(cpu_T[0], dcrn);
j_mayera42bd6c2007-03-30 10:22:46 +00005228 gen_op_load_dcr();
aurel32f78fb442008-09-04 05:25:47 +00005229 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00005230#endif
5231}
5232
5233/* mtdcr */
j_mayer05332d72007-11-17 22:26:51 +00005234GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
j_mayer76a66252007-03-07 08:32:30 +00005235{
5236#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005237 GEN_EXCP_PRIVREG(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005238#else
5239 uint32_t dcrn = SPR(ctx->opcode);
5240
5241 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005242 GEN_EXCP_PRIVREG(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005243 return;
5244 }
aurel3286c581d2008-09-02 23:26:32 +00005245 tcg_gen_movi_tl(cpu_T[0], dcrn);
aurel32f78fb442008-09-04 05:25:47 +00005246 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
j_mayera42bd6c2007-03-30 10:22:46 +00005247 gen_op_store_dcr();
5248#endif
5249}
5250
5251/* mfdcrx */
j_mayer2662a052007-09-21 05:50:37 +00005252/* XXX: not implemented on 440 ? */
j_mayer05332d72007-11-17 22:26:51 +00005253GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
j_mayera42bd6c2007-03-30 10:22:46 +00005254{
5255#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005256 GEN_EXCP_PRIVREG(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005257#else
5258 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005259 GEN_EXCP_PRIVREG(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005260 return;
5261 }
aurel32f78fb442008-09-04 05:25:47 +00005262 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayera42bd6c2007-03-30 10:22:46 +00005263 gen_op_load_dcr();
aurel32f78fb442008-09-04 05:25:47 +00005264 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayera750fc02007-09-26 23:54:22 +00005265 /* Note: Rc update flag set leads to undefined state of Rc0 */
j_mayera42bd6c2007-03-30 10:22:46 +00005266#endif
5267}
5268
5269/* mtdcrx */
j_mayer2662a052007-09-21 05:50:37 +00005270/* XXX: not implemented on 440 ? */
j_mayer05332d72007-11-17 22:26:51 +00005271GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
j_mayera42bd6c2007-03-30 10:22:46 +00005272{
5273#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005274 GEN_EXCP_PRIVREG(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005275#else
5276 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005277 GEN_EXCP_PRIVREG(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005278 return;
5279 }
aurel32f78fb442008-09-04 05:25:47 +00005280 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5281 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
j_mayera42bd6c2007-03-30 10:22:46 +00005282 gen_op_store_dcr();
j_mayera750fc02007-09-26 23:54:22 +00005283 /* Note: Rc update flag set leads to undefined state of Rc0 */
j_mayer76a66252007-03-07 08:32:30 +00005284#endif
5285}
5286
j_mayera750fc02007-09-26 23:54:22 +00005287/* mfdcrux (PPC 460) : user-mode access to DCR */
5288GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5289{
aurel32f78fb442008-09-04 05:25:47 +00005290 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayera750fc02007-09-26 23:54:22 +00005291 gen_op_load_dcr();
aurel32f78fb442008-09-04 05:25:47 +00005292 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayera750fc02007-09-26 23:54:22 +00005293 /* Note: Rc update flag set leads to undefined state of Rc0 */
5294}
5295
5296/* mtdcrux (PPC 460) : user-mode access to DCR */
5297GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5298{
aurel32f78fb442008-09-04 05:25:47 +00005299 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5300 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
j_mayera750fc02007-09-26 23:54:22 +00005301 gen_op_store_dcr();
5302 /* Note: Rc update flag set leads to undefined state of Rc0 */
5303}
5304
j_mayer76a66252007-03-07 08:32:30 +00005305/* dccci */
5306GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5307{
5308#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005309 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005310#else
5311 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005312 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005313 return;
5314 }
5315 /* interpreted as no-op */
5316#endif
5317}
5318
5319/* dcread */
5320GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5321{
5322#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005323 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005324#else
aurel32b61f2752008-10-15 17:00:37 +00005325 TCGv EA, val;
j_mayer76a66252007-03-07 08:32:30 +00005326 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005327 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005328 return;
5329 }
aurel32b61f2752008-10-15 17:00:37 +00005330 EA = tcg_temp_new(TCG_TYPE_TL);
5331 gen_addr_reg_index(EA, ctx);
5332 val = tcg_temp_new(TCG_TYPE_TL);
5333 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5334 tcg_temp_free(val);
5335 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5336 tcg_temp_free(EA);
j_mayer76a66252007-03-07 08:32:30 +00005337#endif
5338}
5339
5340/* icbt */
j_mayerc7697e12007-10-26 00:46:07 +00005341GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
j_mayer76a66252007-03-07 08:32:30 +00005342{
5343 /* interpreted as no-op */
5344 /* XXX: specification say this is treated as a load by the MMU
5345 * but does not generate any exception
5346 */
5347}
5348
5349/* iccci */
5350GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5351{
5352#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005353 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005354#else
5355 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005356 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005357 return;
5358 }
5359 /* interpreted as no-op */
5360#endif
5361}
5362
5363/* icread */
5364GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5365{
5366#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005367 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005368#else
5369 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005370 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005371 return;
5372 }
5373 /* interpreted as no-op */
5374#endif
5375}
5376
5377/* rfci (supervisor only) */
j_mayerc7697e12007-10-26 00:46:07 +00005378GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
j_mayer76a66252007-03-07 08:32:30 +00005379{
5380#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005381 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005382#else
5383 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005384 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005385 return;
5386 }
5387 /* Restore CPU state */
j_mayera42bd6c2007-03-30 10:22:46 +00005388 gen_op_40x_rfci();
j_mayere1833e12007-09-29 13:06:16 +00005389 GEN_SYNC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005390#endif
5391}
5392
j_mayera42bd6c2007-03-30 10:22:46 +00005393GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5394{
5395#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005396 GEN_EXCP_PRIVOPC(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005397#else
5398 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005399 GEN_EXCP_PRIVOPC(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005400 return;
5401 }
5402 /* Restore CPU state */
5403 gen_op_rfci();
j_mayere1833e12007-09-29 13:06:16 +00005404 GEN_SYNC(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005405#endif
5406}
5407
5408/* BookE specific */
j_mayer2662a052007-09-21 05:50:37 +00005409/* XXX: not implemented on 440 ? */
j_mayer05332d72007-11-17 22:26:51 +00005410GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
j_mayera42bd6c2007-03-30 10:22:46 +00005411{
5412#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005413 GEN_EXCP_PRIVOPC(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005414#else
5415 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005416 GEN_EXCP_PRIVOPC(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005417 return;
5418 }
5419 /* Restore CPU state */
5420 gen_op_rfdi();
j_mayere1833e12007-09-29 13:06:16 +00005421 GEN_SYNC(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005422#endif
5423}
5424
j_mayer2662a052007-09-21 05:50:37 +00005425/* XXX: not implemented on 440 ? */
j_mayera750fc02007-09-26 23:54:22 +00005426GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
j_mayera42bd6c2007-03-30 10:22:46 +00005427{
5428#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005429 GEN_EXCP_PRIVOPC(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005430#else
5431 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005432 GEN_EXCP_PRIVOPC(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005433 return;
5434 }
5435 /* Restore CPU state */
5436 gen_op_rfmci();
j_mayere1833e12007-09-29 13:06:16 +00005437 GEN_SYNC(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005438#endif
5439}
j_mayer5eb79952007-09-19 05:44:04 +00005440
j_mayerd9bce9d2007-03-17 14:02:15 +00005441/* TLB management - PowerPC 405 implementation */
j_mayer76a66252007-03-07 08:32:30 +00005442/* tlbre */
j_mayerc7697e12007-10-26 00:46:07 +00005443GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
j_mayer76a66252007-03-07 08:32:30 +00005444{
5445#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005446 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005447#else
5448 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005449 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005450 return;
5451 }
5452 switch (rB(ctx->opcode)) {
5453 case 0:
aurel32f78fb442008-09-04 05:25:47 +00005454 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005455 gen_op_4xx_tlbre_hi();
aurel32f78fb442008-09-04 05:25:47 +00005456 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00005457 break;
5458 case 1:
aurel32f78fb442008-09-04 05:25:47 +00005459 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005460 gen_op_4xx_tlbre_lo();
aurel32f78fb442008-09-04 05:25:47 +00005461 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00005462 break;
5463 default:
j_mayere1833e12007-09-29 13:06:16 +00005464 GEN_EXCP_INVAL(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005465 break;
5466 }
5467#endif
5468}
5469
j_mayerd9bce9d2007-03-17 14:02:15 +00005470/* tlbsx - tlbsx. */
j_mayerc7697e12007-10-26 00:46:07 +00005471GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
j_mayer76a66252007-03-07 08:32:30 +00005472{
5473#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005474 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005475#else
5476 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005477 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005478 return;
5479 }
aurel32e2be8d82008-10-14 19:55:54 +00005480 gen_addr_reg_index(cpu_T[0], ctx);
j_mayerdaf4f962007-10-01 01:51:12 +00005481 gen_op_4xx_tlbsx();
j_mayer76a66252007-03-07 08:32:30 +00005482 if (Rc(ctx->opcode))
j_mayerdaf4f962007-10-01 01:51:12 +00005483 gen_op_4xx_tlbsx_check();
aurel32f78fb442008-09-04 05:25:47 +00005484 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00005485#endif
5486}
5487
5488/* tlbwe */
j_mayerc7697e12007-10-26 00:46:07 +00005489GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
j_mayer76a66252007-03-07 08:32:30 +00005490{
5491#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005492 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005493#else
5494 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005495 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005496 return;
5497 }
5498 switch (rB(ctx->opcode)) {
5499 case 0:
aurel32f78fb442008-09-04 05:25:47 +00005500 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5501 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005502 gen_op_4xx_tlbwe_hi();
5503 break;
5504 case 1:
aurel32f78fb442008-09-04 05:25:47 +00005505 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5506 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005507 gen_op_4xx_tlbwe_lo();
5508 break;
5509 default:
j_mayere1833e12007-09-29 13:06:16 +00005510 GEN_EXCP_INVAL(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005511 break;
5512 }
5513#endif
5514}
5515
j_mayera4bb6c32007-09-21 05:28:33 +00005516/* TLB management - PowerPC 440 implementation */
j_mayer5eb79952007-09-19 05:44:04 +00005517/* tlbre */
j_mayerc7697e12007-10-26 00:46:07 +00005518GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
j_mayer5eb79952007-09-19 05:44:04 +00005519{
5520#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005521 GEN_EXCP_PRIVOPC(ctx);
j_mayer5eb79952007-09-19 05:44:04 +00005522#else
5523 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005524 GEN_EXCP_PRIVOPC(ctx);
j_mayer5eb79952007-09-19 05:44:04 +00005525 return;
5526 }
5527 switch (rB(ctx->opcode)) {
5528 case 0:
j_mayer5eb79952007-09-19 05:44:04 +00005529 case 1:
j_mayer5eb79952007-09-19 05:44:04 +00005530 case 2:
aurel32f78fb442008-09-04 05:25:47 +00005531 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
j_mayera4bb6c32007-09-21 05:28:33 +00005532 gen_op_440_tlbre(rB(ctx->opcode));
aurel32f78fb442008-09-04 05:25:47 +00005533 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer5eb79952007-09-19 05:44:04 +00005534 break;
5535 default:
j_mayere1833e12007-09-29 13:06:16 +00005536 GEN_EXCP_INVAL(ctx);
j_mayer5eb79952007-09-19 05:44:04 +00005537 break;
5538 }
5539#endif
5540}
5541
5542/* tlbsx - tlbsx. */
j_mayerc7697e12007-10-26 00:46:07 +00005543GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
j_mayer5eb79952007-09-19 05:44:04 +00005544{
5545#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005546 GEN_EXCP_PRIVOPC(ctx);
j_mayer5eb79952007-09-19 05:44:04 +00005547#else
5548 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005549 GEN_EXCP_PRIVOPC(ctx);
j_mayer5eb79952007-09-19 05:44:04 +00005550 return;
5551 }
aurel32e2be8d82008-10-14 19:55:54 +00005552 gen_addr_reg_index(cpu_T[0], ctx);
j_mayerdaf4f962007-10-01 01:51:12 +00005553 gen_op_440_tlbsx();
j_mayer5eb79952007-09-19 05:44:04 +00005554 if (Rc(ctx->opcode))
j_mayerdaf4f962007-10-01 01:51:12 +00005555 gen_op_4xx_tlbsx_check();
aurel32f78fb442008-09-04 05:25:47 +00005556 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer5eb79952007-09-19 05:44:04 +00005557#endif
5558}
5559
5560/* tlbwe */
j_mayerc7697e12007-10-26 00:46:07 +00005561GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
j_mayer5eb79952007-09-19 05:44:04 +00005562{
5563#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005564 GEN_EXCP_PRIVOPC(ctx);
j_mayer5eb79952007-09-19 05:44:04 +00005565#else
5566 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005567 GEN_EXCP_PRIVOPC(ctx);
j_mayer5eb79952007-09-19 05:44:04 +00005568 return;
5569 }
5570 switch (rB(ctx->opcode)) {
5571 case 0:
j_mayer5eb79952007-09-19 05:44:04 +00005572 case 1:
j_mayer5eb79952007-09-19 05:44:04 +00005573 case 2:
aurel32f78fb442008-09-04 05:25:47 +00005574 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5575 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
j_mayera4bb6c32007-09-21 05:28:33 +00005576 gen_op_440_tlbwe(rB(ctx->opcode));
j_mayer5eb79952007-09-19 05:44:04 +00005577 break;
5578 default:
j_mayere1833e12007-09-29 13:06:16 +00005579 GEN_EXCP_INVAL(ctx);
j_mayer5eb79952007-09-19 05:44:04 +00005580 break;
5581 }
5582#endif
5583}
5584
j_mayer76a66252007-03-07 08:32:30 +00005585/* wrtee */
j_mayer05332d72007-11-17 22:26:51 +00005586GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
j_mayer76a66252007-03-07 08:32:30 +00005587{
5588#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005589 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005590#else
5591 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005592 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005593 return;
5594 }
aurel32f78fb442008-09-04 05:25:47 +00005595 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
j_mayera42bd6c2007-03-30 10:22:46 +00005596 gen_op_wrte();
j_mayerdee96f62007-09-29 15:02:38 +00005597 /* Stop translation to have a chance to raise an exception
5598 * if we just set msr_ee to 1
5599 */
j_mayere1833e12007-09-29 13:06:16 +00005600 GEN_STOP(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005601#endif
5602}
5603
5604/* wrteei */
j_mayer05332d72007-11-17 22:26:51 +00005605GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
j_mayer76a66252007-03-07 08:32:30 +00005606{
5607#if defined(CONFIG_USER_ONLY)
j_mayere1833e12007-09-29 13:06:16 +00005608 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005609#else
5610 if (unlikely(!ctx->supervisor)) {
j_mayere1833e12007-09-29 13:06:16 +00005611 GEN_EXCP_PRIVOPC(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005612 return;
5613 }
aurel3286c581d2008-09-02 23:26:32 +00005614 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
j_mayera42bd6c2007-03-30 10:22:46 +00005615 gen_op_wrte();
j_mayerdee96f62007-09-29 15:02:38 +00005616 /* Stop translation to have a chance to raise an exception
5617 * if we just set msr_ee to 1
5618 */
j_mayere1833e12007-09-29 13:06:16 +00005619 GEN_STOP(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005620#endif
5621}
5622
j_mayer08e46e52007-04-16 07:18:42 +00005623/* PowerPC 440 specific instructions */
j_mayer76a66252007-03-07 08:32:30 +00005624/* dlmzb */
5625GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5626{
aurel32f78fb442008-09-04 05:25:47 +00005627 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5628 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005629 gen_op_440_dlmzb();
aurel32f78fb442008-09-04 05:25:47 +00005630 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
aurel323d7b4172008-10-21 11:28:46 +00005631 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5632 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
j_mayer76a66252007-03-07 08:32:30 +00005633 if (Rc(ctx->opcode)) {
5634 gen_op_440_dlmzb_update_Rc();
aurel3247e46612008-09-04 17:06:47 +00005635 tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
j_mayer76a66252007-03-07 08:32:30 +00005636 }
5637}
5638
5639/* mbar replaces eieio on 440 */
5640GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5641{
5642 /* interpreted as no-op */
5643}
5644
5645/* msync replaces sync on 440 */
j_mayer0db1b202007-09-30 03:46:38 +00005646GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
j_mayer76a66252007-03-07 08:32:30 +00005647{
5648 /* interpreted as no-op */
5649}
5650
5651/* icbt */
j_mayerc7697e12007-10-26 00:46:07 +00005652GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
j_mayer76a66252007-03-07 08:32:30 +00005653{
5654 /* interpreted as no-op */
5655 /* XXX: specification say this is treated as a load by the MMU
5656 * but does not generate any exception
5657 */
5658}
5659
j_mayera9d9eb82007-10-07 18:19:26 +00005660/*** Altivec vector extension ***/
5661/* Altivec registers moves */
j_mayera9d9eb82007-10-07 18:19:26 +00005662
aurel321d542692008-09-04 14:43:45 +00005663static always_inline void gen_load_avr(int t, int reg) {
5664 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5665 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5666}
5667
5668static always_inline void gen_store_avr(int reg, int t) {
5669 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5670 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5671}
j_mayera9d9eb82007-10-07 18:19:26 +00005672
5673#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
j_mayera9d9eb82007-10-07 18:19:26 +00005674#define OP_VR_LD_TABLE(name) \
j_mayer78636672007-11-16 14:11:28 +00005675static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5676 GEN_MEM_FUNCS(vr_l##name), \
j_mayera9d9eb82007-10-07 18:19:26 +00005677};
5678#define OP_VR_ST_TABLE(name) \
j_mayer78636672007-11-16 14:11:28 +00005679static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5680 GEN_MEM_FUNCS(vr_st##name), \
j_mayera9d9eb82007-10-07 18:19:26 +00005681};
j_mayera9d9eb82007-10-07 18:19:26 +00005682
5683#define GEN_VR_LDX(name, opc2, opc3) \
5684GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5685{ \
5686 if (unlikely(!ctx->altivec_enabled)) { \
5687 GEN_EXCP_NO_VR(ctx); \
5688 return; \
5689 } \
aurel32e2be8d82008-10-14 19:55:54 +00005690 gen_addr_reg_index(cpu_T[0], ctx); \
j_mayera9d9eb82007-10-07 18:19:26 +00005691 op_vr_ldst(vr_l##name); \
aurel321d542692008-09-04 14:43:45 +00005692 gen_store_avr(rD(ctx->opcode), 0); \
j_mayera9d9eb82007-10-07 18:19:26 +00005693}
5694
5695#define GEN_VR_STX(name, opc2, opc3) \
5696GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5697{ \
5698 if (unlikely(!ctx->altivec_enabled)) { \
5699 GEN_EXCP_NO_VR(ctx); \
5700 return; \
5701 } \
aurel32e2be8d82008-10-14 19:55:54 +00005702 gen_addr_reg_index(cpu_T[0], ctx); \
aurel321d542692008-09-04 14:43:45 +00005703 gen_load_avr(0, rS(ctx->opcode)); \
j_mayera9d9eb82007-10-07 18:19:26 +00005704 op_vr_ldst(vr_st##name); \
5705}
5706
5707OP_VR_LD_TABLE(vx);
5708GEN_VR_LDX(vx, 0x07, 0x03);
5709/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5710#define gen_op_vr_lvxl gen_op_vr_lvx
5711GEN_VR_LDX(vxl, 0x07, 0x0B);
5712
5713OP_VR_ST_TABLE(vx);
5714GEN_VR_STX(vx, 0x07, 0x07);
5715/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5716#define gen_op_vr_stvxl gen_op_vr_stvx
5717GEN_VR_STX(vxl, 0x07, 0x0F);
5718
j_mayer0487d6a2007-03-20 22:11:31 +00005719/*** SPE extension ***/
j_mayer0487d6a2007-03-20 22:11:31 +00005720/* Register moves */
j_mayer3cd7d1d2007-11-12 01:56:18 +00005721
aurel32f78fb442008-09-04 05:25:47 +00005722static always_inline void gen_load_gpr64(TCGv t, int reg) {
5723#if defined(TARGET_PPC64)
5724 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5725#else
pbrook36aa55d2008-09-21 13:48:32 +00005726 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
j_mayer0487d6a2007-03-20 22:11:31 +00005727#endif
aurel32f78fb442008-09-04 05:25:47 +00005728}
j_mayer0487d6a2007-03-20 22:11:31 +00005729
aurel32f78fb442008-09-04 05:25:47 +00005730static always_inline void gen_store_gpr64(int reg, TCGv t) {
5731#if defined(TARGET_PPC64)
5732 tcg_gen_mov_i64(cpu_gpr[reg], t);
5733#else
5734 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
aurel3219f98ff2008-10-15 17:00:29 +00005735 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
aurel32f78fb442008-09-04 05:25:47 +00005736 tcg_gen_shri_i64(tmp, t, 32);
5737 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5738 tcg_temp_free(tmp);
j_mayer0487d6a2007-03-20 22:11:31 +00005739#endif
aurel32f78fb442008-09-04 05:25:47 +00005740}
j_mayer3cd7d1d2007-11-12 01:56:18 +00005741
j_mayer0487d6a2007-03-20 22:11:31 +00005742#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5743GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5744{ \
5745 if (Rc(ctx->opcode)) \
5746 gen_##name1(ctx); \
5747 else \
5748 gen_##name0(ctx); \
5749}
5750
5751/* Handler for undefined SPE opcodes */
j_mayerb068d6a2007-10-07 17:13:44 +00005752static always_inline void gen_speundef (DisasContext *ctx)
j_mayer0487d6a2007-03-20 22:11:31 +00005753{
j_mayere1833e12007-09-29 13:06:16 +00005754 GEN_EXCP_INVAL(ctx);
j_mayer0487d6a2007-03-20 22:11:31 +00005755}
5756
5757/* SPE load and stores */
aurel32f0aabd12008-10-15 17:00:18 +00005758static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
j_mayer0487d6a2007-03-20 22:11:31 +00005759{
5760 target_long simm = rB(ctx->opcode);
5761
aurel32f0aabd12008-10-15 17:00:18 +00005762 if (rA(ctx->opcode) == 0)
5763 tcg_gen_movi_tl(EA, simm << sh);
5764 else if (likely(simm != 0))
5765 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5766 else
5767 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
j_mayer0487d6a2007-03-20 22:11:31 +00005768}
5769
5770#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
j_mayer0487d6a2007-03-20 22:11:31 +00005771#define OP_SPE_LD_TABLE(name) \
j_mayer78636672007-11-16 14:11:28 +00005772static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5773 GEN_MEM_FUNCS(spe_l##name), \
j_mayer0487d6a2007-03-20 22:11:31 +00005774};
5775#define OP_SPE_ST_TABLE(name) \
j_mayer78636672007-11-16 14:11:28 +00005776static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5777 GEN_MEM_FUNCS(spe_st##name), \
j_mayer0487d6a2007-03-20 22:11:31 +00005778};
j_mayer0487d6a2007-03-20 22:11:31 +00005779
5780#define GEN_SPE_LD(name, sh) \
j_mayerb068d6a2007-10-07 17:13:44 +00005781static always_inline void gen_evl##name (DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00005782{ \
5783 if (unlikely(!ctx->spe_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00005784 GEN_EXCP_NO_AP(ctx); \
j_mayer0487d6a2007-03-20 22:11:31 +00005785 return; \
5786 } \
aurel32f0aabd12008-10-15 17:00:18 +00005787 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
j_mayer0487d6a2007-03-20 22:11:31 +00005788 op_spe_ldst(spe_l##name); \
aurel32f78fb442008-09-04 05:25:47 +00005789 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
j_mayer0487d6a2007-03-20 22:11:31 +00005790}
5791
5792#define GEN_SPE_LDX(name) \
j_mayerb068d6a2007-10-07 17:13:44 +00005793static always_inline void gen_evl##name##x (DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00005794{ \
5795 if (unlikely(!ctx->spe_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00005796 GEN_EXCP_NO_AP(ctx); \
j_mayer0487d6a2007-03-20 22:11:31 +00005797 return; \
5798 } \
aurel32e2be8d82008-10-14 19:55:54 +00005799 gen_addr_reg_index(cpu_T[0], ctx); \
j_mayer0487d6a2007-03-20 22:11:31 +00005800 op_spe_ldst(spe_l##name); \
aurel32f78fb442008-09-04 05:25:47 +00005801 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
j_mayer0487d6a2007-03-20 22:11:31 +00005802}
5803
5804#define GEN_SPEOP_LD(name, sh) \
5805OP_SPE_LD_TABLE(name); \
5806GEN_SPE_LD(name, sh); \
5807GEN_SPE_LDX(name)
5808
5809#define GEN_SPE_ST(name, sh) \
j_mayerb068d6a2007-10-07 17:13:44 +00005810static always_inline void gen_evst##name (DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00005811{ \
5812 if (unlikely(!ctx->spe_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00005813 GEN_EXCP_NO_AP(ctx); \
j_mayer0487d6a2007-03-20 22:11:31 +00005814 return; \
5815 } \
aurel32f0aabd12008-10-15 17:00:18 +00005816 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
aurel32f78fb442008-09-04 05:25:47 +00005817 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
j_mayer0487d6a2007-03-20 22:11:31 +00005818 op_spe_ldst(spe_st##name); \
5819}
5820
5821#define GEN_SPE_STX(name) \
j_mayerb068d6a2007-10-07 17:13:44 +00005822static always_inline void gen_evst##name##x (DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00005823{ \
5824 if (unlikely(!ctx->spe_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00005825 GEN_EXCP_NO_AP(ctx); \
j_mayer0487d6a2007-03-20 22:11:31 +00005826 return; \
5827 } \
aurel32e2be8d82008-10-14 19:55:54 +00005828 gen_addr_reg_index(cpu_T[0], ctx); \
aurel32f78fb442008-09-04 05:25:47 +00005829 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
j_mayer0487d6a2007-03-20 22:11:31 +00005830 op_spe_ldst(spe_st##name); \
5831}
5832
5833#define GEN_SPEOP_ST(name, sh) \
5834OP_SPE_ST_TABLE(name); \
5835GEN_SPE_ST(name, sh); \
5836GEN_SPE_STX(name)
5837
5838#define GEN_SPEOP_LDST(name, sh) \
5839GEN_SPEOP_LD(name, sh); \
5840GEN_SPEOP_ST(name, sh)
5841
5842/* SPE arithmetic and logic */
5843#define GEN_SPEOP_ARITH2(name) \
j_mayerb068d6a2007-10-07 17:13:44 +00005844static always_inline void gen_##name (DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00005845{ \
5846 if (unlikely(!ctx->spe_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00005847 GEN_EXCP_NO_AP(ctx); \
j_mayer0487d6a2007-03-20 22:11:31 +00005848 return; \
5849 } \
aurel32f78fb442008-09-04 05:25:47 +00005850 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5851 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
j_mayer0487d6a2007-03-20 22:11:31 +00005852 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +00005853 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
j_mayer0487d6a2007-03-20 22:11:31 +00005854}
5855
aurel32cf960812008-10-21 11:29:55 +00005856#define GEN_SPEOP_TCG_ARITH2(name, tcg_op) \
aurel323d3a6a02008-10-15 17:00:45 +00005857static always_inline void gen_##name (DisasContext *ctx) \
5858{ \
5859 if (unlikely(!ctx->spe_enabled)) { \
5860 GEN_EXCP_NO_AP(ctx); \
5861 return; \
5862 } \
5863 TCGv t0 = tcg_temp_new(TCG_TYPE_I64); \
5864 TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
5865 gen_load_gpr64(t0, rA(ctx->opcode)); \
5866 gen_load_gpr64(t1, rB(ctx->opcode)); \
aurel32cf960812008-10-21 11:29:55 +00005867 tcg_op(t0, t0, t1); \
aurel323d3a6a02008-10-15 17:00:45 +00005868 gen_store_gpr64(rD(ctx->opcode), t0); \
5869 tcg_temp_free(t0); \
5870 tcg_temp_free(t1); \
5871}
5872
j_mayer0487d6a2007-03-20 22:11:31 +00005873#define GEN_SPEOP_ARITH1(name) \
j_mayerb068d6a2007-10-07 17:13:44 +00005874static always_inline void gen_##name (DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00005875{ \
5876 if (unlikely(!ctx->spe_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00005877 GEN_EXCP_NO_AP(ctx); \
j_mayer0487d6a2007-03-20 22:11:31 +00005878 return; \
5879 } \
aurel32f78fb442008-09-04 05:25:47 +00005880 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
j_mayer0487d6a2007-03-20 22:11:31 +00005881 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +00005882 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
j_mayer0487d6a2007-03-20 22:11:31 +00005883}
5884
5885#define GEN_SPEOP_COMP(name) \
j_mayerb068d6a2007-10-07 17:13:44 +00005886static always_inline void gen_##name (DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00005887{ \
5888 if (unlikely(!ctx->spe_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00005889 GEN_EXCP_NO_AP(ctx); \
j_mayer0487d6a2007-03-20 22:11:31 +00005890 return; \
5891 } \
aurel32f78fb442008-09-04 05:25:47 +00005892 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5893 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
j_mayer0487d6a2007-03-20 22:11:31 +00005894 gen_op_##name(); \
aurel3247e46612008-09-04 17:06:47 +00005895 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
j_mayer0487d6a2007-03-20 22:11:31 +00005896}
5897
5898/* Logical */
aurel32cf960812008-10-21 11:29:55 +00005899GEN_SPEOP_TCG_ARITH2(evand, tcg_gen_and_i64);
5900GEN_SPEOP_TCG_ARITH2(evandc, tcg_gen_andc_i64);
5901GEN_SPEOP_TCG_ARITH2(evxor, tcg_gen_xor_i64);
5902GEN_SPEOP_TCG_ARITH2(evor, tcg_gen_or_i64);
5903GEN_SPEOP_TCG_ARITH2(evnor, tcg_gen_nor_i64);
5904GEN_SPEOP_TCG_ARITH2(eveqv, tcg_gen_eqv_i64);
5905GEN_SPEOP_TCG_ARITH2(evorc, tcg_gen_orc_i64);
5906GEN_SPEOP_TCG_ARITH2(evnand, tcg_gen_nand_i64);
j_mayer0487d6a2007-03-20 22:11:31 +00005907GEN_SPEOP_ARITH2(evsrwu);
5908GEN_SPEOP_ARITH2(evsrws);
5909GEN_SPEOP_ARITH2(evslw);
5910GEN_SPEOP_ARITH2(evrlw);
5911GEN_SPEOP_ARITH2(evmergehi);
5912GEN_SPEOP_ARITH2(evmergelo);
5913GEN_SPEOP_ARITH2(evmergehilo);
5914GEN_SPEOP_ARITH2(evmergelohi);
5915
5916/* Arithmetic */
5917GEN_SPEOP_ARITH2(evaddw);
5918GEN_SPEOP_ARITH2(evsubfw);
5919GEN_SPEOP_ARITH1(evabs);
5920GEN_SPEOP_ARITH1(evneg);
5921GEN_SPEOP_ARITH1(evextsb);
5922GEN_SPEOP_ARITH1(evextsh);
5923GEN_SPEOP_ARITH1(evrndw);
5924GEN_SPEOP_ARITH1(evcntlzw);
5925GEN_SPEOP_ARITH1(evcntlsw);
j_mayerb068d6a2007-10-07 17:13:44 +00005926static always_inline void gen_brinc (DisasContext *ctx)
j_mayer0487d6a2007-03-20 22:11:31 +00005927{
5928 /* Note: brinc is usable even if SPE is disabled */
aurel32f78fb442008-09-04 05:25:47 +00005929 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5930 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
j_mayer0487d6a2007-03-20 22:11:31 +00005931 gen_op_brinc();
aurel32f78fb442008-09-04 05:25:47 +00005932 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
j_mayer0487d6a2007-03-20 22:11:31 +00005933}
5934
5935#define GEN_SPEOP_ARITH_IMM2(name) \
j_mayerb068d6a2007-10-07 17:13:44 +00005936static always_inline void gen_##name##i (DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00005937{ \
5938 if (unlikely(!ctx->spe_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00005939 GEN_EXCP_NO_AP(ctx); \
j_mayer0487d6a2007-03-20 22:11:31 +00005940 return; \
5941 } \
aurel32f78fb442008-09-04 05:25:47 +00005942 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
j_mayer0487d6a2007-03-20 22:11:31 +00005943 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5944 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +00005945 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
j_mayer0487d6a2007-03-20 22:11:31 +00005946}
5947
5948#define GEN_SPEOP_LOGIC_IMM2(name) \
j_mayerb068d6a2007-10-07 17:13:44 +00005949static always_inline void gen_##name##i (DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00005950{ \
5951 if (unlikely(!ctx->spe_enabled)) { \
j_mayere1833e12007-09-29 13:06:16 +00005952 GEN_EXCP_NO_AP(ctx); \
j_mayer0487d6a2007-03-20 22:11:31 +00005953 return; \
5954 } \
aurel32f78fb442008-09-04 05:25:47 +00005955 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
j_mayer0487d6a2007-03-20 22:11:31 +00005956 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5957 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +00005958 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
j_mayer0487d6a2007-03-20 22:11:31 +00005959}
5960
5961GEN_SPEOP_ARITH_IMM2(evaddw);
5962#define gen_evaddiw gen_evaddwi
5963GEN_SPEOP_ARITH_IMM2(evsubfw);
5964#define gen_evsubifw gen_evsubfwi
5965GEN_SPEOP_LOGIC_IMM2(evslw);
5966GEN_SPEOP_LOGIC_IMM2(evsrwu);
5967#define gen_evsrwis gen_evsrwsi
5968GEN_SPEOP_LOGIC_IMM2(evsrws);
5969#define gen_evsrwiu gen_evsrwui
5970GEN_SPEOP_LOGIC_IMM2(evrlw);
5971
j_mayerb068d6a2007-10-07 17:13:44 +00005972static always_inline void gen_evsplati (DisasContext *ctx)
j_mayer0487d6a2007-03-20 22:11:31 +00005973{
5974 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5975
5976 gen_op_splatwi_T0_64(imm);
aurel32f78fb442008-09-04 05:25:47 +00005977 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
j_mayer0487d6a2007-03-20 22:11:31 +00005978}
5979
j_mayerb068d6a2007-10-07 17:13:44 +00005980static always_inline void gen_evsplatfi (DisasContext *ctx)
j_mayer0487d6a2007-03-20 22:11:31 +00005981{
5982 uint32_t imm = rA(ctx->opcode) << 27;
5983
5984 gen_op_splatwi_T0_64(imm);
aurel32f78fb442008-09-04 05:25:47 +00005985 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
j_mayer0487d6a2007-03-20 22:11:31 +00005986}
5987
5988/* Comparison */
5989GEN_SPEOP_COMP(evcmpgtu);
5990GEN_SPEOP_COMP(evcmpgts);
5991GEN_SPEOP_COMP(evcmpltu);
5992GEN_SPEOP_COMP(evcmplts);
5993GEN_SPEOP_COMP(evcmpeq);
5994
5995GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5996GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5997GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5998GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5999GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6000GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6001GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6002GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6003GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6004GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6005GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6006GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6007GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6008GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6009GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6010GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6011GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6012GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6013GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6014GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6015GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6016GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6017GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6018GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6019GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6020
j_mayerb068d6a2007-10-07 17:13:44 +00006021static always_inline void gen_evsel (DisasContext *ctx)
j_mayer0487d6a2007-03-20 22:11:31 +00006022{
6023 if (unlikely(!ctx->spe_enabled)) {
j_mayere1833e12007-09-29 13:06:16 +00006024 GEN_EXCP_NO_AP(ctx);
j_mayer0487d6a2007-03-20 22:11:31 +00006025 return;
6026 }
aurel3247e46612008-09-04 17:06:47 +00006027 tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]);
aurel32f78fb442008-09-04 05:25:47 +00006028 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
6029 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
j_mayer0487d6a2007-03-20 22:11:31 +00006030 gen_op_evsel();
aurel32f78fb442008-09-04 05:25:47 +00006031 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
j_mayer0487d6a2007-03-20 22:11:31 +00006032}
6033
j_mayerc7697e12007-10-26 00:46:07 +00006034GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
j_mayer0487d6a2007-03-20 22:11:31 +00006035{
6036 gen_evsel(ctx);
6037}
j_mayerc7697e12007-10-26 00:46:07 +00006038GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
j_mayer0487d6a2007-03-20 22:11:31 +00006039{
6040 gen_evsel(ctx);
6041}
j_mayerc7697e12007-10-26 00:46:07 +00006042GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
j_mayer0487d6a2007-03-20 22:11:31 +00006043{
6044 gen_evsel(ctx);
6045}
j_mayerc7697e12007-10-26 00:46:07 +00006046GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
j_mayer0487d6a2007-03-20 22:11:31 +00006047{
6048 gen_evsel(ctx);
6049}
6050
6051/* Load and stores */
j_mayer0487d6a2007-03-20 22:11:31 +00006052GEN_SPEOP_LDST(dd, 3);
6053GEN_SPEOP_LDST(dw, 3);
6054GEN_SPEOP_LDST(dh, 3);
6055GEN_SPEOP_LDST(whe, 2);
6056GEN_SPEOP_LD(whou, 2);
6057GEN_SPEOP_LD(whos, 2);
6058GEN_SPEOP_ST(who, 2);
6059
j_mayer0487d6a2007-03-20 22:11:31 +00006060#define _GEN_OP_SPE_STWWE(suffix) \
j_mayerb068d6a2007-10-07 17:13:44 +00006061static always_inline void gen_op_spe_stwwe_##suffix (void) \
j_mayer0487d6a2007-03-20 22:11:31 +00006062{ \
6063 gen_op_srli32_T1_64(); \
6064 gen_op_spe_stwwo_##suffix(); \
6065}
6066#define _GEN_OP_SPE_STWWE_LE(suffix) \
j_mayerb068d6a2007-10-07 17:13:44 +00006067static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
j_mayer0487d6a2007-03-20 22:11:31 +00006068{ \
6069 gen_op_srli32_T1_64(); \
6070 gen_op_spe_stwwo_le_##suffix(); \
6071}
6072#if defined(TARGET_PPC64)
6073#define GEN_OP_SPE_STWWE(suffix) \
6074_GEN_OP_SPE_STWWE(suffix); \
6075_GEN_OP_SPE_STWWE_LE(suffix); \
j_mayerb068d6a2007-10-07 17:13:44 +00006076static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
j_mayer0487d6a2007-03-20 22:11:31 +00006077{ \
6078 gen_op_srli32_T1_64(); \
6079 gen_op_spe_stwwo_64_##suffix(); \
6080} \
j_mayerb068d6a2007-10-07 17:13:44 +00006081static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
j_mayer0487d6a2007-03-20 22:11:31 +00006082{ \
6083 gen_op_srli32_T1_64(); \
6084 gen_op_spe_stwwo_le_64_##suffix(); \
6085}
6086#else
6087#define GEN_OP_SPE_STWWE(suffix) \
6088_GEN_OP_SPE_STWWE(suffix); \
6089_GEN_OP_SPE_STWWE_LE(suffix)
6090#endif
6091#if defined(CONFIG_USER_ONLY)
6092GEN_OP_SPE_STWWE(raw);
6093#else /* defined(CONFIG_USER_ONLY) */
j_mayer0487d6a2007-03-20 22:11:31 +00006094GEN_OP_SPE_STWWE(user);
j_mayer78636672007-11-16 14:11:28 +00006095GEN_OP_SPE_STWWE(kernel);
6096GEN_OP_SPE_STWWE(hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006097#endif /* defined(CONFIG_USER_ONLY) */
6098GEN_SPEOP_ST(wwe, 2);
6099GEN_SPEOP_ST(wwo, 2);
6100
6101#define GEN_SPE_LDSPLAT(name, op, suffix) \
j_mayerb068d6a2007-10-07 17:13:44 +00006102static always_inline void gen_op_spe_l##name##_##suffix (void) \
j_mayer0487d6a2007-03-20 22:11:31 +00006103{ \
6104 gen_op_##op##_##suffix(); \
6105 gen_op_splatw_T1_64(); \
6106}
6107
6108#define GEN_OP_SPE_LHE(suffix) \
j_mayerb068d6a2007-10-07 17:13:44 +00006109static always_inline void gen_op_spe_lhe_##suffix (void) \
j_mayer0487d6a2007-03-20 22:11:31 +00006110{ \
6111 gen_op_spe_lh_##suffix(); \
6112 gen_op_sli16_T1_64(); \
6113}
6114
6115#define GEN_OP_SPE_LHX(suffix) \
j_mayerb068d6a2007-10-07 17:13:44 +00006116static always_inline void gen_op_spe_lhx_##suffix (void) \
j_mayer0487d6a2007-03-20 22:11:31 +00006117{ \
6118 gen_op_spe_lh_##suffix(); \
6119 gen_op_extsh_T1_64(); \
6120}
6121
6122#if defined(CONFIG_USER_ONLY)
6123GEN_OP_SPE_LHE(raw);
6124GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6125GEN_OP_SPE_LHE(le_raw);
6126GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6127GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6128GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6129GEN_OP_SPE_LHX(raw);
6130GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6131GEN_OP_SPE_LHX(le_raw);
6132GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6133#if defined(TARGET_PPC64)
6134GEN_OP_SPE_LHE(64_raw);
6135GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6136GEN_OP_SPE_LHE(le_64_raw);
6137GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6138GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6139GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6140GEN_OP_SPE_LHX(64_raw);
6141GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6142GEN_OP_SPE_LHX(le_64_raw);
6143GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6144#endif
6145#else
j_mayer0487d6a2007-03-20 22:11:31 +00006146GEN_OP_SPE_LHE(user);
j_mayer78636672007-11-16 14:11:28 +00006147GEN_OP_SPE_LHE(kernel);
6148GEN_OP_SPE_LHE(hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006149GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
j_mayer78636672007-11-16 14:11:28 +00006150GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6151GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006152GEN_OP_SPE_LHE(le_user);
j_mayer78636672007-11-16 14:11:28 +00006153GEN_OP_SPE_LHE(le_kernel);
6154GEN_OP_SPE_LHE(le_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006155GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
j_mayer78636672007-11-16 14:11:28 +00006156GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6157GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006158GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
j_mayer78636672007-11-16 14:11:28 +00006159GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6160GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006161GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
j_mayer78636672007-11-16 14:11:28 +00006162GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6163GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006164GEN_OP_SPE_LHX(user);
j_mayer78636672007-11-16 14:11:28 +00006165GEN_OP_SPE_LHX(kernel);
6166GEN_OP_SPE_LHX(hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006167GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
j_mayer78636672007-11-16 14:11:28 +00006168GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6169GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006170GEN_OP_SPE_LHX(le_user);
j_mayer78636672007-11-16 14:11:28 +00006171GEN_OP_SPE_LHX(le_kernel);
6172GEN_OP_SPE_LHX(le_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006173GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
j_mayer78636672007-11-16 14:11:28 +00006174GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6175GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006176#if defined(TARGET_PPC64)
j_mayer0487d6a2007-03-20 22:11:31 +00006177GEN_OP_SPE_LHE(64_user);
j_mayer78636672007-11-16 14:11:28 +00006178GEN_OP_SPE_LHE(64_kernel);
6179GEN_OP_SPE_LHE(64_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006180GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
j_mayer78636672007-11-16 14:11:28 +00006181GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6182GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006183GEN_OP_SPE_LHE(le_64_user);
j_mayer78636672007-11-16 14:11:28 +00006184GEN_OP_SPE_LHE(le_64_kernel);
6185GEN_OP_SPE_LHE(le_64_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006186GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
j_mayer78636672007-11-16 14:11:28 +00006187GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6188GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006189GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
j_mayer78636672007-11-16 14:11:28 +00006190GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6191GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006192GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
j_mayer78636672007-11-16 14:11:28 +00006193GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6194GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006195GEN_OP_SPE_LHX(64_user);
j_mayer78636672007-11-16 14:11:28 +00006196GEN_OP_SPE_LHX(64_kernel);
6197GEN_OP_SPE_LHX(64_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006198GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
j_mayer78636672007-11-16 14:11:28 +00006199GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6200GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006201GEN_OP_SPE_LHX(le_64_user);
j_mayer78636672007-11-16 14:11:28 +00006202GEN_OP_SPE_LHX(le_64_kernel);
6203GEN_OP_SPE_LHX(le_64_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006204GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
j_mayer78636672007-11-16 14:11:28 +00006205GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6206GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
j_mayer0487d6a2007-03-20 22:11:31 +00006207#endif
6208#endif
6209GEN_SPEOP_LD(hhesplat, 1);
6210GEN_SPEOP_LD(hhousplat, 1);
6211GEN_SPEOP_LD(hhossplat, 1);
6212GEN_SPEOP_LD(wwsplat, 2);
6213GEN_SPEOP_LD(whsplat, 2);
6214
6215GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6216GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6217GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6218GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6219GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6220GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6221GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6222GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6223GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6224GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6225GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6226GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6227GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6228GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6229GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6230GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6231GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6232GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6233
6234/* Multiply and add - TODO */
6235#if 0
6236GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6237GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6238GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6239GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6240GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6241GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6242GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6243GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6244GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6245GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6246GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6247GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6248
6249GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6250GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6251GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6252GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6253GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6254GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6255GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6256GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6257GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6258GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6259GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6260GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6261GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6262GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6263
6264GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6265GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6266GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6267GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6268GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6269GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6270
6271GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6272GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6273GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6274GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6275GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6276GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6277GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6278GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6279GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6280GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6281GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6282GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6283
6284GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6285GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6286GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6287GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6288GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6289
6290GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6291GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6292GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6293GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6294GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6295GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6296GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6297GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6298GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6299GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6300GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6301GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6302
6303GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6304GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6305GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6306GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6307GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6308#endif
6309
6310/*** SPE floating-point extension ***/
6311#define GEN_SPEFPUOP_CONV(name) \
j_mayerb068d6a2007-10-07 17:13:44 +00006312static always_inline void gen_##name (DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00006313{ \
aurel32f78fb442008-09-04 05:25:47 +00006314 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
j_mayer0487d6a2007-03-20 22:11:31 +00006315 gen_op_##name(); \
aurel32f78fb442008-09-04 05:25:47 +00006316 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
j_mayer0487d6a2007-03-20 22:11:31 +00006317}
6318
6319/* Single precision floating-point vectors operations */
6320/* Arithmetic */
6321GEN_SPEOP_ARITH2(evfsadd);
6322GEN_SPEOP_ARITH2(evfssub);
6323GEN_SPEOP_ARITH2(evfsmul);
6324GEN_SPEOP_ARITH2(evfsdiv);
6325GEN_SPEOP_ARITH1(evfsabs);
6326GEN_SPEOP_ARITH1(evfsnabs);
6327GEN_SPEOP_ARITH1(evfsneg);
6328/* Conversion */
6329GEN_SPEFPUOP_CONV(evfscfui);
6330GEN_SPEFPUOP_CONV(evfscfsi);
6331GEN_SPEFPUOP_CONV(evfscfuf);
6332GEN_SPEFPUOP_CONV(evfscfsf);
6333GEN_SPEFPUOP_CONV(evfsctui);
6334GEN_SPEFPUOP_CONV(evfsctsi);
6335GEN_SPEFPUOP_CONV(evfsctuf);
6336GEN_SPEFPUOP_CONV(evfsctsf);
6337GEN_SPEFPUOP_CONV(evfsctuiz);
6338GEN_SPEFPUOP_CONV(evfsctsiz);
6339/* Comparison */
6340GEN_SPEOP_COMP(evfscmpgt);
6341GEN_SPEOP_COMP(evfscmplt);
6342GEN_SPEOP_COMP(evfscmpeq);
6343GEN_SPEOP_COMP(evfststgt);
6344GEN_SPEOP_COMP(evfststlt);
6345GEN_SPEOP_COMP(evfststeq);
6346
6347/* Opcodes definitions */
6348GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6349GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6350GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6351GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6352GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6353GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6354GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6355GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6356GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6357GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6358GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6359GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6360GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6361GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6362
6363/* Single precision floating-point operations */
6364/* Arithmetic */
6365GEN_SPEOP_ARITH2(efsadd);
6366GEN_SPEOP_ARITH2(efssub);
6367GEN_SPEOP_ARITH2(efsmul);
6368GEN_SPEOP_ARITH2(efsdiv);
6369GEN_SPEOP_ARITH1(efsabs);
6370GEN_SPEOP_ARITH1(efsnabs);
6371GEN_SPEOP_ARITH1(efsneg);
6372/* Conversion */
6373GEN_SPEFPUOP_CONV(efscfui);
6374GEN_SPEFPUOP_CONV(efscfsi);
6375GEN_SPEFPUOP_CONV(efscfuf);
6376GEN_SPEFPUOP_CONV(efscfsf);
6377GEN_SPEFPUOP_CONV(efsctui);
6378GEN_SPEFPUOP_CONV(efsctsi);
6379GEN_SPEFPUOP_CONV(efsctuf);
6380GEN_SPEFPUOP_CONV(efsctsf);
6381GEN_SPEFPUOP_CONV(efsctuiz);
6382GEN_SPEFPUOP_CONV(efsctsiz);
6383GEN_SPEFPUOP_CONV(efscfd);
6384/* Comparison */
6385GEN_SPEOP_COMP(efscmpgt);
6386GEN_SPEOP_COMP(efscmplt);
6387GEN_SPEOP_COMP(efscmpeq);
6388GEN_SPEOP_COMP(efststgt);
6389GEN_SPEOP_COMP(efststlt);
6390GEN_SPEOP_COMP(efststeq);
6391
6392/* Opcodes definitions */
j_mayer05332d72007-11-17 22:26:51 +00006393GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
j_mayer0487d6a2007-03-20 22:11:31 +00006394GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6395GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6396GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6397GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6398GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6399GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6400GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6401GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6402GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
ths9ceb2a72008-08-13 11:30:10 +00006403GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6404GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
j_mayer0487d6a2007-03-20 22:11:31 +00006405GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6406GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6407
6408/* Double precision floating-point operations */
6409/* Arithmetic */
6410GEN_SPEOP_ARITH2(efdadd);
6411GEN_SPEOP_ARITH2(efdsub);
6412GEN_SPEOP_ARITH2(efdmul);
6413GEN_SPEOP_ARITH2(efddiv);
6414GEN_SPEOP_ARITH1(efdabs);
6415GEN_SPEOP_ARITH1(efdnabs);
6416GEN_SPEOP_ARITH1(efdneg);
6417/* Conversion */
6418
6419GEN_SPEFPUOP_CONV(efdcfui);
6420GEN_SPEFPUOP_CONV(efdcfsi);
6421GEN_SPEFPUOP_CONV(efdcfuf);
6422GEN_SPEFPUOP_CONV(efdcfsf);
6423GEN_SPEFPUOP_CONV(efdctui);
6424GEN_SPEFPUOP_CONV(efdctsi);
6425GEN_SPEFPUOP_CONV(efdctuf);
6426GEN_SPEFPUOP_CONV(efdctsf);
6427GEN_SPEFPUOP_CONV(efdctuiz);
6428GEN_SPEFPUOP_CONV(efdctsiz);
6429GEN_SPEFPUOP_CONV(efdcfs);
6430GEN_SPEFPUOP_CONV(efdcfuid);
6431GEN_SPEFPUOP_CONV(efdcfsid);
6432GEN_SPEFPUOP_CONV(efdctuidz);
6433GEN_SPEFPUOP_CONV(efdctsidz);
6434/* Comparison */
6435GEN_SPEOP_COMP(efdcmpgt);
6436GEN_SPEOP_COMP(efdcmplt);
6437GEN_SPEOP_COMP(efdcmpeq);
6438GEN_SPEOP_COMP(efdtstgt);
6439GEN_SPEOP_COMP(efdtstlt);
6440GEN_SPEOP_COMP(efdtsteq);
6441
6442/* Opcodes definitions */
6443GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6444GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6445GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6446GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6447GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6448GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6449GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6450GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6451GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6452GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6453GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6454GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6455GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6456GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6457GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6458GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
j_mayer0487d6a2007-03-20 22:11:31 +00006459
bellard79aceca2003-11-23 14:55:54 +00006460/* End opcode list */
6461GEN_OPCODE_MARK(end);
6462
bellard3fc6c082005-07-02 20:59:34 +00006463#include "translate_init.c"
j_mayer0411a972007-10-25 21:35:50 +00006464#include "helper_regs.h"
bellard79aceca2003-11-23 14:55:54 +00006465
bellard9a64fbe2004-01-04 22:58:38 +00006466/*****************************************************************************/
bellard3fc6c082005-07-02 20:59:34 +00006467/* Misc PowerPC helpers */
j_mayer36081602007-09-17 08:21:54 +00006468void cpu_dump_state (CPUState *env, FILE *f,
6469 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6470 int flags)
bellard79aceca2003-11-23 14:55:54 +00006471{
bellard3fc6c082005-07-02 20:59:34 +00006472#define RGPL 4
6473#define RFPL 4
bellard3fc6c082005-07-02 20:59:34 +00006474
bellard79aceca2003-11-23 14:55:54 +00006475 int i;
6476
j_mayer077fc202007-11-04 01:57:29 +00006477 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
aurel323d7b4172008-10-21 11:28:46 +00006478 env->nip, env->lr, env->ctr, env->xer);
j_mayer6b542af2007-11-24 02:03:55 +00006479 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6480 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
j_mayerd9bce9d2007-03-17 14:02:15 +00006481#if !defined(NO_TIMER_DUMP)
j_mayer077fc202007-11-04 01:57:29 +00006482 cpu_fprintf(f, "TB %08x %08x "
j_mayer76a66252007-03-07 08:32:30 +00006483#if !defined(CONFIG_USER_ONLY)
6484 "DECR %08x"
6485#endif
6486 "\n",
j_mayer077fc202007-11-04 01:57:29 +00006487 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
j_mayer76a66252007-03-07 08:32:30 +00006488#if !defined(CONFIG_USER_ONLY)
6489 , cpu_ppc_load_decr(env)
6490#endif
6491 );
j_mayer077fc202007-11-04 01:57:29 +00006492#endif
j_mayer76a66252007-03-07 08:32:30 +00006493 for (i = 0; i < 32; i++) {
bellard3fc6c082005-07-02 20:59:34 +00006494 if ((i & (RGPL - 1)) == 0)
6495 cpu_fprintf(f, "GPR%02d", i);
j_mayer6b542af2007-11-24 02:03:55 +00006496 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
bellard3fc6c082005-07-02 20:59:34 +00006497 if ((i & (RGPL - 1)) == (RGPL - 1))
bellard7fe48482004-10-09 18:08:01 +00006498 cpu_fprintf(f, "\n");
j_mayer76a66252007-03-07 08:32:30 +00006499 }
bellard3fc6c082005-07-02 20:59:34 +00006500 cpu_fprintf(f, "CR ");
j_mayer76a66252007-03-07 08:32:30 +00006501 for (i = 0; i < 8; i++)
bellard7fe48482004-10-09 18:08:01 +00006502 cpu_fprintf(f, "%01x", env->crf[i]);
6503 cpu_fprintf(f, " [");
j_mayer76a66252007-03-07 08:32:30 +00006504 for (i = 0; i < 8; i++) {
6505 char a = '-';
6506 if (env->crf[i] & 0x08)
6507 a = 'L';
6508 else if (env->crf[i] & 0x04)
6509 a = 'G';
6510 else if (env->crf[i] & 0x02)
6511 a = 'E';
bellard7fe48482004-10-09 18:08:01 +00006512 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
j_mayer76a66252007-03-07 08:32:30 +00006513 }
j_mayer6b542af2007-11-24 02:03:55 +00006514 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
bellard3fc6c082005-07-02 20:59:34 +00006515 for (i = 0; i < 32; i++) {
6516 if ((i & (RFPL - 1)) == 0)
6517 cpu_fprintf(f, "FPR%02d", i);
bellard26a76462006-06-25 18:15:32 +00006518 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
bellard3fc6c082005-07-02 20:59:34 +00006519 if ((i & (RFPL - 1)) == (RFPL - 1))
bellard7fe48482004-10-09 18:08:01 +00006520 cpu_fprintf(f, "\n");
bellard79aceca2003-11-23 14:55:54 +00006521 }
j_mayerf2e63a42007-10-07 15:43:50 +00006522#if !defined(CONFIG_USER_ONLY)
j_mayer6b542af2007-11-24 02:03:55 +00006523 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
bellard3fc6c082005-07-02 20:59:34 +00006524 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
j_mayerf2e63a42007-10-07 15:43:50 +00006525#endif
bellard79aceca2003-11-23 14:55:54 +00006526
bellard3fc6c082005-07-02 20:59:34 +00006527#undef RGPL
6528#undef RFPL
bellard79aceca2003-11-23 14:55:54 +00006529}
6530
j_mayer76a66252007-03-07 08:32:30 +00006531void cpu_dump_statistics (CPUState *env, FILE*f,
6532 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6533 int flags)
6534{
6535#if defined(DO_PPC_STATISTICS)
6536 opc_handler_t **t1, **t2, **t3, *handler;
6537 int op1, op2, op3;
6538
6539 t1 = env->opcodes;
6540 for (op1 = 0; op1 < 64; op1++) {
6541 handler = t1[op1];
6542 if (is_indirect_opcode(handler)) {
6543 t2 = ind_table(handler);
6544 for (op2 = 0; op2 < 32; op2++) {
6545 handler = t2[op2];
6546 if (is_indirect_opcode(handler)) {
6547 t3 = ind_table(handler);
6548 for (op3 = 0; op3 < 32; op3++) {
6549 handler = t3[op3];
6550 if (handler->count == 0)
6551 continue;
6552 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6553 "%016llx %lld\n",
6554 op1, op2, op3, op1, (op3 << 5) | op2,
6555 handler->oname,
6556 handler->count, handler->count);
6557 }
6558 } else {
6559 if (handler->count == 0)
6560 continue;
6561 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6562 "%016llx %lld\n",
6563 op1, op2, op1, op2, handler->oname,
6564 handler->count, handler->count);
6565 }
6566 }
6567 } else {
6568 if (handler->count == 0)
6569 continue;
6570 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6571 op1, op1, handler->oname,
6572 handler->count, handler->count);
6573 }
6574 }
6575#endif
6576}
6577
bellard9a64fbe2004-01-04 22:58:38 +00006578/*****************************************************************************/
ths2cfc5f12008-07-18 18:01:29 +00006579static always_inline void gen_intermediate_code_internal (CPUState *env,
6580 TranslationBlock *tb,
6581 int search_pc)
bellard79aceca2003-11-23 14:55:54 +00006582{
bellard9fddaa02004-05-21 12:59:32 +00006583 DisasContext ctx, *ctxp = &ctx;
bellard79aceca2003-11-23 14:55:54 +00006584 opc_handler_t **table, *handler;
bellard0fa85d42005-01-03 23:43:32 +00006585 target_ulong pc_start;
bellard79aceca2003-11-23 14:55:54 +00006586 uint16_t *gen_opc_end;
j_mayer056401e2007-11-04 02:55:33 +00006587 int supervisor, little_endian;
bellard79aceca2003-11-23 14:55:54 +00006588 int j, lj = -1;
pbrook2e70f6e2008-06-29 01:03:05 +00006589 int num_insns;
6590 int max_insns;
bellard79aceca2003-11-23 14:55:54 +00006591
6592 pc_start = tb->pc;
bellard79aceca2003-11-23 14:55:54 +00006593 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
j_mayer7c580442007-10-27 17:54:30 +00006594#if defined(OPTIMIZE_FPRF_UPDATE)
6595 gen_fprf_ptr = gen_fprf_buf;
6596#endif
bellard046d6672004-04-25 21:15:35 +00006597 ctx.nip = pc_start;
bellard79aceca2003-11-23 14:55:54 +00006598 ctx.tb = tb;
j_mayere1833e12007-09-29 13:06:16 +00006599 ctx.exception = POWERPC_EXCP_NONE;
bellard3fc6c082005-07-02 20:59:34 +00006600 ctx.spr_cb = env->spr_cb;
j_mayer6ebbf392007-10-14 07:07:08 +00006601 supervisor = env->mmu_idx;
6602#if !defined(CONFIG_USER_ONLY)
j_mayer28570682007-10-02 10:11:50 +00006603 ctx.supervisor = supervisor;
j_mayerd9bce9d2007-03-17 14:02:15 +00006604#endif
j_mayer056401e2007-11-04 02:55:33 +00006605 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
j_mayerd9bce9d2007-03-17 14:02:15 +00006606#if defined(TARGET_PPC64)
6607 ctx.sf_mode = msr_sf;
j_mayer056401e2007-11-04 02:55:33 +00006608 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
j_mayer28570682007-10-02 10:11:50 +00006609#else
j_mayer056401e2007-11-04 02:55:33 +00006610 ctx.mem_idx = (supervisor << 1) | little_endian;
bellard9a64fbe2004-01-04 22:58:38 +00006611#endif
j_mayerd63001d2007-10-04 00:51:58 +00006612 ctx.dcache_line_size = env->dcache_line_size;
bellard3cc62372005-02-15 23:06:19 +00006613 ctx.fpu_enabled = msr_fp;
j_mayera9d9eb82007-10-07 18:19:26 +00006614 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
j_mayerd26bfc92007-10-07 14:41:00 +00006615 ctx.spe_enabled = msr_spe;
6616 else
6617 ctx.spe_enabled = 0;
j_mayera9d9eb82007-10-07 18:19:26 +00006618 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6619 ctx.altivec_enabled = msr_vr;
6620 else
6621 ctx.altivec_enabled = 0;
j_mayerd26bfc92007-10-07 14:41:00 +00006622 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
aurel328cbcb4f2008-05-10 23:28:14 +00006623 ctx.singlestep_enabled = CPU_SINGLE_STEP;
j_mayerd26bfc92007-10-07 14:41:00 +00006624 else
aurel328cbcb4f2008-05-10 23:28:14 +00006625 ctx.singlestep_enabled = 0;
j_mayerd26bfc92007-10-07 14:41:00 +00006626 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
aurel328cbcb4f2008-05-10 23:28:14 +00006627 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6628 if (unlikely(env->singlestep_enabled))
6629 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
bellard3fc6c082005-07-02 20:59:34 +00006630#if defined (DO_SINGLE_STEP) && 0
bellard9a64fbe2004-01-04 22:58:38 +00006631 /* Single step trace mode */
6632 msr_se = 1;
6633#endif
pbrook2e70f6e2008-06-29 01:03:05 +00006634 num_insns = 0;
6635 max_insns = tb->cflags & CF_COUNT_MASK;
6636 if (max_insns == 0)
6637 max_insns = CF_COUNT_MASK;
6638
6639 gen_icount_start();
bellard9a64fbe2004-01-04 22:58:38 +00006640 /* Set env in case of segfault during code fetch */
j_mayere1833e12007-09-29 13:06:16 +00006641 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
j_mayer76a66252007-03-07 08:32:30 +00006642 if (unlikely(env->nb_breakpoints > 0)) {
6643 for (j = 0; j < env->nb_breakpoints; j++) {
bellardea4e7542006-05-22 21:50:20 +00006644 if (env->breakpoints[j] == ctx.nip) {
ths5fafdf22007-09-16 21:08:06 +00006645 gen_update_nip(&ctx, ctx.nip);
bellardea4e7542006-05-22 21:50:20 +00006646 gen_op_debug();
6647 break;
6648 }
6649 }
6650 }
j_mayer76a66252007-03-07 08:32:30 +00006651 if (unlikely(search_pc)) {
bellard79aceca2003-11-23 14:55:54 +00006652 j = gen_opc_ptr - gen_opc_buf;
6653 if (lj < j) {
6654 lj++;
6655 while (lj < j)
6656 gen_opc_instr_start[lj++] = 0;
bellard046d6672004-04-25 21:15:35 +00006657 gen_opc_pc[lj] = ctx.nip;
bellard79aceca2003-11-23 14:55:54 +00006658 gen_opc_instr_start[lj] = 1;
pbrook2e70f6e2008-06-29 01:03:05 +00006659 gen_opc_icount[lj] = num_insns;
bellard79aceca2003-11-23 14:55:54 +00006660 }
6661 }
bellard9fddaa02004-05-21 12:59:32 +00006662#if defined PPC_DEBUG_DISAS
6663 if (loglevel & CPU_LOG_TB_IN_ASM) {
bellard79aceca2003-11-23 14:55:54 +00006664 fprintf(logfile, "----------------\n");
j_mayer1b9eb032007-03-23 09:40:22 +00006665 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
j_mayer0411a972007-10-25 21:35:50 +00006666 ctx.nip, supervisor, (int)msr_ir);
bellard9a64fbe2004-01-04 22:58:38 +00006667 }
6668#endif
pbrook2e70f6e2008-06-29 01:03:05 +00006669 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6670 gen_io_start();
j_mayer056401e2007-11-04 02:55:33 +00006671 if (unlikely(little_endian)) {
6672 ctx.opcode = bswap32(ldl_code(ctx.nip));
6673 } else {
6674 ctx.opcode = ldl_code(ctx.nip);
bellard111bfab2005-04-23 18:16:07 +00006675 }
bellard9fddaa02004-05-21 12:59:32 +00006676#if defined PPC_DEBUG_DISAS
6677 if (loglevel & CPU_LOG_TB_IN_ASM) {
bellard111bfab2005-04-23 18:16:07 +00006678 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
bellard9a64fbe2004-01-04 22:58:38 +00006679 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
j_mayer056401e2007-11-04 02:55:33 +00006680 opc3(ctx.opcode), little_endian ? "little" : "big");
bellard79aceca2003-11-23 14:55:54 +00006681 }
6682#endif
bellard046d6672004-04-25 21:15:35 +00006683 ctx.nip += 4;
bellard3fc6c082005-07-02 20:59:34 +00006684 table = env->opcodes;
pbrook2e70f6e2008-06-29 01:03:05 +00006685 num_insns++;
bellard79aceca2003-11-23 14:55:54 +00006686 handler = table[opc1(ctx.opcode)];
6687 if (is_indirect_opcode(handler)) {
6688 table = ind_table(handler);
6689 handler = table[opc2(ctx.opcode)];
6690 if (is_indirect_opcode(handler)) {
6691 table = ind_table(handler);
6692 handler = table[opc3(ctx.opcode)];
6693 }
6694 }
6695 /* Is opcode *REALLY* valid ? */
j_mayer76a66252007-03-07 08:32:30 +00006696 if (unlikely(handler->handler == &gen_invalid)) {
j_mayer4a057712007-04-19 08:42:21 +00006697 if (loglevel != 0) {
j_mayer76a66252007-03-07 08:32:30 +00006698 fprintf(logfile, "invalid/unsupported opcode: "
j_mayer6b542af2007-11-24 02:03:55 +00006699 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
j_mayer76a66252007-03-07 08:32:30 +00006700 opc1(ctx.opcode), opc2(ctx.opcode),
j_mayer0411a972007-10-25 21:35:50 +00006701 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
bellard4b3686f2004-05-23 22:18:12 +00006702 } else {
6703 printf("invalid/unsupported opcode: "
j_mayer6b542af2007-11-24 02:03:55 +00006704 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
bellard4b3686f2004-05-23 22:18:12 +00006705 opc1(ctx.opcode), opc2(ctx.opcode),
j_mayer0411a972007-10-25 21:35:50 +00006706 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
bellard4b3686f2004-05-23 22:18:12 +00006707 }
j_mayer76a66252007-03-07 08:32:30 +00006708 } else {
6709 if (unlikely((ctx.opcode & handler->inval) != 0)) {
j_mayer4a057712007-04-19 08:42:21 +00006710 if (loglevel != 0) {
bellard79aceca2003-11-23 14:55:54 +00006711 fprintf(logfile, "invalid bits: %08x for opcode: "
j_mayer6b542af2007-11-24 02:03:55 +00006712 "%02x - %02x - %02x (%08x) " ADDRX "\n",
bellard79aceca2003-11-23 14:55:54 +00006713 ctx.opcode & handler->inval, opc1(ctx.opcode),
6714 opc2(ctx.opcode), opc3(ctx.opcode),
bellard046d6672004-04-25 21:15:35 +00006715 ctx.opcode, ctx.nip - 4);
bellard9a64fbe2004-01-04 22:58:38 +00006716 } else {
6717 printf("invalid bits: %08x for opcode: "
j_mayer6b542af2007-11-24 02:03:55 +00006718 "%02x - %02x - %02x (%08x) " ADDRX "\n",
j_mayer76a66252007-03-07 08:32:30 +00006719 ctx.opcode & handler->inval, opc1(ctx.opcode),
6720 opc2(ctx.opcode), opc3(ctx.opcode),
bellard046d6672004-04-25 21:15:35 +00006721 ctx.opcode, ctx.nip - 4);
j_mayer76a66252007-03-07 08:32:30 +00006722 }
j_mayere1833e12007-09-29 13:06:16 +00006723 GEN_EXCP_INVAL(ctxp);
bellard4b3686f2004-05-23 22:18:12 +00006724 break;
bellard9a64fbe2004-01-04 22:58:38 +00006725 }
bellard79aceca2003-11-23 14:55:54 +00006726 }
bellard4b3686f2004-05-23 22:18:12 +00006727 (*(handler->handler))(&ctx);
j_mayer76a66252007-03-07 08:32:30 +00006728#if defined(DO_PPC_STATISTICS)
6729 handler->count++;
6730#endif
bellard9a64fbe2004-01-04 22:58:38 +00006731 /* Check trace mode exceptions */
aurel328cbcb4f2008-05-10 23:28:14 +00006732 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6733 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6734 ctx.exception != POWERPC_SYSCALL &&
6735 ctx.exception != POWERPC_EXCP_TRAP &&
6736 ctx.exception != POWERPC_EXCP_BRANCH)) {
j_mayerd26bfc92007-10-07 14:41:00 +00006737 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6738 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
pbrook2e70f6e2008-06-29 01:03:05 +00006739 (env->singlestep_enabled) ||
6740 num_insns >= max_insns)) {
j_mayerd26bfc92007-10-07 14:41:00 +00006741 /* if we reach a page boundary or are single stepping, stop
6742 * generation
6743 */
bellard8dd49832005-06-04 22:22:27 +00006744 break;
j_mayer76a66252007-03-07 08:32:30 +00006745 }
bellard3fc6c082005-07-02 20:59:34 +00006746#if defined (DO_SINGLE_STEP)
6747 break;
6748#endif
6749 }
pbrook2e70f6e2008-06-29 01:03:05 +00006750 if (tb->cflags & CF_LAST_IO)
6751 gen_io_end();
j_mayere1833e12007-09-29 13:06:16 +00006752 if (ctx.exception == POWERPC_EXCP_NONE) {
bellardc1942362005-11-20 10:31:08 +00006753 gen_goto_tb(&ctx, 0, ctx.nip);
j_mayere1833e12007-09-29 13:06:16 +00006754 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
aurel328cbcb4f2008-05-10 23:28:14 +00006755 if (unlikely(env->singlestep_enabled)) {
6756 gen_update_nip(&ctx, ctx.nip);
6757 gen_op_debug();
6758 }
j_mayer76a66252007-03-07 08:32:30 +00006759 /* Generate the return instruction */
bellard57fec1f2008-02-01 10:50:11 +00006760 tcg_gen_exit_tb(0);
bellard9a64fbe2004-01-04 22:58:38 +00006761 }
pbrook2e70f6e2008-06-29 01:03:05 +00006762 gen_icount_end(tb, num_insns);
bellard79aceca2003-11-23 14:55:54 +00006763 *gen_opc_ptr = INDEX_op_end;
j_mayer76a66252007-03-07 08:32:30 +00006764 if (unlikely(search_pc)) {
bellard9a64fbe2004-01-04 22:58:38 +00006765 j = gen_opc_ptr - gen_opc_buf;
6766 lj++;
6767 while (lj <= j)
6768 gen_opc_instr_start[lj++] = 0;
bellard9a64fbe2004-01-04 22:58:38 +00006769 } else {
bellard046d6672004-04-25 21:15:35 +00006770 tb->size = ctx.nip - pc_start;
pbrook2e70f6e2008-06-29 01:03:05 +00006771 tb->icount = num_insns;
bellard9a64fbe2004-01-04 22:58:38 +00006772 }
j_mayerd9bce9d2007-03-17 14:02:15 +00006773#if defined(DEBUG_DISAS)
bellard9fddaa02004-05-21 12:59:32 +00006774 if (loglevel & CPU_LOG_TB_CPU) {
bellard9a64fbe2004-01-04 22:58:38 +00006775 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
bellard7fe48482004-10-09 18:08:01 +00006776 cpu_dump_state(env, logfile, fprintf, 0);
bellard9fddaa02004-05-21 12:59:32 +00006777 }
6778 if (loglevel & CPU_LOG_TB_IN_ASM) {
j_mayer76a66252007-03-07 08:32:30 +00006779 int flags;
j_mayer237c0af2007-09-29 12:01:46 +00006780 flags = env->bfd_mach;
j_mayer056401e2007-11-04 02:55:33 +00006781 flags |= little_endian << 16;
bellard0fa85d42005-01-03 23:43:32 +00006782 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
j_mayer76a66252007-03-07 08:32:30 +00006783 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
bellard79aceca2003-11-23 14:55:54 +00006784 fprintf(logfile, "\n");
bellard9fddaa02004-05-21 12:59:32 +00006785 }
bellard79aceca2003-11-23 14:55:54 +00006786#endif
bellard79aceca2003-11-23 14:55:54 +00006787}
6788
ths2cfc5f12008-07-18 18:01:29 +00006789void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
bellard79aceca2003-11-23 14:55:54 +00006790{
ths2cfc5f12008-07-18 18:01:29 +00006791 gen_intermediate_code_internal(env, tb, 0);
bellard79aceca2003-11-23 14:55:54 +00006792}
6793
ths2cfc5f12008-07-18 18:01:29 +00006794void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
bellard79aceca2003-11-23 14:55:54 +00006795{
ths2cfc5f12008-07-18 18:01:29 +00006796 gen_intermediate_code_internal(env, tb, 1);
bellard79aceca2003-11-23 14:55:54 +00006797}
aurel32d2856f12008-04-28 00:32:32 +00006798
6799void gen_pc_load(CPUState *env, TranslationBlock *tb,
6800 unsigned long searched_pc, int pc_pos, void *puc)
6801{
6802 int type, c;
6803 /* for PPC, we need to look at the micro operation to get the
6804 * access type */
6805 env->nip = gen_opc_pc[pc_pos];
6806 c = gen_opc_buf[pc_pos];
6807 switch(c) {
6808#if defined(CONFIG_USER_ONLY)
6809#define CASE3(op)\
6810 case INDEX_op_ ## op ## _raw
6811#else
6812#define CASE3(op)\
6813 case INDEX_op_ ## op ## _user:\
6814 case INDEX_op_ ## op ## _kernel:\
6815 case INDEX_op_ ## op ## _hypv
6816#endif
6817
6818 CASE3(stfd):
6819 CASE3(stfs):
6820 CASE3(lfd):
6821 CASE3(lfs):
6822 type = ACCESS_FLOAT;
6823 break;
6824 CASE3(lwarx):
6825 type = ACCESS_RES;
6826 break;
6827 CASE3(stwcx):
6828 type = ACCESS_RES;
6829 break;
6830 CASE3(eciwx):
6831 CASE3(ecowx):
6832 type = ACCESS_EXT;
6833 break;
6834 default:
6835 type = ACCESS_INT;
6836 break;
6837 }
6838 env->access_type = type;
6839}