bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1 | /* |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 2 | * PowerPC emulation for qemu: main translation routines. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
bellard | c6a1c22 | 2004-05-20 13:10:49 +0000 | [diff] [blame] | 20 | #include <stdarg.h> |
| 21 | #include <stdlib.h> |
| 22 | #include <stdio.h> |
| 23 | #include <string.h> |
| 24 | #include <inttypes.h> |
| 25 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 26 | #include "cpu.h" |
bellard | c6a1c22 | 2004-05-20 13:10:49 +0000 | [diff] [blame] | 27 | #include "exec-all.h" |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 28 | #include "disas.h" |
aurel32 | f10dc08 | 2008-08-28 21:01:45 +0000 | [diff] [blame] | 29 | #include "helper.h" |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 30 | #include "tcg-op.h" |
aurel32 | ca10f86 | 2008-04-11 21:35:42 +0000 | [diff] [blame] | 31 | #include "qemu-common.h" |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 32 | |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 33 | #define CPU_SINGLE_STEP 0x1 |
| 34 | #define CPU_BRANCH_STEP 0x2 |
| 35 | #define GDBSTUB_SINGLE_STEP 0x4 |
| 36 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 37 | /* Include definitions for instructions classes and implementations flags */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 38 | //#define DO_SINGLE_STEP |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 39 | //#define PPC_DEBUG_DISAS |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 40 | //#define DO_PPC_STATISTICS |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 41 | //#define OPTIMIZE_FPRF_UPDATE |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 42 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 43 | /*****************************************************************************/ |
| 44 | /* Code translation helpers */ |
bellard | c53be33 | 2005-10-30 21:39:19 +0000 | [diff] [blame] | 45 | |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 46 | /* global register indexes */ |
| 47 | static TCGv cpu_env; |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 48 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 49 | #if !defined(TARGET_PPC64) |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 50 | + 10*4 + 22*5 /* SPE GPRh */ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 51 | #endif |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 52 | + 10*4 + 22*5 /* FPR */ |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 53 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
| 54 | + 8*5 /* CRF */]; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 55 | static TCGv cpu_gpr[32]; |
| 56 | #if !defined(TARGET_PPC64) |
| 57 | static TCGv cpu_gprh[32]; |
| 58 | #endif |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 59 | static TCGv cpu_fpr[32]; |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 60 | static TCGv cpu_avrh[32], cpu_avrl[32]; |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 61 | static TCGv cpu_crf[8]; |
aurel32 | bd568f1 | 2008-09-04 18:06:03 +0000 | [diff] [blame] | 62 | static TCGv cpu_nip; |
aurel32 | cfdcd37 | 2008-09-14 18:30:23 +0000 | [diff] [blame] | 63 | static TCGv cpu_ctr; |
| 64 | static TCGv cpu_lr; |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 65 | static TCGv cpu_xer; |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 66 | static TCGv cpu_fpscr; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 67 | |
| 68 | /* dyngen register indexes */ |
| 69 | static TCGv cpu_T[3]; |
| 70 | #if defined(TARGET_PPC64) |
| 71 | #define cpu_T64 cpu_T |
| 72 | #else |
| 73 | static TCGv cpu_T64[3]; |
| 74 | #endif |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 75 | static TCGv cpu_FT[3]; |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 76 | static TCGv cpu_AVRh[3], cpu_AVRl[3]; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 77 | |
| 78 | #include "gen-icount.h" |
| 79 | |
| 80 | void ppc_translate_init(void) |
| 81 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 82 | int i; |
| 83 | char* p; |
pbrook | b2437bf | 2008-06-29 12:29:56 +0000 | [diff] [blame] | 84 | static int done_init = 0; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 85 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 86 | if (done_init) |
| 87 | return; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 88 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 89 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); |
aurel32 | 1c73fe5 | 2008-08-28 21:01:36 +0000 | [diff] [blame] | 90 | #if TARGET_LONG_BITS > HOST_LONG_BITS |
| 91 | cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, |
| 92 | TCG_AREG0, offsetof(CPUState, t0), "T0"); |
| 93 | cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL, |
| 94 | TCG_AREG0, offsetof(CPUState, t1), "T1"); |
| 95 | cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL, |
| 96 | TCG_AREG0, offsetof(CPUState, t2), "T2"); |
| 97 | #else |
| 98 | cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); |
| 99 | cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); |
| 100 | cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); |
| 101 | #endif |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 102 | #if !defined(TARGET_PPC64) |
| 103 | cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64, |
aurel32 | bd7d9a6 | 2008-09-04 05:26:09 +0000 | [diff] [blame] | 104 | TCG_AREG0, offsetof(CPUState, t0_64), |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 105 | "T0_64"); |
| 106 | cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64, |
aurel32 | bd7d9a6 | 2008-09-04 05:26:09 +0000 | [diff] [blame] | 107 | TCG_AREG0, offsetof(CPUState, t1_64), |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 108 | "T1_64"); |
| 109 | cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64, |
aurel32 | bd7d9a6 | 2008-09-04 05:26:09 +0000 | [diff] [blame] | 110 | TCG_AREG0, offsetof(CPUState, t2_64), |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 111 | "T2_64"); |
| 112 | #endif |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 113 | |
| 114 | cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 115 | offsetof(CPUState, ft0), "FT0"); |
| 116 | cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 117 | offsetof(CPUState, ft1), "FT1"); |
| 118 | cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 119 | offsetof(CPUState, ft2), "FT2"); |
| 120 | |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 121 | cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 122 | offsetof(CPUState, avr0.u64[0]), "AVR0H"); |
| 123 | cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 124 | offsetof(CPUState, avr0.u64[1]), "AVR0L"); |
| 125 | cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 126 | offsetof(CPUState, avr1.u64[0]), "AVR1H"); |
| 127 | cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 128 | offsetof(CPUState, avr1.u64[1]), "AVR1L"); |
| 129 | cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 130 | offsetof(CPUState, avr2.u64[0]), "AVR2H"); |
| 131 | cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 132 | offsetof(CPUState, avr2.u64[1]), "AVR2L"); |
| 133 | |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 134 | p = cpu_reg_names; |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 135 | |
| 136 | for (i = 0; i < 8; i++) { |
| 137 | sprintf(p, "crf%d", i); |
| 138 | cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
| 139 | offsetof(CPUState, crf[i]), p); |
| 140 | p += 5; |
| 141 | } |
| 142 | |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 143 | for (i = 0; i < 32; i++) { |
| 144 | sprintf(p, "r%d", i); |
| 145 | cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
| 146 | offsetof(CPUState, gpr[i]), p); |
| 147 | p += (i < 10) ? 3 : 4; |
| 148 | #if !defined(TARGET_PPC64) |
| 149 | sprintf(p, "r%dH", i); |
| 150 | cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
| 151 | offsetof(CPUState, gprh[i]), p); |
| 152 | p += (i < 10) ? 4 : 5; |
| 153 | #endif |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 154 | |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 155 | sprintf(p, "fp%d", i); |
| 156 | cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 157 | offsetof(CPUState, fpr[i]), p); |
aurel32 | ec1ac72 | 2008-09-04 15:49:12 +0000 | [diff] [blame] | 158 | p += (i < 10) ? 4 : 5; |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 159 | |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 160 | sprintf(p, "avr%dH", i); |
| 161 | cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 162 | offsetof(CPUState, avr[i].u64[0]), p); |
| 163 | p += (i < 10) ? 6 : 7; |
aurel32 | ec1ac72 | 2008-09-04 15:49:12 +0000 | [diff] [blame] | 164 | |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 165 | sprintf(p, "avr%dL", i); |
| 166 | cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 167 | offsetof(CPUState, avr[i].u64[1]), p); |
| 168 | p += (i < 10) ? 6 : 7; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 169 | } |
aurel32 | f10dc08 | 2008-08-28 21:01:45 +0000 | [diff] [blame] | 170 | |
aurel32 | bd568f1 | 2008-09-04 18:06:03 +0000 | [diff] [blame] | 171 | cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
| 172 | offsetof(CPUState, nip), "nip"); |
| 173 | |
aurel32 | cfdcd37 | 2008-09-14 18:30:23 +0000 | [diff] [blame] | 174 | cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
| 175 | offsetof(CPUState, ctr), "ctr"); |
| 176 | |
| 177 | cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
| 178 | offsetof(CPUState, lr), "lr"); |
| 179 | |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 180 | cpu_xer = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
| 181 | offsetof(CPUState, xer), "xer"); |
| 182 | |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 183 | cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
| 184 | offsetof(CPUState, fpscr), "fpscr"); |
| 185 | |
aurel32 | f10dc08 | 2008-08-28 21:01:45 +0000 | [diff] [blame] | 186 | /* register helpers */ |
| 187 | #undef DEF_HELPER |
| 188 | #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
| 189 | #include "helper.h" |
| 190 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 191 | done_init = 1; |
| 192 | } |
| 193 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 194 | #if defined(OPTIMIZE_FPRF_UPDATE) |
| 195 | static uint16_t *gen_fprf_buf[OPC_BUF_SIZE]; |
| 196 | static uint16_t **gen_fprf_ptr; |
| 197 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 198 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 199 | /* internal defines */ |
| 200 | typedef struct DisasContext { |
| 201 | struct TranslationBlock *tb; |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 202 | target_ulong nip; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 203 | uint32_t opcode; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 204 | uint32_t exception; |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 205 | /* Routine used to access memory */ |
| 206 | int mem_idx; |
| 207 | /* Translation flags */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 208 | #if !defined(CONFIG_USER_ONLY) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 209 | int supervisor; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 210 | #endif |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 211 | #if defined(TARGET_PPC64) |
| 212 | int sf_mode; |
| 213 | #endif |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 214 | int fpu_enabled; |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 215 | int altivec_enabled; |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 216 | int spe_enabled; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 217 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
bellard | ea4e754 | 2006-05-22 21:50:20 +0000 | [diff] [blame] | 218 | int singlestep_enabled; |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 219 | int dcache_line_size; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 220 | } DisasContext; |
| 221 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 222 | struct opc_handler_t { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 223 | /* invalid bits */ |
| 224 | uint32_t inval; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 225 | /* instruction type */ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 226 | uint64_t type; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 227 | /* handler */ |
| 228 | void (*handler)(DisasContext *ctx); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 229 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 230 | const char *oname; |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 231 | #endif |
| 232 | #if defined(DO_PPC_STATISTICS) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 233 | uint64_t count; |
| 234 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 235 | }; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 236 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 237 | static always_inline void gen_reset_fpstatus (void) |
| 238 | { |
| 239 | #ifdef CONFIG_SOFTFLOAT |
| 240 | gen_op_reset_fpstatus(); |
| 241 | #endif |
| 242 | } |
| 243 | |
| 244 | static always_inline void gen_compute_fprf (int set_fprf, int set_rc) |
| 245 | { |
| 246 | if (set_fprf != 0) { |
| 247 | /* This case might be optimized later */ |
| 248 | #if defined(OPTIMIZE_FPRF_UPDATE) |
| 249 | *gen_fprf_ptr++ = gen_opc_ptr; |
| 250 | #endif |
| 251 | gen_op_compute_fprf(1); |
| 252 | if (unlikely(set_rc)) |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 253 | tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 254 | gen_op_float_check_status(); |
| 255 | } else if (unlikely(set_rc)) { |
| 256 | /* We always need to compute fpcc */ |
| 257 | gen_op_compute_fprf(0); |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 258 | tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 259 | if (set_fprf) |
| 260 | gen_op_float_check_status(); |
| 261 | } |
| 262 | } |
| 263 | |
| 264 | static always_inline void gen_optimize_fprf (void) |
| 265 | { |
| 266 | #if defined(OPTIMIZE_FPRF_UPDATE) |
| 267 | uint16_t **ptr; |
| 268 | |
| 269 | for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++) |
| 270 | *ptr = INDEX_op_nop1; |
| 271 | gen_fprf_ptr = gen_fprf_buf; |
| 272 | #endif |
| 273 | } |
| 274 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 275 | static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 276 | { |
| 277 | #if defined(TARGET_PPC64) |
| 278 | if (ctx->sf_mode) |
aurel32 | bd568f1 | 2008-09-04 18:06:03 +0000 | [diff] [blame] | 279 | tcg_gen_movi_tl(cpu_nip, nip); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 280 | else |
| 281 | #endif |
aurel32 | bd568f1 | 2008-09-04 18:06:03 +0000 | [diff] [blame] | 282 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 283 | } |
| 284 | |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 285 | #define GEN_EXCP(ctx, excp, error) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 286 | do { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 287 | if ((ctx)->exception == POWERPC_EXCP_NONE) { \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 288 | gen_update_nip(ctx, (ctx)->nip); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 289 | } \ |
| 290 | gen_op_raise_exception_err((excp), (error)); \ |
| 291 | ctx->exception = (excp); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 292 | } while (0) |
| 293 | |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 294 | #define GEN_EXCP_INVAL(ctx) \ |
| 295 | GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ |
| 296 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL) |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 297 | |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 298 | #define GEN_EXCP_PRIVOPC(ctx) \ |
| 299 | GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ |
| 300 | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC) |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 301 | |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 302 | #define GEN_EXCP_PRIVREG(ctx) \ |
| 303 | GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ |
| 304 | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG) |
| 305 | |
| 306 | #define GEN_EXCP_NO_FP(ctx) \ |
| 307 | GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0) |
| 308 | |
| 309 | #define GEN_EXCP_NO_AP(ctx) \ |
| 310 | GEN_EXCP(ctx, POWERPC_EXCP_APU, 0) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 311 | |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 312 | #define GEN_EXCP_NO_VR(ctx) \ |
| 313 | GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0) |
| 314 | |
bellard | f24e569 | 2005-11-23 21:36:30 +0000 | [diff] [blame] | 315 | /* Stop translation */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 316 | static always_inline void GEN_STOP (DisasContext *ctx) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 317 | { |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 318 | gen_update_nip(ctx, ctx->nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 319 | ctx->exception = POWERPC_EXCP_STOP; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 320 | } |
| 321 | |
bellard | f24e569 | 2005-11-23 21:36:30 +0000 | [diff] [blame] | 322 | /* No need to update nip here, as execution flow will change */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 323 | static always_inline void GEN_SYNC (DisasContext *ctx) |
bellard | 2be0071 | 2005-07-02 22:09:27 +0000 | [diff] [blame] | 324 | { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 325 | ctx->exception = POWERPC_EXCP_SYNC; |
bellard | 2be0071 | 2005-07-02 22:09:27 +0000 | [diff] [blame] | 326 | } |
| 327 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 328 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
| 329 | static void gen_##name (DisasContext *ctx); \ |
| 330 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \ |
| 331 | static void gen_##name (DisasContext *ctx) |
| 332 | |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 333 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
| 334 | static void gen_##name (DisasContext *ctx); \ |
| 335 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \ |
| 336 | static void gen_##name (DisasContext *ctx) |
| 337 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 338 | typedef struct opcode_t { |
| 339 | unsigned char opc1, opc2, opc3; |
ths | 1235fc0 | 2008-06-03 19:51:57 +0000 | [diff] [blame] | 340 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
bellard | 18fba28 | 2005-02-08 21:24:36 +0000 | [diff] [blame] | 341 | unsigned char pad[5]; |
| 342 | #else |
| 343 | unsigned char pad[1]; |
| 344 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 345 | opc_handler_t handler; |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 346 | const char *oname; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 347 | } opcode_t; |
| 348 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 349 | /*****************************************************************************/ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 350 | /*** Instruction decoding ***/ |
| 351 | #define EXTRACT_HELPER(name, shift, nb) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 352 | static always_inline uint32_t name (uint32_t opcode) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 353 | { \ |
| 354 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
| 355 | } |
| 356 | |
| 357 | #define EXTRACT_SHELPER(name, shift, nb) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 358 | static always_inline int32_t name (uint32_t opcode) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 359 | { \ |
bellard | 18fba28 | 2005-02-08 21:24:36 +0000 | [diff] [blame] | 360 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 361 | } |
| 362 | |
| 363 | /* Opcode part 1 */ |
| 364 | EXTRACT_HELPER(opc1, 26, 6); |
| 365 | /* Opcode part 2 */ |
| 366 | EXTRACT_HELPER(opc2, 1, 5); |
| 367 | /* Opcode part 3 */ |
| 368 | EXTRACT_HELPER(opc3, 6, 5); |
| 369 | /* Update Cr0 flags */ |
| 370 | EXTRACT_HELPER(Rc, 0, 1); |
| 371 | /* Destination */ |
| 372 | EXTRACT_HELPER(rD, 21, 5); |
| 373 | /* Source */ |
| 374 | EXTRACT_HELPER(rS, 21, 5); |
| 375 | /* First operand */ |
| 376 | EXTRACT_HELPER(rA, 16, 5); |
| 377 | /* Second operand */ |
| 378 | EXTRACT_HELPER(rB, 11, 5); |
| 379 | /* Third operand */ |
| 380 | EXTRACT_HELPER(rC, 6, 5); |
| 381 | /*** Get CRn ***/ |
| 382 | EXTRACT_HELPER(crfD, 23, 3); |
| 383 | EXTRACT_HELPER(crfS, 18, 3); |
| 384 | EXTRACT_HELPER(crbD, 21, 5); |
| 385 | EXTRACT_HELPER(crbA, 16, 5); |
| 386 | EXTRACT_HELPER(crbB, 11, 5); |
| 387 | /* SPR / TBL */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 388 | EXTRACT_HELPER(_SPR, 11, 10); |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 389 | static always_inline uint32_t SPR (uint32_t opcode) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 390 | { |
| 391 | uint32_t sprn = _SPR(opcode); |
| 392 | |
| 393 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
| 394 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 395 | /*** Get constants ***/ |
| 396 | EXTRACT_HELPER(IMM, 12, 8); |
| 397 | /* 16 bits signed immediate value */ |
| 398 | EXTRACT_SHELPER(SIMM, 0, 16); |
| 399 | /* 16 bits unsigned immediate value */ |
| 400 | EXTRACT_HELPER(UIMM, 0, 16); |
| 401 | /* Bit count */ |
| 402 | EXTRACT_HELPER(NB, 11, 5); |
| 403 | /* Shift count */ |
| 404 | EXTRACT_HELPER(SH, 11, 5); |
| 405 | /* Mask start */ |
| 406 | EXTRACT_HELPER(MB, 6, 5); |
| 407 | /* Mask end */ |
| 408 | EXTRACT_HELPER(ME, 1, 5); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 409 | /* Trap operand */ |
| 410 | EXTRACT_HELPER(TO, 21, 5); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 411 | |
| 412 | EXTRACT_HELPER(CRM, 12, 8); |
| 413 | EXTRACT_HELPER(FM, 17, 8); |
| 414 | EXTRACT_HELPER(SR, 16, 4); |
aurel32 | e4bb997 | 2008-06-18 22:10:12 +0000 | [diff] [blame] | 415 | EXTRACT_HELPER(FPIMM, 12, 4); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 416 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 417 | /*** Jump target decoding ***/ |
| 418 | /* Displacement */ |
| 419 | EXTRACT_SHELPER(d, 0, 16); |
| 420 | /* Immediate address */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 421 | static always_inline target_ulong LI (uint32_t opcode) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 422 | { |
| 423 | return (opcode >> 0) & 0x03FFFFFC; |
| 424 | } |
| 425 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 426 | static always_inline uint32_t BD (uint32_t opcode) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 427 | { |
| 428 | return (opcode >> 0) & 0xFFFC; |
| 429 | } |
| 430 | |
| 431 | EXTRACT_HELPER(BO, 21, 5); |
| 432 | EXTRACT_HELPER(BI, 16, 5); |
| 433 | /* Absolute/relative address */ |
| 434 | EXTRACT_HELPER(AA, 1, 1); |
| 435 | /* Link */ |
| 436 | EXTRACT_HELPER(LK, 0, 1); |
| 437 | |
| 438 | /* Create a mask between <start> and <end> bits */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 439 | static always_inline target_ulong MASK (uint32_t start, uint32_t end) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 440 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 441 | target_ulong ret; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 442 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 443 | #if defined(TARGET_PPC64) |
| 444 | if (likely(start == 0)) { |
j_mayer | 6f2d897 | 2007-11-12 00:04:48 +0000 | [diff] [blame] | 445 | ret = UINT64_MAX << (63 - end); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 446 | } else if (likely(end == 63)) { |
j_mayer | 6f2d897 | 2007-11-12 00:04:48 +0000 | [diff] [blame] | 447 | ret = UINT64_MAX >> start; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 448 | } |
| 449 | #else |
| 450 | if (likely(start == 0)) { |
j_mayer | 6f2d897 | 2007-11-12 00:04:48 +0000 | [diff] [blame] | 451 | ret = UINT32_MAX << (31 - end); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 452 | } else if (likely(end == 31)) { |
j_mayer | 6f2d897 | 2007-11-12 00:04:48 +0000 | [diff] [blame] | 453 | ret = UINT32_MAX >> start; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 454 | } |
| 455 | #endif |
| 456 | else { |
| 457 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ |
| 458 | (((target_ulong)(-1ULL) >> (end)) >> 1); |
| 459 | if (unlikely(start > end)) |
| 460 | return ~ret; |
| 461 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 462 | |
| 463 | return ret; |
| 464 | } |
| 465 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 466 | /*****************************************************************************/ |
| 467 | /* PowerPC Instructions types definitions */ |
| 468 | enum { |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 469 | PPC_NONE = 0x0000000000000000ULL, |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 470 | /* PowerPC base instructions set */ |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 471 | PPC_INSNS_BASE = 0x0000000000000001ULL, |
| 472 | /* integer operations instructions */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 473 | #define PPC_INTEGER PPC_INSNS_BASE |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 474 | /* flow control instructions */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 475 | #define PPC_FLOW PPC_INSNS_BASE |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 476 | /* virtual memory instructions */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 477 | #define PPC_MEM PPC_INSNS_BASE |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 478 | /* ld/st with reservation instructions */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 479 | #define PPC_RES PPC_INSNS_BASE |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 480 | /* spr/msr access instructions */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 481 | #define PPC_MISC PPC_INSNS_BASE |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 482 | /* Deprecated instruction sets */ |
| 483 | /* Original POWER instruction set */ |
j_mayer | f610349 | 2007-11-17 12:01:45 +0000 | [diff] [blame] | 484 | PPC_POWER = 0x0000000000000002ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 485 | /* POWER2 instruction set extension */ |
j_mayer | f610349 | 2007-11-17 12:01:45 +0000 | [diff] [blame] | 486 | PPC_POWER2 = 0x0000000000000004ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 487 | /* Power RTC support */ |
j_mayer | f610349 | 2007-11-17 12:01:45 +0000 | [diff] [blame] | 488 | PPC_POWER_RTC = 0x0000000000000008ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 489 | /* Power-to-PowerPC bridge (601) */ |
j_mayer | f610349 | 2007-11-17 12:01:45 +0000 | [diff] [blame] | 490 | PPC_POWER_BR = 0x0000000000000010ULL, |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 491 | /* 64 bits PowerPC instruction set */ |
j_mayer | f610349 | 2007-11-17 12:01:45 +0000 | [diff] [blame] | 492 | PPC_64B = 0x0000000000000020ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 493 | /* New 64 bits extensions (PowerPC 2.0x) */ |
j_mayer | f610349 | 2007-11-17 12:01:45 +0000 | [diff] [blame] | 494 | PPC_64BX = 0x0000000000000040ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 495 | /* 64 bits hypervisor extensions */ |
j_mayer | f610349 | 2007-11-17 12:01:45 +0000 | [diff] [blame] | 496 | PPC_64H = 0x0000000000000080ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 497 | /* New wait instruction (PowerPC 2.0x) */ |
j_mayer | f610349 | 2007-11-17 12:01:45 +0000 | [diff] [blame] | 498 | PPC_WAIT = 0x0000000000000100ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 499 | /* Time base mftb instruction */ |
j_mayer | f610349 | 2007-11-17 12:01:45 +0000 | [diff] [blame] | 500 | PPC_MFTB = 0x0000000000000200ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 501 | |
| 502 | /* Fixed-point unit extensions */ |
| 503 | /* PowerPC 602 specific */ |
j_mayer | f610349 | 2007-11-17 12:01:45 +0000 | [diff] [blame] | 504 | PPC_602_SPEC = 0x0000000000000400ULL, |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 505 | /* isel instruction */ |
| 506 | PPC_ISEL = 0x0000000000000800ULL, |
| 507 | /* popcntb instruction */ |
| 508 | PPC_POPCNTB = 0x0000000000001000ULL, |
| 509 | /* string load / store */ |
| 510 | PPC_STRING = 0x0000000000002000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 511 | |
| 512 | /* Floating-point unit extensions */ |
| 513 | /* Optional floating point instructions */ |
| 514 | PPC_FLOAT = 0x0000000000010000ULL, |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 515 | /* New floating-point extensions (PowerPC 2.0x) */ |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 516 | PPC_FLOAT_EXT = 0x0000000000020000ULL, |
| 517 | PPC_FLOAT_FSQRT = 0x0000000000040000ULL, |
| 518 | PPC_FLOAT_FRES = 0x0000000000080000ULL, |
| 519 | PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL, |
| 520 | PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL, |
| 521 | PPC_FLOAT_FSEL = 0x0000000000400000ULL, |
| 522 | PPC_FLOAT_STFIWX = 0x0000000000800000ULL, |
| 523 | |
| 524 | /* Vector/SIMD extensions */ |
| 525 | /* Altivec support */ |
| 526 | PPC_ALTIVEC = 0x0000000001000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 527 | /* PowerPC 2.03 SPE extension */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 528 | PPC_SPE = 0x0000000002000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 529 | /* PowerPC 2.03 SPE floating-point extension */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 530 | PPC_SPEFPU = 0x0000000004000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 531 | |
| 532 | /* Optional memory control instructions */ |
| 533 | PPC_MEM_TLBIA = 0x0000000010000000ULL, |
| 534 | PPC_MEM_TLBIE = 0x0000000020000000ULL, |
| 535 | PPC_MEM_TLBSYNC = 0x0000000040000000ULL, |
| 536 | /* sync instruction */ |
| 537 | PPC_MEM_SYNC = 0x0000000080000000ULL, |
| 538 | /* eieio instruction */ |
| 539 | PPC_MEM_EIEIO = 0x0000000100000000ULL, |
| 540 | |
| 541 | /* Cache control instructions */ |
j_mayer | c8623f2 | 2007-11-19 01:48:51 +0000 | [diff] [blame] | 542 | PPC_CACHE = 0x0000000200000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 543 | /* icbi instruction */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 544 | PPC_CACHE_ICBI = 0x0000000400000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 545 | /* dcbz instruction with fixed cache line size */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 546 | PPC_CACHE_DCBZ = 0x0000000800000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 547 | /* dcbz instruction with tunable cache line size */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 548 | PPC_CACHE_DCBZT = 0x0000001000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 549 | /* dcba instruction */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 550 | PPC_CACHE_DCBA = 0x0000002000000000ULL, |
| 551 | /* Freescale cache locking instructions */ |
| 552 | PPC_CACHE_LOCK = 0x0000004000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 553 | |
| 554 | /* MMU related extensions */ |
| 555 | /* external control instructions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 556 | PPC_EXTERN = 0x0000010000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 557 | /* segment register access instructions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 558 | PPC_SEGMENT = 0x0000020000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 559 | /* PowerPC 6xx TLB management instructions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 560 | PPC_6xx_TLB = 0x0000040000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 561 | /* PowerPC 74xx TLB management instructions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 562 | PPC_74xx_TLB = 0x0000080000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 563 | /* PowerPC 40x TLB management instructions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 564 | PPC_40x_TLB = 0x0000100000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 565 | /* segment register access instructions for PowerPC 64 "bridge" */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 566 | PPC_SEGMENT_64B = 0x0000200000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 567 | /* SLB management */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 568 | PPC_SLBI = 0x0000400000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 569 | |
| 570 | /* Embedded PowerPC dedicated instructions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 571 | PPC_WRTEE = 0x0001000000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 572 | /* PowerPC 40x exception model */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 573 | PPC_40x_EXCP = 0x0002000000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 574 | /* PowerPC 405 Mac instructions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 575 | PPC_405_MAC = 0x0004000000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 576 | /* PowerPC 440 specific instructions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 577 | PPC_440_SPEC = 0x0008000000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 578 | /* BookE (embedded) PowerPC specification */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 579 | PPC_BOOKE = 0x0010000000000000ULL, |
| 580 | /* mfapidi instruction */ |
| 581 | PPC_MFAPIDI = 0x0020000000000000ULL, |
| 582 | /* tlbiva instruction */ |
| 583 | PPC_TLBIVA = 0x0040000000000000ULL, |
| 584 | /* tlbivax instruction */ |
| 585 | PPC_TLBIVAX = 0x0080000000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 586 | /* PowerPC 4xx dedicated instructions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 587 | PPC_4xx_COMMON = 0x0100000000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 588 | /* PowerPC 40x ibct instructions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 589 | PPC_40x_ICBT = 0x0200000000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 590 | /* rfmci is not implemented in all BookE PowerPC */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 591 | PPC_RFMCI = 0x0400000000000000ULL, |
| 592 | /* rfdi instruction */ |
| 593 | PPC_RFDI = 0x0800000000000000ULL, |
| 594 | /* DCR accesses */ |
| 595 | PPC_DCR = 0x1000000000000000ULL, |
| 596 | /* DCR extended accesse */ |
| 597 | PPC_DCRX = 0x2000000000000000ULL, |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 598 | /* user-mode DCR access, implemented in PowerPC 460 */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 599 | PPC_DCRUX = 0x4000000000000000ULL, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 600 | }; |
| 601 | |
| 602 | /*****************************************************************************/ |
| 603 | /* PowerPC instructions table */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 604 | #if HOST_LONG_BITS == 64 |
| 605 | #define OPC_ALIGN 8 |
| 606 | #else |
| 607 | #define OPC_ALIGN 4 |
| 608 | #endif |
bellard | 1b039c0 | 2004-07-12 18:39:45 +0000 | [diff] [blame] | 609 | #if defined(__APPLE__) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 610 | #define OPCODES_SECTION \ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 611 | __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) )) |
bellard | 1b039c0 | 2004-07-12 18:39:45 +0000 | [diff] [blame] | 612 | #else |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 613 | #define OPCODES_SECTION \ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 614 | __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) )) |
bellard | 933dc6e | 2004-07-10 15:33:29 +0000 | [diff] [blame] | 615 | #endif |
| 616 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 617 | #if defined(DO_PPC_STATISTICS) |
| 618 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ |
| 619 | OPCODES_SECTION opcode_t opc_##name = { \ |
| 620 | .opc1 = op1, \ |
| 621 | .opc2 = op2, \ |
| 622 | .opc3 = op3, \ |
| 623 | .pad = { 0, }, \ |
| 624 | .handler = { \ |
| 625 | .inval = invl, \ |
| 626 | .type = _typ, \ |
| 627 | .handler = &gen_##name, \ |
| 628 | .oname = stringify(name), \ |
| 629 | }, \ |
| 630 | .oname = stringify(name), \ |
| 631 | } |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 632 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \ |
| 633 | OPCODES_SECTION opcode_t opc_##name = { \ |
| 634 | .opc1 = op1, \ |
| 635 | .opc2 = op2, \ |
| 636 | .opc3 = op3, \ |
| 637 | .pad = { 0, }, \ |
| 638 | .handler = { \ |
| 639 | .inval = invl, \ |
| 640 | .type = _typ, \ |
| 641 | .handler = &gen_##name, \ |
| 642 | .oname = onam, \ |
| 643 | }, \ |
| 644 | .oname = onam, \ |
| 645 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 646 | #else |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 647 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ |
bellard | 18fba28 | 2005-02-08 21:24:36 +0000 | [diff] [blame] | 648 | OPCODES_SECTION opcode_t opc_##name = { \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 649 | .opc1 = op1, \ |
| 650 | .opc2 = op2, \ |
| 651 | .opc3 = op3, \ |
bellard | 18fba28 | 2005-02-08 21:24:36 +0000 | [diff] [blame] | 652 | .pad = { 0, }, \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 653 | .handler = { \ |
| 654 | .inval = invl, \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 655 | .type = _typ, \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 656 | .handler = &gen_##name, \ |
| 657 | }, \ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 658 | .oname = stringify(name), \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 659 | } |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 660 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \ |
| 661 | OPCODES_SECTION opcode_t opc_##name = { \ |
| 662 | .opc1 = op1, \ |
| 663 | .opc2 = op2, \ |
| 664 | .opc3 = op3, \ |
| 665 | .pad = { 0, }, \ |
| 666 | .handler = { \ |
| 667 | .inval = invl, \ |
| 668 | .type = _typ, \ |
| 669 | .handler = &gen_##name, \ |
| 670 | }, \ |
| 671 | .oname = onam, \ |
| 672 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 673 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 674 | |
| 675 | #define GEN_OPCODE_MARK(name) \ |
bellard | 18fba28 | 2005-02-08 21:24:36 +0000 | [diff] [blame] | 676 | OPCODES_SECTION opcode_t opc_##name = { \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 677 | .opc1 = 0xFF, \ |
| 678 | .opc2 = 0xFF, \ |
| 679 | .opc3 = 0xFF, \ |
bellard | 18fba28 | 2005-02-08 21:24:36 +0000 | [diff] [blame] | 680 | .pad = { 0, }, \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 681 | .handler = { \ |
| 682 | .inval = 0x00000000, \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 683 | .type = 0x00, \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 684 | .handler = NULL, \ |
| 685 | }, \ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 686 | .oname = stringify(name), \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 687 | } |
| 688 | |
| 689 | /* Start opcode list */ |
| 690 | GEN_OPCODE_MARK(start); |
| 691 | |
| 692 | /* Invalid instruction */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 693 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 694 | { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 695 | GEN_EXCP_INVAL(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 696 | } |
| 697 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 698 | static opc_handler_t invalid_handler = { |
| 699 | .inval = 0xFFFFFFFF, |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 700 | .type = PPC_NONE, |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 701 | .handler = gen_invalid, |
| 702 | }; |
| 703 | |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 704 | /*** Integer comparison ***/ |
| 705 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 706 | static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 707 | { |
| 708 | int l1, l2, l3; |
| 709 | |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 710 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer); |
| 711 | tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 712 | tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1); |
| 713 | |
| 714 | l1 = gen_new_label(); |
| 715 | l2 = gen_new_label(); |
| 716 | l3 = gen_new_label(); |
| 717 | if (s) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 718 | tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1); |
| 719 | tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 720 | } else { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 721 | tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1); |
| 722 | tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 723 | } |
| 724 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ); |
| 725 | tcg_gen_br(l3); |
| 726 | gen_set_label(l1); |
| 727 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT); |
| 728 | tcg_gen_br(l3); |
| 729 | gen_set_label(l2); |
| 730 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT); |
| 731 | gen_set_label(l3); |
| 732 | } |
| 733 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 734 | static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 735 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 736 | TCGv t0 = tcg_const_local_tl(arg1); |
| 737 | gen_op_cmp(arg0, t0, s, crf); |
| 738 | tcg_temp_free(t0); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 739 | } |
| 740 | |
| 741 | #if defined(TARGET_PPC64) |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 742 | static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 743 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 744 | TCGv t0, t1; |
| 745 | t0 = tcg_temp_local_new(TCG_TYPE_TL); |
| 746 | t1 = tcg_temp_local_new(TCG_TYPE_TL); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 747 | if (s) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 748 | tcg_gen_ext32s_tl(t0, arg0); |
| 749 | tcg_gen_ext32s_tl(t1, arg1); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 750 | } else { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 751 | tcg_gen_ext32u_tl(t0, arg0); |
| 752 | tcg_gen_ext32u_tl(t1, arg1); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 753 | } |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 754 | gen_op_cmp(t0, t1, s, crf); |
| 755 | tcg_temp_free(t1); |
| 756 | tcg_temp_free(t0); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 757 | } |
| 758 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 759 | static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 760 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 761 | TCGv t0 = tcg_const_local_tl(arg1); |
| 762 | gen_op_cmp32(arg0, t0, s, crf); |
| 763 | tcg_temp_free(t0); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 764 | } |
| 765 | #endif |
| 766 | |
| 767 | static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg) |
| 768 | { |
| 769 | #if defined(TARGET_PPC64) |
| 770 | if (!(ctx->sf_mode)) |
| 771 | gen_op_cmpi32(reg, 0, 1, 0); |
| 772 | else |
| 773 | #endif |
| 774 | gen_op_cmpi(reg, 0, 1, 0); |
| 775 | } |
| 776 | |
| 777 | /* cmp */ |
| 778 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER) |
| 779 | { |
| 780 | #if defined(TARGET_PPC64) |
| 781 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
| 782 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 783 | 1, crfD(ctx->opcode)); |
| 784 | else |
| 785 | #endif |
| 786 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 787 | 1, crfD(ctx->opcode)); |
| 788 | } |
| 789 | |
| 790 | /* cmpi */ |
| 791 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
| 792 | { |
| 793 | #if defined(TARGET_PPC64) |
| 794 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
| 795 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
| 796 | 1, crfD(ctx->opcode)); |
| 797 | else |
| 798 | #endif |
| 799 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
| 800 | 1, crfD(ctx->opcode)); |
| 801 | } |
| 802 | |
| 803 | /* cmpl */ |
| 804 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER) |
| 805 | { |
| 806 | #if defined(TARGET_PPC64) |
| 807 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
| 808 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 809 | 0, crfD(ctx->opcode)); |
| 810 | else |
| 811 | #endif |
| 812 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 813 | 0, crfD(ctx->opcode)); |
| 814 | } |
| 815 | |
| 816 | /* cmpli */ |
| 817 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
| 818 | { |
| 819 | #if defined(TARGET_PPC64) |
| 820 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
| 821 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
| 822 | 0, crfD(ctx->opcode)); |
| 823 | else |
| 824 | #endif |
| 825 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
| 826 | 0, crfD(ctx->opcode)); |
| 827 | } |
| 828 | |
| 829 | /* isel (PowerPC 2.03 specification) */ |
| 830 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) |
| 831 | { |
| 832 | int l1, l2; |
| 833 | uint32_t bi = rC(ctx->opcode); |
| 834 | uint32_t mask; |
| 835 | TCGv temp; |
| 836 | |
| 837 | l1 = gen_new_label(); |
| 838 | l2 = gen_new_label(); |
| 839 | |
| 840 | mask = 1 << (3 - (bi & 0x03)); |
| 841 | temp = tcg_temp_new(TCG_TYPE_I32); |
| 842 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
| 843 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); |
| 844 | if (rA(ctx->opcode) == 0) |
| 845 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); |
| 846 | else |
| 847 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 848 | tcg_gen_br(l2); |
| 849 | gen_set_label(l1); |
| 850 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
| 851 | gen_set_label(l2); |
| 852 | } |
| 853 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 854 | /*** Integer arithmetic ***/ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 855 | #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \ |
| 856 | GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 857 | { \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 858 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ |
| 859 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 860 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 861 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 862 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 863 | gen_set_Rc0(ctx, cpu_T[0]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 864 | } |
| 865 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 866 | #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \ |
| 867 | GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 868 | { \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 869 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ |
| 870 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 871 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 872 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 873 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 874 | gen_set_Rc0(ctx, cpu_T[0]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 875 | } |
| 876 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 877 | #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \ |
| 878 | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 879 | { \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 880 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 881 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 882 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 883 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 884 | gen_set_Rc0(ctx, cpu_T[0]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 885 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 886 | #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \ |
| 887 | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 888 | { \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 889 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 890 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 891 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 892 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 893 | gen_set_Rc0(ctx, cpu_T[0]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 894 | } |
| 895 | |
| 896 | /* Two operands arithmetic functions */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 897 | #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \ |
| 898 | __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \ |
| 899 | __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 900 | |
| 901 | /* Two operands arithmetic functions with no overflow allowed */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 902 | #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \ |
| 903 | __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 904 | |
| 905 | /* One operand arithmetic functions */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 906 | #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \ |
| 907 | __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \ |
| 908 | __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type) |
| 909 | |
| 910 | #if defined(TARGET_PPC64) |
| 911 | #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \ |
| 912 | GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
| 913 | { \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 914 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ |
| 915 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 916 | if (ctx->sf_mode) \ |
| 917 | gen_op_##name##_64(); \ |
| 918 | else \ |
| 919 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 920 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 921 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 922 | gen_set_Rc0(ctx, cpu_T[0]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 923 | } |
| 924 | |
| 925 | #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \ |
| 926 | GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
| 927 | { \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 928 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ |
| 929 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 930 | if (ctx->sf_mode) \ |
| 931 | gen_op_##name##_64(); \ |
| 932 | else \ |
| 933 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 934 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 935 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 936 | gen_set_Rc0(ctx, cpu_T[0]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 937 | } |
| 938 | |
| 939 | #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \ |
| 940 | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ |
| 941 | { \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 942 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 943 | if (ctx->sf_mode) \ |
| 944 | gen_op_##name##_64(); \ |
| 945 | else \ |
| 946 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 947 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 948 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 949 | gen_set_Rc0(ctx, cpu_T[0]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 950 | } |
| 951 | #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \ |
| 952 | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ |
| 953 | { \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 954 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 955 | if (ctx->sf_mode) \ |
| 956 | gen_op_##name##_64(); \ |
| 957 | else \ |
| 958 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 959 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 960 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 961 | gen_set_Rc0(ctx, cpu_T[0]); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 962 | } |
| 963 | |
| 964 | /* Two operands arithmetic functions */ |
| 965 | #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \ |
| 966 | __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \ |
| 967 | __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type) |
| 968 | |
| 969 | /* Two operands arithmetic functions with no overflow allowed */ |
| 970 | #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \ |
| 971 | __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type) |
| 972 | |
| 973 | /* One operand arithmetic functions */ |
| 974 | #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \ |
| 975 | __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \ |
| 976 | __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type) |
| 977 | #else |
| 978 | #define GEN_INT_ARITH2_64 GEN_INT_ARITH2 |
| 979 | #define GEN_INT_ARITHN_64 GEN_INT_ARITHN |
| 980 | #define GEN_INT_ARITH1_64 GEN_INT_ARITH1 |
| 981 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 982 | |
| 983 | /* add add. addo addo. */ |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 984 | static always_inline void gen_op_add (void) |
| 985 | { |
| 986 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 987 | } |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 988 | static always_inline void gen_op_addo (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 989 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 990 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 991 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 992 | gen_op_check_addo(); |
| 993 | } |
| 994 | #if defined(TARGET_PPC64) |
| 995 | #define gen_op_add_64 gen_op_add |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 996 | static always_inline void gen_op_addo_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 997 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 998 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 999 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1000 | gen_op_check_addo_64(); |
| 1001 | } |
| 1002 | #endif |
| 1003 | GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1004 | /* addc addc. addco addco. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1005 | static always_inline void gen_op_addc (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1006 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1007 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 1008 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1009 | gen_op_check_addc(); |
| 1010 | } |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1011 | static always_inline void gen_op_addco (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1012 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1013 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 1014 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1015 | gen_op_check_addc(); |
| 1016 | gen_op_check_addo(); |
| 1017 | } |
| 1018 | #if defined(TARGET_PPC64) |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1019 | static always_inline void gen_op_addc_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1020 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1021 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 1022 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1023 | gen_op_check_addc_64(); |
| 1024 | } |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1025 | static always_inline void gen_op_addco_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1026 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1027 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 1028 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1029 | gen_op_check_addc_64(); |
| 1030 | gen_op_check_addo_64(); |
| 1031 | } |
| 1032 | #endif |
| 1033 | GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1034 | /* adde adde. addeo addeo. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1035 | static always_inline void gen_op_addeo (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1036 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1037 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1038 | gen_op_adde(); |
| 1039 | gen_op_check_addo(); |
| 1040 | } |
| 1041 | #if defined(TARGET_PPC64) |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1042 | static always_inline void gen_op_addeo_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1043 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1044 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1045 | gen_op_adde_64(); |
| 1046 | gen_op_check_addo_64(); |
| 1047 | } |
| 1048 | #endif |
| 1049 | GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1050 | /* addme addme. addmeo addmeo. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1051 | static always_inline void gen_op_addme (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1052 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1053 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1054 | gen_op_add_me(); |
| 1055 | } |
| 1056 | #if defined(TARGET_PPC64) |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1057 | static always_inline void gen_op_addme_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1058 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1059 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1060 | gen_op_add_me_64(); |
| 1061 | } |
| 1062 | #endif |
| 1063 | GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1064 | /* addze addze. addzeo addzeo. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1065 | static always_inline void gen_op_addze (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1066 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1067 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1068 | gen_op_add_ze(); |
| 1069 | gen_op_check_addc(); |
| 1070 | } |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1071 | static always_inline void gen_op_addzeo (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1072 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1073 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1074 | gen_op_add_ze(); |
| 1075 | gen_op_check_addc(); |
| 1076 | gen_op_check_addo(); |
| 1077 | } |
| 1078 | #if defined(TARGET_PPC64) |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1079 | static always_inline void gen_op_addze_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1080 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1081 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1082 | gen_op_add_ze(); |
| 1083 | gen_op_check_addc_64(); |
| 1084 | } |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1085 | static always_inline void gen_op_addzeo_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1086 | { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1087 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1088 | gen_op_add_ze(); |
| 1089 | gen_op_check_addc_64(); |
| 1090 | gen_op_check_addo_64(); |
| 1091 | } |
| 1092 | #endif |
| 1093 | GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1094 | /* divw divw. divwo divwo. */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1095 | GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1096 | /* divwu divwu. divwuo divwuo. */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1097 | GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1098 | /* mulhw mulhw. */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1099 | GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1100 | /* mulhwu mulhwu. */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1101 | GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1102 | /* mullw mullw. mullwo mullwo. */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1103 | GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1104 | /* neg neg. nego nego. */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1105 | GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1106 | /* subf subf. subfo subfo. */ |
aurel32 | 7c41796 | 2008-09-05 14:19:51 +0000 | [diff] [blame] | 1107 | static always_inline void gen_op_subf (void) |
| 1108 | { |
| 1109 | tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); |
| 1110 | } |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1111 | static always_inline void gen_op_subfo (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1112 | { |
aurel32 | f041347 | 2008-09-02 23:26:40 +0000 | [diff] [blame] | 1113 | tcg_gen_not_tl(cpu_T[2], cpu_T[0]); |
aurel32 | 7c41796 | 2008-09-05 14:19:51 +0000 | [diff] [blame] | 1114 | tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); |
j_mayer | c3e10c7 | 2007-11-11 00:18:34 +0000 | [diff] [blame] | 1115 | gen_op_check_addo(); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1116 | } |
| 1117 | #if defined(TARGET_PPC64) |
| 1118 | #define gen_op_subf_64 gen_op_subf |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1119 | static always_inline void gen_op_subfo_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1120 | { |
aurel32 | f041347 | 2008-09-02 23:26:40 +0000 | [diff] [blame] | 1121 | tcg_gen_not_i64(cpu_T[2], cpu_T[0]); |
aurel32 | 7c41796 | 2008-09-05 14:19:51 +0000 | [diff] [blame] | 1122 | tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); |
j_mayer | c3e10c7 | 2007-11-11 00:18:34 +0000 | [diff] [blame] | 1123 | gen_op_check_addo_64(); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1124 | } |
| 1125 | #endif |
| 1126 | GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1127 | /* subfc subfc. subfco subfco. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1128 | static always_inline void gen_op_subfc (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1129 | { |
aurel32 | 7c41796 | 2008-09-05 14:19:51 +0000 | [diff] [blame] | 1130 | tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1131 | gen_op_check_subfc(); |
| 1132 | } |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1133 | static always_inline void gen_op_subfco (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1134 | { |
aurel32 | f041347 | 2008-09-02 23:26:40 +0000 | [diff] [blame] | 1135 | tcg_gen_not_tl(cpu_T[2], cpu_T[0]); |
aurel32 | 7c41796 | 2008-09-05 14:19:51 +0000 | [diff] [blame] | 1136 | tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1137 | gen_op_check_subfc(); |
j_mayer | c3e10c7 | 2007-11-11 00:18:34 +0000 | [diff] [blame] | 1138 | gen_op_check_addo(); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1139 | } |
| 1140 | #if defined(TARGET_PPC64) |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1141 | static always_inline void gen_op_subfc_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1142 | { |
aurel32 | 7c41796 | 2008-09-05 14:19:51 +0000 | [diff] [blame] | 1143 | tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1144 | gen_op_check_subfc_64(); |
| 1145 | } |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1146 | static always_inline void gen_op_subfco_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1147 | { |
aurel32 | f041347 | 2008-09-02 23:26:40 +0000 | [diff] [blame] | 1148 | tcg_gen_not_i64(cpu_T[2], cpu_T[0]); |
aurel32 | 7c41796 | 2008-09-05 14:19:51 +0000 | [diff] [blame] | 1149 | tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1150 | gen_op_check_subfc_64(); |
j_mayer | c3e10c7 | 2007-11-11 00:18:34 +0000 | [diff] [blame] | 1151 | gen_op_check_addo_64(); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1152 | } |
| 1153 | #endif |
| 1154 | GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1155 | /* subfe subfe. subfeo subfeo. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1156 | static always_inline void gen_op_subfeo (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1157 | { |
aurel32 | f041347 | 2008-09-02 23:26:40 +0000 | [diff] [blame] | 1158 | tcg_gen_not_tl(cpu_T[2], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1159 | gen_op_subfe(); |
j_mayer | c3e10c7 | 2007-11-11 00:18:34 +0000 | [diff] [blame] | 1160 | gen_op_check_addo(); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1161 | } |
| 1162 | #if defined(TARGET_PPC64) |
| 1163 | #define gen_op_subfe_64 gen_op_subfe |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1164 | static always_inline void gen_op_subfeo_64 (void) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1165 | { |
aurel32 | f041347 | 2008-09-02 23:26:40 +0000 | [diff] [blame] | 1166 | tcg_gen_not_i64(cpu_T[2], cpu_T[0]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1167 | gen_op_subfe_64(); |
j_mayer | c3e10c7 | 2007-11-11 00:18:34 +0000 | [diff] [blame] | 1168 | gen_op_check_addo_64(); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1169 | } |
| 1170 | #endif |
| 1171 | GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1172 | /* subfme subfme. subfmeo subfmeo. */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1173 | GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1174 | /* subfze subfze. subfzeo subfzeo. */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1175 | GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1176 | /* addi */ |
| 1177 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1178 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1179 | target_long simm = SIMM(ctx->opcode); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1180 | |
| 1181 | if (rA(ctx->opcode) == 0) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1182 | /* li case */ |
aurel32 | 02f4f6c | 2008-09-02 16:18:55 +0000 | [diff] [blame] | 1183 | tcg_gen_movi_tl(cpu_T[0], simm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1184 | } else { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1185 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1186 | if (likely(simm != 0)) |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 1187 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1188 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1189 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1190 | } |
| 1191 | /* addic */ |
| 1192 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1193 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1194 | target_long simm = SIMM(ctx->opcode); |
| 1195 | |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1196 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1197 | if (likely(simm != 0)) { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1198 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 1199 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1200 | #if defined(TARGET_PPC64) |
| 1201 | if (ctx->sf_mode) |
| 1202 | gen_op_check_addc_64(); |
| 1203 | else |
| 1204 | #endif |
| 1205 | gen_op_check_addc(); |
j_mayer | e864cab | 2007-03-22 22:17:08 +0000 | [diff] [blame] | 1206 | } else { |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 1207 | tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1208 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1209 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1210 | } |
| 1211 | /* addic. */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1212 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1213 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1214 | target_long simm = SIMM(ctx->opcode); |
| 1215 | |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1216 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1217 | if (likely(simm != 0)) { |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 1218 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 1219 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1220 | #if defined(TARGET_PPC64) |
| 1221 | if (ctx->sf_mode) |
| 1222 | gen_op_check_addc_64(); |
| 1223 | else |
| 1224 | #endif |
| 1225 | gen_op_check_addc(); |
j_mayer | 966439a | 2007-09-17 09:51:40 +0000 | [diff] [blame] | 1226 | } else { |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 1227 | tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1228 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1229 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 1230 | gen_set_Rc0(ctx, cpu_T[0]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1231 | } |
| 1232 | /* addis */ |
| 1233 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1234 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1235 | target_long simm = SIMM(ctx->opcode); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1236 | |
| 1237 | if (rA(ctx->opcode) == 0) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1238 | /* lis case */ |
aurel32 | 02f4f6c | 2008-09-02 16:18:55 +0000 | [diff] [blame] | 1239 | tcg_gen_movi_tl(cpu_T[0], simm << 16); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1240 | } else { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1241 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1242 | if (likely(simm != 0)) |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 1243 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1244 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1245 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1246 | } |
| 1247 | /* mulli */ |
| 1248 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1249 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1250 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1251 | gen_op_mulli(SIMM(ctx->opcode)); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1252 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1253 | } |
| 1254 | /* subfic */ |
| 1255 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1256 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1257 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1258 | #if defined(TARGET_PPC64) |
| 1259 | if (ctx->sf_mode) |
| 1260 | gen_op_subfic_64(SIMM(ctx->opcode)); |
| 1261 | else |
| 1262 | #endif |
| 1263 | gen_op_subfic(SIMM(ctx->opcode)); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 1264 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1265 | } |
| 1266 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1267 | #if defined(TARGET_PPC64) |
| 1268 | /* mulhd mulhd. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 1269 | GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1270 | /* mulhdu mulhdu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 1271 | GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1272 | /* mulld mulld. mulldo mulldo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 1273 | GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1274 | /* divd divd. divdo divdo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 1275 | GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1276 | /* divdu divdu. divduo divduo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 1277 | GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1278 | #endif |
| 1279 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1280 | /*** Integer logical ***/ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1281 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
| 1282 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1283 | { \ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1284 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
| 1285 | cpu_gpr[rB(ctx->opcode)]); \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1286 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1287 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1288 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1289 | |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1290 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1291 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1292 | { \ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1293 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1294 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1295 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1296 | } |
| 1297 | |
| 1298 | /* and & and. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1299 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1300 | /* andc & andc. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1301 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1302 | /* andi. */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1303 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1304 | { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1305 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
| 1306 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1307 | } |
| 1308 | /* andis. */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1309 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1310 | { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1311 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
| 1312 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1313 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1314 | /* cntlzw */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1315 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER) |
| 1316 | { |
| 1317 | tcg_gen_helper_1_1(helper_cntlzw, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 1318 | if (unlikely(Rc(ctx->opcode) != 0)) |
pbrook | 2e31f5d | 2008-10-24 12:03:16 +0000 | [diff] [blame] | 1319 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1320 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1321 | /* eqv & eqv. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1322 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1323 | /* extsb & extsb. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1324 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1325 | /* extsh & extsh. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1326 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1327 | /* nand & nand. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1328 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1329 | /* nor & nor. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1330 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1331 | /* or & or. */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1332 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) |
| 1333 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1334 | int rs, ra, rb; |
| 1335 | |
| 1336 | rs = rS(ctx->opcode); |
| 1337 | ra = rA(ctx->opcode); |
| 1338 | rb = rB(ctx->opcode); |
| 1339 | /* Optimisation for mr. ri case */ |
| 1340 | if (rs != ra || rs != rb) { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1341 | if (rs != rb) |
| 1342 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); |
| 1343 | else |
| 1344 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1345 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1346 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1347 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1348 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1349 | #if defined(TARGET_PPC64) |
| 1350 | } else { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1351 | int prio = 0; |
| 1352 | |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1353 | switch (rs) { |
| 1354 | case 1: |
| 1355 | /* Set process priority to low */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1356 | prio = 2; |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1357 | break; |
| 1358 | case 6: |
| 1359 | /* Set process priority to medium-low */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1360 | prio = 3; |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1361 | break; |
| 1362 | case 2: |
| 1363 | /* Set process priority to normal */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1364 | prio = 4; |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1365 | break; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1366 | #if !defined(CONFIG_USER_ONLY) |
| 1367 | case 31: |
| 1368 | if (ctx->supervisor > 0) { |
| 1369 | /* Set process priority to very low */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1370 | prio = 1; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1371 | } |
| 1372 | break; |
| 1373 | case 5: |
| 1374 | if (ctx->supervisor > 0) { |
| 1375 | /* Set process priority to medium-hight */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1376 | prio = 5; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1377 | } |
| 1378 | break; |
| 1379 | case 3: |
| 1380 | if (ctx->supervisor > 0) { |
| 1381 | /* Set process priority to high */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1382 | prio = 6; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1383 | } |
| 1384 | break; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1385 | case 7: |
| 1386 | if (ctx->supervisor > 1) { |
| 1387 | /* Set process priority to very high */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1388 | prio = 7; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1389 | } |
| 1390 | break; |
| 1391 | #endif |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1392 | default: |
| 1393 | /* nop */ |
| 1394 | break; |
| 1395 | } |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1396 | if (prio) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 1397 | TCGv t0 = tcg_temp_new(TCG_TYPE_TL); |
| 1398 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR])); |
| 1399 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
| 1400 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); |
| 1401 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR])); |
| 1402 | tcg_temp_free(t0); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1403 | } |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1404 | #endif |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1405 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1406 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1407 | /* orc & orc. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1408 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1409 | /* xor & xor. */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1410 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) |
| 1411 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1412 | /* Optimisation for "set to zero" case */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1413 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
aurel32 | 312179c | 2008-10-27 22:50:31 +0000 | [diff] [blame] | 1414 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1415 | else |
| 1416 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1417 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1418 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1419 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1420 | /* ori */ |
| 1421 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1422 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1423 | target_ulong uimm = UIMM(ctx->opcode); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1424 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1425 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 1426 | /* NOP */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1427 | /* XXX: should handle special NOPs for POWER series */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1428 | return; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1429 | } |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1430 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1431 | } |
| 1432 | /* oris */ |
| 1433 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1434 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1435 | target_ulong uimm = UIMM(ctx->opcode); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1436 | |
| 1437 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 1438 | /* NOP */ |
| 1439 | return; |
| 1440 | } |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1441 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1442 | } |
| 1443 | /* xori */ |
| 1444 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1445 | { |
| 1446 | target_ulong uimm = UIMM(ctx->opcode); |
| 1447 | |
| 1448 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 1449 | /* NOP */ |
| 1450 | return; |
| 1451 | } |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1452 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1453 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1454 | /* xoris */ |
| 1455 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1456 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1457 | target_ulong uimm = UIMM(ctx->opcode); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1458 | |
| 1459 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 1460 | /* NOP */ |
| 1461 | return; |
| 1462 | } |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1463 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1464 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1465 | /* popcntb : PowerPC 2.03 specification */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 1466 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1467 | { |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1468 | #if defined(TARGET_PPC64) |
| 1469 | if (ctx->sf_mode) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1470 | tcg_gen_helper_1_1(helper_popcntb_64, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1471 | else |
| 1472 | #endif |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1473 | tcg_gen_helper_1_1(helper_popcntb, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1474 | } |
| 1475 | |
| 1476 | #if defined(TARGET_PPC64) |
| 1477 | /* extsw & extsw. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1478 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1479 | /* cntlzd */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1480 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B) |
| 1481 | { |
| 1482 | tcg_gen_helper_1_1(helper_cntlzd, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 1483 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1484 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1485 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1486 | #endif |
| 1487 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1488 | /*** Integer rotate ***/ |
| 1489 | /* rlwimi & rlwimi. */ |
| 1490 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1491 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1492 | uint32_t mb, me, sh; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1493 | |
| 1494 | mb = MB(ctx->opcode); |
| 1495 | me = ME(ctx->opcode); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1496 | sh = SH(ctx->opcode); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1497 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
| 1498 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 1499 | } else { |
| 1500 | TCGv t0, t1; |
| 1501 | target_ulong mask; |
| 1502 | |
| 1503 | t0 = tcg_temp_new(TCG_TYPE_TL); |
| 1504 | t1 = tcg_temp_new(TCG_TYPE_TL); |
| 1505 | if (likely(sh == 0)) { |
| 1506 | tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
| 1507 | } else { |
| 1508 | tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); |
| 1509 | tcg_gen_shli_tl(t0, t1, sh); |
| 1510 | tcg_gen_shri_tl(t1, t1, 32 - sh); |
| 1511 | tcg_gen_or_tl(t0, t0, t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1512 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1513 | #if defined(TARGET_PPC64) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1514 | mb += 32; |
| 1515 | me += 32; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1516 | #endif |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1517 | mask = MASK(mb, me); |
| 1518 | tcg_gen_andi_tl(t0, t0, mask); |
| 1519 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
| 1520 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 1521 | tcg_temp_free(t0); |
| 1522 | tcg_temp_free(t1); |
| 1523 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1524 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1525 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1526 | } |
| 1527 | /* rlwinm & rlwinm. */ |
| 1528 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1529 | { |
| 1530 | uint32_t mb, me, sh; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1531 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1532 | sh = SH(ctx->opcode); |
| 1533 | mb = MB(ctx->opcode); |
| 1534 | me = ME(ctx->opcode); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1535 | |
| 1536 | if (likely(mb == 0 && me == (31 - sh))) { |
| 1537 | if (likely(sh == 0)) { |
| 1538 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 1539 | } else { |
| 1540 | TCGv t0 = tcg_temp_new(TCG_TYPE_TL); |
| 1541 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
| 1542 | tcg_gen_shli_tl(t0, t0, sh); |
| 1543 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 1544 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1545 | } |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1546 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
| 1547 | TCGv t0 = tcg_temp_new(TCG_TYPE_TL); |
| 1548 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
| 1549 | tcg_gen_shri_tl(t0, t0, mb); |
| 1550 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 1551 | tcg_temp_free(t0); |
| 1552 | } else { |
| 1553 | TCGv t0 = tcg_temp_new(TCG_TYPE_TL); |
| 1554 | if (likely(sh != 0)) { |
| 1555 | TCGv t1 = tcg_temp_new(TCG_TYPE_TL); |
| 1556 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
| 1557 | tcg_gen_shli_tl(t1, t0, sh); |
| 1558 | tcg_gen_shri_tl(t0, t0, 32 - sh); |
| 1559 | tcg_gen_or_tl(t0, t0, t1); |
| 1560 | tcg_temp_free(t1); |
| 1561 | } else { |
| 1562 | tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1563 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1564 | #if defined(TARGET_PPC64) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1565 | mb += 32; |
| 1566 | me += 32; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1567 | #endif |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1568 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
| 1569 | tcg_temp_free(t0); |
| 1570 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1571 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1572 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1573 | } |
| 1574 | /* rlwnm & rlwnm. */ |
| 1575 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1576 | { |
| 1577 | uint32_t mb, me; |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1578 | TCGv t0, t1, t2, t3; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1579 | |
| 1580 | mb = MB(ctx->opcode); |
| 1581 | me = ME(ctx->opcode); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1582 | t0 = tcg_temp_new(TCG_TYPE_TL); |
| 1583 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
| 1584 | t1 = tcg_temp_new(TCG_TYPE_TL); |
| 1585 | tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); |
| 1586 | t2 = tcg_temp_new(TCG_TYPE_TL); |
| 1587 | tcg_gen_shl_tl(t2, t1, t0); |
| 1588 | t3 = tcg_const_tl(32); |
| 1589 | tcg_gen_sub_tl(t0, t3, t0); |
| 1590 | tcg_temp_free(t3); |
| 1591 | tcg_gen_shr_tl(t1, t1, t0); |
| 1592 | tcg_temp_free(t0); |
| 1593 | tcg_gen_or_tl(t2, t2, t1); |
| 1594 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1595 | if (unlikely(mb != 0 || me != 31)) { |
| 1596 | #if defined(TARGET_PPC64) |
| 1597 | mb += 32; |
| 1598 | me += 32; |
| 1599 | #endif |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1600 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t2, MASK(mb, me)); |
| 1601 | } else { |
| 1602 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t2); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1603 | } |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1604 | tcg_temp_free(t2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1605 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1606 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1607 | } |
| 1608 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1609 | #if defined(TARGET_PPC64) |
| 1610 | #define GEN_PPC64_R2(name, opc1, opc2) \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1611 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1612 | { \ |
| 1613 | gen_##name(ctx, 0); \ |
| 1614 | } \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1615 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
| 1616 | PPC_64B) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1617 | { \ |
| 1618 | gen_##name(ctx, 1); \ |
| 1619 | } |
| 1620 | #define GEN_PPC64_R4(name, opc1, opc2) \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1621 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1622 | { \ |
| 1623 | gen_##name(ctx, 0, 0); \ |
| 1624 | } \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1625 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ |
| 1626 | PPC_64B) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1627 | { \ |
| 1628 | gen_##name(ctx, 0, 1); \ |
| 1629 | } \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1630 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
| 1631 | PPC_64B) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1632 | { \ |
| 1633 | gen_##name(ctx, 1, 0); \ |
| 1634 | } \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1635 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ |
| 1636 | PPC_64B) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1637 | { \ |
| 1638 | gen_##name(ctx, 1, 1); \ |
| 1639 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1640 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1641 | static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, |
| 1642 | uint32_t me, uint32_t sh) |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1643 | { |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1644 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
| 1645 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
| 1646 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { |
| 1647 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); |
| 1648 | } else { |
| 1649 | TCGv t0 = tcg_temp_new(TCG_TYPE_TL); |
| 1650 | if (likely(sh != 0)) { |
| 1651 | TCGv t1 = tcg_temp_new(TCG_TYPE_TL); |
| 1652 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
| 1653 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh); |
| 1654 | tcg_gen_or_tl(t0, t0, t1); |
| 1655 | tcg_temp_free(t1); |
| 1656 | } else { |
| 1657 | tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1658 | } |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1659 | if (likely(mb == 0 && me == 63)) { |
| 1660 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 1661 | } else { |
| 1662 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1663 | } |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1664 | tcg_temp_free(t0); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1665 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1666 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1667 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1668 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1669 | /* rldicl - rldicl. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1670 | static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1671 | { |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1672 | uint32_t sh, mb; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1673 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1674 | sh = SH(ctx->opcode) | (shn << 5); |
| 1675 | mb = MB(ctx->opcode) | (mbn << 5); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1676 | gen_rldinm(ctx, mb, 63, sh); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1677 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1678 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1679 | /* rldicr - rldicr. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1680 | static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1681 | { |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1682 | uint32_t sh, me; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1683 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1684 | sh = SH(ctx->opcode) | (shn << 5); |
| 1685 | me = MB(ctx->opcode) | (men << 5); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1686 | gen_rldinm(ctx, 0, me, sh); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1687 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1688 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1689 | /* rldic - rldic. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1690 | static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1691 | { |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1692 | uint32_t sh, mb; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1693 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1694 | sh = SH(ctx->opcode) | (shn << 5); |
| 1695 | mb = MB(ctx->opcode) | (mbn << 5); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1696 | gen_rldinm(ctx, mb, 63 - sh, sh); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1697 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1698 | GEN_PPC64_R4(rldic, 0x1E, 0x04); |
| 1699 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1700 | static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, |
| 1701 | uint32_t me) |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1702 | { |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1703 | TCGv t0, t1, t2; |
| 1704 | |
| 1705 | mb = MB(ctx->opcode); |
| 1706 | me = ME(ctx->opcode); |
| 1707 | t0 = tcg_temp_new(TCG_TYPE_TL); |
| 1708 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
| 1709 | t1 = tcg_temp_new(TCG_TYPE_TL); |
| 1710 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t0); |
| 1711 | t2 = tcg_const_tl(32); |
| 1712 | tcg_gen_sub_tl(t0, t2, t0); |
| 1713 | tcg_temp_free(t2); |
| 1714 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
| 1715 | tcg_gen_or_tl(t1, t1, t0); |
| 1716 | tcg_temp_free(t0); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1717 | if (unlikely(mb != 0 || me != 63)) { |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1718 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t1, MASK(mb, me)); |
| 1719 | } else |
| 1720 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); |
| 1721 | tcg_temp_free(t1); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1722 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1723 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1724 | } |
| 1725 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1726 | /* rldcl - rldcl. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1727 | static always_inline void gen_rldcl (DisasContext *ctx, int mbn) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1728 | { |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1729 | uint32_t mb; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1730 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1731 | mb = MB(ctx->opcode) | (mbn << 5); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1732 | gen_rldnm(ctx, mb, 63); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1733 | } |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 1734 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1735 | /* rldcr - rldcr. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1736 | static always_inline void gen_rldcr (DisasContext *ctx, int men) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1737 | { |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1738 | uint32_t me; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1739 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1740 | me = MB(ctx->opcode) | (men << 5); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1741 | gen_rldnm(ctx, 0, me); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1742 | } |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 1743 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1744 | /* rldimi - rldimi. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1745 | static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1746 | { |
j_mayer | 271a916 | 2007-11-14 05:26:46 +0000 | [diff] [blame] | 1747 | uint32_t sh, mb, me; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1748 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1749 | sh = SH(ctx->opcode) | (shn << 5); |
| 1750 | mb = MB(ctx->opcode) | (mbn << 5); |
j_mayer | 271a916 | 2007-11-14 05:26:46 +0000 | [diff] [blame] | 1751 | me = 63 - sh; |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1752 | if (unlikely(sh == 0 && mb == 0)) { |
| 1753 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 1754 | } else { |
| 1755 | TCGv t0, t1; |
| 1756 | target_ulong mask; |
| 1757 | |
| 1758 | t0 = tcg_temp_new(TCG_TYPE_TL); |
| 1759 | t1 = tcg_temp_new(TCG_TYPE_TL); |
| 1760 | if (likely(sh == 0)) { |
| 1761 | tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
| 1762 | } else { |
| 1763 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
| 1764 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh); |
| 1765 | tcg_gen_or_tl(t0, t0, t1); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1766 | } |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1767 | mask = MASK(mb, me); |
| 1768 | tcg_gen_andi_tl(t0, t0, mask); |
| 1769 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
| 1770 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 1771 | tcg_temp_free(t0); |
| 1772 | tcg_temp_free(t1); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1773 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1774 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1775 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1776 | } |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 1777 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1778 | #endif |
| 1779 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1780 | /*** Integer shift ***/ |
| 1781 | /* slw & slw. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1782 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER) |
| 1783 | { |
| 1784 | TCGv temp; |
| 1785 | int l1, l2; |
| 1786 | l1 = gen_new_label(); |
| 1787 | l2 = gen_new_label(); |
| 1788 | |
| 1789 | temp = tcg_temp_local_new(TCG_TYPE_TL); |
| 1790 | tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20); |
| 1791 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); |
| 1792 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
| 1793 | tcg_gen_br(l2); |
| 1794 | gen_set_label(l1); |
| 1795 | tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f); |
| 1796 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp); |
| 1797 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 1798 | gen_set_label(l2); |
| 1799 | tcg_temp_free(temp); |
| 1800 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1801 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1802 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1803 | /* sraw & sraw. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1804 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER) |
| 1805 | { |
| 1806 | tcg_gen_helper_1_2(helper_sraw, cpu_gpr[rA(ctx->opcode)], |
| 1807 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
| 1808 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1809 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1810 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1811 | /* srawi & srawi. */ |
| 1812 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) |
| 1813 | { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1814 | int sh = SH(ctx->opcode); |
| 1815 | if (sh != 0) { |
| 1816 | int l1, l2; |
| 1817 | TCGv temp; |
| 1818 | l1 = gen_new_label(); |
| 1819 | l2 = gen_new_label(); |
| 1820 | temp = tcg_temp_local_new(TCG_TYPE_TL); |
| 1821 | tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]); |
| 1822 | tcg_gen_brcondi_tl(TCG_COND_GE, temp, 0, l1); |
| 1823 | tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
| 1824 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1825 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1826 | tcg_gen_br(l2); |
| 1827 | gen_set_label(l1); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1828 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1829 | gen_set_label(l2); |
| 1830 | tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]); |
| 1831 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], temp, sh); |
| 1832 | tcg_temp_free(temp); |
| 1833 | } else { |
| 1834 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1835 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1836 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1837 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1838 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1839 | } |
| 1840 | /* srw & srw. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1841 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER) |
| 1842 | { |
| 1843 | TCGv temp; |
| 1844 | int l1, l2; |
| 1845 | l1 = gen_new_label(); |
| 1846 | l2 = gen_new_label(); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1847 | |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1848 | temp = tcg_temp_local_new(TCG_TYPE_TL); |
| 1849 | tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20); |
| 1850 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); |
| 1851 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
| 1852 | tcg_gen_br(l2); |
| 1853 | gen_set_label(l1); |
| 1854 | tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f); |
| 1855 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp); |
| 1856 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 1857 | gen_set_label(l2); |
| 1858 | tcg_temp_free(temp); |
| 1859 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1860 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1861 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1862 | #if defined(TARGET_PPC64) |
| 1863 | /* sld & sld. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1864 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B) |
| 1865 | { |
| 1866 | TCGv temp; |
| 1867 | int l1, l2; |
| 1868 | l1 = gen_new_label(); |
| 1869 | l2 = gen_new_label(); |
| 1870 | |
| 1871 | temp = tcg_temp_local_new(TCG_TYPE_TL); |
| 1872 | tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40); |
| 1873 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); |
| 1874 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
| 1875 | tcg_gen_br(l2); |
| 1876 | gen_set_label(l1); |
| 1877 | tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f); |
| 1878 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp); |
| 1879 | gen_set_label(l2); |
| 1880 | tcg_temp_free(temp); |
| 1881 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1882 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1883 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1884 | /* srad & srad. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1885 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B) |
| 1886 | { |
| 1887 | tcg_gen_helper_1_2(helper_srad, cpu_gpr[rA(ctx->opcode)], |
| 1888 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
| 1889 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1890 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1891 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1892 | /* sradi & sradi. */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 1893 | static always_inline void gen_sradi (DisasContext *ctx, int n) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1894 | { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1895 | int sh = SH(ctx->opcode) + (n << 5); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1896 | if (sh != 0) { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1897 | int l1, l2; |
| 1898 | TCGv temp; |
| 1899 | l1 = gen_new_label(); |
| 1900 | l2 = gen_new_label(); |
| 1901 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); |
| 1902 | temp = tcg_temp_new(TCG_TYPE_TL); |
| 1903 | tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
| 1904 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1905 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1906 | tcg_gen_br(l2); |
| 1907 | gen_set_label(l1); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1908 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1909 | gen_set_label(l2); |
| 1910 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
| 1911 | } else { |
| 1912 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1913 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1914 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1915 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1916 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1917 | } |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1918 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1919 | { |
| 1920 | gen_sradi(ctx, 0); |
| 1921 | } |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 1922 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1923 | { |
| 1924 | gen_sradi(ctx, 1); |
| 1925 | } |
| 1926 | /* srd & srd. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1927 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B) |
| 1928 | { |
| 1929 | TCGv temp; |
| 1930 | int l1, l2; |
| 1931 | l1 = gen_new_label(); |
| 1932 | l2 = gen_new_label(); |
| 1933 | |
| 1934 | temp = tcg_temp_local_new(TCG_TYPE_TL); |
| 1935 | tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40); |
| 1936 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); |
| 1937 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
| 1938 | tcg_gen_br(l2); |
| 1939 | gen_set_label(l1); |
| 1940 | tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f); |
| 1941 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp); |
| 1942 | gen_set_label(l2); |
| 1943 | tcg_temp_free(temp); |
| 1944 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1945 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1946 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1947 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1948 | |
| 1949 | /*** Floating-Point arithmetic ***/ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 1950 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 1951 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1952 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1953 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 1954 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 1955 | return; \ |
| 1956 | } \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 1957 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \ |
| 1958 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \ |
| 1959 | tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 1960 | gen_reset_fpstatus(); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 1961 | gen_op_f##op(); \ |
| 1962 | if (isfloat) { \ |
| 1963 | gen_op_frsp(); \ |
| 1964 | } \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 1965 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 1966 | gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1967 | } |
| 1968 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 1969 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
| 1970 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ |
| 1971 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1972 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 1973 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
| 1974 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1975 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1976 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 1977 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 1978 | return; \ |
| 1979 | } \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 1980 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \ |
| 1981 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 1982 | gen_reset_fpstatus(); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 1983 | gen_op_f##op(); \ |
| 1984 | if (isfloat) { \ |
| 1985 | gen_op_frsp(); \ |
| 1986 | } \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 1987 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 1988 | gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1989 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 1990 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
| 1991 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
| 1992 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1993 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 1994 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
| 1995 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1996 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1997 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 1998 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 1999 | return; \ |
| 2000 | } \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2001 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \ |
| 2002 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2003 | gen_reset_fpstatus(); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2004 | gen_op_f##op(); \ |
| 2005 | if (isfloat) { \ |
| 2006 | gen_op_frsp(); \ |
| 2007 | } \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2008 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2009 | gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2010 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2011 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
| 2012 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
| 2013 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2014 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2015 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 2016 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2017 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2018 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2019 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2020 | return; \ |
| 2021 | } \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2022 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2023 | gen_reset_fpstatus(); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2024 | gen_op_f##name(); \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2025 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2026 | gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2027 | } |
| 2028 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2029 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 2030 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2031 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2032 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2033 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2034 | return; \ |
| 2035 | } \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2036 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2037 | gen_reset_fpstatus(); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2038 | gen_op_f##name(); \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2039 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2040 | gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2041 | } |
| 2042 | |
| 2043 | /* fadd - fadds */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2044 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2045 | /* fdiv - fdivs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2046 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2047 | /* fmul - fmuls */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2048 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2049 | |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2050 | /* fre */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2051 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2052 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 2053 | /* fres */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2054 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2055 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 2056 | /* frsqrte */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2057 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
| 2058 | |
| 2059 | /* frsqrtes */ |
| 2060 | static always_inline void gen_op_frsqrtes (void) |
| 2061 | { |
| 2062 | gen_op_frsqrte(); |
| 2063 | gen_op_frsp(); |
| 2064 | } |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 2065 | GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2066 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 2067 | /* fsel */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2068 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2069 | /* fsub - fsubs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2070 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2071 | /* Optional: */ |
| 2072 | /* fsqrt */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 2073 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) |
bellard | c7d344a | 2005-04-23 18:05:46 +0000 | [diff] [blame] | 2074 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2075 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2076 | GEN_EXCP_NO_FP(ctx); |
bellard | c7d344a | 2005-04-23 18:05:46 +0000 | [diff] [blame] | 2077 | return; |
| 2078 | } |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2079 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2080 | gen_reset_fpstatus(); |
bellard | c7d344a | 2005-04-23 18:05:46 +0000 | [diff] [blame] | 2081 | gen_op_fsqrt(); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2082 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2083 | gen_compute_fprf(1, Rc(ctx->opcode) != 0); |
bellard | c7d344a | 2005-04-23 18:05:46 +0000 | [diff] [blame] | 2084 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2085 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 2086 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2087 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2088 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2089 | GEN_EXCP_NO_FP(ctx); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2090 | return; |
| 2091 | } |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2092 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2093 | gen_reset_fpstatus(); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2094 | gen_op_fsqrt(); |
| 2095 | gen_op_frsp(); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2096 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2097 | gen_compute_fprf(1, Rc(ctx->opcode) != 0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2098 | } |
| 2099 | |
| 2100 | /*** Floating-Point multiply-and-add ***/ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2101 | /* fmadd - fmadds */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2102 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2103 | /* fmsub - fmsubs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2104 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2105 | /* fnmadd - fnmadds */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2106 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2107 | /* fnmsub - fnmsubs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2108 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2109 | |
| 2110 | /*** Floating-Point round & convert ***/ |
| 2111 | /* fctiw */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2112 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2113 | /* fctiwz */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2114 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2115 | /* frsp */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2116 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 2117 | #if defined(TARGET_PPC64) |
| 2118 | /* fcfid */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2119 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 2120 | /* fctid */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2121 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 2122 | /* fctidz */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2123 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 2124 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2125 | |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2126 | /* frin */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2127 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2128 | /* friz */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2129 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2130 | /* frip */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2131 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2132 | /* frim */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2133 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2134 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2135 | /*** Floating-Point compare ***/ |
| 2136 | /* fcmpo */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2137 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2138 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2139 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2140 | GEN_EXCP_NO_FP(ctx); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2141 | return; |
| 2142 | } |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2143 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); |
| 2144 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2145 | gen_reset_fpstatus(); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2146 | tcg_gen_helper_1_0(helper_fcmpo, cpu_crf[crfD(ctx->opcode)]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2147 | gen_op_float_check_status(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2148 | } |
| 2149 | |
| 2150 | /* fcmpu */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2151 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2152 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2153 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2154 | GEN_EXCP_NO_FP(ctx); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2155 | return; |
| 2156 | } |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2157 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); |
| 2158 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2159 | gen_reset_fpstatus(); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2160 | tcg_gen_helper_1_0(helper_fcmpu, cpu_crf[crfD(ctx->opcode)]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2161 | gen_op_float_check_status(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2162 | } |
| 2163 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2164 | /*** Floating-point move ***/ |
| 2165 | /* fabs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2166 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
| 2167 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2168 | |
| 2169 | /* fmr - fmr. */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2170 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2171 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) |
| 2172 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2173 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2174 | GEN_EXCP_NO_FP(ctx); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2175 | return; |
| 2176 | } |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2177 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); |
| 2178 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2179 | gen_compute_fprf(0, Rc(ctx->opcode) != 0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2180 | } |
| 2181 | |
| 2182 | /* fnabs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2183 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
| 2184 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2185 | /* fneg */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2186 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
| 2187 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2188 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2189 | /*** Floating-Point status & ctrl register ***/ |
| 2190 | /* mcrfs */ |
| 2191 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) |
| 2192 | { |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2193 | int bfa; |
| 2194 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2195 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2196 | GEN_EXCP_NO_FP(ctx); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2197 | return; |
| 2198 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2199 | gen_optimize_fprf(); |
| 2200 | bfa = 4 * (7 - crfS(ctx->opcode)); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2201 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); |
| 2202 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2203 | gen_op_fpscr_resetbit(~(0xF << bfa)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2204 | } |
| 2205 | |
| 2206 | /* mffs */ |
| 2207 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) |
| 2208 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2209 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2210 | GEN_EXCP_NO_FP(ctx); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2211 | return; |
| 2212 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2213 | gen_optimize_fprf(); |
| 2214 | gen_reset_fpstatus(); |
| 2215 | gen_op_load_fpscr_FT0(); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2216 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2217 | gen_compute_fprf(0, Rc(ctx->opcode) != 0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2218 | } |
| 2219 | |
| 2220 | /* mtfsb0 */ |
| 2221 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT) |
| 2222 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 2223 | uint8_t crb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2224 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2225 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2226 | GEN_EXCP_NO_FP(ctx); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2227 | return; |
| 2228 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2229 | crb = 32 - (crbD(ctx->opcode) >> 2); |
| 2230 | gen_optimize_fprf(); |
| 2231 | gen_reset_fpstatus(); |
| 2232 | if (likely(crb != 30 && crb != 29)) |
| 2233 | gen_op_fpscr_resetbit(~(1 << crb)); |
| 2234 | if (unlikely(Rc(ctx->opcode) != 0)) { |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2235 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2236 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2237 | } |
| 2238 | |
| 2239 | /* mtfsb1 */ |
| 2240 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) |
| 2241 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 2242 | uint8_t crb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2243 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2244 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2245 | GEN_EXCP_NO_FP(ctx); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2246 | return; |
| 2247 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2248 | crb = 32 - (crbD(ctx->opcode) >> 2); |
| 2249 | gen_optimize_fprf(); |
| 2250 | gen_reset_fpstatus(); |
| 2251 | /* XXX: we pretend we can only do IEEE floating-point computations */ |
| 2252 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) |
| 2253 | gen_op_fpscr_setbit(crb); |
| 2254 | if (unlikely(Rc(ctx->opcode) != 0)) { |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2255 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2256 | } |
| 2257 | /* We can raise a differed exception */ |
| 2258 | gen_op_float_check_status(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2259 | } |
| 2260 | |
| 2261 | /* mtfsf */ |
| 2262 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) |
| 2263 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2264 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2265 | GEN_EXCP_NO_FP(ctx); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2266 | return; |
| 2267 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2268 | gen_optimize_fprf(); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 2269 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2270 | gen_reset_fpstatus(); |
bellard | 28b6751 | 2003-11-23 16:58:08 +0000 | [diff] [blame] | 2271 | gen_op_store_fpscr(FM(ctx->opcode)); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2272 | if (unlikely(Rc(ctx->opcode) != 0)) { |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2273 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2274 | } |
| 2275 | /* We can raise a differed exception */ |
| 2276 | gen_op_float_check_status(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2277 | } |
| 2278 | |
| 2279 | /* mtfsfi */ |
| 2280 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) |
| 2281 | { |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2282 | int bf, sh; |
| 2283 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2284 | if (unlikely(!ctx->fpu_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2285 | GEN_EXCP_NO_FP(ctx); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2286 | return; |
| 2287 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2288 | bf = crbD(ctx->opcode) >> 2; |
| 2289 | sh = 7 - bf; |
| 2290 | gen_optimize_fprf(); |
aurel32 | 489251f | 2008-09-04 20:34:31 +0000 | [diff] [blame] | 2291 | tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh)); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2292 | gen_reset_fpstatus(); |
| 2293 | gen_op_store_fpscr(1 << sh); |
| 2294 | if (unlikely(Rc(ctx->opcode) != 0)) { |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2295 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2296 | } |
| 2297 | /* We can raise a differed exception */ |
| 2298 | gen_op_float_check_status(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2299 | } |
| 2300 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2301 | /*** Addressing modes ***/ |
| 2302 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2303 | static always_inline void gen_addr_imm_index (TCGv EA, |
| 2304 | DisasContext *ctx, |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 2305 | target_long maskl) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2306 | { |
| 2307 | target_long simm = SIMM(ctx->opcode); |
| 2308 | |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2309 | simm &= ~maskl; |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2310 | if (rA(ctx->opcode) == 0) |
| 2311 | tcg_gen_movi_tl(EA, simm); |
| 2312 | else if (likely(simm != 0)) |
| 2313 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
| 2314 | else |
| 2315 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2316 | } |
| 2317 | |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2318 | static always_inline void gen_addr_reg_index (TCGv EA, |
| 2319 | DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2320 | { |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2321 | if (rA(ctx->opcode) == 0) |
| 2322 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
| 2323 | else |
| 2324 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2325 | } |
| 2326 | |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2327 | static always_inline void gen_addr_register (TCGv EA, |
| 2328 | DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2329 | { |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2330 | if (rA(ctx->opcode) == 0) |
| 2331 | tcg_gen_movi_tl(EA, 0); |
| 2332 | else |
| 2333 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2334 | } |
| 2335 | |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2336 | #if defined(TARGET_PPC64) |
| 2337 | #define _GEN_MEM_FUNCS(name, mode) \ |
| 2338 | &gen_op_##name##_##mode, \ |
| 2339 | &gen_op_##name##_le_##mode, \ |
| 2340 | &gen_op_##name##_64_##mode, \ |
| 2341 | &gen_op_##name##_le_64_##mode |
| 2342 | #else |
| 2343 | #define _GEN_MEM_FUNCS(name, mode) \ |
| 2344 | &gen_op_##name##_##mode, \ |
| 2345 | &gen_op_##name##_le_##mode |
| 2346 | #endif |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 2347 | #if defined(CONFIG_USER_ONLY) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2348 | #if defined(TARGET_PPC64) |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2349 | #define NB_MEM_FUNCS 4 |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2350 | #else |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2351 | #define NB_MEM_FUNCS 2 |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2352 | #endif |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2353 | #define GEN_MEM_FUNCS(name) \ |
| 2354 | _GEN_MEM_FUNCS(name, raw) |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 2355 | #else |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2356 | #if defined(TARGET_PPC64) |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2357 | #define NB_MEM_FUNCS 12 |
j_mayer | 2857068 | 2007-10-02 10:11:50 +0000 | [diff] [blame] | 2358 | #else |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2359 | #define NB_MEM_FUNCS 6 |
j_mayer | 2857068 | 2007-10-02 10:11:50 +0000 | [diff] [blame] | 2360 | #endif |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2361 | #define GEN_MEM_FUNCS(name) \ |
| 2362 | _GEN_MEM_FUNCS(name, user), \ |
| 2363 | _GEN_MEM_FUNCS(name, kernel), \ |
| 2364 | _GEN_MEM_FUNCS(name, hypv) |
| 2365 | #endif |
| 2366 | |
| 2367 | /*** Integer load ***/ |
| 2368 | #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2369 | #define OP_LD_TABLE(width) \ |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2370 | static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \ |
| 2371 | GEN_MEM_FUNCS(l##width), \ |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 2372 | }; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2373 | #define OP_ST_TABLE(width) \ |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2374 | static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \ |
| 2375 | GEN_MEM_FUNCS(st##width), \ |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 2376 | }; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2377 | |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2378 | |
| 2379 | #if defined(TARGET_PPC64) |
| 2380 | #define GEN_QEMU_LD_PPC64(width) \ |
| 2381 | static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\ |
| 2382 | { \ |
| 2383 | if (likely(flags & 2)) \ |
| 2384 | tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \ |
| 2385 | else { \ |
| 2386 | TCGv addr = tcg_temp_new(TCG_TYPE_TL); \ |
| 2387 | tcg_gen_ext32u_tl(addr, t1); \ |
| 2388 | tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \ |
| 2389 | tcg_temp_free(addr); \ |
| 2390 | } \ |
| 2391 | } |
| 2392 | GEN_QEMU_LD_PPC64(8u) |
| 2393 | GEN_QEMU_LD_PPC64(8s) |
| 2394 | GEN_QEMU_LD_PPC64(16u) |
| 2395 | GEN_QEMU_LD_PPC64(16s) |
| 2396 | GEN_QEMU_LD_PPC64(32u) |
| 2397 | GEN_QEMU_LD_PPC64(32s) |
| 2398 | GEN_QEMU_LD_PPC64(64) |
| 2399 | |
| 2400 | #define GEN_QEMU_ST_PPC64(width) \ |
| 2401 | static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\ |
| 2402 | { \ |
| 2403 | if (likely(flags & 2)) \ |
| 2404 | tcg_gen_qemu_st##width(t0, t1, flags >> 2); \ |
| 2405 | else { \ |
| 2406 | TCGv addr = tcg_temp_new(TCG_TYPE_TL); \ |
| 2407 | tcg_gen_ext32u_tl(addr, t1); \ |
| 2408 | tcg_gen_qemu_st##width(t0, addr, flags >> 2); \ |
| 2409 | tcg_temp_free(addr); \ |
| 2410 | } \ |
| 2411 | } |
| 2412 | GEN_QEMU_ST_PPC64(8) |
| 2413 | GEN_QEMU_ST_PPC64(16) |
| 2414 | GEN_QEMU_ST_PPC64(32) |
| 2415 | GEN_QEMU_ST_PPC64(64) |
| 2416 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2417 | static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2418 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2419 | gen_qemu_ld8u_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2420 | } |
| 2421 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2422 | static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2423 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2424 | gen_qemu_ld8s_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2425 | } |
| 2426 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2427 | static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2428 | { |
| 2429 | if (unlikely(flags & 1)) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2430 | TCGv t0; |
| 2431 | gen_qemu_ld16u_ppc64(arg0, arg1, flags); |
| 2432 | t0 = tcg_temp_new(TCG_TYPE_I32); |
| 2433 | tcg_gen_trunc_tl_i32(t0, arg0); |
| 2434 | tcg_gen_bswap16_i32(t0, t0); |
| 2435 | tcg_gen_extu_i32_tl(arg0, t0); |
| 2436 | tcg_temp_free(t0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2437 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2438 | gen_qemu_ld16u_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2439 | } |
| 2440 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2441 | static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2442 | { |
| 2443 | if (unlikely(flags & 1)) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2444 | TCGv t0; |
| 2445 | gen_qemu_ld16u_ppc64(arg0, arg1, flags); |
| 2446 | t0 = tcg_temp_new(TCG_TYPE_I32); |
| 2447 | tcg_gen_trunc_tl_i32(t0, arg0); |
| 2448 | tcg_gen_bswap16_i32(t0, t0); |
| 2449 | tcg_gen_extu_i32_tl(arg0, t0); |
| 2450 | tcg_gen_ext16s_tl(arg0, arg0); |
| 2451 | tcg_temp_free(t0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2452 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2453 | gen_qemu_ld16s_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2454 | } |
| 2455 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2456 | static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2457 | { |
| 2458 | if (unlikely(flags & 1)) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2459 | TCGv t0; |
| 2460 | gen_qemu_ld32u_ppc64(arg0, arg1, flags); |
| 2461 | t0 = tcg_temp_new(TCG_TYPE_I32); |
| 2462 | tcg_gen_trunc_tl_i32(t0, arg0); |
| 2463 | tcg_gen_bswap_i32(t0, t0); |
| 2464 | tcg_gen_extu_i32_tl(arg0, t0); |
| 2465 | tcg_temp_free(t0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2466 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2467 | gen_qemu_ld32u_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2468 | } |
| 2469 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2470 | static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2471 | { |
| 2472 | if (unlikely(flags & 1)) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2473 | TCGv t0; |
| 2474 | gen_qemu_ld32u_ppc64(arg0, arg1, flags); |
| 2475 | t0 = tcg_temp_new(TCG_TYPE_I32); |
| 2476 | tcg_gen_trunc_tl_i32(t0, arg0); |
| 2477 | tcg_gen_bswap_i32(t0, t0); |
| 2478 | tcg_gen_ext_i32_tl(arg0, t0); |
| 2479 | tcg_temp_free(t0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2480 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2481 | gen_qemu_ld32s_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2482 | } |
| 2483 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2484 | static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2485 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2486 | gen_qemu_ld64_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2487 | if (unlikely(flags & 1)) |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2488 | tcg_gen_bswap_i64(arg0, arg0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2489 | } |
| 2490 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2491 | static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2492 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2493 | gen_qemu_st8_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2494 | } |
| 2495 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2496 | static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2497 | { |
| 2498 | if (unlikely(flags & 1)) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2499 | TCGv t0, t1; |
| 2500 | t0 = tcg_temp_new(TCG_TYPE_I32); |
| 2501 | tcg_gen_trunc_tl_i32(t0, arg0); |
| 2502 | tcg_gen_ext16u_i32(t0, t0); |
| 2503 | tcg_gen_bswap16_i32(t0, t0); |
| 2504 | t1 = tcg_temp_new(TCG_TYPE_I64); |
| 2505 | tcg_gen_extu_i32_tl(t1, t0); |
| 2506 | tcg_temp_free(t0); |
| 2507 | gen_qemu_st16_ppc64(t1, arg1, flags); |
| 2508 | tcg_temp_free(t1); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2509 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2510 | gen_qemu_st16_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2511 | } |
| 2512 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2513 | static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2514 | { |
| 2515 | if (unlikely(flags & 1)) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2516 | TCGv t0, t1; |
| 2517 | t0 = tcg_temp_new(TCG_TYPE_I32); |
| 2518 | tcg_gen_trunc_tl_i32(t0, arg0); |
| 2519 | tcg_gen_bswap_i32(t0, t0); |
| 2520 | t1 = tcg_temp_new(TCG_TYPE_I64); |
| 2521 | tcg_gen_extu_i32_tl(t1, t0); |
| 2522 | tcg_temp_free(t0); |
| 2523 | gen_qemu_st32_ppc64(t1, arg1, flags); |
| 2524 | tcg_temp_free(t1); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2525 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2526 | gen_qemu_st32_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2527 | } |
| 2528 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2529 | static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2530 | { |
| 2531 | if (unlikely(flags & 1)) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2532 | TCGv t0 = tcg_temp_new(TCG_TYPE_I64); |
| 2533 | tcg_gen_bswap_i64(t0, arg0); |
| 2534 | gen_qemu_st64_ppc64(t0, arg1, flags); |
| 2535 | tcg_temp_free(t0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2536 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2537 | gen_qemu_st64_ppc64(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2538 | } |
| 2539 | |
| 2540 | |
| 2541 | #else /* defined(TARGET_PPC64) */ |
| 2542 | #define GEN_QEMU_LD_PPC32(width) \ |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2543 | static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2544 | { \ |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2545 | tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2546 | } |
| 2547 | GEN_QEMU_LD_PPC32(8u) |
| 2548 | GEN_QEMU_LD_PPC32(8s) |
| 2549 | GEN_QEMU_LD_PPC32(16u) |
| 2550 | GEN_QEMU_LD_PPC32(16s) |
| 2551 | GEN_QEMU_LD_PPC32(32u) |
| 2552 | GEN_QEMU_LD_PPC32(32s) |
| 2553 | GEN_QEMU_LD_PPC32(64) |
| 2554 | |
| 2555 | #define GEN_QEMU_ST_PPC32(width) \ |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2556 | static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2557 | { \ |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2558 | tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2559 | } |
| 2560 | GEN_QEMU_ST_PPC32(8) |
| 2561 | GEN_QEMU_ST_PPC32(16) |
| 2562 | GEN_QEMU_ST_PPC32(32) |
| 2563 | GEN_QEMU_ST_PPC32(64) |
| 2564 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2565 | static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2566 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2567 | gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2568 | } |
| 2569 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2570 | static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2571 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2572 | gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2573 | } |
| 2574 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2575 | static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2576 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2577 | gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2578 | if (unlikely(flags & 1)) |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2579 | tcg_gen_bswap16_i32(arg0, arg0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2580 | } |
| 2581 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2582 | static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2583 | { |
| 2584 | if (unlikely(flags & 1)) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2585 | gen_qemu_ld16u_ppc32(arg0, arg1, flags); |
| 2586 | tcg_gen_bswap16_i32(arg0, arg0); |
| 2587 | tcg_gen_ext16s_i32(arg0, arg0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2588 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2589 | gen_qemu_ld16s_ppc32(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2590 | } |
| 2591 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2592 | static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2593 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2594 | gen_qemu_ld32u_ppc32(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2595 | if (unlikely(flags & 1)) |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2596 | tcg_gen_bswap_i32(arg0, arg0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2597 | } |
| 2598 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2599 | static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2600 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2601 | gen_qemu_ld64_ppc32(arg0, arg1, flags); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2602 | if (unlikely(flags & 1)) |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2603 | tcg_gen_bswap_i64(arg0, arg0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2604 | } |
| 2605 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2606 | static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2607 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2608 | gen_qemu_st8_ppc32(arg0, arg1, flags >> 1); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2609 | } |
| 2610 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2611 | static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2612 | { |
| 2613 | if (unlikely(flags & 1)) { |
| 2614 | TCGv temp = tcg_temp_new(TCG_TYPE_I32); |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2615 | tcg_gen_ext16u_i32(temp, arg0); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2616 | tcg_gen_bswap16_i32(temp, temp); |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2617 | gen_qemu_st16_ppc32(temp, arg1, flags >> 1); |
aurel32 | 312179c | 2008-10-27 22:50:31 +0000 | [diff] [blame] | 2618 | tcg_temp_free(temp); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2619 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2620 | gen_qemu_st16_ppc32(arg0, arg1, flags >> 1); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2621 | } |
| 2622 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2623 | static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2624 | { |
| 2625 | if (unlikely(flags & 1)) { |
| 2626 | TCGv temp = tcg_temp_new(TCG_TYPE_I32); |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2627 | tcg_gen_bswap_i32(temp, arg0); |
| 2628 | gen_qemu_st32_ppc32(temp, arg1, flags >> 1); |
aurel32 | 312179c | 2008-10-27 22:50:31 +0000 | [diff] [blame] | 2629 | tcg_temp_free(temp); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2630 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2631 | gen_qemu_st32_ppc32(arg0, arg1, flags >> 1); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2632 | } |
| 2633 | |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2634 | static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2635 | { |
| 2636 | if (unlikely(flags & 1)) { |
| 2637 | TCGv temp = tcg_temp_new(TCG_TYPE_I64); |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2638 | tcg_gen_bswap_i64(temp, arg0); |
| 2639 | gen_qemu_st64_ppc32(temp, arg1, flags >> 1); |
aurel32 | 312179c | 2008-10-27 22:50:31 +0000 | [diff] [blame] | 2640 | tcg_temp_free(temp); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2641 | } else |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 2642 | gen_qemu_st64_ppc32(arg0, arg1, flags >> 1); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2643 | } |
| 2644 | |
| 2645 | #endif |
| 2646 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2647 | #define GEN_LD(width, opc, type) \ |
| 2648 | GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2649 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2650 | TCGv EA = tcg_temp_new(TCG_TYPE_TL); \ |
| 2651 | gen_addr_imm_index(EA, ctx, 0); \ |
| 2652 | gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ |
| 2653 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2654 | } |
| 2655 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2656 | #define GEN_LDU(width, opc, type) \ |
| 2657 | GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2658 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2659 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2660 | if (unlikely(rA(ctx->opcode) == 0 || \ |
| 2661 | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2662 | GEN_EXCP_INVAL(ctx); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2663 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2664 | } \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2665 | EA = tcg_temp_new(TCG_TYPE_TL); \ |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 2666 | if (type == PPC_64B) \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2667 | gen_addr_imm_index(EA, ctx, 0x03); \ |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 2668 | else \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2669 | gen_addr_imm_index(EA, ctx, 0); \ |
| 2670 | gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ |
| 2671 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 2672 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2673 | } |
| 2674 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2675 | #define GEN_LDUX(width, opc2, opc3, type) \ |
| 2676 | GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2677 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2678 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2679 | if (unlikely(rA(ctx->opcode) == 0 || \ |
| 2680 | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2681 | GEN_EXCP_INVAL(ctx); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2682 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2683 | } \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2684 | EA = tcg_temp_new(TCG_TYPE_TL); \ |
| 2685 | gen_addr_reg_index(EA, ctx); \ |
| 2686 | gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ |
| 2687 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 2688 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2689 | } |
| 2690 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2691 | #define GEN_LDX(width, opc2, opc3, type) \ |
| 2692 | GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2693 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2694 | TCGv EA = tcg_temp_new(TCG_TYPE_TL); \ |
| 2695 | gen_addr_reg_index(EA, ctx); \ |
| 2696 | gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ |
| 2697 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2698 | } |
| 2699 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2700 | #define GEN_LDS(width, op, type) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2701 | GEN_LD(width, op | 0x20, type); \ |
| 2702 | GEN_LDU(width, op | 0x21, type); \ |
| 2703 | GEN_LDUX(width, 0x17, op | 0x01, type); \ |
| 2704 | GEN_LDX(width, 0x17, op | 0x00, type) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2705 | |
| 2706 | /* lbz lbzu lbzux lbzx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2707 | GEN_LDS(8u, 0x02, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2708 | /* lha lhau lhaux lhax */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2709 | GEN_LDS(16s, 0x0A, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2710 | /* lhz lhzu lhzux lhzx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2711 | GEN_LDS(16u, 0x08, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2712 | /* lwz lwzu lwzux lwzx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2713 | GEN_LDS(32u, 0x00, PPC_INTEGER); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2714 | #if defined(TARGET_PPC64) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2715 | /* lwaux */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2716 | GEN_LDUX(32s, 0x15, 0x0B, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2717 | /* lwax */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2718 | GEN_LDX(32s, 0x15, 0x0A, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2719 | /* ldux */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2720 | GEN_LDUX(64, 0x15, 0x01, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2721 | /* ldx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2722 | GEN_LDX(64, 0x15, 0x00, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2723 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B) |
| 2724 | { |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2725 | TCGv EA; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2726 | if (Rc(ctx->opcode)) { |
| 2727 | if (unlikely(rA(ctx->opcode) == 0 || |
| 2728 | rA(ctx->opcode) == rD(ctx->opcode))) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2729 | GEN_EXCP_INVAL(ctx); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2730 | return; |
| 2731 | } |
| 2732 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2733 | EA = tcg_temp_new(TCG_TYPE_TL); |
| 2734 | gen_addr_imm_index(EA, ctx, 0x03); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2735 | if (ctx->opcode & 0x02) { |
| 2736 | /* lwa (lwau is undefined) */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2737 | gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2738 | } else { |
| 2739 | /* ld - ldu */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2740 | gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2741 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2742 | if (Rc(ctx->opcode)) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2743 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
| 2744 | tcg_temp_free(EA); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2745 | } |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2746 | /* lq */ |
| 2747 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) |
| 2748 | { |
| 2749 | #if defined(CONFIG_USER_ONLY) |
| 2750 | GEN_EXCP_PRIVOPC(ctx); |
| 2751 | #else |
| 2752 | int ra, rd; |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2753 | TCGv EA; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2754 | |
| 2755 | /* Restore CPU state */ |
| 2756 | if (unlikely(ctx->supervisor == 0)) { |
| 2757 | GEN_EXCP_PRIVOPC(ctx); |
| 2758 | return; |
| 2759 | } |
| 2760 | ra = rA(ctx->opcode); |
| 2761 | rd = rD(ctx->opcode); |
| 2762 | if (unlikely((rd & 1) || rd == ra)) { |
| 2763 | GEN_EXCP_INVAL(ctx); |
| 2764 | return; |
| 2765 | } |
| 2766 | if (unlikely(ctx->mem_idx & 1)) { |
| 2767 | /* Little-endian mode is not handled */ |
| 2768 | GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
| 2769 | return; |
| 2770 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2771 | EA = tcg_temp_new(TCG_TYPE_TL); |
| 2772 | gen_addr_imm_index(EA, ctx, 0x0F); |
| 2773 | gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx); |
| 2774 | tcg_gen_addi_tl(EA, EA, 8); |
| 2775 | gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx); |
| 2776 | tcg_temp_free(EA); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2777 | #endif |
| 2778 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2779 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2780 | |
| 2781 | /*** Integer store ***/ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2782 | #define GEN_ST(width, opc, type) \ |
| 2783 | GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2784 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2785 | TCGv EA = tcg_temp_new(TCG_TYPE_TL); \ |
| 2786 | gen_addr_imm_index(EA, ctx, 0); \ |
| 2787 | gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ |
| 2788 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2789 | } |
| 2790 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2791 | #define GEN_STU(width, opc, type) \ |
| 2792 | GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2793 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2794 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2795 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2796 | GEN_EXCP_INVAL(ctx); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2797 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2798 | } \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2799 | EA = tcg_temp_new(TCG_TYPE_TL); \ |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 2800 | if (type == PPC_64B) \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2801 | gen_addr_imm_index(EA, ctx, 0x03); \ |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 2802 | else \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2803 | gen_addr_imm_index(EA, ctx, 0); \ |
| 2804 | gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ |
| 2805 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 2806 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2807 | } |
| 2808 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2809 | #define GEN_STUX(width, opc2, opc3, type) \ |
| 2810 | GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2811 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2812 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2813 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2814 | GEN_EXCP_INVAL(ctx); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2815 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2816 | } \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2817 | EA = tcg_temp_new(TCG_TYPE_TL); \ |
| 2818 | gen_addr_reg_index(EA, ctx); \ |
| 2819 | gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ |
| 2820 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 2821 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2822 | } |
| 2823 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2824 | #define GEN_STX(width, opc2, opc3, type) \ |
| 2825 | GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2826 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2827 | TCGv EA = tcg_temp_new(TCG_TYPE_TL); \ |
| 2828 | gen_addr_reg_index(EA, ctx); \ |
| 2829 | gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ |
| 2830 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2831 | } |
| 2832 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2833 | #define GEN_STS(width, op, type) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2834 | GEN_ST(width, op | 0x20, type); \ |
| 2835 | GEN_STU(width, op | 0x21, type); \ |
| 2836 | GEN_STUX(width, 0x17, op | 0x01, type); \ |
| 2837 | GEN_STX(width, 0x17, op | 0x00, type) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2838 | |
| 2839 | /* stb stbu stbux stbx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2840 | GEN_STS(8, 0x06, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2841 | /* sth sthu sthux sthx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2842 | GEN_STS(16, 0x0C, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2843 | /* stw stwu stwux stwx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2844 | GEN_STS(32, 0x04, PPC_INTEGER); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2845 | #if defined(TARGET_PPC64) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2846 | GEN_STUX(64, 0x15, 0x05, PPC_64B); |
| 2847 | GEN_STX(64, 0x15, 0x04, PPC_64B); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2848 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2849 | { |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2850 | int rs; |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2851 | TCGv EA; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2852 | |
| 2853 | rs = rS(ctx->opcode); |
| 2854 | if ((ctx->opcode & 0x3) == 0x2) { |
| 2855 | #if defined(CONFIG_USER_ONLY) |
| 2856 | GEN_EXCP_PRIVOPC(ctx); |
| 2857 | #else |
| 2858 | /* stq */ |
| 2859 | if (unlikely(ctx->supervisor == 0)) { |
| 2860 | GEN_EXCP_PRIVOPC(ctx); |
| 2861 | return; |
| 2862 | } |
| 2863 | if (unlikely(rs & 1)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2864 | GEN_EXCP_INVAL(ctx); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2865 | return; |
| 2866 | } |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2867 | if (unlikely(ctx->mem_idx & 1)) { |
| 2868 | /* Little-endian mode is not handled */ |
| 2869 | GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
| 2870 | return; |
| 2871 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2872 | EA = tcg_temp_new(TCG_TYPE_TL); |
| 2873 | gen_addr_imm_index(EA, ctx, 0x03); |
| 2874 | gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx); |
| 2875 | tcg_gen_addi_tl(EA, EA, 8); |
| 2876 | gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx); |
| 2877 | tcg_temp_free(EA); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2878 | #endif |
| 2879 | } else { |
| 2880 | /* std / stdu */ |
| 2881 | if (Rc(ctx->opcode)) { |
| 2882 | if (unlikely(rA(ctx->opcode) == 0)) { |
| 2883 | GEN_EXCP_INVAL(ctx); |
| 2884 | return; |
| 2885 | } |
| 2886 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2887 | EA = tcg_temp_new(TCG_TYPE_TL); |
| 2888 | gen_addr_imm_index(EA, ctx, 0x03); |
| 2889 | gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2890 | if (Rc(ctx->opcode)) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2891 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
| 2892 | tcg_temp_free(EA); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2893 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2894 | } |
| 2895 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2896 | /*** Integer load and store with byte reverse ***/ |
| 2897 | /* lhbrx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2898 | void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags) |
| 2899 | { |
| 2900 | TCGv temp = tcg_temp_new(TCG_TYPE_I32); |
| 2901 | gen_qemu_ld16u(temp, t1, flags); |
| 2902 | tcg_gen_bswap16_i32(temp, temp); |
| 2903 | tcg_gen_extu_i32_tl(t0, temp); |
| 2904 | tcg_temp_free(temp); |
| 2905 | } |
| 2906 | GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER); |
| 2907 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2908 | /* lwbrx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2909 | void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags) |
| 2910 | { |
| 2911 | TCGv temp = tcg_temp_new(TCG_TYPE_I32); |
| 2912 | gen_qemu_ld32u(temp, t1, flags); |
| 2913 | tcg_gen_bswap_i32(temp, temp); |
| 2914 | tcg_gen_extu_i32_tl(t0, temp); |
| 2915 | tcg_temp_free(temp); |
| 2916 | } |
| 2917 | GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER); |
| 2918 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2919 | /* sthbrx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2920 | void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags) |
| 2921 | { |
| 2922 | TCGv temp = tcg_temp_new(TCG_TYPE_I32); |
| 2923 | tcg_gen_trunc_tl_i32(temp, t0); |
| 2924 | tcg_gen_ext16u_i32(temp, temp); |
| 2925 | tcg_gen_bswap16_i32(temp, temp); |
| 2926 | gen_qemu_st16(temp, t1, flags); |
| 2927 | tcg_temp_free(temp); |
| 2928 | } |
| 2929 | GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER); |
| 2930 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2931 | /* stwbrx */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2932 | void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags) |
| 2933 | { |
| 2934 | TCGv temp = tcg_temp_new(TCG_TYPE_I32); |
| 2935 | tcg_gen_trunc_tl_i32(temp, t0); |
| 2936 | tcg_gen_bswap_i32(temp, temp); |
| 2937 | gen_qemu_st32(temp, t1, flags); |
| 2938 | tcg_temp_free(temp); |
| 2939 | } |
| 2940 | GEN_STX(32r, 0x16, 0x14, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2941 | |
| 2942 | /*** Integer load and store multiple ***/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2943 | #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg) |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2944 | static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = { |
| 2945 | GEN_MEM_FUNCS(lmw), |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 2946 | }; |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2947 | static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = { |
| 2948 | GEN_MEM_FUNCS(stmw), |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 2949 | }; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2950 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2951 | /* lmw */ |
| 2952 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 2953 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2954 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2955 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2956 | gen_addr_imm_index(cpu_T[0], ctx, 0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2957 | op_ldstm(lmw, rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2958 | } |
| 2959 | |
| 2960 | /* stmw */ |
| 2961 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 2962 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2963 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2964 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2965 | gen_addr_imm_index(cpu_T[0], ctx, 0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2966 | op_ldstm(stmw, rS(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2967 | } |
| 2968 | |
| 2969 | /*** Integer load and store strings ***/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2970 | #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start) |
| 2971 | #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb) |
j_mayer | e7c2400 | 2007-11-22 11:00:46 +0000 | [diff] [blame] | 2972 | /* string load & stores are by definition endian-safe */ |
| 2973 | #define gen_op_lswi_le_raw gen_op_lswi_raw |
| 2974 | #define gen_op_lswi_le_user gen_op_lswi_user |
| 2975 | #define gen_op_lswi_le_kernel gen_op_lswi_kernel |
| 2976 | #define gen_op_lswi_le_hypv gen_op_lswi_hypv |
| 2977 | #define gen_op_lswi_le_64_raw gen_op_lswi_raw |
| 2978 | #define gen_op_lswi_le_64_user gen_op_lswi_user |
| 2979 | #define gen_op_lswi_le_64_kernel gen_op_lswi_kernel |
| 2980 | #define gen_op_lswi_le_64_hypv gen_op_lswi_hypv |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2981 | static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = { |
| 2982 | GEN_MEM_FUNCS(lswi), |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2983 | }; |
j_mayer | e7c2400 | 2007-11-22 11:00:46 +0000 | [diff] [blame] | 2984 | #define gen_op_lswx_le_raw gen_op_lswx_raw |
| 2985 | #define gen_op_lswx_le_user gen_op_lswx_user |
| 2986 | #define gen_op_lswx_le_kernel gen_op_lswx_kernel |
| 2987 | #define gen_op_lswx_le_hypv gen_op_lswx_hypv |
| 2988 | #define gen_op_lswx_le_64_raw gen_op_lswx_raw |
| 2989 | #define gen_op_lswx_le_64_user gen_op_lswx_user |
| 2990 | #define gen_op_lswx_le_64_kernel gen_op_lswx_kernel |
| 2991 | #define gen_op_lswx_le_64_hypv gen_op_lswx_hypv |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2992 | static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = { |
| 2993 | GEN_MEM_FUNCS(lswx), |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2994 | }; |
j_mayer | e7c2400 | 2007-11-22 11:00:46 +0000 | [diff] [blame] | 2995 | #define gen_op_stsw_le_raw gen_op_stsw_raw |
| 2996 | #define gen_op_stsw_le_user gen_op_stsw_user |
| 2997 | #define gen_op_stsw_le_kernel gen_op_stsw_kernel |
| 2998 | #define gen_op_stsw_le_hypv gen_op_stsw_hypv |
| 2999 | #define gen_op_stsw_le_64_raw gen_op_stsw_raw |
| 3000 | #define gen_op_stsw_le_64_user gen_op_stsw_user |
| 3001 | #define gen_op_stsw_le_64_kernel gen_op_stsw_kernel |
| 3002 | #define gen_op_stsw_le_64_hypv gen_op_stsw_hypv |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3003 | static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = { |
| 3004 | GEN_MEM_FUNCS(stsw), |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3005 | }; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3006 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3007 | /* lswi */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3008 | /* PowerPC32 specification says we must generate an exception if |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3009 | * rA is in the range of registers to be loaded. |
| 3010 | * In an other hand, IBM says this is valid, but rA won't be loaded. |
| 3011 | * For now, I'll follow the spec... |
| 3012 | */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 3013 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3014 | { |
| 3015 | int nb = NB(ctx->opcode); |
| 3016 | int start = rD(ctx->opcode); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3017 | int ra = rA(ctx->opcode); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3018 | int nr; |
| 3019 | |
| 3020 | if (nb == 0) |
| 3021 | nb = 32; |
| 3022 | nr = nb / 4; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3023 | if (unlikely(((start + nr) > 32 && |
| 3024 | start <= ra && (start + nr - 32) > ra) || |
| 3025 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3026 | GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, |
| 3027 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3028 | return; |
bellard | 297d8e6 | 2004-02-21 14:11:27 +0000 | [diff] [blame] | 3029 | } |
bellard | 8dd4983 | 2005-06-04 22:22:27 +0000 | [diff] [blame] | 3030 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3031 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3032 | gen_addr_register(cpu_T[0], ctx); |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 3033 | tcg_gen_movi_tl(cpu_T[1], nb); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3034 | op_ldsts(lswi, start); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3035 | } |
| 3036 | |
| 3037 | /* lswx */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 3038 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3039 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3040 | int ra = rA(ctx->opcode); |
| 3041 | int rb = rB(ctx->opcode); |
| 3042 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3043 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3044 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3045 | gen_addr_reg_index(cpu_T[0], ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3046 | if (ra == 0) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3047 | ra = rb; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3048 | } |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 3049 | tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3050 | op_ldstsx(lswx, rD(ctx->opcode), ra, rb); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3051 | } |
| 3052 | |
| 3053 | /* stswi */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 3054 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3055 | { |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3056 | int nb = NB(ctx->opcode); |
| 3057 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3058 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3059 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3060 | gen_addr_register(cpu_T[0], ctx); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3061 | if (nb == 0) |
| 3062 | nb = 32; |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 3063 | tcg_gen_movi_tl(cpu_T[1], nb); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3064 | op_ldsts(stsw, rS(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3065 | } |
| 3066 | |
| 3067 | /* stswx */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 3068 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3069 | { |
bellard | 8dd4983 | 2005-06-04 22:22:27 +0000 | [diff] [blame] | 3070 | /* NIP cannot be restored if the memory exception comes from an helper */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3071 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3072 | gen_addr_reg_index(cpu_T[0], ctx); |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 3073 | tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3074 | op_ldsts(stsw, rS(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3075 | } |
| 3076 | |
| 3077 | /*** Memory synchronisation ***/ |
| 3078 | /* eieio */ |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3079 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3080 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3081 | } |
| 3082 | |
| 3083 | /* isync */ |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3084 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3085 | { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3086 | GEN_STOP(ctx); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3087 | } |
| 3088 | |
bellard | 985a19d | 2004-01-18 22:49:57 +0000 | [diff] [blame] | 3089 | #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])() |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 3090 | #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])() |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3091 | static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = { |
| 3092 | GEN_MEM_FUNCS(lwarx), |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3093 | }; |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3094 | static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = { |
| 3095 | GEN_MEM_FUNCS(stwcx), |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3096 | }; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3097 | |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 3098 | /* lwarx */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3099 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3100 | { |
j_mayer | 30032c9 | 2007-10-01 05:22:17 +0000 | [diff] [blame] | 3101 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 3102 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3103 | gen_addr_reg_index(cpu_T[0], ctx); |
bellard | 985a19d | 2004-01-18 22:49:57 +0000 | [diff] [blame] | 3104 | op_lwarx(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3105 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3106 | } |
| 3107 | |
| 3108 | /* stwcx. */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 3109 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3110 | { |
j_mayer | 30032c9 | 2007-10-01 05:22:17 +0000 | [diff] [blame] | 3111 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 3112 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3113 | gen_addr_reg_index(cpu_T[0], ctx); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3114 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3115 | op_stwcx(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3116 | } |
| 3117 | |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3118 | #if defined(TARGET_PPC64) |
| 3119 | #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])() |
| 3120 | #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])() |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3121 | static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = { |
| 3122 | GEN_MEM_FUNCS(ldarx), |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3123 | }; |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3124 | static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = { |
| 3125 | GEN_MEM_FUNCS(stdcx), |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3126 | }; |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3127 | |
| 3128 | /* ldarx */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 3129 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3130 | { |
j_mayer | 30032c9 | 2007-10-01 05:22:17 +0000 | [diff] [blame] | 3131 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 3132 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3133 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3134 | op_ldarx(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3135 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3136 | } |
| 3137 | |
| 3138 | /* stdcx. */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 3139 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3140 | { |
j_mayer | 30032c9 | 2007-10-01 05:22:17 +0000 | [diff] [blame] | 3141 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 3142 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3143 | gen_addr_reg_index(cpu_T[0], ctx); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3144 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3145 | op_stdcx(); |
| 3146 | } |
| 3147 | #endif /* defined(TARGET_PPC64) */ |
| 3148 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3149 | /* sync */ |
j_mayer | a902d88 | 2007-09-30 15:21:15 +0000 | [diff] [blame] | 3150 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3151 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3152 | } |
| 3153 | |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3154 | /* wait */ |
| 3155 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT) |
| 3156 | { |
| 3157 | /* Stop translation, as the CPU is supposed to sleep from now */ |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3158 | gen_op_wait(); |
| 3159 | GEN_EXCP(ctx, EXCP_HLT, 1); |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3160 | } |
| 3161 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3162 | /*** Floating-point load ***/ |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3163 | #define GEN_LDF(width, opc, type) \ |
| 3164 | GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3165 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3166 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3167 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3168 | return; \ |
| 3169 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3170 | gen_addr_imm_index(cpu_T[0], ctx, 0); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3171 | op_ldst(l##width); \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 3172 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3173 | } |
| 3174 | |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3175 | #define GEN_LDUF(width, opc, type) \ |
| 3176 | GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3177 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3178 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3179 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3180 | return; \ |
| 3181 | } \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3182 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3183 | GEN_EXCP_INVAL(ctx); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3184 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3185 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3186 | gen_addr_imm_index(cpu_T[0], ctx, 0); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3187 | op_ldst(l##width); \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 3188 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3189 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3190 | } |
| 3191 | |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3192 | #define GEN_LDUXF(width, opc, type) \ |
| 3193 | GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3194 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3195 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3196 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3197 | return; \ |
| 3198 | } \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3199 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3200 | GEN_EXCP_INVAL(ctx); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3201 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3202 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3203 | gen_addr_reg_index(cpu_T[0], ctx); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3204 | op_ldst(l##width); \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 3205 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3206 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3207 | } |
| 3208 | |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3209 | #define GEN_LDXF(width, opc2, opc3, type) \ |
| 3210 | GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3211 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3212 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3213 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3214 | return; \ |
| 3215 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3216 | gen_addr_reg_index(cpu_T[0], ctx); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3217 | op_ldst(l##width); \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 3218 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3219 | } |
| 3220 | |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3221 | #define GEN_LDFS(width, op, type) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3222 | OP_LD_TABLE(width); \ |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3223 | GEN_LDF(width, op | 0x20, type); \ |
| 3224 | GEN_LDUF(width, op | 0x21, type); \ |
| 3225 | GEN_LDUXF(width, op | 0x01, type); \ |
| 3226 | GEN_LDXF(width, 0x17, op | 0x00, type) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3227 | |
| 3228 | /* lfd lfdu lfdux lfdx */ |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3229 | GEN_LDFS(fd, 0x12, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3230 | /* lfs lfsu lfsux lfsx */ |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3231 | GEN_LDFS(fs, 0x10, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3232 | |
| 3233 | /*** Floating-point store ***/ |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3234 | #define GEN_STF(width, opc, type) \ |
| 3235 | GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3236 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3237 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3238 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3239 | return; \ |
| 3240 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3241 | gen_addr_imm_index(cpu_T[0], ctx, 0); \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 3242 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3243 | op_ldst(st##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3244 | } |
| 3245 | |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3246 | #define GEN_STUF(width, opc, type) \ |
| 3247 | GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3248 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3249 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3250 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3251 | return; \ |
| 3252 | } \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3253 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3254 | GEN_EXCP_INVAL(ctx); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3255 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3256 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3257 | gen_addr_imm_index(cpu_T[0], ctx, 0); \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 3258 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3259 | op_ldst(st##width); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3260 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3261 | } |
| 3262 | |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3263 | #define GEN_STUXF(width, opc, type) \ |
| 3264 | GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3265 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3266 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3267 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3268 | return; \ |
| 3269 | } \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3270 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3271 | GEN_EXCP_INVAL(ctx); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3272 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3273 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3274 | gen_addr_reg_index(cpu_T[0], ctx); \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 3275 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3276 | op_ldst(st##width); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3277 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3278 | } |
| 3279 | |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3280 | #define GEN_STXF(width, opc2, opc3, type) \ |
| 3281 | GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3282 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3283 | if (unlikely(!ctx->fpu_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3284 | GEN_EXCP_NO_FP(ctx); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3285 | return; \ |
| 3286 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 3287 | gen_addr_reg_index(cpu_T[0], ctx); \ |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 3288 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3289 | op_ldst(st##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3290 | } |
| 3291 | |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3292 | #define GEN_STFS(width, op, type) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3293 | OP_ST_TABLE(width); \ |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3294 | GEN_STF(width, op | 0x20, type); \ |
| 3295 | GEN_STUF(width, op | 0x21, type); \ |
| 3296 | GEN_STUXF(width, op | 0x01, type); \ |
| 3297 | GEN_STXF(width, 0x17, op | 0x00, type) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3298 | |
| 3299 | /* stfd stfdu stfdux stfdx */ |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3300 | GEN_STFS(fd, 0x16, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3301 | /* stfs stfsu stfsux stfsx */ |
j_mayer | 477023a | 2007-09-30 01:01:08 +0000 | [diff] [blame] | 3302 | GEN_STFS(fs, 0x14, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3303 | |
| 3304 | /* Optional: */ |
| 3305 | /* stfiwx */ |
j_mayer | 5b8105f | 2007-11-19 11:39:29 +0000 | [diff] [blame] | 3306 | OP_ST_TABLE(fiw); |
| 3307 | GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3308 | |
| 3309 | /*** Branch ***/ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 3310 | static always_inline void gen_goto_tb (DisasContext *ctx, int n, |
| 3311 | target_ulong dest) |
bellard | c53be33 | 2005-10-30 21:39:19 +0000 | [diff] [blame] | 3312 | { |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 3313 | TranslationBlock *tb; |
| 3314 | tb = ctx->tb; |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3315 | #if defined(TARGET_PPC64) |
| 3316 | if (!ctx->sf_mode) |
| 3317 | dest = (uint32_t) dest; |
| 3318 | #endif |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3319 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3320 | likely(!ctx->singlestep_enabled)) { |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3321 | tcg_gen_goto_tb(n); |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3322 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3323 | tcg_gen_exit_tb((long)tb + n); |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 3324 | } else { |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3325 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3326 | if (unlikely(ctx->singlestep_enabled)) { |
| 3327 | if ((ctx->singlestep_enabled & |
| 3328 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
| 3329 | ctx->exception == POWERPC_EXCP_BRANCH) { |
| 3330 | target_ulong tmp = ctx->nip; |
| 3331 | ctx->nip = dest; |
| 3332 | GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0); |
| 3333 | ctx->nip = tmp; |
| 3334 | } |
| 3335 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { |
| 3336 | gen_update_nip(ctx, dest); |
| 3337 | gen_op_debug(); |
| 3338 | } |
| 3339 | } |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3340 | tcg_gen_exit_tb(0); |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 3341 | } |
bellard | c53be33 | 2005-10-30 21:39:19 +0000 | [diff] [blame] | 3342 | } |
| 3343 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 3344 | static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3345 | { |
| 3346 | #if defined(TARGET_PPC64) |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3347 | if (ctx->sf_mode == 0) |
| 3348 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3349 | else |
| 3350 | #endif |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3351 | tcg_gen_movi_tl(cpu_lr, nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3352 | } |
| 3353 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3354 | /* b ba bl bla */ |
| 3355 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
| 3356 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3357 | target_ulong li, target; |
bellard | 38a64f9 | 2004-07-07 22:06:01 +0000 | [diff] [blame] | 3358 | |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3359 | ctx->exception = POWERPC_EXCP_BRANCH; |
bellard | 38a64f9 | 2004-07-07 22:06:01 +0000 | [diff] [blame] | 3360 | /* sign extend LI */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3361 | #if defined(TARGET_PPC64) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3362 | if (ctx->sf_mode) |
| 3363 | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; |
| 3364 | else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3365 | #endif |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3366 | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3367 | if (likely(AA(ctx->opcode) == 0)) |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3368 | target = ctx->nip + li - 4; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3369 | else |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3370 | target = li; |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3371 | if (LK(ctx->opcode)) |
| 3372 | gen_setlr(ctx, ctx->nip); |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 3373 | gen_goto_tb(ctx, 0, target); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3374 | } |
| 3375 | |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3376 | #define BCOND_IM 0 |
| 3377 | #define BCOND_LR 1 |
| 3378 | #define BCOND_CTR 2 |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3379 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 3380 | static always_inline void gen_bcond (DisasContext *ctx, int type) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3381 | { |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3382 | uint32_t bo = BO(ctx->opcode); |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3383 | int l1 = gen_new_label(); |
| 3384 | TCGv target; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3385 | |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3386 | ctx->exception = POWERPC_EXCP_BRANCH; |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3387 | if (type == BCOND_LR || type == BCOND_CTR) { |
| 3388 | target = tcg_temp_local_new(TCG_TYPE_TL); |
| 3389 | if (type == BCOND_CTR) |
| 3390 | tcg_gen_mov_tl(target, cpu_ctr); |
| 3391 | else |
| 3392 | tcg_gen_mov_tl(target, cpu_lr); |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3393 | } |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3394 | if (LK(ctx->opcode)) |
| 3395 | gen_setlr(ctx, ctx->nip); |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3396 | l1 = gen_new_label(); |
| 3397 | if ((bo & 0x4) == 0) { |
| 3398 | /* Decrement and test CTR */ |
| 3399 | TCGv temp = tcg_temp_new(TCG_TYPE_TL); |
| 3400 | if (unlikely(type == BCOND_CTR)) { |
| 3401 | GEN_EXCP_INVAL(ctx); |
| 3402 | return; |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3403 | } |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3404 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3405 | #if defined(TARGET_PPC64) |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3406 | if (!ctx->sf_mode) |
| 3407 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
| 3408 | else |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3409 | #endif |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3410 | tcg_gen_mov_tl(temp, cpu_ctr); |
| 3411 | if (bo & 0x2) { |
| 3412 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3413 | } else { |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3414 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); |
| 3415 | } |
| 3416 | } |
| 3417 | if ((bo & 0x10) == 0) { |
| 3418 | /* Test CR */ |
| 3419 | uint32_t bi = BI(ctx->opcode); |
| 3420 | uint32_t mask = 1 << (3 - (bi & 0x03)); |
| 3421 | TCGv temp = tcg_temp_new(TCG_TYPE_I32); |
| 3422 | |
| 3423 | if (bo & 0x8) { |
| 3424 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
| 3425 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); |
| 3426 | } else { |
| 3427 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
| 3428 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3429 | } |
| 3430 | } |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3431 | if (type == BCOND_IM) { |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3432 | |
| 3433 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
| 3434 | if (likely(AA(ctx->opcode) == 0)) { |
| 3435 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); |
| 3436 | } else { |
| 3437 | gen_goto_tb(ctx, 0, li); |
| 3438 | } |
bellard | c53be33 | 2005-10-30 21:39:19 +0000 | [diff] [blame] | 3439 | gen_set_label(l1); |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 3440 | gen_goto_tb(ctx, 1, ctx->nip); |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3441 | } else { |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3442 | #if defined(TARGET_PPC64) |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3443 | if (!(ctx->sf_mode)) |
| 3444 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3445 | else |
| 3446 | #endif |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3447 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
| 3448 | tcg_gen_exit_tb(0); |
| 3449 | gen_set_label(l1); |
| 3450 | #if defined(TARGET_PPC64) |
| 3451 | if (!(ctx->sf_mode)) |
| 3452 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); |
| 3453 | else |
| 3454 | #endif |
| 3455 | tcg_gen_movi_tl(cpu_nip, ctx->nip); |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3456 | tcg_gen_exit_tb(0); |
j_mayer | 08e46e5 | 2007-04-16 07:18:42 +0000 | [diff] [blame] | 3457 | } |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3458 | } |
| 3459 | |
| 3460 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3461 | { |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3462 | gen_bcond(ctx, BCOND_IM); |
| 3463 | } |
| 3464 | |
| 3465 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW) |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3466 | { |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3467 | gen_bcond(ctx, BCOND_CTR); |
| 3468 | } |
| 3469 | |
| 3470 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW) |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3471 | { |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3472 | gen_bcond(ctx, BCOND_LR); |
| 3473 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3474 | |
| 3475 | /*** Condition register logical ***/ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3476 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
| 3477 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3478 | { \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3479 | uint8_t bitmask; \ |
| 3480 | int sh; \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3481 | TCGv temp1, temp2; \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3482 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3483 | temp1 = tcg_temp_new(TCG_TYPE_I32); \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3484 | if (sh > 0) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3485 | tcg_gen_shri_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3486 | else if (sh < 0) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3487 | tcg_gen_shli_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
| 3488 | else \ |
pbrook | 2e31f5d | 2008-10-24 12:03:16 +0000 | [diff] [blame] | 3489 | tcg_gen_mov_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3490 | temp2 = tcg_temp_new(TCG_TYPE_I32); \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3491 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
| 3492 | if (sh > 0) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3493 | tcg_gen_shri_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3494 | else if (sh < 0) \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3495 | tcg_gen_shli_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
| 3496 | else \ |
| 3497 | tcg_gen_mov_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
| 3498 | tcg_op(temp1, temp1, temp2); \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3499 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3500 | tcg_gen_andi_i32(temp1, temp1, bitmask); \ |
| 3501 | tcg_gen_andi_i32(temp2, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ |
| 3502 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], temp1, temp2); \ |
| 3503 | tcg_temp_free(temp1); \ |
| 3504 | tcg_temp_free(temp2); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3505 | } |
| 3506 | |
| 3507 | /* crand */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3508 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3509 | /* crandc */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3510 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3511 | /* creqv */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3512 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3513 | /* crnand */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3514 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3515 | /* crnor */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3516 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3517 | /* cror */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3518 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3519 | /* crorc */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3520 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3521 | /* crxor */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3522 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3523 | /* mcrf */ |
| 3524 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER) |
| 3525 | { |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 3526 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3527 | } |
| 3528 | |
| 3529 | /*** System linkage ***/ |
| 3530 | /* rfi (supervisor only) */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3531 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3532 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3533 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3534 | GEN_EXCP_PRIVOPC(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3535 | #else |
| 3536 | /* Restore CPU state */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3537 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3538 | GEN_EXCP_PRIVOPC(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3539 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3540 | } |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 3541 | gen_op_rfi(); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3542 | GEN_SYNC(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3543 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3544 | } |
| 3545 | |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3546 | #if defined(TARGET_PPC64) |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 3547 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3548 | { |
| 3549 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3550 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3551 | #else |
| 3552 | /* Restore CPU state */ |
| 3553 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3554 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3555 | return; |
| 3556 | } |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 3557 | gen_op_rfid(); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3558 | GEN_SYNC(ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3559 | #endif |
| 3560 | } |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3561 | |
j_mayer | 5b8105f | 2007-11-19 11:39:29 +0000 | [diff] [blame] | 3562 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H) |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3563 | { |
| 3564 | #if defined(CONFIG_USER_ONLY) |
| 3565 | GEN_EXCP_PRIVOPC(ctx); |
| 3566 | #else |
| 3567 | /* Restore CPU state */ |
| 3568 | if (unlikely(ctx->supervisor <= 1)) { |
| 3569 | GEN_EXCP_PRIVOPC(ctx); |
| 3570 | return; |
| 3571 | } |
| 3572 | gen_op_hrfid(); |
| 3573 | GEN_SYNC(ctx); |
| 3574 | #endif |
| 3575 | } |
| 3576 | #endif |
| 3577 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3578 | /* sc */ |
j_mayer | 417bf01 | 2007-10-07 23:10:08 +0000 | [diff] [blame] | 3579 | #if defined(CONFIG_USER_ONLY) |
| 3580 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER |
| 3581 | #else |
| 3582 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL |
| 3583 | #endif |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3584 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3585 | { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3586 | uint32_t lev; |
| 3587 | |
| 3588 | lev = (ctx->opcode >> 5) & 0x7F; |
j_mayer | 417bf01 | 2007-10-07 23:10:08 +0000 | [diff] [blame] | 3589 | GEN_EXCP(ctx, POWERPC_SYSCALL, lev); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3590 | } |
| 3591 | |
| 3592 | /*** Trap ***/ |
| 3593 | /* tw */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3594 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3595 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3596 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 3597 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
ths | a0ae05a | 2007-01-05 16:54:16 +0000 | [diff] [blame] | 3598 | /* Update the nip since this might generate a trap exception */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3599 | gen_update_nip(ctx, ctx->nip); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3600 | gen_op_tw(TO(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3601 | } |
| 3602 | |
| 3603 | /* twi */ |
| 3604 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
| 3605 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3606 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
aurel32 | 02f4f6c | 2008-09-02 16:18:55 +0000 | [diff] [blame] | 3607 | tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3608 | /* Update the nip since this might generate a trap exception */ |
| 3609 | gen_update_nip(ctx, ctx->nip); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3610 | gen_op_tw(TO(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3611 | } |
| 3612 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3613 | #if defined(TARGET_PPC64) |
| 3614 | /* td */ |
| 3615 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) |
| 3616 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3617 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 3618 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3619 | /* Update the nip since this might generate a trap exception */ |
| 3620 | gen_update_nip(ctx, ctx->nip); |
| 3621 | gen_op_td(TO(ctx->opcode)); |
| 3622 | } |
| 3623 | |
| 3624 | /* tdi */ |
| 3625 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) |
| 3626 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3627 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
aurel32 | 02f4f6c | 2008-09-02 16:18:55 +0000 | [diff] [blame] | 3628 | tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3629 | /* Update the nip since this might generate a trap exception */ |
| 3630 | gen_update_nip(ctx, ctx->nip); |
| 3631 | gen_op_td(TO(ctx->opcode)); |
| 3632 | } |
| 3633 | #endif |
| 3634 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3635 | /*** Processor control ***/ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3636 | /* mcrxr */ |
| 3637 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC) |
| 3638 | { |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 3639 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer); |
| 3640 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 3641 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3642 | } |
| 3643 | |
| 3644 | /* mfcr */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3645 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3646 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3647 | uint32_t crm, crn; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3648 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3649 | if (likely(ctx->opcode & 0x00100000)) { |
| 3650 | crm = CRM(ctx->opcode); |
| 3651 | if (likely((crm ^ (crm - 1)) == 0)) { |
| 3652 | crn = ffs(crm); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3653 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3654 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3655 | } else { |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3656 | tcg_gen_helper_1_0(helper_load_cr, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3657 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3658 | } |
| 3659 | |
| 3660 | /* mfmsr */ |
| 3661 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC) |
| 3662 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3663 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3664 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3665 | #else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3666 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3667 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3668 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3669 | } |
aurel32 | 6676f42 | 2008-08-24 23:16:35 +0000 | [diff] [blame] | 3670 | gen_op_load_msr(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3671 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3672 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3673 | } |
| 3674 | |
j_mayer | a11b815 | 2007-10-28 00:55:05 +0000 | [diff] [blame] | 3675 | #if 1 |
j_mayer | 6f2d897 | 2007-11-12 00:04:48 +0000 | [diff] [blame] | 3676 | #define SPR_NOACCESS ((void *)(-1UL)) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3677 | #else |
| 3678 | static void spr_noaccess (void *opaque, int sprn) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3679 | { |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3680 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
| 3681 | printf("ERROR: try to access SPR %d !\n", sprn); |
| 3682 | } |
| 3683 | #define SPR_NOACCESS (&spr_noaccess) |
| 3684 | #endif |
| 3685 | |
| 3686 | /* mfspr */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 3687 | static always_inline void gen_op_mfspr (DisasContext *ctx) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3688 | { |
| 3689 | void (*read_cb)(void *opaque, int sprn); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3690 | uint32_t sprn = SPR(ctx->opcode); |
| 3691 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3692 | #if !defined(CONFIG_USER_ONLY) |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3693 | if (ctx->supervisor == 2) |
| 3694 | read_cb = ctx->spr_cb[sprn].hea_read; |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3695 | else if (ctx->supervisor) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3696 | read_cb = ctx->spr_cb[sprn].oea_read; |
| 3697 | else |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3698 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3699 | read_cb = ctx->spr_cb[sprn].uea_read; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3700 | if (likely(read_cb != NULL)) { |
| 3701 | if (likely(read_cb != SPR_NOACCESS)) { |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3702 | (*read_cb)(ctx, sprn); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3703 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3704 | } else { |
| 3705 | /* Privilege exception */ |
j_mayer | 9fceefa | 2007-11-02 22:47:50 +0000 | [diff] [blame] | 3706 | /* This is a hack to avoid warnings when running Linux: |
| 3707 | * this OS breaks the PowerPC virtualisation model, |
| 3708 | * allowing userland application to read the PVR |
| 3709 | */ |
| 3710 | if (sprn != SPR_PVR) { |
| 3711 | if (loglevel != 0) { |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 3712 | fprintf(logfile, "Trying to read privileged spr %d %03x at " |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 3713 | ADDRX "\n", sprn, sprn, ctx->nip); |
j_mayer | 9fceefa | 2007-11-02 22:47:50 +0000 | [diff] [blame] | 3714 | } |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 3715 | printf("Trying to read privileged spr %d %03x at " ADDRX "\n", |
| 3716 | sprn, sprn, ctx->nip); |
bellard | f24e569 | 2005-11-23 21:36:30 +0000 | [diff] [blame] | 3717 | } |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3718 | GEN_EXCP_PRIVREG(ctx); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3719 | } |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3720 | } else { |
| 3721 | /* Not defined */ |
j_mayer | 4a05771 | 2007-04-19 08:42:21 +0000 | [diff] [blame] | 3722 | if (loglevel != 0) { |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 3723 | fprintf(logfile, "Trying to read invalid spr %d %03x at " |
| 3724 | ADDRX "\n", sprn, sprn, ctx->nip); |
bellard | f24e569 | 2005-11-23 21:36:30 +0000 | [diff] [blame] | 3725 | } |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 3726 | printf("Trying to read invalid spr %d %03x at " ADDRX "\n", |
| 3727 | sprn, sprn, ctx->nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3728 | GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, |
| 3729 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3730 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3731 | } |
| 3732 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3733 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3734 | { |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3735 | gen_op_mfspr(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3736 | } |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3737 | |
| 3738 | /* mftb */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 3739 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3740 | { |
| 3741 | gen_op_mfspr(ctx); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3742 | } |
| 3743 | |
| 3744 | /* mtcrf */ |
bellard | 8dd4983 | 2005-06-04 22:22:27 +0000 | [diff] [blame] | 3745 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3746 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3747 | uint32_t crm, crn; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3748 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3749 | crm = CRM(ctx->opcode); |
| 3750 | if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) { |
| 3751 | crn = ffs(crm); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3752 | tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4); |
| 3753 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3754 | } else { |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3755 | TCGv temp = tcg_const_tl(crm); |
| 3756 | tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], temp); |
| 3757 | tcg_temp_free(temp); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3758 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3759 | } |
| 3760 | |
| 3761 | /* mtmsr */ |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3762 | #if defined(TARGET_PPC64) |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3763 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3764 | { |
| 3765 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3766 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3767 | #else |
| 3768 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3769 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3770 | return; |
| 3771 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3772 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3773 | if (ctx->opcode & 0x00010000) { |
| 3774 | /* Special form that does not need any synchronisation */ |
| 3775 | gen_op_update_riee(); |
| 3776 | } else { |
j_mayer | 056b05f | 2007-10-01 03:03:51 +0000 | [diff] [blame] | 3777 | /* XXX: we need to update nip before the store |
| 3778 | * if we enter power saving mode, we will exit the loop |
| 3779 | * directly from ppc_store_msr |
| 3780 | */ |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3781 | gen_update_nip(ctx, ctx->nip); |
aurel32 | 6676f42 | 2008-08-24 23:16:35 +0000 | [diff] [blame] | 3782 | gen_op_store_msr(); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3783 | /* Must stop the translation as machine state (may have) changed */ |
| 3784 | /* Note that mtmsr is not always defined as context-synchronizing */ |
j_mayer | 056b05f | 2007-10-01 03:03:51 +0000 | [diff] [blame] | 3785 | ctx->exception = POWERPC_EXCP_STOP; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3786 | } |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3787 | #endif |
| 3788 | } |
| 3789 | #endif |
| 3790 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3791 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) |
| 3792 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3793 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3794 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3795 | #else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3796 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3797 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3798 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3799 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3800 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3801 | if (ctx->opcode & 0x00010000) { |
| 3802 | /* Special form that does not need any synchronisation */ |
| 3803 | gen_op_update_riee(); |
| 3804 | } else { |
j_mayer | 056b05f | 2007-10-01 03:03:51 +0000 | [diff] [blame] | 3805 | /* XXX: we need to update nip before the store |
| 3806 | * if we enter power saving mode, we will exit the loop |
| 3807 | * directly from ppc_store_msr |
| 3808 | */ |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3809 | gen_update_nip(ctx, ctx->nip); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3810 | #if defined(TARGET_PPC64) |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3811 | if (!ctx->sf_mode) |
aurel32 | 6676f42 | 2008-08-24 23:16:35 +0000 | [diff] [blame] | 3812 | gen_op_store_msr_32(); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3813 | else |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3814 | #endif |
aurel32 | 6676f42 | 2008-08-24 23:16:35 +0000 | [diff] [blame] | 3815 | gen_op_store_msr(); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3816 | /* Must stop the translation as machine state (may have) changed */ |
| 3817 | /* Note that mtmsrd is not always defined as context-synchronizing */ |
j_mayer | 056b05f | 2007-10-01 03:03:51 +0000 | [diff] [blame] | 3818 | ctx->exception = POWERPC_EXCP_STOP; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3819 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3820 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3821 | } |
| 3822 | |
| 3823 | /* mtspr */ |
| 3824 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) |
| 3825 | { |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3826 | void (*write_cb)(void *opaque, int sprn); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3827 | uint32_t sprn = SPR(ctx->opcode); |
| 3828 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3829 | #if !defined(CONFIG_USER_ONLY) |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3830 | if (ctx->supervisor == 2) |
| 3831 | write_cb = ctx->spr_cb[sprn].hea_write; |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3832 | else if (ctx->supervisor) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3833 | write_cb = ctx->spr_cb[sprn].oea_write; |
| 3834 | else |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3835 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3836 | write_cb = ctx->spr_cb[sprn].uea_write; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3837 | if (likely(write_cb != NULL)) { |
| 3838 | if (likely(write_cb != SPR_NOACCESS)) { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 3839 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3840 | (*write_cb)(ctx, sprn); |
| 3841 | } else { |
| 3842 | /* Privilege exception */ |
j_mayer | 4a05771 | 2007-04-19 08:42:21 +0000 | [diff] [blame] | 3843 | if (loglevel != 0) { |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 3844 | fprintf(logfile, "Trying to write privileged spr %d %03x at " |
| 3845 | ADDRX "\n", sprn, sprn, ctx->nip); |
bellard | f24e569 | 2005-11-23 21:36:30 +0000 | [diff] [blame] | 3846 | } |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 3847 | printf("Trying to write privileged spr %d %03x at " ADDRX "\n", |
| 3848 | sprn, sprn, ctx->nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3849 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3850 | } |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3851 | } else { |
| 3852 | /* Not defined */ |
j_mayer | 4a05771 | 2007-04-19 08:42:21 +0000 | [diff] [blame] | 3853 | if (loglevel != 0) { |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 3854 | fprintf(logfile, "Trying to write invalid spr %d %03x at " |
| 3855 | ADDRX "\n", sprn, sprn, ctx->nip); |
bellard | f24e569 | 2005-11-23 21:36:30 +0000 | [diff] [blame] | 3856 | } |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 3857 | printf("Trying to write invalid spr %d %03x at " ADDRX "\n", |
| 3858 | sprn, sprn, ctx->nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3859 | GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, |
| 3860 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3861 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3862 | } |
| 3863 | |
| 3864 | /*** Cache management ***/ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3865 | /* dcbf */ |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3866 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3867 | { |
j_mayer | dac454a | 2007-10-26 00:48:00 +0000 | [diff] [blame] | 3868 | /* XXX: specification says this is treated as a load by the MMU */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 3869 | TCGv temp = tcg_temp_new(TCG_TYPE_TL); |
| 3870 | gen_addr_reg_index(temp, ctx); |
| 3871 | gen_qemu_ld8u(temp, temp, ctx->mem_idx); |
| 3872 | tcg_temp_free(temp); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3873 | } |
| 3874 | |
| 3875 | /* dcbi (Supervisor only) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3876 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3877 | { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 3878 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3879 | GEN_EXCP_PRIVOPC(ctx); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 3880 | #else |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 3881 | TCGv EA, val; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3882 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3883 | GEN_EXCP_PRIVOPC(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3884 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3885 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 3886 | EA = tcg_temp_new(TCG_TYPE_TL); |
| 3887 | gen_addr_reg_index(EA, ctx); |
aurel32 | ed69522 | 2008-10-15 22:25:21 +0000 | [diff] [blame] | 3888 | val = tcg_temp_new(TCG_TYPE_TL); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3889 | /* XXX: specification says this should be treated as a store by the MMU */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 3890 | gen_qemu_ld8u(val, EA, ctx->mem_idx); |
| 3891 | gen_qemu_st8(val, EA, ctx->mem_idx); |
| 3892 | tcg_temp_free(val); |
| 3893 | tcg_temp_free(EA); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 3894 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3895 | } |
| 3896 | |
| 3897 | /* dcdst */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3898 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3899 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3900 | /* XXX: specification say this is treated as a load by the MMU */ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 3901 | TCGv temp = tcg_temp_new(TCG_TYPE_TL); |
| 3902 | gen_addr_reg_index(temp, ctx); |
| 3903 | gen_qemu_ld8u(temp, temp, ctx->mem_idx); |
| 3904 | tcg_temp_free(temp); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3905 | } |
| 3906 | |
| 3907 | /* dcbt */ |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3908 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3909 | { |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3910 | /* interpreted as no-op */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3911 | /* XXX: specification say this is treated as a load by the MMU |
| 3912 | * but does not generate any exception |
| 3913 | */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3914 | } |
| 3915 | |
| 3916 | /* dcbtst */ |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3917 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3918 | { |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3919 | /* interpreted as no-op */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3920 | /* XXX: specification say this is treated as a load by the MMU |
| 3921 | * but does not generate any exception |
| 3922 | */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3923 | } |
| 3924 | |
| 3925 | /* dcbz */ |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 3926 | #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])() |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3927 | static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = { |
| 3928 | /* 32 bytes cache line size */ |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 3929 | { |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3930 | #define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw |
| 3931 | #define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user |
| 3932 | #define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel |
| 3933 | #define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv |
| 3934 | #define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw |
| 3935 | #define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user |
| 3936 | #define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel |
| 3937 | #define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv |
| 3938 | GEN_MEM_FUNCS(dcbz_l32), |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 3939 | }, |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3940 | /* 64 bytes cache line size */ |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 3941 | { |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3942 | #define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw |
| 3943 | #define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user |
| 3944 | #define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel |
| 3945 | #define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv |
| 3946 | #define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw |
| 3947 | #define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user |
| 3948 | #define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel |
| 3949 | #define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv |
| 3950 | GEN_MEM_FUNCS(dcbz_l64), |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 3951 | }, |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3952 | /* 128 bytes cache line size */ |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 3953 | { |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3954 | #define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw |
| 3955 | #define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user |
| 3956 | #define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel |
| 3957 | #define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv |
| 3958 | #define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw |
| 3959 | #define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user |
| 3960 | #define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel |
| 3961 | #define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv |
| 3962 | GEN_MEM_FUNCS(dcbz_l128), |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 3963 | }, |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3964 | /* tunable cache line size */ |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 3965 | { |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 3966 | #define gen_op_dcbz_le_raw gen_op_dcbz_raw |
| 3967 | #define gen_op_dcbz_le_user gen_op_dcbz_user |
| 3968 | #define gen_op_dcbz_le_kernel gen_op_dcbz_kernel |
| 3969 | #define gen_op_dcbz_le_hypv gen_op_dcbz_hypv |
| 3970 | #define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw |
| 3971 | #define gen_op_dcbz_le_64_user gen_op_dcbz_64_user |
| 3972 | #define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel |
| 3973 | #define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv |
| 3974 | GEN_MEM_FUNCS(dcbz), |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 3975 | }, |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3976 | }; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3977 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 3978 | static always_inline void handler_dcbz (DisasContext *ctx, |
| 3979 | int dcache_line_size) |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 3980 | { |
| 3981 | int n; |
| 3982 | |
| 3983 | switch (dcache_line_size) { |
| 3984 | case 32: |
| 3985 | n = 0; |
| 3986 | break; |
| 3987 | case 64: |
| 3988 | n = 1; |
| 3989 | break; |
| 3990 | case 128: |
| 3991 | n = 2; |
| 3992 | break; |
| 3993 | default: |
| 3994 | n = 3; |
| 3995 | break; |
| 3996 | } |
| 3997 | op_dcbz(n); |
| 3998 | } |
| 3999 | |
| 4000 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4001 | { |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4002 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 4003 | handler_dcbz(ctx, ctx->dcache_line_size); |
| 4004 | gen_op_check_reservation(); |
| 4005 | } |
| 4006 | |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4007 | GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT) |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 4008 | { |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4009 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 4010 | if (ctx->opcode & 0x00200000) |
| 4011 | handler_dcbz(ctx, ctx->dcache_line_size); |
| 4012 | else |
| 4013 | handler_dcbz(ctx, -1); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 4014 | gen_op_check_reservation(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4015 | } |
| 4016 | |
| 4017 | /* icbi */ |
j_mayer | 36f6965 | 2007-03-18 08:47:10 +0000 | [diff] [blame] | 4018 | #define op_icbi() (*gen_op_icbi[ctx->mem_idx])() |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 4019 | #define gen_op_icbi_le_raw gen_op_icbi_raw |
| 4020 | #define gen_op_icbi_le_user gen_op_icbi_user |
| 4021 | #define gen_op_icbi_le_kernel gen_op_icbi_kernel |
| 4022 | #define gen_op_icbi_le_hypv gen_op_icbi_hypv |
| 4023 | #define gen_op_icbi_le_64_raw gen_op_icbi_64_raw |
| 4024 | #define gen_op_icbi_le_64_user gen_op_icbi_64_user |
| 4025 | #define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel |
| 4026 | #define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv |
| 4027 | static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = { |
| 4028 | GEN_MEM_FUNCS(icbi), |
j_mayer | 36f6965 | 2007-03-18 08:47:10 +0000 | [diff] [blame] | 4029 | }; |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4030 | |
j_mayer | 1b413d5 | 2007-11-14 01:08:45 +0000 | [diff] [blame] | 4031 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4032 | { |
j_mayer | 30032c9 | 2007-10-01 05:22:17 +0000 | [diff] [blame] | 4033 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 4034 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4035 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | 36f6965 | 2007-03-18 08:47:10 +0000 | [diff] [blame] | 4036 | op_icbi(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4037 | } |
| 4038 | |
| 4039 | /* Optional: */ |
| 4040 | /* dcba */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 4041 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4042 | { |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 4043 | /* interpreted as no-op */ |
| 4044 | /* XXX: specification say this is treated as a store by the MMU |
| 4045 | * but does not generate any exception |
| 4046 | */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4047 | } |
| 4048 | |
| 4049 | /*** Segment register manipulation ***/ |
| 4050 | /* Supervisor only: */ |
| 4051 | /* mfsr */ |
| 4052 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) |
| 4053 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4054 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4055 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4056 | #else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4057 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4058 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4059 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4060 | } |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 4061 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4062 | gen_op_load_sr(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4063 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4064 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4065 | } |
| 4066 | |
| 4067 | /* mfsrin */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4068 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4069 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4070 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4071 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4072 | #else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4073 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4074 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4075 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4076 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4077 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4078 | gen_op_srli_T1(28); |
| 4079 | gen_op_load_sr(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4080 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4081 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4082 | } |
| 4083 | |
| 4084 | /* mtsr */ |
bellard | e63c59c | 2004-05-17 21:05:06 +0000 | [diff] [blame] | 4085 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4086 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4087 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4088 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4089 | #else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4090 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4091 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4092 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4093 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4094 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 4095 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4096 | gen_op_store_sr(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4097 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4098 | } |
| 4099 | |
| 4100 | /* mtsrin */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4101 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4102 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4103 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4104 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4105 | #else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4106 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4107 | GEN_EXCP_PRIVREG(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4108 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4109 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4110 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4111 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4112 | gen_op_srli_T1(28); |
| 4113 | gen_op_store_sr(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4114 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4115 | } |
| 4116 | |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4117 | #if defined(TARGET_PPC64) |
| 4118 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ |
| 4119 | /* mfsr */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4120 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4121 | { |
| 4122 | #if defined(CONFIG_USER_ONLY) |
| 4123 | GEN_EXCP_PRIVREG(ctx); |
| 4124 | #else |
| 4125 | if (unlikely(!ctx->supervisor)) { |
| 4126 | GEN_EXCP_PRIVREG(ctx); |
| 4127 | return; |
| 4128 | } |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 4129 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4130 | gen_op_load_slb(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4131 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4132 | #endif |
| 4133 | } |
| 4134 | |
| 4135 | /* mfsrin */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4136 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, |
| 4137 | PPC_SEGMENT_64B) |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4138 | { |
| 4139 | #if defined(CONFIG_USER_ONLY) |
| 4140 | GEN_EXCP_PRIVREG(ctx); |
| 4141 | #else |
| 4142 | if (unlikely(!ctx->supervisor)) { |
| 4143 | GEN_EXCP_PRIVREG(ctx); |
| 4144 | return; |
| 4145 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4146 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4147 | gen_op_srli_T1(28); |
| 4148 | gen_op_load_slb(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4149 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4150 | #endif |
| 4151 | } |
| 4152 | |
| 4153 | /* mtsr */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4154 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4155 | { |
| 4156 | #if defined(CONFIG_USER_ONLY) |
| 4157 | GEN_EXCP_PRIVREG(ctx); |
| 4158 | #else |
| 4159 | if (unlikely(!ctx->supervisor)) { |
| 4160 | GEN_EXCP_PRIVREG(ctx); |
| 4161 | return; |
| 4162 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4163 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 4164 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4165 | gen_op_store_slb(); |
| 4166 | #endif |
| 4167 | } |
| 4168 | |
| 4169 | /* mtsrin */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4170 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, |
| 4171 | PPC_SEGMENT_64B) |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4172 | { |
| 4173 | #if defined(CONFIG_USER_ONLY) |
| 4174 | GEN_EXCP_PRIVREG(ctx); |
| 4175 | #else |
| 4176 | if (unlikely(!ctx->supervisor)) { |
| 4177 | GEN_EXCP_PRIVREG(ctx); |
| 4178 | return; |
| 4179 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4180 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4181 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4182 | gen_op_srli_T1(28); |
| 4183 | gen_op_store_slb(); |
| 4184 | #endif |
| 4185 | } |
| 4186 | #endif /* defined(TARGET_PPC64) */ |
| 4187 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4188 | /*** Lookaside buffer management ***/ |
| 4189 | /* Optional & supervisor only: */ |
| 4190 | /* tlbia */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 4191 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4192 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4193 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4194 | GEN_EXCP_PRIVOPC(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4195 | #else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4196 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4197 | GEN_EXCP_PRIVOPC(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4198 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4199 | } |
| 4200 | gen_op_tlbia(); |
| 4201 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4202 | } |
| 4203 | |
| 4204 | /* tlbie */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4205 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4206 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4207 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4208 | GEN_EXCP_PRIVOPC(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4209 | #else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4210 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4211 | GEN_EXCP_PRIVOPC(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4212 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4213 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4214 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4215 | #if defined(TARGET_PPC64) |
| 4216 | if (ctx->sf_mode) |
| 4217 | gen_op_tlbie_64(); |
| 4218 | else |
| 4219 | #endif |
| 4220 | gen_op_tlbie(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4221 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4222 | } |
| 4223 | |
| 4224 | /* tlbsync */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4225 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4226 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4227 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4228 | GEN_EXCP_PRIVOPC(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4229 | #else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4230 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4231 | GEN_EXCP_PRIVOPC(ctx); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4232 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4233 | } |
| 4234 | /* This has no effect: it should ensure that all previous |
| 4235 | * tlbie have completed |
| 4236 | */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4237 | GEN_STOP(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4238 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4239 | } |
| 4240 | |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4241 | #if defined(TARGET_PPC64) |
| 4242 | /* slbia */ |
| 4243 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI) |
| 4244 | { |
| 4245 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4246 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4247 | #else |
| 4248 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4249 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4250 | return; |
| 4251 | } |
| 4252 | gen_op_slbia(); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4253 | #endif |
| 4254 | } |
| 4255 | |
| 4256 | /* slbie */ |
| 4257 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI) |
| 4258 | { |
| 4259 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4260 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4261 | #else |
| 4262 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4263 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4264 | return; |
| 4265 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4266 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4267 | gen_op_slbie(); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4268 | #endif |
| 4269 | } |
| 4270 | #endif |
| 4271 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4272 | /*** External control ***/ |
| 4273 | /* Optional: */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4274 | #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])() |
| 4275 | #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])() |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 4276 | static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = { |
| 4277 | GEN_MEM_FUNCS(eciwx), |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4278 | }; |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 4279 | static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = { |
| 4280 | GEN_MEM_FUNCS(ecowx), |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4281 | }; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4282 | |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 4283 | /* eciwx */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4284 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN) |
| 4285 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4286 | /* Should check EAR[E] & alignment ! */ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4287 | gen_addr_reg_index(cpu_T[0], ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4288 | op_eciwx(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4289 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4290 | } |
| 4291 | |
| 4292 | /* ecowx */ |
| 4293 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) |
| 4294 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4295 | /* Should check EAR[E] & alignment ! */ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4296 | gen_addr_reg_index(cpu_T[0], ctx); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4297 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4298 | op_ecowx(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4299 | } |
| 4300 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4301 | /* PowerPC 601 specific instructions */ |
| 4302 | /* abs - abs. */ |
| 4303 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) |
| 4304 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4305 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4306 | gen_op_POWER_abs(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4307 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4308 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4309 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4310 | } |
| 4311 | |
| 4312 | /* abso - abso. */ |
| 4313 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) |
| 4314 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4315 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4316 | gen_op_POWER_abso(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4317 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4318 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4319 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4320 | } |
| 4321 | |
| 4322 | /* clcs */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 4323 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4324 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4325 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4326 | gen_op_POWER_clcs(); |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4327 | /* Rc=1 sets CR0 to an undefined state */ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4328 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4329 | } |
| 4330 | |
| 4331 | /* div - div. */ |
| 4332 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) |
| 4333 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4334 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 4335 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4336 | gen_op_POWER_div(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4337 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4338 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4339 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4340 | } |
| 4341 | |
| 4342 | /* divo - divo. */ |
| 4343 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) |
| 4344 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4345 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 4346 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4347 | gen_op_POWER_divo(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4348 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4349 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4350 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4351 | } |
| 4352 | |
| 4353 | /* divs - divs. */ |
| 4354 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) |
| 4355 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4356 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 4357 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4358 | gen_op_POWER_divs(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4359 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4360 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4361 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4362 | } |
| 4363 | |
| 4364 | /* divso - divso. */ |
| 4365 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) |
| 4366 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4367 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 4368 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4369 | gen_op_POWER_divso(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4370 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4371 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4372 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4373 | } |
| 4374 | |
| 4375 | /* doz - doz. */ |
| 4376 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) |
| 4377 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4378 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 4379 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4380 | gen_op_POWER_doz(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4381 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4382 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4383 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4384 | } |
| 4385 | |
| 4386 | /* dozo - dozo. */ |
| 4387 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) |
| 4388 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4389 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 4390 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4391 | gen_op_POWER_dozo(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4392 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4393 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4394 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4395 | } |
| 4396 | |
| 4397 | /* dozi */ |
| 4398 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) |
| 4399 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4400 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 4401 | tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4402 | gen_op_POWER_doz(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4403 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4404 | } |
| 4405 | |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 4406 | /* As lscbx load from memory byte after byte, it's always endian safe. |
| 4407 | * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones |
| 4408 | */ |
j_mayer | 2857068 | 2007-10-02 10:11:50 +0000 | [diff] [blame] | 4409 | #define op_POWER_lscbx(start, ra, rb) \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4410 | (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb) |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 4411 | #define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw |
| 4412 | #define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user |
| 4413 | #define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel |
| 4414 | #define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv |
| 4415 | #define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw |
| 4416 | #define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user |
| 4417 | #define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel |
| 4418 | #define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv |
| 4419 | #define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw |
| 4420 | #define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user |
| 4421 | #define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel |
| 4422 | #define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv |
| 4423 | static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = { |
| 4424 | GEN_MEM_FUNCS(POWER_lscbx), |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4425 | }; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4426 | |
| 4427 | /* lscbx - lscbx. */ |
| 4428 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR) |
| 4429 | { |
| 4430 | int ra = rA(ctx->opcode); |
| 4431 | int rb = rB(ctx->opcode); |
| 4432 | |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4433 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4434 | if (ra == 0) { |
| 4435 | ra = rb; |
| 4436 | } |
| 4437 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4438 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 4439 | tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F); |
| 4440 | tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP); |
| 4441 | tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4442 | op_POWER_lscbx(rD(ctx->opcode), ra, rb); |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 4443 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
| 4444 | tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4445 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4446 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4447 | } |
| 4448 | |
| 4449 | /* maskg - maskg. */ |
| 4450 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) |
| 4451 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4452 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4453 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4454 | gen_op_POWER_maskg(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4455 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4456 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4457 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4458 | } |
| 4459 | |
| 4460 | /* maskir - maskir. */ |
| 4461 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) |
| 4462 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4463 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 4464 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); |
| 4465 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4466 | gen_op_POWER_maskir(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4467 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4468 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4469 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4470 | } |
| 4471 | |
| 4472 | /* mul - mul. */ |
| 4473 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) |
| 4474 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4475 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 4476 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4477 | gen_op_POWER_mul(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4478 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4479 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4480 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4481 | } |
| 4482 | |
| 4483 | /* mulo - mulo. */ |
| 4484 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) |
| 4485 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4486 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 4487 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4488 | gen_op_POWER_mulo(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4489 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4490 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4491 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4492 | } |
| 4493 | |
| 4494 | /* nabs - nabs. */ |
| 4495 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) |
| 4496 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4497 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4498 | gen_op_POWER_nabs(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4499 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4500 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4501 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4502 | } |
| 4503 | |
| 4504 | /* nabso - nabso. */ |
| 4505 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR) |
| 4506 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4507 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4508 | gen_op_POWER_nabso(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4509 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4510 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4511 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4512 | } |
| 4513 | |
| 4514 | /* rlmi - rlmi. */ |
| 4515 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) |
| 4516 | { |
| 4517 | uint32_t mb, me; |
| 4518 | |
| 4519 | mb = MB(ctx->opcode); |
| 4520 | me = ME(ctx->opcode); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4521 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4522 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); |
| 4523 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4524 | gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me)); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4525 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4526 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4527 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4528 | } |
| 4529 | |
| 4530 | /* rrib - rrib. */ |
| 4531 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) |
| 4532 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4533 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4534 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); |
| 4535 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4536 | gen_op_POWER_rrib(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4537 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4538 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4539 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4540 | } |
| 4541 | |
| 4542 | /* sle - sle. */ |
| 4543 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) |
| 4544 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4545 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4546 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4547 | gen_op_POWER_sle(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4548 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4549 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4550 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4551 | } |
| 4552 | |
| 4553 | /* sleq - sleq. */ |
| 4554 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) |
| 4555 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4556 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4557 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4558 | gen_op_POWER_sleq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4559 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4560 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4561 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4562 | } |
| 4563 | |
| 4564 | /* sliq - sliq. */ |
| 4565 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) |
| 4566 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4567 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 4568 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4569 | gen_op_POWER_sle(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4570 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4571 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4572 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4573 | } |
| 4574 | |
| 4575 | /* slliq - slliq. */ |
| 4576 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) |
| 4577 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4578 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 4579 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4580 | gen_op_POWER_sleq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4581 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4582 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4583 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4584 | } |
| 4585 | |
| 4586 | /* sllq - sllq. */ |
| 4587 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) |
| 4588 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4589 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4590 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4591 | gen_op_POWER_sllq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4592 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4593 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4594 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4595 | } |
| 4596 | |
| 4597 | /* slq - slq. */ |
| 4598 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) |
| 4599 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4600 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4601 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4602 | gen_op_POWER_slq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4603 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4604 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4605 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4606 | } |
| 4607 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4608 | /* sraiq - sraiq. */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4609 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) |
| 4610 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4611 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 4612 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4613 | gen_op_POWER_sraq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4614 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4615 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4616 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4617 | } |
| 4618 | |
| 4619 | /* sraq - sraq. */ |
| 4620 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) |
| 4621 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4622 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4623 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4624 | gen_op_POWER_sraq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4625 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4626 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4627 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4628 | } |
| 4629 | |
| 4630 | /* sre - sre. */ |
| 4631 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) |
| 4632 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4633 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4634 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4635 | gen_op_POWER_sre(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4636 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4637 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4638 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4639 | } |
| 4640 | |
| 4641 | /* srea - srea. */ |
| 4642 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) |
| 4643 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4644 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4645 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4646 | gen_op_POWER_srea(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4647 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4648 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4649 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4650 | } |
| 4651 | |
| 4652 | /* sreq */ |
| 4653 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) |
| 4654 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4655 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4656 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4657 | gen_op_POWER_sreq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4658 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4659 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4660 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4661 | } |
| 4662 | |
| 4663 | /* sriq */ |
| 4664 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) |
| 4665 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4666 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 4667 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4668 | gen_op_POWER_srq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4669 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4670 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4671 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4672 | } |
| 4673 | |
| 4674 | /* srliq */ |
| 4675 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) |
| 4676 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4677 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4678 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 4679 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4680 | gen_op_POWER_srlq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4681 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4682 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4683 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4684 | } |
| 4685 | |
| 4686 | /* srlq */ |
| 4687 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) |
| 4688 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4689 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4690 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4691 | gen_op_POWER_srlq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4692 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4693 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4694 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4695 | } |
| 4696 | |
| 4697 | /* srq */ |
| 4698 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR) |
| 4699 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4700 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 4701 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4702 | gen_op_POWER_srq(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4703 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4704 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 4705 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4706 | } |
| 4707 | |
| 4708 | /* PowerPC 602 specific instructions */ |
| 4709 | /* dsa */ |
| 4710 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC) |
| 4711 | { |
| 4712 | /* XXX: TODO */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4713 | GEN_EXCP_INVAL(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4714 | } |
| 4715 | |
| 4716 | /* esa */ |
| 4717 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC) |
| 4718 | { |
| 4719 | /* XXX: TODO */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4720 | GEN_EXCP_INVAL(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4721 | } |
| 4722 | |
| 4723 | /* mfrom */ |
| 4724 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC) |
| 4725 | { |
| 4726 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4727 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4728 | #else |
| 4729 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4730 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4731 | return; |
| 4732 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4733 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4734 | gen_op_602_mfrom(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4735 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4736 | #endif |
| 4737 | } |
| 4738 | |
| 4739 | /* 602 - 603 - G2 TLB management */ |
| 4740 | /* tlbld */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4741 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4742 | { |
| 4743 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4744 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4745 | #else |
| 4746 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4747 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4748 | return; |
| 4749 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4750 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4751 | gen_op_6xx_tlbld(); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4752 | #endif |
| 4753 | } |
| 4754 | |
| 4755 | /* tlbli */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4756 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4757 | { |
| 4758 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4759 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4760 | #else |
| 4761 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4762 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4763 | return; |
| 4764 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4765 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4766 | gen_op_6xx_tlbli(); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4767 | #endif |
| 4768 | } |
| 4769 | |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 4770 | /* 74xx TLB management */ |
| 4771 | /* tlbld */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4772 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB) |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 4773 | { |
| 4774 | #if defined(CONFIG_USER_ONLY) |
| 4775 | GEN_EXCP_PRIVOPC(ctx); |
| 4776 | #else |
| 4777 | if (unlikely(!ctx->supervisor)) { |
| 4778 | GEN_EXCP_PRIVOPC(ctx); |
| 4779 | return; |
| 4780 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4781 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 4782 | gen_op_74xx_tlbld(); |
| 4783 | #endif |
| 4784 | } |
| 4785 | |
| 4786 | /* tlbli */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4787 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB) |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 4788 | { |
| 4789 | #if defined(CONFIG_USER_ONLY) |
| 4790 | GEN_EXCP_PRIVOPC(ctx); |
| 4791 | #else |
| 4792 | if (unlikely(!ctx->supervisor)) { |
| 4793 | GEN_EXCP_PRIVOPC(ctx); |
| 4794 | return; |
| 4795 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4796 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 4797 | gen_op_74xx_tlbli(); |
| 4798 | #endif |
| 4799 | } |
| 4800 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4801 | /* POWER instructions not in PowerPC 601 */ |
| 4802 | /* clf */ |
| 4803 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER) |
| 4804 | { |
| 4805 | /* Cache line flush: implemented as no-op */ |
| 4806 | } |
| 4807 | |
| 4808 | /* cli */ |
| 4809 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER) |
| 4810 | { |
blueswir1 | 7f75ffd | 2007-05-27 19:39:27 +0000 | [diff] [blame] | 4811 | /* Cache line invalidate: privileged and treated as no-op */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4812 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4813 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4814 | #else |
| 4815 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4816 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4817 | return; |
| 4818 | } |
| 4819 | #endif |
| 4820 | } |
| 4821 | |
| 4822 | /* dclst */ |
| 4823 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER) |
| 4824 | { |
| 4825 | /* Data cache line store: treated as no-op */ |
| 4826 | } |
| 4827 | |
| 4828 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER) |
| 4829 | { |
| 4830 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4831 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4832 | #else |
| 4833 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4834 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4835 | return; |
| 4836 | } |
| 4837 | int ra = rA(ctx->opcode); |
| 4838 | int rd = rD(ctx->opcode); |
| 4839 | |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4840 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4841 | gen_op_POWER_mfsri(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4842 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4843 | if (ra != 0 && ra != rd) |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4844 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4845 | #endif |
| 4846 | } |
| 4847 | |
| 4848 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER) |
| 4849 | { |
| 4850 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4851 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4852 | #else |
| 4853 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4854 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4855 | return; |
| 4856 | } |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4857 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4858 | gen_op_POWER_rac(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4859 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4860 | #endif |
| 4861 | } |
| 4862 | |
| 4863 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER) |
| 4864 | { |
| 4865 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4866 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4867 | #else |
| 4868 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4869 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4870 | return; |
| 4871 | } |
| 4872 | gen_op_POWER_rfsvc(); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 4873 | GEN_SYNC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4874 | #endif |
| 4875 | } |
| 4876 | |
| 4877 | /* svc is not implemented for now */ |
| 4878 | |
| 4879 | /* POWER2 specific instructions */ |
| 4880 | /* Quad manipulation (load/store two floats at a time) */ |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 4881 | /* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4882 | #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])() |
| 4883 | #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])() |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 4884 | #define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw |
| 4885 | #define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user |
| 4886 | #define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel |
| 4887 | #define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv |
| 4888 | #define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw |
| 4889 | #define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user |
| 4890 | #define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel |
| 4891 | #define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv |
| 4892 | #define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw |
| 4893 | #define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user |
| 4894 | #define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel |
| 4895 | #define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv |
| 4896 | #define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw |
| 4897 | #define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user |
| 4898 | #define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel |
| 4899 | #define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv |
| 4900 | static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = { |
| 4901 | GEN_MEM_FUNCS(POWER2_lfq), |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4902 | }; |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 4903 | static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = { |
| 4904 | GEN_MEM_FUNCS(POWER2_stfq), |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4905 | }; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4906 | |
| 4907 | /* lfq */ |
| 4908 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
| 4909 | { |
| 4910 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4911 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4912 | gen_addr_imm_index(cpu_T[0], ctx, 0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4913 | op_POWER2_lfq(); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 4914 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
| 4915 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4916 | } |
| 4917 | |
| 4918 | /* lfqu */ |
| 4919 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
| 4920 | { |
| 4921 | int ra = rA(ctx->opcode); |
| 4922 | |
| 4923 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4924 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4925 | gen_addr_imm_index(cpu_T[0], ctx, 0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4926 | op_POWER2_lfq(); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 4927 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
| 4928 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4929 | if (ra != 0) |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4930 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4931 | } |
| 4932 | |
| 4933 | /* lfqux */ |
| 4934 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2) |
| 4935 | { |
| 4936 | int ra = rA(ctx->opcode); |
| 4937 | |
| 4938 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4939 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4940 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4941 | op_POWER2_lfq(); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 4942 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
| 4943 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4944 | if (ra != 0) |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4945 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4946 | } |
| 4947 | |
| 4948 | /* lfqx */ |
| 4949 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2) |
| 4950 | { |
| 4951 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4952 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4953 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4954 | op_POWER2_lfq(); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 4955 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
| 4956 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4957 | } |
| 4958 | |
| 4959 | /* stfq */ |
| 4960 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
| 4961 | { |
| 4962 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4963 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4964 | gen_addr_imm_index(cpu_T[0], ctx, 0); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 4965 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); |
| 4966 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4967 | op_POWER2_stfq(); |
| 4968 | } |
| 4969 | |
| 4970 | /* stfqu */ |
| 4971 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
| 4972 | { |
| 4973 | int ra = rA(ctx->opcode); |
| 4974 | |
| 4975 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4976 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4977 | gen_addr_imm_index(cpu_T[0], ctx, 0); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 4978 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); |
| 4979 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4980 | op_POWER2_stfq(); |
| 4981 | if (ra != 0) |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4982 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4983 | } |
| 4984 | |
| 4985 | /* stfqux */ |
| 4986 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2) |
| 4987 | { |
| 4988 | int ra = rA(ctx->opcode); |
| 4989 | |
| 4990 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4991 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 4992 | gen_addr_reg_index(cpu_T[0], ctx); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 4993 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); |
| 4994 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4995 | op_POWER2_stfq(); |
| 4996 | if (ra != 0) |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 4997 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4998 | } |
| 4999 | |
| 5000 | /* stfqx */ |
| 5001 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2) |
| 5002 | { |
| 5003 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 5004 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 5005 | gen_addr_reg_index(cpu_T[0], ctx); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 5006 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); |
| 5007 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5008 | op_POWER2_stfq(); |
| 5009 | } |
| 5010 | |
| 5011 | /* BookE specific instructions */ |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 5012 | /* XXX: not implemented on 440 ? */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 5013 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5014 | { |
| 5015 | /* XXX: TODO */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5016 | GEN_EXCP_INVAL(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5017 | } |
| 5018 | |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 5019 | /* XXX: not implemented on 440 ? */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 5020 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5021 | { |
| 5022 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5023 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5024 | #else |
| 5025 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5026 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5027 | return; |
| 5028 | } |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 5029 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5030 | /* Use the same micro-ops as for tlbie */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 5031 | #if defined(TARGET_PPC64) |
| 5032 | if (ctx->sf_mode) |
| 5033 | gen_op_tlbie_64(); |
| 5034 | else |
| 5035 | #endif |
| 5036 | gen_op_tlbie(); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5037 | #endif |
| 5038 | } |
| 5039 | |
| 5040 | /* All 405 MAC instructions are translated here */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5041 | static always_inline void gen_405_mulladd_insn (DisasContext *ctx, |
| 5042 | int opc2, int opc3, |
| 5043 | int ra, int rb, int rt, int Rc) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5044 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5045 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]); |
| 5046 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5047 | switch (opc3 & 0x0D) { |
| 5048 | case 0x05: |
| 5049 | /* macchw - macchw. - macchwo - macchwo. */ |
| 5050 | /* macchws - macchws. - macchwso - macchwso. */ |
| 5051 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ |
| 5052 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ |
| 5053 | /* mulchw - mulchw. */ |
| 5054 | gen_op_405_mulchw(); |
| 5055 | break; |
| 5056 | case 0x04: |
| 5057 | /* macchwu - macchwu. - macchwuo - macchwuo. */ |
| 5058 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ |
| 5059 | /* mulchwu - mulchwu. */ |
| 5060 | gen_op_405_mulchwu(); |
| 5061 | break; |
| 5062 | case 0x01: |
| 5063 | /* machhw - machhw. - machhwo - machhwo. */ |
| 5064 | /* machhws - machhws. - machhwso - machhwso. */ |
| 5065 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ |
| 5066 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ |
| 5067 | /* mulhhw - mulhhw. */ |
| 5068 | gen_op_405_mulhhw(); |
| 5069 | break; |
| 5070 | case 0x00: |
| 5071 | /* machhwu - machhwu. - machhwuo - machhwuo. */ |
| 5072 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ |
| 5073 | /* mulhhwu - mulhhwu. */ |
| 5074 | gen_op_405_mulhhwu(); |
| 5075 | break; |
| 5076 | case 0x0D: |
| 5077 | /* maclhw - maclhw. - maclhwo - maclhwo. */ |
| 5078 | /* maclhws - maclhws. - maclhwso - maclhwso. */ |
| 5079 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ |
| 5080 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ |
| 5081 | /* mullhw - mullhw. */ |
| 5082 | gen_op_405_mullhw(); |
| 5083 | break; |
| 5084 | case 0x0C: |
| 5085 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ |
| 5086 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ |
| 5087 | /* mullhwu - mullhwu. */ |
| 5088 | gen_op_405_mullhwu(); |
| 5089 | break; |
| 5090 | } |
| 5091 | if (opc2 & 0x02) { |
| 5092 | /* nmultiply-and-accumulate (0x0E) */ |
| 5093 | gen_op_neg(); |
| 5094 | } |
| 5095 | if (opc2 & 0x04) { |
| 5096 | /* (n)multiply-and-accumulate (0x0C - 0x0E) */ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5097 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]); |
aurel32 | e55fd93 | 2008-09-02 16:19:05 +0000 | [diff] [blame] | 5098 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5099 | gen_op_405_add_T0_T2(); |
| 5100 | } |
| 5101 | if (opc3 & 0x10) { |
| 5102 | /* Check overflow */ |
| 5103 | if (opc3 & 0x01) |
j_mayer | c3e10c7 | 2007-11-11 00:18:34 +0000 | [diff] [blame] | 5104 | gen_op_check_addo(); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5105 | else |
| 5106 | gen_op_405_check_ovu(); |
| 5107 | } |
| 5108 | if (opc3 & 0x02) { |
| 5109 | /* Saturate */ |
| 5110 | if (opc3 & 0x01) |
| 5111 | gen_op_405_check_sat(); |
| 5112 | else |
| 5113 | gen_op_405_check_satu(); |
| 5114 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5115 | tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5116 | if (unlikely(Rc) != 0) { |
| 5117 | /* Update Rc0 */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 5118 | gen_set_Rc0(ctx, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5119 | } |
| 5120 | } |
| 5121 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5122 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
| 5123 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5124 | { \ |
| 5125 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ |
| 5126 | rD(ctx->opcode), Rc(ctx->opcode)); \ |
| 5127 | } |
| 5128 | |
| 5129 | /* macchw - macchw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5130 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5131 | /* macchwo - macchwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5132 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5133 | /* macchws - macchws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5134 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5135 | /* macchwso - macchwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5136 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5137 | /* macchwsu - macchwsu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5138 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5139 | /* macchwsuo - macchwsuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5140 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5141 | /* macchwu - macchwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5142 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5143 | /* macchwuo - macchwuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5144 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5145 | /* machhw - machhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5146 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5147 | /* machhwo - machhwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5148 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5149 | /* machhws - machhws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5150 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5151 | /* machhwso - machhwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5152 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5153 | /* machhwsu - machhwsu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5154 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5155 | /* machhwsuo - machhwsuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5156 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5157 | /* machhwu - machhwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5158 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5159 | /* machhwuo - machhwuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5160 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5161 | /* maclhw - maclhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5162 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5163 | /* maclhwo - maclhwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5164 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5165 | /* maclhws - maclhws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5166 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5167 | /* maclhwso - maclhwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5168 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5169 | /* maclhwu - maclhwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5170 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5171 | /* maclhwuo - maclhwuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5172 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5173 | /* maclhwsu - maclhwsu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5174 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5175 | /* maclhwsuo - maclhwsuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5176 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5177 | /* nmacchw - nmacchw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5178 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5179 | /* nmacchwo - nmacchwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5180 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5181 | /* nmacchws - nmacchws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5182 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5183 | /* nmacchwso - nmacchwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5184 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5185 | /* nmachhw - nmachhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5186 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5187 | /* nmachhwo - nmachhwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5188 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5189 | /* nmachhws - nmachhws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5190 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5191 | /* nmachhwso - nmachhwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5192 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5193 | /* nmaclhw - nmaclhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5194 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5195 | /* nmaclhwo - nmaclhwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5196 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5197 | /* nmaclhws - nmaclhws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5198 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5199 | /* nmaclhwso - nmaclhwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5200 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5201 | |
| 5202 | /* mulchw - mulchw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5203 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5204 | /* mulchwu - mulchwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5205 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5206 | /* mulhhw - mulhhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5207 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5208 | /* mulhhwu - mulhhwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5209 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5210 | /* mullhw - mullhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5211 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5212 | /* mullhwu - mullhwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5213 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5214 | |
| 5215 | /* mfdcr */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 5216 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5217 | { |
| 5218 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5219 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5220 | #else |
| 5221 | uint32_t dcrn = SPR(ctx->opcode); |
| 5222 | |
| 5223 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5224 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5225 | return; |
| 5226 | } |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 5227 | tcg_gen_movi_tl(cpu_T[0], dcrn); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5228 | gen_op_load_dcr(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5229 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5230 | #endif |
| 5231 | } |
| 5232 | |
| 5233 | /* mtdcr */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 5234 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5235 | { |
| 5236 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5237 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5238 | #else |
| 5239 | uint32_t dcrn = SPR(ctx->opcode); |
| 5240 | |
| 5241 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5242 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5243 | return; |
| 5244 | } |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 5245 | tcg_gen_movi_tl(cpu_T[0], dcrn); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5246 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5247 | gen_op_store_dcr(); |
| 5248 | #endif |
| 5249 | } |
| 5250 | |
| 5251 | /* mfdcrx */ |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 5252 | /* XXX: not implemented on 440 ? */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 5253 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX) |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5254 | { |
| 5255 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5256 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5257 | #else |
| 5258 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5259 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5260 | return; |
| 5261 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5262 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5263 | gen_op_load_dcr(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5264 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5265 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5266 | #endif |
| 5267 | } |
| 5268 | |
| 5269 | /* mtdcrx */ |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 5270 | /* XXX: not implemented on 440 ? */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 5271 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5272 | { |
| 5273 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5274 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5275 | #else |
| 5276 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5277 | GEN_EXCP_PRIVREG(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5278 | return; |
| 5279 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5280 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 5281 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5282 | gen_op_store_dcr(); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5283 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5284 | #endif |
| 5285 | } |
| 5286 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5287 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
| 5288 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) |
| 5289 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5290 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5291 | gen_op_load_dcr(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5292 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5293 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
| 5294 | } |
| 5295 | |
| 5296 | /* mtdcrux (PPC 460) : user-mode access to DCR */ |
| 5297 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX) |
| 5298 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5299 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 5300 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5301 | gen_op_store_dcr(); |
| 5302 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
| 5303 | } |
| 5304 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5305 | /* dccci */ |
| 5306 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON) |
| 5307 | { |
| 5308 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5309 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5310 | #else |
| 5311 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5312 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5313 | return; |
| 5314 | } |
| 5315 | /* interpreted as no-op */ |
| 5316 | #endif |
| 5317 | } |
| 5318 | |
| 5319 | /* dcread */ |
| 5320 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON) |
| 5321 | { |
| 5322 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5323 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5324 | #else |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 5325 | TCGv EA, val; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5326 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5327 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5328 | return; |
| 5329 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 5330 | EA = tcg_temp_new(TCG_TYPE_TL); |
| 5331 | gen_addr_reg_index(EA, ctx); |
| 5332 | val = tcg_temp_new(TCG_TYPE_TL); |
| 5333 | gen_qemu_ld32u(val, EA, ctx->mem_idx); |
| 5334 | tcg_temp_free(val); |
| 5335 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); |
| 5336 | tcg_temp_free(EA); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5337 | #endif |
| 5338 | } |
| 5339 | |
| 5340 | /* icbt */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 5341 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5342 | { |
| 5343 | /* interpreted as no-op */ |
| 5344 | /* XXX: specification say this is treated as a load by the MMU |
| 5345 | * but does not generate any exception |
| 5346 | */ |
| 5347 | } |
| 5348 | |
| 5349 | /* iccci */ |
| 5350 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON) |
| 5351 | { |
| 5352 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5353 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5354 | #else |
| 5355 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5356 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5357 | return; |
| 5358 | } |
| 5359 | /* interpreted as no-op */ |
| 5360 | #endif |
| 5361 | } |
| 5362 | |
| 5363 | /* icread */ |
| 5364 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON) |
| 5365 | { |
| 5366 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5367 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5368 | #else |
| 5369 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5370 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5371 | return; |
| 5372 | } |
| 5373 | /* interpreted as no-op */ |
| 5374 | #endif |
| 5375 | } |
| 5376 | |
| 5377 | /* rfci (supervisor only) */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 5378 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5379 | { |
| 5380 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5381 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5382 | #else |
| 5383 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5384 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5385 | return; |
| 5386 | } |
| 5387 | /* Restore CPU state */ |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5388 | gen_op_40x_rfci(); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5389 | GEN_SYNC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5390 | #endif |
| 5391 | } |
| 5392 | |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5393 | GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE) |
| 5394 | { |
| 5395 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5396 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5397 | #else |
| 5398 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5399 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5400 | return; |
| 5401 | } |
| 5402 | /* Restore CPU state */ |
| 5403 | gen_op_rfci(); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5404 | GEN_SYNC(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5405 | #endif |
| 5406 | } |
| 5407 | |
| 5408 | /* BookE specific */ |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 5409 | /* XXX: not implemented on 440 ? */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 5410 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI) |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5411 | { |
| 5412 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5413 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5414 | #else |
| 5415 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5416 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5417 | return; |
| 5418 | } |
| 5419 | /* Restore CPU state */ |
| 5420 | gen_op_rfdi(); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5421 | GEN_SYNC(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5422 | #endif |
| 5423 | } |
| 5424 | |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 5425 | /* XXX: not implemented on 440 ? */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5426 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI) |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5427 | { |
| 5428 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5429 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5430 | #else |
| 5431 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5432 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5433 | return; |
| 5434 | } |
| 5435 | /* Restore CPU state */ |
| 5436 | gen_op_rfmci(); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5437 | GEN_SYNC(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5438 | #endif |
| 5439 | } |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5440 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 5441 | /* TLB management - PowerPC 405 implementation */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5442 | /* tlbre */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 5443 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5444 | { |
| 5445 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5446 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5447 | #else |
| 5448 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5449 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5450 | return; |
| 5451 | } |
| 5452 | switch (rB(ctx->opcode)) { |
| 5453 | case 0: |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5454 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5455 | gen_op_4xx_tlbre_hi(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5456 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5457 | break; |
| 5458 | case 1: |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5459 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5460 | gen_op_4xx_tlbre_lo(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5461 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5462 | break; |
| 5463 | default: |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5464 | GEN_EXCP_INVAL(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5465 | break; |
| 5466 | } |
| 5467 | #endif |
| 5468 | } |
| 5469 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 5470 | /* tlbsx - tlbsx. */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 5471 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5472 | { |
| 5473 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5474 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5475 | #else |
| 5476 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5477 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5478 | return; |
| 5479 | } |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 5480 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | daf4f96 | 2007-10-01 01:51:12 +0000 | [diff] [blame] | 5481 | gen_op_4xx_tlbsx(); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5482 | if (Rc(ctx->opcode)) |
j_mayer | daf4f96 | 2007-10-01 01:51:12 +0000 | [diff] [blame] | 5483 | gen_op_4xx_tlbsx_check(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5484 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5485 | #endif |
| 5486 | } |
| 5487 | |
| 5488 | /* tlbwe */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 5489 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5490 | { |
| 5491 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5492 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5493 | #else |
| 5494 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5495 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5496 | return; |
| 5497 | } |
| 5498 | switch (rB(ctx->opcode)) { |
| 5499 | case 0: |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5500 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 5501 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5502 | gen_op_4xx_tlbwe_hi(); |
| 5503 | break; |
| 5504 | case 1: |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5505 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 5506 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5507 | gen_op_4xx_tlbwe_lo(); |
| 5508 | break; |
| 5509 | default: |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5510 | GEN_EXCP_INVAL(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5511 | break; |
| 5512 | } |
| 5513 | #endif |
| 5514 | } |
| 5515 | |
j_mayer | a4bb6c3 | 2007-09-21 05:28:33 +0000 | [diff] [blame] | 5516 | /* TLB management - PowerPC 440 implementation */ |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5517 | /* tlbre */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 5518 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5519 | { |
| 5520 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5521 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5522 | #else |
| 5523 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5524 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5525 | return; |
| 5526 | } |
| 5527 | switch (rB(ctx->opcode)) { |
| 5528 | case 0: |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5529 | case 1: |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5530 | case 2: |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5531 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | a4bb6c3 | 2007-09-21 05:28:33 +0000 | [diff] [blame] | 5532 | gen_op_440_tlbre(rB(ctx->opcode)); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5533 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5534 | break; |
| 5535 | default: |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5536 | GEN_EXCP_INVAL(ctx); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5537 | break; |
| 5538 | } |
| 5539 | #endif |
| 5540 | } |
| 5541 | |
| 5542 | /* tlbsx - tlbsx. */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 5543 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE) |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5544 | { |
| 5545 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5546 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5547 | #else |
| 5548 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5549 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5550 | return; |
| 5551 | } |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 5552 | gen_addr_reg_index(cpu_T[0], ctx); |
j_mayer | daf4f96 | 2007-10-01 01:51:12 +0000 | [diff] [blame] | 5553 | gen_op_440_tlbsx(); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5554 | if (Rc(ctx->opcode)) |
j_mayer | daf4f96 | 2007-10-01 01:51:12 +0000 | [diff] [blame] | 5555 | gen_op_4xx_tlbsx_check(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5556 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5557 | #endif |
| 5558 | } |
| 5559 | |
| 5560 | /* tlbwe */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 5561 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5562 | { |
| 5563 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5564 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5565 | #else |
| 5566 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5567 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5568 | return; |
| 5569 | } |
| 5570 | switch (rB(ctx->opcode)) { |
| 5571 | case 0: |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5572 | case 1: |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5573 | case 2: |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5574 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 5575 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | a4bb6c3 | 2007-09-21 05:28:33 +0000 | [diff] [blame] | 5576 | gen_op_440_tlbwe(rB(ctx->opcode)); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5577 | break; |
| 5578 | default: |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5579 | GEN_EXCP_INVAL(ctx); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5580 | break; |
| 5581 | } |
| 5582 | #endif |
| 5583 | } |
| 5584 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5585 | /* wrtee */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 5586 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5587 | { |
| 5588 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5589 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5590 | #else |
| 5591 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5592 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5593 | return; |
| 5594 | } |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5595 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5596 | gen_op_wrte(); |
j_mayer | dee96f6 | 2007-09-29 15:02:38 +0000 | [diff] [blame] | 5597 | /* Stop translation to have a chance to raise an exception |
| 5598 | * if we just set msr_ee to 1 |
| 5599 | */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5600 | GEN_STOP(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5601 | #endif |
| 5602 | } |
| 5603 | |
| 5604 | /* wrteei */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 5605 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5606 | { |
| 5607 | #if defined(CONFIG_USER_ONLY) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5608 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5609 | #else |
| 5610 | if (unlikely(!ctx->supervisor)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5611 | GEN_EXCP_PRIVOPC(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5612 | return; |
| 5613 | } |
aurel32 | 86c581d | 2008-09-02 23:26:32 +0000 | [diff] [blame] | 5614 | tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5615 | gen_op_wrte(); |
j_mayer | dee96f6 | 2007-09-29 15:02:38 +0000 | [diff] [blame] | 5616 | /* Stop translation to have a chance to raise an exception |
| 5617 | * if we just set msr_ee to 1 |
| 5618 | */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5619 | GEN_STOP(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5620 | #endif |
| 5621 | } |
| 5622 | |
j_mayer | 08e46e5 | 2007-04-16 07:18:42 +0000 | [diff] [blame] | 5623 | /* PowerPC 440 specific instructions */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5624 | /* dlmzb */ |
| 5625 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC) |
| 5626 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5627 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
| 5628 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5629 | gen_op_440_dlmzb(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5630 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 5631 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
| 5632 | tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5633 | if (Rc(ctx->opcode)) { |
| 5634 | gen_op_440_dlmzb_update_Rc(); |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 5635 | tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5636 | } |
| 5637 | } |
| 5638 | |
| 5639 | /* mbar replaces eieio on 440 */ |
| 5640 | GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE) |
| 5641 | { |
| 5642 | /* interpreted as no-op */ |
| 5643 | } |
| 5644 | |
| 5645 | /* msync replaces sync on 440 */ |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 5646 | GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5647 | { |
| 5648 | /* interpreted as no-op */ |
| 5649 | } |
| 5650 | |
| 5651 | /* icbt */ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 5652 | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5653 | { |
| 5654 | /* interpreted as no-op */ |
| 5655 | /* XXX: specification say this is treated as a load by the MMU |
| 5656 | * but does not generate any exception |
| 5657 | */ |
| 5658 | } |
| 5659 | |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 5660 | /*** Altivec vector extension ***/ |
| 5661 | /* Altivec registers moves */ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 5662 | |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 5663 | static always_inline void gen_load_avr(int t, int reg) { |
| 5664 | tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]); |
| 5665 | tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]); |
| 5666 | } |
| 5667 | |
| 5668 | static always_inline void gen_store_avr(int reg, int t) { |
| 5669 | tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]); |
| 5670 | tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]); |
| 5671 | } |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 5672 | |
| 5673 | #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 5674 | #define OP_VR_LD_TABLE(name) \ |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 5675 | static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \ |
| 5676 | GEN_MEM_FUNCS(vr_l##name), \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 5677 | }; |
| 5678 | #define OP_VR_ST_TABLE(name) \ |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 5679 | static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \ |
| 5680 | GEN_MEM_FUNCS(vr_st##name), \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 5681 | }; |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 5682 | |
| 5683 | #define GEN_VR_LDX(name, opc2, opc3) \ |
| 5684 | GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ |
| 5685 | { \ |
| 5686 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 5687 | GEN_EXCP_NO_VR(ctx); \ |
| 5688 | return; \ |
| 5689 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 5690 | gen_addr_reg_index(cpu_T[0], ctx); \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 5691 | op_vr_ldst(vr_l##name); \ |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 5692 | gen_store_avr(rD(ctx->opcode), 0); \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 5693 | } |
| 5694 | |
| 5695 | #define GEN_VR_STX(name, opc2, opc3) \ |
| 5696 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ |
| 5697 | { \ |
| 5698 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 5699 | GEN_EXCP_NO_VR(ctx); \ |
| 5700 | return; \ |
| 5701 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 5702 | gen_addr_reg_index(cpu_T[0], ctx); \ |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 5703 | gen_load_avr(0, rS(ctx->opcode)); \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 5704 | op_vr_ldst(vr_st##name); \ |
| 5705 | } |
| 5706 | |
| 5707 | OP_VR_LD_TABLE(vx); |
| 5708 | GEN_VR_LDX(vx, 0x07, 0x03); |
| 5709 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
| 5710 | #define gen_op_vr_lvxl gen_op_vr_lvx |
| 5711 | GEN_VR_LDX(vxl, 0x07, 0x0B); |
| 5712 | |
| 5713 | OP_VR_ST_TABLE(vx); |
| 5714 | GEN_VR_STX(vx, 0x07, 0x07); |
| 5715 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
| 5716 | #define gen_op_vr_stvxl gen_op_vr_stvx |
| 5717 | GEN_VR_STX(vxl, 0x07, 0x0F); |
| 5718 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5719 | /*** SPE extension ***/ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5720 | /* Register moves */ |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 5721 | |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5722 | static always_inline void gen_load_gpr64(TCGv t, int reg) { |
| 5723 | #if defined(TARGET_PPC64) |
| 5724 | tcg_gen_mov_i64(t, cpu_gpr[reg]); |
| 5725 | #else |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 5726 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5727 | #endif |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5728 | } |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5729 | |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5730 | static always_inline void gen_store_gpr64(int reg, TCGv t) { |
| 5731 | #if defined(TARGET_PPC64) |
| 5732 | tcg_gen_mov_i64(cpu_gpr[reg], t); |
| 5733 | #else |
| 5734 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
aurel32 | 19f98ff | 2008-10-15 17:00:29 +0000 | [diff] [blame] | 5735 | TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5736 | tcg_gen_shri_i64(tmp, t, 32); |
| 5737 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); |
| 5738 | tcg_temp_free(tmp); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5739 | #endif |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5740 | } |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 5741 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5742 | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \ |
| 5743 | GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \ |
| 5744 | { \ |
| 5745 | if (Rc(ctx->opcode)) \ |
| 5746 | gen_##name1(ctx); \ |
| 5747 | else \ |
| 5748 | gen_##name0(ctx); \ |
| 5749 | } |
| 5750 | |
| 5751 | /* Handler for undefined SPE opcodes */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5752 | static always_inline void gen_speundef (DisasContext *ctx) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5753 | { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5754 | GEN_EXCP_INVAL(ctx); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5755 | } |
| 5756 | |
| 5757 | /* SPE load and stores */ |
aurel32 | f0aabd1 | 2008-10-15 17:00:18 +0000 | [diff] [blame] | 5758 | static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5759 | { |
| 5760 | target_long simm = rB(ctx->opcode); |
| 5761 | |
aurel32 | f0aabd1 | 2008-10-15 17:00:18 +0000 | [diff] [blame] | 5762 | if (rA(ctx->opcode) == 0) |
| 5763 | tcg_gen_movi_tl(EA, simm << sh); |
| 5764 | else if (likely(simm != 0)) |
| 5765 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh); |
| 5766 | else |
| 5767 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5768 | } |
| 5769 | |
| 5770 | #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5771 | #define OP_SPE_LD_TABLE(name) \ |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 5772 | static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \ |
| 5773 | GEN_MEM_FUNCS(spe_l##name), \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5774 | }; |
| 5775 | #define OP_SPE_ST_TABLE(name) \ |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 5776 | static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \ |
| 5777 | GEN_MEM_FUNCS(spe_st##name), \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5778 | }; |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5779 | |
| 5780 | #define GEN_SPE_LD(name, sh) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5781 | static always_inline void gen_evl##name (DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5782 | { \ |
| 5783 | if (unlikely(!ctx->spe_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5784 | GEN_EXCP_NO_AP(ctx); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5785 | return; \ |
| 5786 | } \ |
aurel32 | f0aabd1 | 2008-10-15 17:00:18 +0000 | [diff] [blame] | 5787 | gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5788 | op_spe_ldst(spe_l##name); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5789 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5790 | } |
| 5791 | |
| 5792 | #define GEN_SPE_LDX(name) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5793 | static always_inline void gen_evl##name##x (DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5794 | { \ |
| 5795 | if (unlikely(!ctx->spe_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5796 | GEN_EXCP_NO_AP(ctx); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5797 | return; \ |
| 5798 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 5799 | gen_addr_reg_index(cpu_T[0], ctx); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5800 | op_spe_ldst(spe_l##name); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5801 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5802 | } |
| 5803 | |
| 5804 | #define GEN_SPEOP_LD(name, sh) \ |
| 5805 | OP_SPE_LD_TABLE(name); \ |
| 5806 | GEN_SPE_LD(name, sh); \ |
| 5807 | GEN_SPE_LDX(name) |
| 5808 | |
| 5809 | #define GEN_SPE_ST(name, sh) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5810 | static always_inline void gen_evst##name (DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5811 | { \ |
| 5812 | if (unlikely(!ctx->spe_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5813 | GEN_EXCP_NO_AP(ctx); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5814 | return; \ |
| 5815 | } \ |
aurel32 | f0aabd1 | 2008-10-15 17:00:18 +0000 | [diff] [blame] | 5816 | gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5817 | gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5818 | op_spe_ldst(spe_st##name); \ |
| 5819 | } |
| 5820 | |
| 5821 | #define GEN_SPE_STX(name) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5822 | static always_inline void gen_evst##name##x (DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5823 | { \ |
| 5824 | if (unlikely(!ctx->spe_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5825 | GEN_EXCP_NO_AP(ctx); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5826 | return; \ |
| 5827 | } \ |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 5828 | gen_addr_reg_index(cpu_T[0], ctx); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5829 | gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5830 | op_spe_ldst(spe_st##name); \ |
| 5831 | } |
| 5832 | |
| 5833 | #define GEN_SPEOP_ST(name, sh) \ |
| 5834 | OP_SPE_ST_TABLE(name); \ |
| 5835 | GEN_SPE_ST(name, sh); \ |
| 5836 | GEN_SPE_STX(name) |
| 5837 | |
| 5838 | #define GEN_SPEOP_LDST(name, sh) \ |
| 5839 | GEN_SPEOP_LD(name, sh); \ |
| 5840 | GEN_SPEOP_ST(name, sh) |
| 5841 | |
| 5842 | /* SPE arithmetic and logic */ |
| 5843 | #define GEN_SPEOP_ARITH2(name) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5844 | static always_inline void gen_##name (DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5845 | { \ |
| 5846 | if (unlikely(!ctx->spe_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5847 | GEN_EXCP_NO_AP(ctx); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5848 | return; \ |
| 5849 | } \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5850 | gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \ |
| 5851 | gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5852 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5853 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5854 | } |
| 5855 | |
aurel32 | cf96081 | 2008-10-21 11:29:55 +0000 | [diff] [blame] | 5856 | #define GEN_SPEOP_TCG_ARITH2(name, tcg_op) \ |
aurel32 | 3d3a6a0 | 2008-10-15 17:00:45 +0000 | [diff] [blame] | 5857 | static always_inline void gen_##name (DisasContext *ctx) \ |
| 5858 | { \ |
| 5859 | if (unlikely(!ctx->spe_enabled)) { \ |
| 5860 | GEN_EXCP_NO_AP(ctx); \ |
| 5861 | return; \ |
| 5862 | } \ |
| 5863 | TCGv t0 = tcg_temp_new(TCG_TYPE_I64); \ |
| 5864 | TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \ |
| 5865 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
| 5866 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
aurel32 | cf96081 | 2008-10-21 11:29:55 +0000 | [diff] [blame] | 5867 | tcg_op(t0, t0, t1); \ |
aurel32 | 3d3a6a0 | 2008-10-15 17:00:45 +0000 | [diff] [blame] | 5868 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
| 5869 | tcg_temp_free(t0); \ |
| 5870 | tcg_temp_free(t1); \ |
| 5871 | } |
| 5872 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5873 | #define GEN_SPEOP_ARITH1(name) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5874 | static always_inline void gen_##name (DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5875 | { \ |
| 5876 | if (unlikely(!ctx->spe_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5877 | GEN_EXCP_NO_AP(ctx); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5878 | return; \ |
| 5879 | } \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5880 | gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5881 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5882 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5883 | } |
| 5884 | |
| 5885 | #define GEN_SPEOP_COMP(name) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5886 | static always_inline void gen_##name (DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5887 | { \ |
| 5888 | if (unlikely(!ctx->spe_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5889 | GEN_EXCP_NO_AP(ctx); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5890 | return; \ |
| 5891 | } \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5892 | gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \ |
| 5893 | gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5894 | gen_op_##name(); \ |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 5895 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5896 | } |
| 5897 | |
| 5898 | /* Logical */ |
aurel32 | cf96081 | 2008-10-21 11:29:55 +0000 | [diff] [blame] | 5899 | GEN_SPEOP_TCG_ARITH2(evand, tcg_gen_and_i64); |
| 5900 | GEN_SPEOP_TCG_ARITH2(evandc, tcg_gen_andc_i64); |
| 5901 | GEN_SPEOP_TCG_ARITH2(evxor, tcg_gen_xor_i64); |
| 5902 | GEN_SPEOP_TCG_ARITH2(evor, tcg_gen_or_i64); |
| 5903 | GEN_SPEOP_TCG_ARITH2(evnor, tcg_gen_nor_i64); |
| 5904 | GEN_SPEOP_TCG_ARITH2(eveqv, tcg_gen_eqv_i64); |
| 5905 | GEN_SPEOP_TCG_ARITH2(evorc, tcg_gen_orc_i64); |
| 5906 | GEN_SPEOP_TCG_ARITH2(evnand, tcg_gen_nand_i64); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5907 | GEN_SPEOP_ARITH2(evsrwu); |
| 5908 | GEN_SPEOP_ARITH2(evsrws); |
| 5909 | GEN_SPEOP_ARITH2(evslw); |
| 5910 | GEN_SPEOP_ARITH2(evrlw); |
| 5911 | GEN_SPEOP_ARITH2(evmergehi); |
| 5912 | GEN_SPEOP_ARITH2(evmergelo); |
| 5913 | GEN_SPEOP_ARITH2(evmergehilo); |
| 5914 | GEN_SPEOP_ARITH2(evmergelohi); |
| 5915 | |
| 5916 | /* Arithmetic */ |
| 5917 | GEN_SPEOP_ARITH2(evaddw); |
| 5918 | GEN_SPEOP_ARITH2(evsubfw); |
| 5919 | GEN_SPEOP_ARITH1(evabs); |
| 5920 | GEN_SPEOP_ARITH1(evneg); |
| 5921 | GEN_SPEOP_ARITH1(evextsb); |
| 5922 | GEN_SPEOP_ARITH1(evextsh); |
| 5923 | GEN_SPEOP_ARITH1(evrndw); |
| 5924 | GEN_SPEOP_ARITH1(evcntlzw); |
| 5925 | GEN_SPEOP_ARITH1(evcntlsw); |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5926 | static always_inline void gen_brinc (DisasContext *ctx) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5927 | { |
| 5928 | /* Note: brinc is usable even if SPE is disabled */ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5929 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
| 5930 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5931 | gen_op_brinc(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5932 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5933 | } |
| 5934 | |
| 5935 | #define GEN_SPEOP_ARITH_IMM2(name) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5936 | static always_inline void gen_##name##i (DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5937 | { \ |
| 5938 | if (unlikely(!ctx->spe_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5939 | GEN_EXCP_NO_AP(ctx); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5940 | return; \ |
| 5941 | } \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5942 | gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5943 | gen_op_splatwi_T1_64(rA(ctx->opcode)); \ |
| 5944 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5945 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5946 | } |
| 5947 | |
| 5948 | #define GEN_SPEOP_LOGIC_IMM2(name) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5949 | static always_inline void gen_##name##i (DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5950 | { \ |
| 5951 | if (unlikely(!ctx->spe_enabled)) { \ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 5952 | GEN_EXCP_NO_AP(ctx); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5953 | return; \ |
| 5954 | } \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5955 | gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5956 | gen_op_splatwi_T1_64(rB(ctx->opcode)); \ |
| 5957 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5958 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5959 | } |
| 5960 | |
| 5961 | GEN_SPEOP_ARITH_IMM2(evaddw); |
| 5962 | #define gen_evaddiw gen_evaddwi |
| 5963 | GEN_SPEOP_ARITH_IMM2(evsubfw); |
| 5964 | #define gen_evsubifw gen_evsubfwi |
| 5965 | GEN_SPEOP_LOGIC_IMM2(evslw); |
| 5966 | GEN_SPEOP_LOGIC_IMM2(evsrwu); |
| 5967 | #define gen_evsrwis gen_evsrwsi |
| 5968 | GEN_SPEOP_LOGIC_IMM2(evsrws); |
| 5969 | #define gen_evsrwiu gen_evsrwui |
| 5970 | GEN_SPEOP_LOGIC_IMM2(evrlw); |
| 5971 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5972 | static always_inline void gen_evsplati (DisasContext *ctx) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5973 | { |
| 5974 | int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27; |
| 5975 | |
| 5976 | gen_op_splatwi_T0_64(imm); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5977 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5978 | } |
| 5979 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 5980 | static always_inline void gen_evsplatfi (DisasContext *ctx) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5981 | { |
| 5982 | uint32_t imm = rA(ctx->opcode) << 27; |
| 5983 | |
| 5984 | gen_op_splatwi_T0_64(imm); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 5985 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 5986 | } |
| 5987 | |
| 5988 | /* Comparison */ |
| 5989 | GEN_SPEOP_COMP(evcmpgtu); |
| 5990 | GEN_SPEOP_COMP(evcmpgts); |
| 5991 | GEN_SPEOP_COMP(evcmpltu); |
| 5992 | GEN_SPEOP_COMP(evcmplts); |
| 5993 | GEN_SPEOP_COMP(evcmpeq); |
| 5994 | |
| 5995 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); //// |
| 5996 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE); |
| 5997 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); //// |
| 5998 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE); |
| 5999 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); //// |
| 6000 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); //// |
| 6001 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); //// |
| 6002 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); // |
| 6003 | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); //// |
| 6004 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); //// |
| 6005 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); //// |
| 6006 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); //// |
| 6007 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); //// |
| 6008 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); //// |
| 6009 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); //// |
| 6010 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE); |
| 6011 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); //// |
| 6012 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE); |
| 6013 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); // |
| 6014 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE); |
| 6015 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); //// |
| 6016 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); //// |
| 6017 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); //// |
| 6018 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// |
| 6019 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// |
| 6020 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 6021 | static always_inline void gen_evsel (DisasContext *ctx) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6022 | { |
| 6023 | if (unlikely(!ctx->spe_enabled)) { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 6024 | GEN_EXCP_NO_AP(ctx); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6025 | return; |
| 6026 | } |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 6027 | tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 6028 | gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); |
| 6029 | gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6030 | gen_op_evsel(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 6031 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6032 | } |
| 6033 | |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 6034 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6035 | { |
| 6036 | gen_evsel(ctx); |
| 6037 | } |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 6038 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6039 | { |
| 6040 | gen_evsel(ctx); |
| 6041 | } |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 6042 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6043 | { |
| 6044 | gen_evsel(ctx); |
| 6045 | } |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 6046 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6047 | { |
| 6048 | gen_evsel(ctx); |
| 6049 | } |
| 6050 | |
| 6051 | /* Load and stores */ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6052 | GEN_SPEOP_LDST(dd, 3); |
| 6053 | GEN_SPEOP_LDST(dw, 3); |
| 6054 | GEN_SPEOP_LDST(dh, 3); |
| 6055 | GEN_SPEOP_LDST(whe, 2); |
| 6056 | GEN_SPEOP_LD(whou, 2); |
| 6057 | GEN_SPEOP_LD(whos, 2); |
| 6058 | GEN_SPEOP_ST(who, 2); |
| 6059 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6060 | #define _GEN_OP_SPE_STWWE(suffix) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 6061 | static always_inline void gen_op_spe_stwwe_##suffix (void) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6062 | { \ |
| 6063 | gen_op_srli32_T1_64(); \ |
| 6064 | gen_op_spe_stwwo_##suffix(); \ |
| 6065 | } |
| 6066 | #define _GEN_OP_SPE_STWWE_LE(suffix) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 6067 | static always_inline void gen_op_spe_stwwe_le_##suffix (void) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6068 | { \ |
| 6069 | gen_op_srli32_T1_64(); \ |
| 6070 | gen_op_spe_stwwo_le_##suffix(); \ |
| 6071 | } |
| 6072 | #if defined(TARGET_PPC64) |
| 6073 | #define GEN_OP_SPE_STWWE(suffix) \ |
| 6074 | _GEN_OP_SPE_STWWE(suffix); \ |
| 6075 | _GEN_OP_SPE_STWWE_LE(suffix); \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 6076 | static always_inline void gen_op_spe_stwwe_64_##suffix (void) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6077 | { \ |
| 6078 | gen_op_srli32_T1_64(); \ |
| 6079 | gen_op_spe_stwwo_64_##suffix(); \ |
| 6080 | } \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 6081 | static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6082 | { \ |
| 6083 | gen_op_srli32_T1_64(); \ |
| 6084 | gen_op_spe_stwwo_le_64_##suffix(); \ |
| 6085 | } |
| 6086 | #else |
| 6087 | #define GEN_OP_SPE_STWWE(suffix) \ |
| 6088 | _GEN_OP_SPE_STWWE(suffix); \ |
| 6089 | _GEN_OP_SPE_STWWE_LE(suffix) |
| 6090 | #endif |
| 6091 | #if defined(CONFIG_USER_ONLY) |
| 6092 | GEN_OP_SPE_STWWE(raw); |
| 6093 | #else /* defined(CONFIG_USER_ONLY) */ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6094 | GEN_OP_SPE_STWWE(user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6095 | GEN_OP_SPE_STWWE(kernel); |
| 6096 | GEN_OP_SPE_STWWE(hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6097 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 6098 | GEN_SPEOP_ST(wwe, 2); |
| 6099 | GEN_SPEOP_ST(wwo, 2); |
| 6100 | |
| 6101 | #define GEN_SPE_LDSPLAT(name, op, suffix) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 6102 | static always_inline void gen_op_spe_l##name##_##suffix (void) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6103 | { \ |
| 6104 | gen_op_##op##_##suffix(); \ |
| 6105 | gen_op_splatw_T1_64(); \ |
| 6106 | } |
| 6107 | |
| 6108 | #define GEN_OP_SPE_LHE(suffix) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 6109 | static always_inline void gen_op_spe_lhe_##suffix (void) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6110 | { \ |
| 6111 | gen_op_spe_lh_##suffix(); \ |
| 6112 | gen_op_sli16_T1_64(); \ |
| 6113 | } |
| 6114 | |
| 6115 | #define GEN_OP_SPE_LHX(suffix) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 6116 | static always_inline void gen_op_spe_lhx_##suffix (void) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6117 | { \ |
| 6118 | gen_op_spe_lh_##suffix(); \ |
| 6119 | gen_op_extsh_T1_64(); \ |
| 6120 | } |
| 6121 | |
| 6122 | #if defined(CONFIG_USER_ONLY) |
| 6123 | GEN_OP_SPE_LHE(raw); |
| 6124 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw); |
| 6125 | GEN_OP_SPE_LHE(le_raw); |
| 6126 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw); |
| 6127 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw); |
| 6128 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw); |
| 6129 | GEN_OP_SPE_LHX(raw); |
| 6130 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw); |
| 6131 | GEN_OP_SPE_LHX(le_raw); |
| 6132 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw); |
| 6133 | #if defined(TARGET_PPC64) |
| 6134 | GEN_OP_SPE_LHE(64_raw); |
| 6135 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw); |
| 6136 | GEN_OP_SPE_LHE(le_64_raw); |
| 6137 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw); |
| 6138 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw); |
| 6139 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw); |
| 6140 | GEN_OP_SPE_LHX(64_raw); |
| 6141 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw); |
| 6142 | GEN_OP_SPE_LHX(le_64_raw); |
| 6143 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw); |
| 6144 | #endif |
| 6145 | #else |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6146 | GEN_OP_SPE_LHE(user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6147 | GEN_OP_SPE_LHE(kernel); |
| 6148 | GEN_OP_SPE_LHE(hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6149 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6150 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel); |
| 6151 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6152 | GEN_OP_SPE_LHE(le_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6153 | GEN_OP_SPE_LHE(le_kernel); |
| 6154 | GEN_OP_SPE_LHE(le_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6155 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6156 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel); |
| 6157 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6158 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6159 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel); |
| 6160 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6161 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6162 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel); |
| 6163 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6164 | GEN_OP_SPE_LHX(user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6165 | GEN_OP_SPE_LHX(kernel); |
| 6166 | GEN_OP_SPE_LHX(hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6167 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6168 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel); |
| 6169 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6170 | GEN_OP_SPE_LHX(le_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6171 | GEN_OP_SPE_LHX(le_kernel); |
| 6172 | GEN_OP_SPE_LHX(le_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6173 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6174 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel); |
| 6175 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6176 | #if defined(TARGET_PPC64) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6177 | GEN_OP_SPE_LHE(64_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6178 | GEN_OP_SPE_LHE(64_kernel); |
| 6179 | GEN_OP_SPE_LHE(64_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6180 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6181 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel); |
| 6182 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6183 | GEN_OP_SPE_LHE(le_64_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6184 | GEN_OP_SPE_LHE(le_64_kernel); |
| 6185 | GEN_OP_SPE_LHE(le_64_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6186 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6187 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel); |
| 6188 | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6189 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6190 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel); |
| 6191 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6192 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6193 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel); |
| 6194 | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6195 | GEN_OP_SPE_LHX(64_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6196 | GEN_OP_SPE_LHX(64_kernel); |
| 6197 | GEN_OP_SPE_LHX(64_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6198 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6199 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel); |
| 6200 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6201 | GEN_OP_SPE_LHX(le_64_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6202 | GEN_OP_SPE_LHX(le_64_kernel); |
| 6203 | GEN_OP_SPE_LHX(le_64_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6204 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user); |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 6205 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel); |
| 6206 | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6207 | #endif |
| 6208 | #endif |
| 6209 | GEN_SPEOP_LD(hhesplat, 1); |
| 6210 | GEN_SPEOP_LD(hhousplat, 1); |
| 6211 | GEN_SPEOP_LD(hhossplat, 1); |
| 6212 | GEN_SPEOP_LD(wwsplat, 2); |
| 6213 | GEN_SPEOP_LD(whsplat, 2); |
| 6214 | |
| 6215 | GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); // |
| 6216 | GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); // |
| 6217 | GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); // |
| 6218 | GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); // |
| 6219 | GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); // |
| 6220 | GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); // |
| 6221 | GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); // |
| 6222 | GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); // |
| 6223 | GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); // |
| 6224 | GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); // |
| 6225 | GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); // |
| 6226 | GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); // |
| 6227 | GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); // |
| 6228 | GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); // |
| 6229 | GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); // |
| 6230 | GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); // |
| 6231 | GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); // |
| 6232 | GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); // |
| 6233 | |
| 6234 | /* Multiply and add - TODO */ |
| 6235 | #if 0 |
| 6236 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE); |
| 6237 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE); |
| 6238 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE); |
| 6239 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE); |
| 6240 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE); |
| 6241 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE); |
| 6242 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE); |
| 6243 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE); |
| 6244 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE); |
| 6245 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE); |
| 6246 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE); |
| 6247 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE); |
| 6248 | |
| 6249 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE); |
| 6250 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE); |
| 6251 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE); |
| 6252 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE); |
| 6253 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE); |
| 6254 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE); |
| 6255 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE); |
| 6256 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE); |
| 6257 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE); |
| 6258 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE); |
| 6259 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE); |
| 6260 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE); |
| 6261 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE); |
| 6262 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE); |
| 6263 | |
| 6264 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE); |
| 6265 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE); |
| 6266 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE); |
| 6267 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE); |
| 6268 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE); |
| 6269 | GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE); |
| 6270 | |
| 6271 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE); |
| 6272 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE); |
| 6273 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE); |
| 6274 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE); |
| 6275 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE); |
| 6276 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE); |
| 6277 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE); |
| 6278 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE); |
| 6279 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE); |
| 6280 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE); |
| 6281 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE); |
| 6282 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE); |
| 6283 | |
| 6284 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE); |
| 6285 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE); |
| 6286 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE); |
| 6287 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE); |
| 6288 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE); |
| 6289 | |
| 6290 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE); |
| 6291 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE); |
| 6292 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE); |
| 6293 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE); |
| 6294 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE); |
| 6295 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE); |
| 6296 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE); |
| 6297 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE); |
| 6298 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE); |
| 6299 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE); |
| 6300 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE); |
| 6301 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE); |
| 6302 | |
| 6303 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE); |
| 6304 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE); |
| 6305 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE); |
| 6306 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE); |
| 6307 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE); |
| 6308 | #endif |
| 6309 | |
| 6310 | /*** SPE floating-point extension ***/ |
| 6311 | #define GEN_SPEFPUOP_CONV(name) \ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 6312 | static always_inline void gen_##name (DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6313 | { \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 6314 | gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6315 | gen_op_##name(); \ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 6316 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6317 | } |
| 6318 | |
| 6319 | /* Single precision floating-point vectors operations */ |
| 6320 | /* Arithmetic */ |
| 6321 | GEN_SPEOP_ARITH2(evfsadd); |
| 6322 | GEN_SPEOP_ARITH2(evfssub); |
| 6323 | GEN_SPEOP_ARITH2(evfsmul); |
| 6324 | GEN_SPEOP_ARITH2(evfsdiv); |
| 6325 | GEN_SPEOP_ARITH1(evfsabs); |
| 6326 | GEN_SPEOP_ARITH1(evfsnabs); |
| 6327 | GEN_SPEOP_ARITH1(evfsneg); |
| 6328 | /* Conversion */ |
| 6329 | GEN_SPEFPUOP_CONV(evfscfui); |
| 6330 | GEN_SPEFPUOP_CONV(evfscfsi); |
| 6331 | GEN_SPEFPUOP_CONV(evfscfuf); |
| 6332 | GEN_SPEFPUOP_CONV(evfscfsf); |
| 6333 | GEN_SPEFPUOP_CONV(evfsctui); |
| 6334 | GEN_SPEFPUOP_CONV(evfsctsi); |
| 6335 | GEN_SPEFPUOP_CONV(evfsctuf); |
| 6336 | GEN_SPEFPUOP_CONV(evfsctsf); |
| 6337 | GEN_SPEFPUOP_CONV(evfsctuiz); |
| 6338 | GEN_SPEFPUOP_CONV(evfsctsiz); |
| 6339 | /* Comparison */ |
| 6340 | GEN_SPEOP_COMP(evfscmpgt); |
| 6341 | GEN_SPEOP_COMP(evfscmplt); |
| 6342 | GEN_SPEOP_COMP(evfscmpeq); |
| 6343 | GEN_SPEOP_COMP(evfststgt); |
| 6344 | GEN_SPEOP_COMP(evfststlt); |
| 6345 | GEN_SPEOP_COMP(evfststeq); |
| 6346 | |
| 6347 | /* Opcodes definitions */ |
| 6348 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); // |
| 6349 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); // |
| 6350 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); // |
| 6351 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); // |
| 6352 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); // |
| 6353 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); // |
| 6354 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); // |
| 6355 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); // |
| 6356 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); // |
| 6357 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); // |
| 6358 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); // |
| 6359 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); // |
| 6360 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); // |
| 6361 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); // |
| 6362 | |
| 6363 | /* Single precision floating-point operations */ |
| 6364 | /* Arithmetic */ |
| 6365 | GEN_SPEOP_ARITH2(efsadd); |
| 6366 | GEN_SPEOP_ARITH2(efssub); |
| 6367 | GEN_SPEOP_ARITH2(efsmul); |
| 6368 | GEN_SPEOP_ARITH2(efsdiv); |
| 6369 | GEN_SPEOP_ARITH1(efsabs); |
| 6370 | GEN_SPEOP_ARITH1(efsnabs); |
| 6371 | GEN_SPEOP_ARITH1(efsneg); |
| 6372 | /* Conversion */ |
| 6373 | GEN_SPEFPUOP_CONV(efscfui); |
| 6374 | GEN_SPEFPUOP_CONV(efscfsi); |
| 6375 | GEN_SPEFPUOP_CONV(efscfuf); |
| 6376 | GEN_SPEFPUOP_CONV(efscfsf); |
| 6377 | GEN_SPEFPUOP_CONV(efsctui); |
| 6378 | GEN_SPEFPUOP_CONV(efsctsi); |
| 6379 | GEN_SPEFPUOP_CONV(efsctuf); |
| 6380 | GEN_SPEFPUOP_CONV(efsctsf); |
| 6381 | GEN_SPEFPUOP_CONV(efsctuiz); |
| 6382 | GEN_SPEFPUOP_CONV(efsctsiz); |
| 6383 | GEN_SPEFPUOP_CONV(efscfd); |
| 6384 | /* Comparison */ |
| 6385 | GEN_SPEOP_COMP(efscmpgt); |
| 6386 | GEN_SPEOP_COMP(efscmplt); |
| 6387 | GEN_SPEOP_COMP(efscmpeq); |
| 6388 | GEN_SPEOP_COMP(efststgt); |
| 6389 | GEN_SPEOP_COMP(efststlt); |
| 6390 | GEN_SPEOP_COMP(efststeq); |
| 6391 | |
| 6392 | /* Opcodes definitions */ |
j_mayer | 05332d7 | 2007-11-17 22:26:51 +0000 | [diff] [blame] | 6393 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); // |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6394 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); // |
| 6395 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); // |
| 6396 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); // |
| 6397 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); // |
| 6398 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); // |
| 6399 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6400 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6401 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6402 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); // |
ths | 9ceb2a7 | 2008-08-13 11:30:10 +0000 | [diff] [blame] | 6403 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6404 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); // |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6405 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); // |
| 6406 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); // |
| 6407 | |
| 6408 | /* Double precision floating-point operations */ |
| 6409 | /* Arithmetic */ |
| 6410 | GEN_SPEOP_ARITH2(efdadd); |
| 6411 | GEN_SPEOP_ARITH2(efdsub); |
| 6412 | GEN_SPEOP_ARITH2(efdmul); |
| 6413 | GEN_SPEOP_ARITH2(efddiv); |
| 6414 | GEN_SPEOP_ARITH1(efdabs); |
| 6415 | GEN_SPEOP_ARITH1(efdnabs); |
| 6416 | GEN_SPEOP_ARITH1(efdneg); |
| 6417 | /* Conversion */ |
| 6418 | |
| 6419 | GEN_SPEFPUOP_CONV(efdcfui); |
| 6420 | GEN_SPEFPUOP_CONV(efdcfsi); |
| 6421 | GEN_SPEFPUOP_CONV(efdcfuf); |
| 6422 | GEN_SPEFPUOP_CONV(efdcfsf); |
| 6423 | GEN_SPEFPUOP_CONV(efdctui); |
| 6424 | GEN_SPEFPUOP_CONV(efdctsi); |
| 6425 | GEN_SPEFPUOP_CONV(efdctuf); |
| 6426 | GEN_SPEFPUOP_CONV(efdctsf); |
| 6427 | GEN_SPEFPUOP_CONV(efdctuiz); |
| 6428 | GEN_SPEFPUOP_CONV(efdctsiz); |
| 6429 | GEN_SPEFPUOP_CONV(efdcfs); |
| 6430 | GEN_SPEFPUOP_CONV(efdcfuid); |
| 6431 | GEN_SPEFPUOP_CONV(efdcfsid); |
| 6432 | GEN_SPEFPUOP_CONV(efdctuidz); |
| 6433 | GEN_SPEFPUOP_CONV(efdctsidz); |
| 6434 | /* Comparison */ |
| 6435 | GEN_SPEOP_COMP(efdcmpgt); |
| 6436 | GEN_SPEOP_COMP(efdcmplt); |
| 6437 | GEN_SPEOP_COMP(efdcmpeq); |
| 6438 | GEN_SPEOP_COMP(efdtstgt); |
| 6439 | GEN_SPEOP_COMP(efdtstlt); |
| 6440 | GEN_SPEOP_COMP(efdtsteq); |
| 6441 | |
| 6442 | /* Opcodes definitions */ |
| 6443 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); // |
| 6444 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6445 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); // |
| 6446 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); // |
| 6447 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); // |
| 6448 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6449 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); // |
| 6450 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); // |
| 6451 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6452 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6453 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6454 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6455 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6456 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); // |
| 6457 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); // |
| 6458 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); // |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6459 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6460 | /* End opcode list */ |
| 6461 | GEN_OPCODE_MARK(end); |
| 6462 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6463 | #include "translate_init.c" |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 6464 | #include "helper_regs.h" |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6465 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6466 | /*****************************************************************************/ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6467 | /* Misc PowerPC helpers */ |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 6468 | void cpu_dump_state (CPUState *env, FILE *f, |
| 6469 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 6470 | int flags) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6471 | { |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6472 | #define RGPL 4 |
| 6473 | #define RFPL 4 |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6474 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6475 | int i; |
| 6476 | |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 6477 | cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n", |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 6478 | env->nip, env->lr, env->ctr, env->xer); |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 6479 | cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n", |
| 6480 | env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 6481 | #if !defined(NO_TIMER_DUMP) |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 6482 | cpu_fprintf(f, "TB %08x %08x " |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6483 | #if !defined(CONFIG_USER_ONLY) |
| 6484 | "DECR %08x" |
| 6485 | #endif |
| 6486 | "\n", |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 6487 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6488 | #if !defined(CONFIG_USER_ONLY) |
| 6489 | , cpu_ppc_load_decr(env) |
| 6490 | #endif |
| 6491 | ); |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 6492 | #endif |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6493 | for (i = 0; i < 32; i++) { |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6494 | if ((i & (RGPL - 1)) == 0) |
| 6495 | cpu_fprintf(f, "GPR%02d", i); |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 6496 | cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i)); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6497 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 6498 | cpu_fprintf(f, "\n"); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6499 | } |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6500 | cpu_fprintf(f, "CR "); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6501 | for (i = 0; i < 8; i++) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 6502 | cpu_fprintf(f, "%01x", env->crf[i]); |
| 6503 | cpu_fprintf(f, " ["); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6504 | for (i = 0; i < 8; i++) { |
| 6505 | char a = '-'; |
| 6506 | if (env->crf[i] & 0x08) |
| 6507 | a = 'L'; |
| 6508 | else if (env->crf[i] & 0x04) |
| 6509 | a = 'G'; |
| 6510 | else if (env->crf[i] & 0x02) |
| 6511 | a = 'E'; |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 6512 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6513 | } |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 6514 | cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6515 | for (i = 0; i < 32; i++) { |
| 6516 | if ((i & (RFPL - 1)) == 0) |
| 6517 | cpu_fprintf(f, "FPR%02d", i); |
bellard | 26a7646 | 2006-06-25 18:15:32 +0000 | [diff] [blame] | 6518 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6519 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 6520 | cpu_fprintf(f, "\n"); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6521 | } |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 6522 | #if !defined(CONFIG_USER_ONLY) |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 6523 | cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n", |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6524 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1); |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 6525 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6526 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6527 | #undef RGPL |
| 6528 | #undef RFPL |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6529 | } |
| 6530 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6531 | void cpu_dump_statistics (CPUState *env, FILE*f, |
| 6532 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 6533 | int flags) |
| 6534 | { |
| 6535 | #if defined(DO_PPC_STATISTICS) |
| 6536 | opc_handler_t **t1, **t2, **t3, *handler; |
| 6537 | int op1, op2, op3; |
| 6538 | |
| 6539 | t1 = env->opcodes; |
| 6540 | for (op1 = 0; op1 < 64; op1++) { |
| 6541 | handler = t1[op1]; |
| 6542 | if (is_indirect_opcode(handler)) { |
| 6543 | t2 = ind_table(handler); |
| 6544 | for (op2 = 0; op2 < 32; op2++) { |
| 6545 | handler = t2[op2]; |
| 6546 | if (is_indirect_opcode(handler)) { |
| 6547 | t3 = ind_table(handler); |
| 6548 | for (op3 = 0; op3 < 32; op3++) { |
| 6549 | handler = t3[op3]; |
| 6550 | if (handler->count == 0) |
| 6551 | continue; |
| 6552 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " |
| 6553 | "%016llx %lld\n", |
| 6554 | op1, op2, op3, op1, (op3 << 5) | op2, |
| 6555 | handler->oname, |
| 6556 | handler->count, handler->count); |
| 6557 | } |
| 6558 | } else { |
| 6559 | if (handler->count == 0) |
| 6560 | continue; |
| 6561 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " |
| 6562 | "%016llx %lld\n", |
| 6563 | op1, op2, op1, op2, handler->oname, |
| 6564 | handler->count, handler->count); |
| 6565 | } |
| 6566 | } |
| 6567 | } else { |
| 6568 | if (handler->count == 0) |
| 6569 | continue; |
| 6570 | cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n", |
| 6571 | op1, op1, handler->oname, |
| 6572 | handler->count, handler->count); |
| 6573 | } |
| 6574 | } |
| 6575 | #endif |
| 6576 | } |
| 6577 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6578 | /*****************************************************************************/ |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 6579 | static always_inline void gen_intermediate_code_internal (CPUState *env, |
| 6580 | TranslationBlock *tb, |
| 6581 | int search_pc) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6582 | { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 6583 | DisasContext ctx, *ctxp = &ctx; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6584 | opc_handler_t **table, *handler; |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 6585 | target_ulong pc_start; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6586 | uint16_t *gen_opc_end; |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 6587 | int supervisor, little_endian; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6588 | int j, lj = -1; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 6589 | int num_insns; |
| 6590 | int max_insns; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6591 | |
| 6592 | pc_start = tb->pc; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6593 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 6594 | #if defined(OPTIMIZE_FPRF_UPDATE) |
| 6595 | gen_fprf_ptr = gen_fprf_buf; |
| 6596 | #endif |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 6597 | ctx.nip = pc_start; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6598 | ctx.tb = tb; |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 6599 | ctx.exception = POWERPC_EXCP_NONE; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6600 | ctx.spr_cb = env->spr_cb; |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 6601 | supervisor = env->mmu_idx; |
| 6602 | #if !defined(CONFIG_USER_ONLY) |
j_mayer | 2857068 | 2007-10-02 10:11:50 +0000 | [diff] [blame] | 6603 | ctx.supervisor = supervisor; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 6604 | #endif |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 6605 | little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 6606 | #if defined(TARGET_PPC64) |
| 6607 | ctx.sf_mode = msr_sf; |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 6608 | ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian; |
j_mayer | 2857068 | 2007-10-02 10:11:50 +0000 | [diff] [blame] | 6609 | #else |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 6610 | ctx.mem_idx = (supervisor << 1) | little_endian; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6611 | #endif |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 6612 | ctx.dcache_line_size = env->dcache_line_size; |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 6613 | ctx.fpu_enabled = msr_fp; |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6614 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 6615 | ctx.spe_enabled = msr_spe; |
| 6616 | else |
| 6617 | ctx.spe_enabled = 0; |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6618 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
| 6619 | ctx.altivec_enabled = msr_vr; |
| 6620 | else |
| 6621 | ctx.altivec_enabled = 0; |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 6622 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 6623 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 6624 | else |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 6625 | ctx.singlestep_enabled = 0; |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 6626 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 6627 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
| 6628 | if (unlikely(env->singlestep_enabled)) |
| 6629 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6630 | #if defined (DO_SINGLE_STEP) && 0 |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6631 | /* Single step trace mode */ |
| 6632 | msr_se = 1; |
| 6633 | #endif |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 6634 | num_insns = 0; |
| 6635 | max_insns = tb->cflags & CF_COUNT_MASK; |
| 6636 | if (max_insns == 0) |
| 6637 | max_insns = CF_COUNT_MASK; |
| 6638 | |
| 6639 | gen_icount_start(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6640 | /* Set env in case of segfault during code fetch */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 6641 | while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6642 | if (unlikely(env->nb_breakpoints > 0)) { |
| 6643 | for (j = 0; j < env->nb_breakpoints; j++) { |
bellard | ea4e754 | 2006-05-22 21:50:20 +0000 | [diff] [blame] | 6644 | if (env->breakpoints[j] == ctx.nip) { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 6645 | gen_update_nip(&ctx, ctx.nip); |
bellard | ea4e754 | 2006-05-22 21:50:20 +0000 | [diff] [blame] | 6646 | gen_op_debug(); |
| 6647 | break; |
| 6648 | } |
| 6649 | } |
| 6650 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6651 | if (unlikely(search_pc)) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6652 | j = gen_opc_ptr - gen_opc_buf; |
| 6653 | if (lj < j) { |
| 6654 | lj++; |
| 6655 | while (lj < j) |
| 6656 | gen_opc_instr_start[lj++] = 0; |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 6657 | gen_opc_pc[lj] = ctx.nip; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6658 | gen_opc_instr_start[lj] = 1; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 6659 | gen_opc_icount[lj] = num_insns; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6660 | } |
| 6661 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 6662 | #if defined PPC_DEBUG_DISAS |
| 6663 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6664 | fprintf(logfile, "----------------\n"); |
j_mayer | 1b9eb03 | 2007-03-23 09:40:22 +0000 | [diff] [blame] | 6665 | fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n", |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 6666 | ctx.nip, supervisor, (int)msr_ir); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6667 | } |
| 6668 | #endif |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 6669 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
| 6670 | gen_io_start(); |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 6671 | if (unlikely(little_endian)) { |
| 6672 | ctx.opcode = bswap32(ldl_code(ctx.nip)); |
| 6673 | } else { |
| 6674 | ctx.opcode = ldl_code(ctx.nip); |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 6675 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 6676 | #if defined PPC_DEBUG_DISAS |
| 6677 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 6678 | fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n", |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6679 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 6680 | opc3(ctx.opcode), little_endian ? "little" : "big"); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6681 | } |
| 6682 | #endif |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 6683 | ctx.nip += 4; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6684 | table = env->opcodes; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 6685 | num_insns++; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6686 | handler = table[opc1(ctx.opcode)]; |
| 6687 | if (is_indirect_opcode(handler)) { |
| 6688 | table = ind_table(handler); |
| 6689 | handler = table[opc2(ctx.opcode)]; |
| 6690 | if (is_indirect_opcode(handler)) { |
| 6691 | table = ind_table(handler); |
| 6692 | handler = table[opc3(ctx.opcode)]; |
| 6693 | } |
| 6694 | } |
| 6695 | /* Is opcode *REALLY* valid ? */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6696 | if (unlikely(handler->handler == &gen_invalid)) { |
j_mayer | 4a05771 | 2007-04-19 08:42:21 +0000 | [diff] [blame] | 6697 | if (loglevel != 0) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6698 | fprintf(logfile, "invalid/unsupported opcode: " |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 6699 | "%02x - %02x - %02x (%08x) " ADDRX " %d\n", |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6700 | opc1(ctx.opcode), opc2(ctx.opcode), |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 6701 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 6702 | } else { |
| 6703 | printf("invalid/unsupported opcode: " |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 6704 | "%02x - %02x - %02x (%08x) " ADDRX " %d\n", |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 6705 | opc1(ctx.opcode), opc2(ctx.opcode), |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 6706 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 6707 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6708 | } else { |
| 6709 | if (unlikely((ctx.opcode & handler->inval) != 0)) { |
j_mayer | 4a05771 | 2007-04-19 08:42:21 +0000 | [diff] [blame] | 6710 | if (loglevel != 0) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6711 | fprintf(logfile, "invalid bits: %08x for opcode: " |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 6712 | "%02x - %02x - %02x (%08x) " ADDRX "\n", |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6713 | ctx.opcode & handler->inval, opc1(ctx.opcode), |
| 6714 | opc2(ctx.opcode), opc3(ctx.opcode), |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 6715 | ctx.opcode, ctx.nip - 4); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6716 | } else { |
| 6717 | printf("invalid bits: %08x for opcode: " |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 6718 | "%02x - %02x - %02x (%08x) " ADDRX "\n", |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6719 | ctx.opcode & handler->inval, opc1(ctx.opcode), |
| 6720 | opc2(ctx.opcode), opc3(ctx.opcode), |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 6721 | ctx.opcode, ctx.nip - 4); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6722 | } |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 6723 | GEN_EXCP_INVAL(ctxp); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 6724 | break; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6725 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6726 | } |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 6727 | (*(handler->handler))(&ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6728 | #if defined(DO_PPC_STATISTICS) |
| 6729 | handler->count++; |
| 6730 | #endif |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6731 | /* Check trace mode exceptions */ |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 6732 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
| 6733 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && |
| 6734 | ctx.exception != POWERPC_SYSCALL && |
| 6735 | ctx.exception != POWERPC_EXCP_TRAP && |
| 6736 | ctx.exception != POWERPC_EXCP_BRANCH)) { |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 6737 | GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0); |
| 6738 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 6739 | (env->singlestep_enabled) || |
| 6740 | num_insns >= max_insns)) { |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 6741 | /* if we reach a page boundary or are single stepping, stop |
| 6742 | * generation |
| 6743 | */ |
bellard | 8dd4983 | 2005-06-04 22:22:27 +0000 | [diff] [blame] | 6744 | break; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6745 | } |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 6746 | #if defined (DO_SINGLE_STEP) |
| 6747 | break; |
| 6748 | #endif |
| 6749 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 6750 | if (tb->cflags & CF_LAST_IO) |
| 6751 | gen_io_end(); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 6752 | if (ctx.exception == POWERPC_EXCP_NONE) { |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 6753 | gen_goto_tb(&ctx, 0, ctx.nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 6754 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 6755 | if (unlikely(env->singlestep_enabled)) { |
| 6756 | gen_update_nip(&ctx, ctx.nip); |
| 6757 | gen_op_debug(); |
| 6758 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6759 | /* Generate the return instruction */ |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 6760 | tcg_gen_exit_tb(0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6761 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 6762 | gen_icount_end(tb, num_insns); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6763 | *gen_opc_ptr = INDEX_op_end; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6764 | if (unlikely(search_pc)) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6765 | j = gen_opc_ptr - gen_opc_buf; |
| 6766 | lj++; |
| 6767 | while (lj <= j) |
| 6768 | gen_opc_instr_start[lj++] = 0; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6769 | } else { |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 6770 | tb->size = ctx.nip - pc_start; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 6771 | tb->icount = num_insns; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6772 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 6773 | #if defined(DEBUG_DISAS) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 6774 | if (loglevel & CPU_LOG_TB_CPU) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 6775 | fprintf(logfile, "---------------- excp: %04x\n", ctx.exception); |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 6776 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 6777 | } |
| 6778 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6779 | int flags; |
j_mayer | 237c0af | 2007-09-29 12:01:46 +0000 | [diff] [blame] | 6780 | flags = env->bfd_mach; |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 6781 | flags |= little_endian << 16; |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 6782 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6783 | target_disas(logfile, pc_start, ctx.nip - pc_start, flags); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6784 | fprintf(logfile, "\n"); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 6785 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6786 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6787 | } |
| 6788 | |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 6789 | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6790 | { |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 6791 | gen_intermediate_code_internal(env, tb, 0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6792 | } |
| 6793 | |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 6794 | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6795 | { |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 6796 | gen_intermediate_code_internal(env, tb, 1); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6797 | } |
aurel32 | d2856f1 | 2008-04-28 00:32:32 +0000 | [diff] [blame] | 6798 | |
| 6799 | void gen_pc_load(CPUState *env, TranslationBlock *tb, |
| 6800 | unsigned long searched_pc, int pc_pos, void *puc) |
| 6801 | { |
| 6802 | int type, c; |
| 6803 | /* for PPC, we need to look at the micro operation to get the |
| 6804 | * access type */ |
| 6805 | env->nip = gen_opc_pc[pc_pos]; |
| 6806 | c = gen_opc_buf[pc_pos]; |
| 6807 | switch(c) { |
| 6808 | #if defined(CONFIG_USER_ONLY) |
| 6809 | #define CASE3(op)\ |
| 6810 | case INDEX_op_ ## op ## _raw |
| 6811 | #else |
| 6812 | #define CASE3(op)\ |
| 6813 | case INDEX_op_ ## op ## _user:\ |
| 6814 | case INDEX_op_ ## op ## _kernel:\ |
| 6815 | case INDEX_op_ ## op ## _hypv |
| 6816 | #endif |
| 6817 | |
| 6818 | CASE3(stfd): |
| 6819 | CASE3(stfs): |
| 6820 | CASE3(lfd): |
| 6821 | CASE3(lfs): |
| 6822 | type = ACCESS_FLOAT; |
| 6823 | break; |
| 6824 | CASE3(lwarx): |
| 6825 | type = ACCESS_RES; |
| 6826 | break; |
| 6827 | CASE3(stwcx): |
| 6828 | type = ACCESS_RES; |
| 6829 | break; |
| 6830 | CASE3(eciwx): |
| 6831 | CASE3(ecowx): |
| 6832 | type = ACCESS_EXT; |
| 6833 | break; |
| 6834 | default: |
| 6835 | type = ACCESS_INT; |
| 6836 | break; |
| 6837 | } |
| 6838 | env->access_type = type; |
| 6839 | } |