Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 1 | # successful events |
| 2 | pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u" |
| 3 | pci_nvme_irq_pin(void) "pulsing IRQ pin" |
| 4 | pci_nvme_irq_masked(void) "IRQ is masked" |
| 5 | pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=0x%"PRIx64" prp2=0x%"PRIx64"" |
Jinhao Fan | 387350d | 2022-06-16 20:34:08 +0800 | [diff] [blame] | 6 | pci_nvme_dbbuf_config(uint64_t dbs_addr, uint64_t eis_addr) "dbs_addr=0x%"PRIx64" eis_addr=0x%"PRIx64"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 7 | pci_nvme_map_addr(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64"" |
| 8 | pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64"" |
| 9 | pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2, int num_prps) "trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" prp2 0x%"PRIx64" num_prps %d" |
| 10 | pci_nvme_map_sgl(uint8_t typ, uint64_t len) "type 0x%"PRIx8" len %"PRIu64"" |
Klaus Jensen | 38f4ac6 | 2021-06-17 21:06:47 +0200 | [diff] [blame] | 11 | pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" nsid 0x%"PRIx32" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 12 | pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'" |
Klaus Jensen | 38f4ac6 | 2021-06-17 21:06:47 +0200 | [diff] [blame] | 13 | pci_nvme_flush_ns(uint32_t nsid) "nsid 0x%"PRIx32"" |
Klaus Jensen | 3bcf26d | 2021-06-17 21:06:56 +0200 | [diff] [blame] | 14 | pci_nvme_format_set(uint32_t nsid, uint8_t lbaf, uint8_t mset, uint8_t pi, uint8_t pil) "nsid %"PRIu32" lbaf %"PRIu8" mset %"PRIu8" pi %"PRIu8" pil %"PRIu8"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 15 | pci_nvme_read(uint16_t cid, uint32_t nsid, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64"" |
| 16 | pci_nvme_write(uint16_t cid, const char *verb, uint32_t nsid, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" opname '%s' nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64"" |
| 17 | pci_nvme_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'" |
Klaus Jensen | 38f4ac6 | 2021-06-17 21:06:47 +0200 | [diff] [blame] | 18 | pci_nvme_misc_cb(uint16_t cid) "cid %"PRIu16"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 19 | pci_nvme_dif_rw(uint8_t pract, uint8_t prinfo) "pract 0x%"PRIx8" prinfo 0x%"PRIx8"" |
| 20 | pci_nvme_dif_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'" |
| 21 | pci_nvme_dif_rw_mdata_in_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'" |
| 22 | pci_nvme_dif_rw_mdata_out_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'" |
| 23 | pci_nvme_dif_rw_check_cb(uint16_t cid, uint8_t prinfo, uint16_t apptag, uint16_t appmask, uint32_t reftag) "cid %"PRIu16" prinfo 0x%"PRIx8" apptag 0x%"PRIx16" appmask 0x%"PRIx16" reftag 0x%"PRIx32"" |
Naveen Nagar | 44219b6 | 2021-11-16 18:56:52 +0530 | [diff] [blame] | 24 | pci_nvme_dif_pract_generate_dif_crc16(size_t len, size_t lba_size, size_t chksum_len, uint16_t apptag, uint32_t reftag) "len %zu lba_size %zu chksum_len %zu apptag 0x%"PRIx16" reftag 0x%"PRIx32"" |
| 25 | pci_nvme_dif_pract_generate_dif_crc64(size_t len, size_t lba_size, size_t chksum_len, uint16_t apptag, uint64_t reftag) "len %zu lba_size %zu chksum_len %zu apptag 0x%"PRIx16" reftag 0x%"PRIx64"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 26 | pci_nvme_dif_check(uint8_t prinfo, uint16_t chksum_len) "prinfo 0x%"PRIx8" chksum_len %"PRIu16"" |
Naveen Nagar | 44219b6 | 2021-11-16 18:56:52 +0530 | [diff] [blame] | 27 | pci_nvme_dif_prchk_disabled_crc16(uint16_t apptag, uint32_t reftag) "apptag 0x%"PRIx16" reftag 0x%"PRIx32"" |
| 28 | pci_nvme_dif_prchk_disabled_crc64(uint16_t apptag, uint64_t reftag) "apptag 0x%"PRIx16" reftag 0x%"PRIx64"" |
| 29 | pci_nvme_dif_prchk_guard_crc16(uint16_t guard, uint16_t crc) "guard 0x%"PRIx16" crc 0x%"PRIx16"" |
| 30 | pci_nvme_dif_prchk_guard_crc64(uint64_t guard, uint64_t crc) "guard 0x%"PRIx64" crc 0x%"PRIx64"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 31 | pci_nvme_dif_prchk_apptag(uint16_t apptag, uint16_t elbat, uint16_t elbatm) "apptag 0x%"PRIx16" elbat 0x%"PRIx16" elbatm 0x%"PRIx16"" |
Naveen Nagar | 44219b6 | 2021-11-16 18:56:52 +0530 | [diff] [blame] | 32 | pci_nvme_dif_prchk_reftag_crc16(uint32_t reftag, uint32_t elbrt) "reftag 0x%"PRIx32" elbrt 0x%"PRIx32"" |
| 33 | pci_nvme_dif_prchk_reftag_crc64(uint64_t reftag, uint64_t elbrt) "reftag 0x%"PRIx64" elbrt 0x%"PRIx64"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 34 | pci_nvme_copy(uint16_t cid, uint32_t nsid, uint16_t nr, uint8_t format) "cid %"PRIu16" nsid %"PRIu32" nr %"PRIu16" format 0x%"PRIx8"" |
| 35 | pci_nvme_copy_source_range(uint64_t slba, uint32_t nlb) "slba 0x%"PRIx64" nlb %"PRIu32"" |
Klaus Jensen | 796d206 | 2021-06-17 21:06:54 +0200 | [diff] [blame] | 36 | pci_nvme_copy_out(uint64_t slba, uint32_t nlb) "slba 0x%"PRIx64" nlb %"PRIu32"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 37 | pci_nvme_verify(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32"" |
| 38 | pci_nvme_verify_mdata_in_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'" |
| 39 | pci_nvme_verify_cb(uint16_t cid, uint8_t prinfo, uint16_t apptag, uint16_t appmask, uint32_t reftag) "cid %"PRIu16" prinfo 0x%"PRIx8" apptag 0x%"PRIx16" appmask 0x%"PRIx16" reftag 0x%"PRIx32"" |
| 40 | pci_nvme_rw_complete_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'" |
| 41 | pci_nvme_block_status(int64_t offset, int64_t bytes, int64_t pnum, int ret, bool zeroed) "offset %"PRId64" bytes %"PRId64" pnum %"PRId64" ret 0x%x zeroed %d" |
Klaus Jensen | d7d1474 | 2021-06-17 21:06:49 +0200 | [diff] [blame] | 42 | pci_nvme_dsm(uint32_t nr, uint32_t attr) "nr %"PRIu32" attr 0x%"PRIx32"" |
| 43 | pci_nvme_dsm_deallocate(uint64_t slba, uint32_t nlb) "slba %"PRIu64" nlb %"PRIu32"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 44 | pci_nvme_dsm_single_range_limit_exceeded(uint32_t nlb, uint32_t dmrsl) "nlb %"PRIu32" dmrsl %"PRIu32"" |
| 45 | pci_nvme_compare(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32"" |
| 46 | pci_nvme_compare_data_cb(uint16_t cid) "cid %"PRIu16"" |
| 47 | pci_nvme_compare_mdata_cb(uint16_t cid) "cid %"PRIu16"" |
| 48 | pci_nvme_aio_discard_cb(uint16_t cid) "cid %"PRIu16"" |
| 49 | pci_nvme_aio_copy_in_cb(uint16_t cid) "cid %"PRIu16"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 50 | pci_nvme_aio_flush_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'" |
| 51 | pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize, uint16_t qflags) "create submission queue, addr=0x%"PRIx64", sqid=%"PRIu16", cqid=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16"" |
| 52 | pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t size, uint16_t qflags, int ien) "create completion queue, addr=0x%"PRIx64", cqid=%"PRIu16", vector=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16", ien=%d" |
| 53 | pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=%"PRIu16"" |
| 54 | pci_nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=%"PRIu16"" |
| 55 | pci_nvme_identify(uint16_t cid, uint8_t cns, uint16_t ctrlid, uint8_t csi) "cid %"PRIu16" cns 0x%"PRIx8" ctrlid %"PRIu16" csi 0x%"PRIx8"" |
| 56 | pci_nvme_identify_ctrl(void) "identify controller" |
| 57 | pci_nvme_identify_ctrl_csi(uint8_t csi) "identify controller, csi=0x%"PRIx8"" |
| 58 | pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32"" |
Gollu Appalanaidu | 5f4eb94 | 2021-06-14 21:59:26 +0530 | [diff] [blame] | 59 | pci_nvme_identify_ctrl_list(uint8_t cns, uint16_t cntid) "cns 0x%"PRIx8" cntid %"PRIu16"" |
Lukasz Maniak | 5e6f963 | 2022-05-09 16:16:10 +0200 | [diff] [blame] | 60 | pci_nvme_identify_pri_ctrl_cap(uint16_t cntlid) "identify primary controller capabilities cntlid=%"PRIu16"" |
Lukasz Maniak | 99f48ae | 2022-05-09 16:16:11 +0200 | [diff] [blame] | 61 | pci_nvme_identify_sec_ctrl_list(uint16_t cntlid, uint8_t numcntl) "identify secondary controller list cntlid=%"PRIu16" numcntl=%"PRIu8"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 62 | pci_nvme_identify_ns_csi(uint32_t ns, uint8_t csi) "nsid=%"PRIu32", csi=0x%"PRIx8"" |
| 63 | pci_nvme_identify_nslist(uint32_t ns) "nsid %"PRIu32"" |
| 64 | pci_nvme_identify_nslist_csi(uint16_t ns, uint8_t csi) "nsid=%"PRIu16", csi=0x%"PRIx8"" |
| 65 | pci_nvme_identify_cmd_set(void) "identify i/o command set" |
| 66 | pci_nvme_identify_ns_descr_list(uint32_t ns) "nsid %"PRIu32"" |
| 67 | pci_nvme_get_log(uint16_t cid, uint8_t lid, uint8_t lsp, uint8_t rae, uint32_t len, uint64_t off) "cid %"PRIu16" lid 0x%"PRIx8" lsp 0x%"PRIx8" rae 0x%"PRIx8" len %"PRIu32" off %"PRIu64"" |
| 68 | pci_nvme_getfeat(uint16_t cid, uint32_t nsid, uint8_t fid, uint8_t sel, uint32_t cdw11) "cid %"PRIu16" nsid 0x%"PRIx32" fid 0x%"PRIx8" sel 0x%"PRIx8" cdw11 0x%"PRIx32"" |
| 69 | pci_nvme_setfeat(uint16_t cid, uint32_t nsid, uint8_t fid, uint8_t save, uint32_t cdw11) "cid %"PRIu16" nsid 0x%"PRIx32" fid 0x%"PRIx8" save 0x%"PRIx8" cdw11 0x%"PRIx32"" |
| 70 | pci_nvme_getfeat_vwcache(const char* result) "get feature volatile write cache, result=%s" |
| 71 | pci_nvme_getfeat_numq(int result) "get feature number of queues, result=%d" |
| 72 | pci_nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "requested cq_count=%d sq_count=%d, responding with cq_count=%d sq_count=%d" |
| 73 | pci_nvme_setfeat_timestamp(uint64_t ts) "set feature timestamp = 0x%"PRIx64"" |
| 74 | pci_nvme_getfeat_timestamp(uint64_t ts) "get feature timestamp = 0x%"PRIx64"" |
| 75 | pci_nvme_process_aers(int queued) "queued %d" |
| 76 | pci_nvme_aer(uint16_t cid) "cid %"PRIu16"" |
| 77 | pci_nvme_aer_aerl_exceeded(void) "aerl exceeded" |
| 78 | pci_nvme_aer_masked(uint8_t type, uint8_t mask) "type 0x%"PRIx8" mask 0x%"PRIx8"" |
| 79 | pci_nvme_aer_post_cqe(uint8_t typ, uint8_t info, uint8_t log_page) "type 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" |
| 80 | pci_nvme_ns_attachment(uint16_t cid, uint8_t sel) "cid %"PRIu16", sel=0x%"PRIx8"" |
| 81 | pci_nvme_ns_attachment_attach(uint16_t cntlid, uint32_t nsid) "cntlid=0x%"PRIx16", nsid=0x%"PRIx32"" |
| 82 | pci_nvme_enqueue_event(uint8_t typ, uint8_t info, uint8_t log_page) "type 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" |
| 83 | pci_nvme_enqueue_event_noqueue(int queued) "queued %d" |
| 84 | pci_nvme_enqueue_event_masked(uint8_t typ) "type 0x%"PRIx8"" |
| 85 | pci_nvme_no_outstanding_aers(void) "ignoring event; no outstanding AERs" |
Klaus Jensen | f1c9740 | 2021-06-17 21:06:53 +0200 | [diff] [blame] | 86 | pci_nvme_enqueue_req_completion(uint16_t cid, uint16_t cqid, uint32_t dw0, uint32_t dw1, uint16_t status) "cid %"PRIu16" cqid %"PRIu16" dw0 0x%"PRIx32" dw1 0x%"PRIx32" status 0x%"PRIx16"" |
Klaus Jensen | 47cd353 | 2022-12-08 12:49:04 +0100 | [diff] [blame] | 87 | pci_nvme_update_cq_eventidx(uint16_t cqid, uint16_t new_eventidx) "cqid %"PRIu16" new_eventidx %"PRIu16"" |
| 88 | pci_nvme_update_sq_eventidx(uint16_t sqid, uint16_t new_eventidx) "sqid %"PRIu16" new_eventidx %"PRIu16"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 89 | pci_nvme_mmio_read(uint64_t addr, unsigned size) "addr 0x%"PRIx64" size %d" |
| 90 | pci_nvme_mmio_write(uint64_t addr, uint64_t data, unsigned size) "addr 0x%"PRIx64" data 0x%"PRIx64" size %d" |
| 91 | pci_nvme_mmio_doorbell_cq(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16" new_head %"PRIu16"" |
| 92 | pci_nvme_mmio_doorbell_sq(uint16_t sqid, uint16_t new_tail) "sqid %"PRIu16" new_tail %"PRIu16"" |
| 93 | pci_nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask set, data=0x%"PRIx64", new_mask=0x%"PRIx64"" |
| 94 | pci_nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask clr, data=0x%"PRIx64", new_mask=0x%"PRIx64"" |
| 95 | pci_nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=0x%"PRIx64"" |
| 96 | pci_nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=0x%"PRIx64"" |
| 97 | pci_nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue address=0x%"PRIx64"" |
| 98 | pci_nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue address=0x%"PRIx64"" |
| 99 | pci_nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin submission queue high half=0x%"PRIx64", new_address=0x%"PRIx64"" |
| 100 | pci_nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin completion queue high half=0x%"PRIx64", new_address=0x%"PRIx64"" |
| 101 | pci_nvme_mmio_start_success(void) "setting controller enable bit succeeded" |
| 102 | pci_nvme_mmio_stopped(void) "cleared controller enable bit" |
| 103 | pci_nvme_mmio_shutdown_set(void) "shutdown bit set" |
| 104 | pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" |
Klaus Jensen | 47cd353 | 2022-12-08 12:49:04 +0100 | [diff] [blame] | 105 | pci_nvme_update_cq_head(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16" new_head %"PRIu16"" |
| 106 | pci_nvme_update_sq_tail(uint16_t sqid, uint16_t new_tail) "sqid %"PRIu16" new_tail %"PRIu16"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 107 | pci_nvme_open_zone(uint64_t slba, uint32_t zone_idx, int all) "open zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" |
| 108 | pci_nvme_close_zone(uint64_t slba, uint32_t zone_idx, int all) "close zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" |
| 109 | pci_nvme_finish_zone(uint64_t slba, uint32_t zone_idx, int all) "finish zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" |
| 110 | pci_nvme_reset_zone(uint64_t slba, uint32_t zone_idx, int all) "reset zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" |
Klaus Jensen | 63d96e4 | 2021-06-17 21:06:55 +0200 | [diff] [blame] | 111 | pci_nvme_zns_zone_reset(uint64_t zslba) "zslba 0x%"PRIx64"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 112 | pci_nvme_offline_zone(uint64_t slba, uint32_t zone_idx, int all) "offline zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" |
| 113 | pci_nvme_set_descriptor_extension(uint64_t slba, uint32_t zone_idx) "set zone descriptor extension, slba=%"PRIu64", idx=%"PRIu32"" |
| 114 | pci_nvme_zd_extension_set(uint32_t zone_idx) "set descriptor extension for zone_idx=%"PRIu32"" |
| 115 | pci_nvme_clear_ns_close(uint32_t state, uint64_t slba) "zone state=%"PRIu32", slba=%"PRIu64" transitioned to Closed state" |
| 116 | pci_nvme_clear_ns_reset(uint32_t state, uint64_t slba) "zone state=%"PRIu32", slba=%"PRIu64" transitioned to Empty state" |
Klaus Jensen | e321b4c | 2021-03-04 08:40:11 +0100 | [diff] [blame] | 117 | pci_nvme_zoned_zrwa_implicit_flush(uint64_t zslba, uint32_t nlb) "zslba 0x%"PRIx64" nlb %"PRIu32"" |
Łukasz Gieryk | 1e9c685 | 2022-05-09 16:16:12 +0200 | [diff] [blame] | 118 | pci_nvme_pci_reset(void) "PCI Function Level Reset" |
Łukasz Gieryk | 11871f5 | 2022-05-09 16:16:17 +0200 | [diff] [blame] | 119 | pci_nvme_virt_mngmt(uint16_t cid, uint16_t act, uint16_t cntlid, const char* rt, uint16_t nr) "cid %"PRIu16", act=0x%"PRIx16", ctrlid=%"PRIu16" %s nr=%"PRIu16"" |
Jesper Devantier | 73064ed | 2023-02-20 12:59:26 +0100 | [diff] [blame] | 120 | pci_nvme_fdp_ruh_change(uint16_t rgid, uint16_t ruhid) "change RU on RUH rgid=%"PRIu16", ruhid=%"PRIu16"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 121 | |
| 122 | # error conditions |
| 123 | pci_nvme_err_mdts(size_t len) "len %zu" |
| 124 | pci_nvme_err_zasl(size_t len) "len %zu" |
| 125 | pci_nvme_err_req_status(uint16_t cid, uint32_t nsid, uint16_t status, uint8_t opc) "cid %"PRIu16" nsid %"PRIu32" status 0x%"PRIx16" opc 0x%"PRIx8"" |
| 126 | pci_nvme_err_addr_read(uint64_t addr) "addr 0x%"PRIx64"" |
| 127 | pci_nvme_err_addr_write(uint64_t addr) "addr 0x%"PRIx64"" |
| 128 | pci_nvme_err_cfs(void) "controller fatal status" |
| 129 | pci_nvme_err_aio(uint16_t cid, const char *errname, uint16_t status) "cid %"PRIu16" err '%s' status 0x%"PRIx16"" |
| 130 | pci_nvme_err_copy_invalid_format(uint8_t format) "format 0x%"PRIx8"" |
| 131 | pci_nvme_err_invalid_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" type 0x%"PRIx8"" |
| 132 | pci_nvme_err_invalid_num_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" type 0x%"PRIx8"" |
| 133 | pci_nvme_err_invalid_sgl_excess_length(uint32_t residual) "residual %"PRIu32"" |
| 134 | pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size" |
| 135 | pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is not page aligned: 0x%"PRIx64"" |
| 136 | pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"PRIx64"" |
| 137 | pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" |
| 138 | pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8"" |
| 139 | pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit) "Invalid LBA start=%"PRIu64" len=%"PRIu64" limit=%"PRIu64"" |
| 140 | pci_nvme_err_invalid_log_page_offset(uint64_t ofs, uint64_t size) "must be <= %"PRIu64", got %"PRIu64"" |
| 141 | pci_nvme_err_cmb_invalid_cba(uint64_t cmbmsc) "cmbmsc 0x%"PRIx64"" |
| 142 | pci_nvme_err_cmb_not_enabled(uint64_t cmbmsc) "cmbmsc 0x%"PRIx64"" |
| 143 | pci_nvme_err_unaligned_zone_cmd(uint8_t action, uint64_t slba, uint64_t zslba) "unaligned zone op 0x%"PRIx32", got slba=%"PRIu64", zslba=%"PRIu64"" |
| 144 | pci_nvme_err_invalid_zone_state_transition(uint8_t action, uint64_t slba, uint8_t attrs) "action=0x%"PRIx8", slba=%"PRIu64", attrs=0x%"PRIx32"" |
| 145 | pci_nvme_err_write_not_at_wp(uint64_t slba, uint64_t zone, uint64_t wp) "writing at slba=%"PRIu64", zone=%"PRIu64", but wp=%"PRIu64"" |
| 146 | pci_nvme_err_append_not_at_start(uint64_t slba, uint64_t zone) "appending at slba=%"PRIu64", but zone=%"PRIu64"" |
| 147 | pci_nvme_err_zone_is_full(uint64_t zslba) "zslba 0x%"PRIx64"" |
| 148 | pci_nvme_err_zone_is_read_only(uint64_t zslba) "zslba 0x%"PRIx64"" |
| 149 | pci_nvme_err_zone_is_offline(uint64_t zslba) "zslba 0x%"PRIx64"" |
| 150 | pci_nvme_err_zone_boundary(uint64_t slba, uint32_t nlb, uint64_t zcap) "lba 0x%"PRIx64" nlb %"PRIu32" zcap 0x%"PRIx64"" |
| 151 | pci_nvme_err_zone_invalid_write(uint64_t slba, uint64_t wp) "lba 0x%"PRIx64" wp 0x%"PRIx64"" |
| 152 | pci_nvme_err_zone_write_not_ok(uint64_t slba, uint32_t nlb, uint16_t status) "slba=%"PRIu64", nlb=%"PRIu32", status=0x%"PRIx16"" |
| 153 | pci_nvme_err_zone_read_not_ok(uint64_t slba, uint32_t nlb, uint16_t status) "slba=%"PRIu64", nlb=%"PRIu32", status=0x%"PRIx16"" |
| 154 | pci_nvme_err_insuff_active_res(uint32_t max_active) "max_active=%"PRIu32" zone limit exceeded" |
| 155 | pci_nvme_err_insuff_open_res(uint32_t max_open) "max_open=%"PRIu32" zone limit exceeded" |
| 156 | pci_nvme_err_zd_extension_map_error(uint32_t zone_idx) "can't map descriptor extension for zone_idx=%"PRIu32"" |
| 157 | pci_nvme_err_invalid_iocsci(uint32_t idx) "unsupported command set combination index %"PRIu32"" |
| 158 | pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deletion, sid=%"PRIu16"" |
| 159 | pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submission queue, invalid cqid=%"PRIu16"" |
| 160 | pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submission queue, invalid sqid=%"PRIu16"" |
| 161 | pci_nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submission queue, invalid qsize=%"PRIu16"" |
| 162 | pci_nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submission queue, addr=0x%"PRIx64"" |
| 163 | pci_nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating submission queue, qflags=%"PRIu16"" |
| 164 | pci_nvme_err_invalid_del_cq_cqid(uint16_t cqid) "failed deleting completion queue, cqid=%"PRIu16"" |
| 165 | pci_nvme_err_invalid_del_cq_notempty(uint16_t cqid) "failed deleting completion queue, it is not empty, cqid=%"PRIu16"" |
| 166 | pci_nvme_err_invalid_create_cq_cqid(uint16_t cqid) "failed creating completion queue, cqid=%"PRIu16"" |
| 167 | pci_nvme_err_invalid_create_cq_size(uint16_t size) "failed creating completion queue, size=%"PRIu16"" |
| 168 | pci_nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating completion queue, addr=0x%"PRIx64"" |
| 169 | pci_nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating completion queue, vector=%"PRIu16"" |
| 170 | pci_nvme_err_invalid_create_cq_qflags(uint16_t qflags) "failed creating completion queue, qflags=%"PRIu16"" |
Klaus Jensen | 6a33f2e | 2023-07-19 20:21:58 +0200 | [diff] [blame] | 171 | pci_nvme_err_invalid_create_cq_entry_size(uint8_t iosqes, uint8_t iocqes) "iosqes %"PRIu8" iocqes %"PRIu8"" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 172 | pci_nvme_err_invalid_identify_cns(uint16_t cns) "identify, invalid cns=0x%"PRIx16"" |
| 173 | pci_nvme_err_invalid_getfeat(int dw10) "invalid get features, dw10=0x%"PRIx32"" |
| 174 | pci_nvme_err_invalid_setfeat(uint32_t dw10) "invalid set features, dw10=0x%"PRIx32"" |
| 175 | pci_nvme_err_invalid_log_page(uint16_t cid, uint16_t lid) "cid %"PRIu16" lid 0x%"PRIx16"" |
| 176 | pci_nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are non-admin completion queues" |
| 177 | pci_nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are non-admin submission queues" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 178 | pci_nvme_err_startfail_asq_misaligned(uint64_t addr) "nvme_start_ctrl failed because the admin submission queue address is misaligned: 0x%"PRIx64"" |
| 179 | pci_nvme_err_startfail_acq_misaligned(uint64_t addr) "nvme_start_ctrl failed because the admin completion queue address is misaligned: 0x%"PRIx64"" |
| 180 | pci_nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the page size is too small: log2size=%u, min=%u" |
| 181 | pci_nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the page size is too large: log2size=%u, max=%u" |
| 182 | pci_nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the completion queue entry size is too small: log2size=%u, min=%u" |
| 183 | pci_nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the completion queue entry size is too large: log2size=%u, max=%u" |
| 184 | pci_nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the submission queue entry size is too small: log2size=%u, min=%u" |
| 185 | pci_nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the submission queue entry size is too large: log2size=%u, max=%u" |
| 186 | pci_nvme_err_startfail_css(uint8_t css) "nvme_start_ctrl failed because invalid command set selected:%u" |
| 187 | pci_nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed because the admin submission queue size is zero" |
| 188 | pci_nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed because the admin completion queue size is zero" |
| 189 | pci_nvme_err_startfail_zasl_too_small(uint32_t zasl, uint32_t pagesz) "nvme_start_ctrl failed because zone append size limit %"PRIu32" is too small, needs to be >= %"PRIu32"" |
| 190 | pci_nvme_err_startfail(void) "setting controller enable bit failed" |
Paolo Bonzini | 3488fc3 | 2023-03-30 14:14:31 +0200 | [diff] [blame] | 191 | pci_nvme_err_startfail_virt_state(uint16_t vq, uint16_t vi) "nvme_start_ctrl failed due to ctrl state: vi=%u vq=%u" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 192 | pci_nvme_err_invalid_mgmt_action(uint8_t action) "action=0x%"PRIx8"" |
Łukasz Gieryk | 11871f5 | 2022-05-09 16:16:17 +0200 | [diff] [blame] | 193 | pci_nvme_err_ignored_mmio_vf_offline(uint64_t addr, unsigned size) "addr 0x%"PRIx64" size %d" |
Klaus Jensen | 88eea45 | 2021-04-14 22:14:30 +0200 | [diff] [blame] | 194 | |
| 195 | # undefined behavior |
| 196 | pci_nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit aligned, offset=0x%"PRIx64"" |
| 197 | pci_nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size) "MMIO write smaller than 32 bits, offset=0x%"PRIx64", size=%u" |
| 198 | pci_nvme_ub_mmiowr_intmask_with_msix(void) "undefined access to interrupt mask set when MSI-X is enabled" |
| 199 | pci_nvme_ub_mmiowr_ro_csts(void) "attempted to set a read only bit of controller status" |
| 200 | pci_nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NSSRO but CAP.NSSRS is zero (not supported)" |
| 201 | pci_nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem reset but CAP.NSSRS is zero (not supported)" |
| 202 | pci_nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC when CMBSZ is zero, ignored" |
| 203 | pci_nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ, ignored" |
| 204 | pci_nvme_ub_mmiowr_pmrcap_readonly(void) "invalid write to read only PMRCAP, ignored" |
| 205 | pci_nvme_ub_mmiowr_pmrsts_readonly(void) "invalid write to read only PMRSTS, ignored" |
| 206 | pci_nvme_ub_mmiowr_pmrebs_readonly(void) "invalid write to read only PMREBS, ignored" |
| 207 | pci_nvme_ub_mmiowr_pmrswtp_readonly(void) "invalid write to read only PMRSWTP, ignored" |
| 208 | pci_nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO write, offset=0x%"PRIx64", data=0x%"PRIx64"" |
| 209 | pci_nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit aligned, offset=0x%"PRIx64"" |
| 210 | pci_nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bits, offset=0x%"PRIx64"" |
| 211 | pci_nvme_ub_mmiord_invalid_ofs(uint64_t offset) "MMIO read beyond last register, offset=0x%"PRIx64", returning 0" |
| 212 | pci_nvme_ub_db_wr_misaligned(uint64_t offset) "doorbell write not 32-bit aligned, offset=0x%"PRIx64", ignoring" |
| 213 | pci_nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell write for nonexistent queue, cqid=%"PRIu32", ignoring" |
| 214 | pci_nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "completion queue doorbell write value beyond queue size, cqid=%"PRIu32", new_head=%"PRIu16", ignoring" |
| 215 | pci_nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell write for nonexistent queue, sqid=%"PRIu32", ignoring" |
| 216 | pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submission queue doorbell write value beyond queue size, sqid=%"PRIu32", new_head=%"PRIu16", ignoring" |
| 217 | pci_nvme_ub_unknown_css_value(void) "unknown value in cc.css field" |
Padmakar Kalghatgi | 2342147 | 2021-07-09 07:58:40 +0200 | [diff] [blame] | 218 | pci_nvme_ub_too_many_mappings(void) "too many prp/sgl mappings" |