Steffen Görtz | c5a4829 | 2019-01-07 15:23:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * nRF51 System-on-Chip Timer peripheral |
| 3 | * |
| 4 | * QEMU interface: |
| 5 | * + sysbus MMIO regions 0: GPIO registers |
| 6 | * + sysbus irq |
| 7 | * |
| 8 | * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> |
| 9 | * |
| 10 | * This code is licensed under the GPL version 2 or later. See |
| 11 | * the COPYING file in the top-level directory. |
| 12 | */ |
| 13 | #ifndef NRF51_TIMER_H |
| 14 | #define NRF51_TIMER_H |
| 15 | |
| 16 | #include "hw/sysbus.h" |
| 17 | #include "qemu/timer.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 18 | #include "qom/object.h" |
Steffen Görtz | c5a4829 | 2019-01-07 15:23:47 +0000 | [diff] [blame] | 19 | #define TYPE_NRF51_TIMER "nrf51_soc.timer" |
Eduardo Habkost | 8063396 | 2020-09-16 14:25:19 -0400 | [diff] [blame] | 20 | OBJECT_DECLARE_SIMPLE_TYPE(NRF51TimerState, NRF51_TIMER) |
Steffen Görtz | c5a4829 | 2019-01-07 15:23:47 +0000 | [diff] [blame] | 21 | |
| 22 | #define NRF51_TIMER_REG_COUNT 4 |
| 23 | |
| 24 | #define NRF51_TIMER_TASK_START 0x000 |
| 25 | #define NRF51_TIMER_TASK_STOP 0x004 |
| 26 | #define NRF51_TIMER_TASK_COUNT 0x008 |
| 27 | #define NRF51_TIMER_TASK_CLEAR 0x00C |
| 28 | #define NRF51_TIMER_TASK_SHUTDOWN 0x010 |
| 29 | #define NRF51_TIMER_TASK_CAPTURE_0 0x040 |
| 30 | #define NRF51_TIMER_TASK_CAPTURE_3 0x04C |
| 31 | |
| 32 | #define NRF51_TIMER_EVENT_COMPARE_0 0x140 |
| 33 | #define NRF51_TIMER_EVENT_COMPARE_1 0x144 |
| 34 | #define NRF51_TIMER_EVENT_COMPARE_2 0x148 |
| 35 | #define NRF51_TIMER_EVENT_COMPARE_3 0x14C |
| 36 | |
| 37 | #define NRF51_TIMER_REG_SHORTS 0x200 |
| 38 | #define NRF51_TIMER_REG_SHORTS_MASK 0xf0f |
| 39 | #define NRF51_TIMER_REG_INTENSET 0x304 |
| 40 | #define NRF51_TIMER_REG_INTENCLR 0x308 |
| 41 | #define NRF51_TIMER_REG_INTEN_MASK 0xf0000 |
| 42 | #define NRF51_TIMER_REG_MODE 0x504 |
| 43 | #define NRF51_TIMER_REG_MODE_MASK 0x01 |
| 44 | #define NRF51_TIMER_TIMER 0 |
| 45 | #define NRF51_TIMER_COUNTER 1 |
| 46 | #define NRF51_TIMER_REG_BITMODE 0x508 |
| 47 | #define NRF51_TIMER_REG_BITMODE_MASK 0x03 |
| 48 | #define NRF51_TIMER_WIDTH_16 0 |
| 49 | #define NRF51_TIMER_WIDTH_8 1 |
| 50 | #define NRF51_TIMER_WIDTH_24 2 |
| 51 | #define NRF51_TIMER_WIDTH_32 3 |
| 52 | #define NRF51_TIMER_REG_PRESCALER 0x510 |
| 53 | #define NRF51_TIMER_REG_PRESCALER_MASK 0x0F |
| 54 | #define NRF51_TIMER_REG_CC0 0x540 |
| 55 | #define NRF51_TIMER_REG_CC3 0x54C |
| 56 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 57 | struct NRF51TimerState { |
Steffen Görtz | c5a4829 | 2019-01-07 15:23:47 +0000 | [diff] [blame] | 58 | SysBusDevice parent_obj; |
| 59 | |
| 60 | MemoryRegion iomem; |
| 61 | qemu_irq irq; |
| 62 | |
Philippe Mathieu-Daudé | 27d6dea | 2020-05-04 09:28:21 +0200 | [diff] [blame] | 63 | uint8_t id; |
Steffen Görtz | c5a4829 | 2019-01-07 15:23:47 +0000 | [diff] [blame] | 64 | QEMUTimer timer; |
| 65 | int64_t timer_start_ns; |
| 66 | int64_t update_counter_ns; |
| 67 | uint32_t counter; |
| 68 | |
| 69 | bool running; |
| 70 | |
| 71 | uint8_t events_compare[NRF51_TIMER_REG_COUNT]; |
| 72 | uint32_t cc[NRF51_TIMER_REG_COUNT]; |
| 73 | uint32_t shorts; |
| 74 | uint32_t inten; |
| 75 | uint32_t mode; |
| 76 | uint32_t bitmode; |
| 77 | uint32_t prescaler; |
| 78 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 79 | }; |
Steffen Görtz | c5a4829 | 2019-01-07 15:23:47 +0000 | [diff] [blame] | 80 | |
| 81 | |
| 82 | #endif |