Yoshinori Sato | e5918d7 | 2019-01-21 05:24:40 -0800 | [diff] [blame] | 1 | # |
| 2 | # Renesas RX instruction decode definitions. |
| 3 | # |
| 4 | # Copyright (c) 2019 Richard Henderson <richard.henderson@linaro.org> |
| 5 | # Copyright (c) 2019 Yoshinori Sato <ysato@users.sourceforge.jp> |
| 6 | # |
| 7 | # This library is free software; you can redistribute it and/or |
| 8 | # modify it under the terms of the GNU Lesser General Public |
| 9 | # License as published by the Free Software Foundation; either |
Chetan Pant | 81c7643 | 2020-10-23 12:38:40 +0000 | [diff] [blame] | 10 | # version 2.1 of the License, or (at your option) any later version. |
Yoshinori Sato | e5918d7 | 2019-01-21 05:24:40 -0800 | [diff] [blame] | 11 | # |
| 12 | # This library is distributed in the hope that it will be useful, |
| 13 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | # Lesser General Public License for more details. |
| 16 | # |
| 17 | # You should have received a copy of the GNU Lesser General Public |
| 18 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | # |
| 20 | |
| 21 | &bcnd cd dsp sz |
| 22 | &jdsp dsp sz |
| 23 | &jreg rs |
| 24 | &rr rd rs |
| 25 | &ri rd imm |
| 26 | &rrr rd rs rs2 |
| 27 | &rri rd imm rs2 |
| 28 | &rm rd rs ld mi |
| 29 | &mi rs ld mi imm |
| 30 | &mr rs ld mi rs2 |
| 31 | &mcnd ld sz rd cd |
| 32 | ######## |
| 33 | %b1_bdsp 24:3 !function=bdsp_s |
| 34 | |
| 35 | @b1_bcnd_s .... cd:1 ... &bcnd dsp=%b1_bdsp sz=1 |
| 36 | @b1_bra_s .... .... &jdsp dsp=%b1_bdsp sz=1 |
| 37 | |
| 38 | %b2_r_0 16:4 |
| 39 | %b2_li_2 18:2 !function=li |
| 40 | %b2_li_8 24:2 !function=li |
| 41 | %b2_dsp5_3 23:4 19:1 |
| 42 | |
| 43 | @b2_rds .... .... .... rd:4 &rr rs=%b2_r_0 |
| 44 | @b2_rds_li .... .... .... rd:4 &rri rs2=%b2_r_0 imm=%b2_li_8 |
| 45 | @b2_rds_uimm4 .... .... imm:4 rd:4 &rri rs2=%b2_r_0 |
| 46 | @b2_rs2_uimm4 .... .... imm:4 rs2:4 &rri rd=0 |
| 47 | @b2_rds_imm5 .... ... imm:5 rd:4 &rri rs2=%b2_r_0 |
| 48 | @b2_rd_rs_li .... .... rs2:4 rd:4 &rri imm=%b2_li_8 |
| 49 | @b2_rd_ld_ub .... .. ld:2 rs:4 rd:4 &rm mi=4 |
| 50 | @b2_ld_imm3 .... .. ld:2 rs:4 . imm:3 &mi mi=4 |
| 51 | @b2_bcnd_b .... cd:4 dsp:s8 &bcnd sz=2 |
| 52 | @b2_bra_b .... .... dsp:s8 &jdsp sz=2 |
| 53 | |
| 54 | ######## |
| 55 | |
| 56 | %b3_r_0 8:4 |
| 57 | %b3_li_10 18:2 !function=li |
| 58 | %b3_dsp5_8 23:1 16:4 |
| 59 | %b3_bdsp 8:s8 16:8 |
| 60 | |
| 61 | @b3_rd_rs .... .... .... .... rs:4 rd:4 &rr |
| 62 | @b3_rs_rd .... .... .... .... rd:4 rs:4 &rr |
| 63 | @b3_rd_li .... .... .... .... .... rd:4 \ |
| 64 | &rri rs2=%b3_r_0 imm=%b3_li_10 |
| 65 | @b3_rd_ld .... .... mi:2 .... ld:2 rs:4 rd:4 &rm |
| 66 | @b3_rd_ld_ub .... .... .... .. ld:2 rs:4 rd:4 &rm mi=4 |
| 67 | @b3_rd_ld_ul .... .... .... .. ld:2 rs:4 rd:4 &rm mi=2 |
| 68 | @b3_rd_rs_rs2 .... .... .... rd:4 rs:4 rs2:4 &rrr |
| 69 | @b3_rds_imm5 .... .... ....... imm:5 rd:4 &rri rs2=%b3_r_0 |
| 70 | @b3_rd_rs_imm5 .... .... ... imm:5 rs2:4 rd:4 &rri |
| 71 | @b3_bcnd_w .... ... cd:1 .... .... .... .... &bcnd dsp=%b3_bdsp sz=3 |
| 72 | @b3_bra_w .... .... .... .... .... .... &jdsp dsp=%b3_bdsp sz=3 |
| 73 | @b3_ld_rd_rs .... .... .... .. ld:2 rs:4 rd:4 &rm mi=0 |
| 74 | @b3_sz_ld_rd_cd .... .... .... sz:2 ld:2 rd:4 cd:4 &mcnd |
| 75 | |
| 76 | ######## |
| 77 | |
| 78 | %b4_li_18 18:2 !function=li |
| 79 | %b4_dsp_16 0:s8 8:8 |
| 80 | %b4_bdsp 0:s8 8:8 16:8 |
| 81 | |
| 82 | @b4_rd_ldmi .... .... mi:2 .... ld:2 .... .... rs:4 rd:4 &rm |
| 83 | @b4_bra_a .... .... .... .... .... .... .... .... \ |
| 84 | &jdsp dsp=%b4_bdsp sz=4 |
| 85 | ######## |
| 86 | # ABS rd |
| 87 | ABS_rr 0111 1110 0010 .... @b2_rds |
| 88 | # ABS rs, rd |
| 89 | ABS_rr 1111 1100 0000 1111 .... .... @b3_rd_rs |
| 90 | |
| 91 | # ADC #imm, rd |
| 92 | ADC_ir 1111 1101 0111 ..00 0010 .... @b3_rd_li |
| 93 | # ADC rs, rd |
| 94 | ADC_rr 1111 1100 0000 1011 .... .... @b3_rd_rs |
| 95 | # ADC dsp[rs].l, rd |
| 96 | # Note only mi==2 allowed. |
| 97 | ADC_mr 0000 0110 ..10 00.. 0000 0010 .... .... @b4_rd_ldmi |
| 98 | |
| 99 | # ADD #uimm4, rd |
| 100 | ADD_irr 0110 0010 .... .... @b2_rds_uimm4 |
| 101 | # ADD #imm, rs, rd |
| 102 | ADD_irr 0111 00.. .... .... @b2_rd_rs_li |
| 103 | # ADD dsp[rs].ub, rd |
| 104 | # ADD rs, rd |
| 105 | ADD_mr 0100 10.. .... .... @b2_rd_ld_ub |
| 106 | # ADD dsp[rs], rd |
| 107 | ADD_mr 0000 0110 ..00 10.. .... .... @b3_rd_ld |
| 108 | # ADD rs, rs2, rd |
| 109 | ADD_rrr 1111 1111 0010 .... .... .... @b3_rd_rs_rs2 |
| 110 | |
| 111 | # AND #uimm4, rd |
| 112 | AND_ir 0110 0100 .... .... @b2_rds_uimm4 |
| 113 | # AND #imm, rd |
| 114 | AND_ir 0111 01.. 0010 .... @b2_rds_li |
| 115 | # AND dsp[rs].ub, rd |
| 116 | # AND rs, rd |
| 117 | AND_mr 0101 00.. .... .... @b2_rd_ld_ub |
| 118 | # AND dsp[rs], rd |
| 119 | AND_mr 0000 0110 ..01 00.. .... .... @b3_rd_ld |
| 120 | # AND rs, rs2, rd |
| 121 | AND_rrr 1111 1111 0100 .... .... .... @b3_rd_rs_rs2 |
| 122 | |
| 123 | # BCLR #imm, dsp[rd] |
| 124 | BCLR_im 1111 00.. .... 1... @b2_ld_imm3 |
| 125 | # BCLR #imm, rs |
| 126 | BCLR_ir 0111 101. .... .... @b2_rds_imm5 |
| 127 | # BCLR rs, rd |
| 128 | # BCLR rs, dsp[rd] |
| 129 | { |
| 130 | BCLR_rr 1111 1100 0110 0111 .... .... @b3_rs_rd |
| 131 | BCLR_rm 1111 1100 0110 01.. .... .... @b3_rd_ld_ub |
| 132 | } |
| 133 | |
| 134 | # BCnd.s dsp |
| 135 | BCnd 0001 .... @b1_bcnd_s |
| 136 | # BRA.b dsp |
| 137 | # BCnd.b dsp |
| 138 | { |
| 139 | BRA 0010 1110 .... .... @b2_bra_b |
| 140 | BCnd 0010 .... .... .... @b2_bcnd_b |
| 141 | } |
| 142 | |
| 143 | # BCnd.w dsp |
| 144 | BCnd 0011 101 . .... .... .... .... @b3_bcnd_w |
| 145 | |
| 146 | # BNOT #imm, dsp[rd] |
| 147 | # BMCnd #imm, dsp[rd] |
| 148 | { |
| 149 | BNOT_im 1111 1100 111 imm:3 ld:2 rs:4 1111 |
| 150 | BMCnd_im 1111 1100 111 imm:3 ld:2 rd:4 cd:4 |
| 151 | } |
| 152 | |
| 153 | # BNOT #imm, rd |
| 154 | # BMCnd #imm, rd |
| 155 | { |
| 156 | BNOT_ir 1111 1101 111 imm:5 1111 rd:4 |
| 157 | BMCnd_ir 1111 1101 111 imm:5 cd:4 rd:4 |
| 158 | } |
| 159 | |
| 160 | # BNOT rs, rd |
| 161 | # BNOT rs, dsp[rd] |
| 162 | { |
| 163 | BNOT_rr 1111 1100 0110 1111 .... .... @b3_rs_rd |
| 164 | BNOT_rm 1111 1100 0110 11.. .... .... @b3_rd_ld_ub |
| 165 | } |
| 166 | |
| 167 | # BRA.s dsp |
| 168 | BRA 0000 1 ... @b1_bra_s |
| 169 | # BRA.w dsp |
| 170 | BRA 0011 1000 .... .... .... .... @b3_bra_w |
| 171 | # BRA.a dsp |
| 172 | BRA 0000 0100 .... .... .... .... .... .... @b4_bra_a |
| 173 | # BRA.l rs |
| 174 | BRA_l 0111 1111 0100 rd:4 |
| 175 | |
| 176 | BRK 0000 0000 |
| 177 | |
| 178 | # BSET #imm, dsp[rd] |
| 179 | BSET_im 1111 00.. .... 0... @b2_ld_imm3 |
| 180 | # BSET #imm, rd |
| 181 | BSET_ir 0111 100. .... .... @b2_rds_imm5 |
| 182 | # BSET rs, rd |
| 183 | # BSET rs, dsp[rd] |
| 184 | { |
| 185 | BSET_rr 1111 1100 0110 0011 .... .... @b3_rs_rd |
| 186 | BSET_rm 1111 1100 0110 00.. .... .... @b3_rd_ld_ub |
| 187 | } |
| 188 | |
| 189 | # BSR.w dsp |
| 190 | BSR 0011 1001 .... .... .... .... @b3_bra_w |
| 191 | # BSR.a dsp |
| 192 | BSR 0000 0101 .... .... .... .... .... .... @b4_bra_a |
| 193 | # BSR.l rs |
| 194 | BSR_l 0111 1111 0101 rd:4 |
| 195 | |
| 196 | # BSET #imm, dsp[rd] |
| 197 | BTST_im 1111 01.. .... 0... @b2_ld_imm3 |
| 198 | # BSET #imm, rd |
| 199 | BTST_ir 0111 110. .... .... @b2_rds_imm5 |
| 200 | # BSET rs, rd |
| 201 | # BSET rs, dsp[rd] |
| 202 | { |
| 203 | BTST_rr 1111 1100 0110 1011 .... .... @b3_rs_rd |
| 204 | BTST_rm 1111 1100 0110 10.. .... .... @b3_rd_ld_ub |
| 205 | } |
| 206 | |
| 207 | # CLRSPW psw |
| 208 | CLRPSW 0111 1111 1011 cb:4 |
| 209 | |
| 210 | # CMP #uimm4, rs2 |
| 211 | CMP_ir 0110 0001 .... .... @b2_rs2_uimm4 |
| 212 | # CMP #uimm8, rs2 |
| 213 | CMP_ir 0111 0101 0101 rs2:4 imm:8 &rri rd=0 |
| 214 | # CMP #imm, rs2 |
| 215 | CMP_ir 0111 01.. 0000 rs2:4 &rri imm=%b2_li_8 rd=0 |
| 216 | # CMP dsp[rs].ub, rs2 |
| 217 | # CMP rs, rs2 |
| 218 | CMP_mr 0100 01.. .... .... @b2_rd_ld_ub |
| 219 | # CMP dsp[rs], rs2 |
| 220 | CMP_mr 0000 0110 ..00 01.. .... .... @b3_rd_ld |
| 221 | |
| 222 | # DIV #imm, rd |
| 223 | DIV_ir 1111 1101 0111 ..00 1000 .... @b3_rd_li |
| 224 | # DIV dsp[rs].ub, rd |
| 225 | # DIV rs, rd |
| 226 | DIV_mr 1111 1100 0010 00.. .... .... @b3_rd_ld_ub |
| 227 | # DIV dsp[rs], rd |
| 228 | DIV_mr 0000 0110 ..10 00.. 0000 1000 .... .... @b4_rd_ldmi |
| 229 | |
| 230 | # DIVU #imm, rd |
| 231 | DIVU_ir 1111 1101 0111 ..00 1001 .... @b3_rd_li |
| 232 | # DIVU dsp[rs].ub, rd |
| 233 | # DIVU rs, rd |
| 234 | DIVU_mr 1111 1100 0010 01.. .... .... @b3_rd_ld_ub |
| 235 | # DIVU dsp[rs], rd |
| 236 | DIVU_mr 0000 0110 ..10 00.. 0000 1001 .... .... @b4_rd_ldmi |
| 237 | |
| 238 | # EMUL #imm, rd |
| 239 | EMUL_ir 1111 1101 0111 ..00 0110 .... @b3_rd_li |
| 240 | # EMUL dsp[rs].ub, rd |
| 241 | # EMUL rs, rd |
| 242 | EMUL_mr 1111 1100 0001 10.. .... .... @b3_rd_ld_ub |
| 243 | # EMUL dsp[rs], rd |
| 244 | EMUL_mr 0000 0110 ..10 00.. 0000 0110 .... .... @b4_rd_ldmi |
| 245 | |
| 246 | # EMULU #imm, rd |
| 247 | EMULU_ir 1111 1101 0111 ..00 0111 .... @b3_rd_li |
| 248 | # EMULU dsp[rs].ub, rd |
| 249 | # EMULU rs, rd |
| 250 | EMULU_mr 1111 1100 0001 11.. .... .... @b3_rd_ld_ub |
| 251 | # EMULU dsp[rs], rd |
| 252 | EMULU_mr 0000 0110 ..10 00.. 0000 0111 .... .... @b4_rd_ldmi |
| 253 | |
| 254 | # FADD #imm, rd |
| 255 | FADD_ir 1111 1101 0111 0010 0010 rd:4 |
| 256 | # FADD rs, rd |
| 257 | # FADD dsp[rs], rd |
| 258 | FADD_mr 1111 1100 1000 10.. .... .... @b3_rd_ld_ul |
| 259 | |
| 260 | # FCMP #imm, rd |
| 261 | FCMP_ir 1111 1101 0111 0010 0001 rd:4 |
| 262 | # FCMP rs, rd |
| 263 | # FCMP dsp[rs], rd |
| 264 | FCMP_mr 1111 1100 1000 01.. .... .... @b3_rd_ld_ul |
| 265 | |
| 266 | # FDIV #imm, rd |
| 267 | FDIV_ir 1111 1101 0111 0010 0100 rd:4 |
| 268 | # FDIV rs, rd |
| 269 | # FDIV dsp[rs], rd |
| 270 | FDIV_mr 1111 1100 1001 00.. .... .... @b3_rd_ld_ul |
| 271 | |
| 272 | # FMUL #imm, rd |
| 273 | FMUL_ir 1111 1101 0111 0010 0011 rd:4 |
| 274 | # FMUL rs, rd |
| 275 | # FMUL dsp[rs], rd |
| 276 | FMUL_mr 1111 1100 1000 11.. .... .... @b3_rd_ld_ul |
| 277 | |
| 278 | # FSUB #imm, rd |
| 279 | FSUB_ir 1111 1101 0111 0010 0000 rd:4 |
| 280 | # FSUB rs, rd |
| 281 | # FSUB dsp[rs], rd |
| 282 | FSUB_mr 1111 1100 1000 00.. .... .... @b3_rd_ld_ul |
| 283 | |
| 284 | # FTOI rs, rd |
| 285 | # FTOI dsp[rs], rd |
| 286 | FTOI 1111 1100 1001 01.. .... .... @b3_rd_ld_ul |
| 287 | |
| 288 | # INT #uimm8 |
| 289 | INT 0111 0101 0110 0000 imm:8 |
| 290 | |
| 291 | # ITOF dsp[rs].ub, rd |
| 292 | # ITOF rs, rd |
| 293 | ITOF 1111 1100 0100 01.. .... .... @b3_rd_ld_ub |
| 294 | # ITOF dsp[rs], rd |
| 295 | ITOF 0000 0110 ..10 00.. 0001 0001 .... .... @b4_rd_ldmi |
| 296 | |
| 297 | # JMP rs |
| 298 | JMP 0111 1111 0000 rs:4 &jreg |
| 299 | # JSR rs |
| 300 | JSR 0111 1111 0001 rs:4 &jreg |
| 301 | |
| 302 | # MACHI rs, rs2 |
| 303 | MACHI 1111 1101 0000 0100 rs:4 rs2:4 |
| 304 | # MACLO rs, rs2 |
| 305 | MACLO 1111 1101 0000 0101 rs:4 rs2:4 |
| 306 | |
| 307 | # MAX #imm, rd |
| 308 | MAX_ir 1111 1101 0111 ..00 0100 .... @b3_rd_li |
| 309 | # MAX dsp[rs].ub, rd |
| 310 | # MAX rs, rd |
| 311 | MAX_mr 1111 1100 0001 00.. .... .... @b3_rd_ld_ub |
| 312 | # MAX dsp[rs], rd |
| 313 | MAX_mr 0000 0110 ..10 00.. 0000 0100 .... .... @b4_rd_ldmi |
| 314 | |
| 315 | # MIN #imm, rd |
| 316 | MIN_ir 1111 1101 0111 ..00 0101 .... @b3_rd_li |
| 317 | # MIN dsp[rs].ub, rd |
| 318 | # MIN rs, rd |
| 319 | MIN_mr 1111 1100 0001 01.. .... .... @b3_rd_ld_ub |
| 320 | # MIN dsp[rs], rd |
| 321 | MIN_mr 0000 0110 ..10 00.. 0000 0101 .... .... @b4_rd_ldmi |
| 322 | |
| 323 | # MOV.b rs, dsp5[rd] |
| 324 | MOV_rm 1000 0 .... rd:3 . rs:3 dsp=%b2_dsp5_3 sz=0 |
| 325 | # MOV.w rs, dsp5[rd] |
| 326 | MOV_rm 1001 0 .... rd:3 . rs:3 dsp=%b2_dsp5_3 sz=1 |
| 327 | # MOV.l rs, dsp5[rd] |
| 328 | MOV_rm 1010 0 .... rd:3 . rs:3 dsp=%b2_dsp5_3 sz=2 |
| 329 | # MOV.b dsp5[rs], rd |
| 330 | MOV_mr 1000 1 .... rs:3 . rd:3 dsp=%b2_dsp5_3 sz=0 |
| 331 | # MOV.w dsp5[rs], rd |
| 332 | MOV_mr 1001 1 .... rs:3 . rd:3 dsp=%b2_dsp5_3 sz=1 |
| 333 | # MOV.l dsp5[rs], rd |
| 334 | MOV_mr 1010 1 .... rs:3 . rd:3 dsp=%b2_dsp5_3 sz=2 |
| 335 | # MOV.l #uimm4, rd |
| 336 | MOV_ir 0110 0110 imm:4 rd:4 |
| 337 | # MOV.b #imm8, dsp5[rd] |
| 338 | MOV_im 0011 1100 . rd:3 .... imm:8 sz=0 dsp=%b3_dsp5_8 |
| 339 | # MOV.w #imm8, dsp5[rd] |
| 340 | MOV_im 0011 1101 . rd:3 .... imm:8 sz=1 dsp=%b3_dsp5_8 |
| 341 | # MOV.l #imm8, dsp5[rd] |
| 342 | MOV_im 0011 1110 . rd:3 .... imm:8 sz=2 dsp=%b3_dsp5_8 |
| 343 | # MOV.l #imm8, rd |
| 344 | MOV_ir 0111 0101 0100 rd:4 imm:8 |
| 345 | # MOV.l #mm8, rd |
| 346 | MOV_ir 1111 1011 rd:4 .. 10 imm=%b2_li_2 |
| 347 | # MOV.<bwl> #imm, [rd] |
| 348 | MOV_im 1111 1000 rd:4 .. sz:2 dsp=0 imm=%b2_li_2 |
| 349 | # MOV.<bwl> #imm, dsp8[rd] |
| 350 | MOV_im 1111 1001 rd:4 .. sz:2 dsp:8 imm=%b3_li_10 |
| 351 | # MOV.<bwl> #imm, dsp16[rd] |
| 352 | MOV_im 1111 1010 rd:4 .. sz:2 .... .... .... .... \ |
| 353 | imm=%b4_li_18 dsp=%b4_dsp_16 |
| 354 | # MOV.<bwl> [ri,rb], rd |
| 355 | MOV_ar 1111 1110 01 sz:2 ri:4 rb:4 rd:4 |
| 356 | # MOV.<bwl> rs, [ri,rb] |
| 357 | MOV_ra 1111 1110 00 sz:2 ri:4 rb:4 rs:4 |
| 358 | # Note ldd=3 and lds=3 indicate register src or dst |
| 359 | # MOV.b rs, rd |
| 360 | # MOV.b rs, dsp[rd] |
| 361 | # MOV.b dsp[rs], rd |
| 362 | # MOV.b dsp[rs], dsp[rd] |
| 363 | MOV_mm 1100 ldd:2 lds:2 rs:4 rd:4 sz=0 |
| 364 | # MOV.w rs, rd |
| 365 | # MOV.w rs, dsp[rd] |
| 366 | # MOV.w dsp[rs], rd |
| 367 | # MOV.w dsp[rs], dsp[rd] |
| 368 | MOV_mm 1101 ldd:2 lds:2 rs:4 rd:4 sz=1 |
| 369 | # MOV.l rs, rd |
| 370 | # MOV.l rs, dsp[rd] |
| 371 | # MOV.l dsp[rs], rd |
| 372 | # MOV.l dsp[rs], dsp[rd] |
| 373 | MOV_mm 1110 ldd:2 lds:2 rs:4 rd:4 sz=2 |
| 374 | # MOV.l rs, [rd+] |
| 375 | # MOV.l rs, [-rd] |
| 376 | MOV_rp 1111 1101 0010 0 ad:1 sz:2 rd:4 rs:4 |
| 377 | # MOV.l [rs+], rd |
| 378 | # MOV.l [-rs], rd |
| 379 | MOV_pr 1111 1101 0010 1 ad:1 sz:2 rd:4 rs:4 |
| 380 | |
| 381 | # MOVU.<bw> dsp5[rs], rd |
| 382 | MOVU_mr 1011 sz:1 ... . rs:3 . rd:3 dsp=%b2_dsp5_3 |
| 383 | # MOVU.<bw> [rs], rd |
| 384 | MOVU_mr 0101 1 sz:1 00 rs:4 rd:4 dsp=0 |
| 385 | # MOVU.<bw> dsp8[rs], rd |
| 386 | MOVU_mr 0101 1 sz:1 01 rs:4 rd:4 dsp:8 |
| 387 | # MOVU.<bw> dsp16[rs], rd |
| 388 | MOVU_mr 0101 1 sz:1 10 rs:4 rd:4 .... .... .... .... dsp=%b4_dsp_16 |
| 389 | # MOVU.<bw> rs, rd |
| 390 | MOVU_rr 0101 1 sz:1 11 rs:4 rd:4 |
| 391 | # MOVU.<bw> [ri, rb], rd |
| 392 | MOVU_ar 1111 1110 110 sz:1 ri:4 rb:4 rd:4 |
| 393 | # MOVU.<bw> [rs+], rd |
| 394 | MOVU_pr 1111 1101 0011 1 ad:1 0 sz:1 rd:4 rs:4 |
| 395 | |
| 396 | # MUL #uimm4, rd |
| 397 | MUL_ir 0110 0011 .... .... @b2_rds_uimm4 |
| 398 | # MUL #imm4, rd |
| 399 | MUL_ir 0111 01.. 0001 .... @b2_rds_li |
| 400 | # MUL dsp[rs].ub, rd |
| 401 | # MUL rs, rd |
| 402 | MUL_mr 0100 11.. .... .... @b2_rd_ld_ub |
| 403 | # MUL dsp[rs], rd |
| 404 | MUL_mr 0000 0110 ..00 11.. .... .... @b3_rd_ld |
| 405 | # MOV rs, rs2, rd |
| 406 | MUL_rrr 1111 1111 0011 .... .... .... @b3_rd_rs_rs2 |
| 407 | |
| 408 | # MULHI rs, rs2 |
| 409 | MULHI 1111 1101 0000 0000 rs:4 rs2:4 |
| 410 | # MULLO rs, rs2 |
| 411 | MULLO 1111 1101 0000 0001 rs:4 rs2:4 |
| 412 | |
| 413 | # MVFACHI rd |
| 414 | MVFACHI 1111 1101 0001 1111 0000 rd:4 |
| 415 | # MVFACMI rd |
| 416 | MVFACMI 1111 1101 0001 1111 0010 rd:4 |
| 417 | |
| 418 | # MVFC cr, rd |
| 419 | MVFC 1111 1101 0110 1010 cr:4 rd:4 |
| 420 | |
| 421 | # MVTACHI rs |
| 422 | MVTACHI 1111 1101 0001 0111 0000 rs:4 |
| 423 | # MVTACLO rs |
| 424 | MVTACLO 1111 1101 0001 0111 0001 rs:4 |
| 425 | |
| 426 | # MVTC #imm, cr |
| 427 | MVTC_i 1111 1101 0111 ..11 0000 cr:4 imm=%b3_li_10 |
| 428 | # MVTC rs, cr |
| 429 | MVTC_r 1111 1101 0110 1000 rs:4 cr:4 |
| 430 | |
| 431 | # MVTIPL #imm |
| 432 | MVTIPL 0111 0101 0111 0000 0000 imm:4 |
| 433 | |
| 434 | # NEG rd |
| 435 | NEG_rr 0111 1110 0001 .... @b2_rds |
| 436 | # NEG rs, rd |
| 437 | NEG_rr 1111 1100 0000 0111 .... .... @b3_rd_rs |
| 438 | |
| 439 | NOP 0000 0011 |
| 440 | |
| 441 | # NOT rd |
| 442 | NOT_rr 0111 1110 0000 .... @b2_rds |
| 443 | # NOT rs, rd |
| 444 | NOT_rr 1111 1100 0011 1011 .... .... @b3_rd_rs |
| 445 | |
| 446 | # OR #uimm4, rd |
| 447 | OR_ir 0110 0101 .... .... @b2_rds_uimm4 |
| 448 | # OR #imm, rd |
| 449 | OR_ir 0111 01.. 0011 .... @b2_rds_li |
| 450 | # OR dsp[rs].ub, rd |
| 451 | # OR rs, rd |
| 452 | OR_mr 0101 01.. .... .... @b2_rd_ld_ub |
| 453 | # OR dsp[rs], rd |
| 454 | OR_mr 0000 0110 .. 0101 .. .... .... @b3_rd_ld |
| 455 | # OR rs, rs2, rd |
| 456 | OR_rrr 1111 1111 0101 .... .... .... @b3_rd_rs_rs2 |
| 457 | |
| 458 | # POP cr |
| 459 | POPC 0111 1110 1110 cr:4 |
| 460 | # POP rd-rd2 |
| 461 | POPM 0110 1111 rd:4 rd2:4 |
| 462 | |
| 463 | # POP rd |
| 464 | # PUSH.<bwl> rs |
| 465 | { |
| 466 | POP 0111 1110 1011 rd:4 |
| 467 | PUSH_r 0111 1110 10 sz:2 rs:4 |
| 468 | } |
| 469 | # PUSH.<bwl> dsp[rs] |
| 470 | PUSH_m 1111 01 ld:2 rs:4 10 sz:2 |
| 471 | # PUSH cr |
| 472 | PUSHC 0111 1110 1100 cr:4 |
| 473 | # PUSHM rs-rs2 |
| 474 | PUSHM 0110 1110 rs:4 rs2:4 |
| 475 | |
| 476 | # RACW #imm |
| 477 | RACW 1111 1101 0001 1000 000 imm:1 0000 |
| 478 | |
| 479 | # REVL rs,rd |
| 480 | REVL 1111 1101 0110 0111 .... .... @b3_rd_rs |
| 481 | # REVW rs,rd |
| 482 | REVW 1111 1101 0110 0101 .... .... @b3_rd_rs |
| 483 | |
| 484 | # SMOVF |
| 485 | # RPMA.<bwl> |
| 486 | { |
| 487 | SMOVF 0111 1111 1000 1111 |
| 488 | RMPA 0111 1111 1000 11 sz:2 |
| 489 | } |
| 490 | |
| 491 | # ROLC rd |
| 492 | ROLC 0111 1110 0101 .... @b2_rds |
| 493 | # RORC rd |
| 494 | RORC 0111 1110 0100 .... @b2_rds |
| 495 | |
| 496 | # ROTL #imm, rd |
| 497 | ROTL_ir 1111 1101 0110 111. .... .... @b3_rds_imm5 |
| 498 | # ROTL rs, rd |
| 499 | ROTL_rr 1111 1101 0110 0110 .... .... @b3_rd_rs |
| 500 | |
| 501 | # ROTR #imm, rd |
| 502 | ROTR_ir 1111 1101 0110 110. .... .... @b3_rds_imm5 |
| 503 | # ROTR #imm, rd |
| 504 | ROTR_rr 1111 1101 0110 0100 .... .... @b3_rd_rs |
| 505 | |
| 506 | # ROUND rs,rd |
| 507 | # ROUND dsp[rs],rd |
| 508 | ROUND 1111 1100 1001 10 .. .... .... @b3_ld_rd_rs |
| 509 | |
| 510 | RTE 0111 1111 1001 0101 |
| 511 | |
| 512 | RTFI 0111 1111 1001 0100 |
| 513 | |
| 514 | RTS 0000 0010 |
| 515 | |
| 516 | # RTSD #imm |
| 517 | RTSD_i 0110 0111 imm:8 |
| 518 | # RTSD #imm, rd-rd2 |
| 519 | RTSD_irr 0011 1111 rd:4 rd2:4 imm:8 |
| 520 | |
| 521 | # SAT rd |
| 522 | SAT 0111 1110 0011 .... @b2_rds |
| 523 | # SATR |
| 524 | SATR 0111 1111 1001 0011 |
| 525 | |
| 526 | # SBB rs, rd |
| 527 | SBB_rr 1111 1100 0000 0011 .... .... @b3_rd_rs |
| 528 | # SBB dsp[rs].l, rd |
| 529 | # Note only mi==2 allowed. |
| 530 | SBB_mr 0000 0110 ..10 00.. 0000 0000 .... .... @b4_rd_ldmi |
| 531 | |
| 532 | # SCCnd dsp[rd] |
| 533 | # SCCnd rd |
| 534 | SCCnd 1111 1100 1101 .... .... .... @b3_sz_ld_rd_cd |
| 535 | |
| 536 | # SETPSW psw |
| 537 | SETPSW 0111 1111 1010 cb:4 |
| 538 | |
| 539 | # SHAR #imm, rd |
| 540 | SHAR_irr 0110 101. .... .... @b2_rds_imm5 |
| 541 | # SHAR #imm, rs, rd |
| 542 | SHAR_irr 1111 1101 101. .... .... .... @b3_rd_rs_imm5 |
| 543 | # SHAR rs, rd |
| 544 | SHAR_rr 1111 1101 0110 0001 .... .... @b3_rd_rs |
| 545 | |
| 546 | # SHLL #imm, rd |
| 547 | SHLL_irr 0110 110. .... .... @b2_rds_imm5 |
| 548 | # SHLL #imm, rs, rd |
| 549 | SHLL_irr 1111 1101 110. .... .... .... @b3_rd_rs_imm5 |
| 550 | # SHLL rs, rd |
| 551 | SHLL_rr 1111 1101 0110 0010 .... .... @b3_rd_rs |
| 552 | |
| 553 | # SHLR #imm, rd |
| 554 | SHLR_irr 0110 100. .... .... @b2_rds_imm5 |
| 555 | # SHLR #imm, rs, rd |
| 556 | SHLR_irr 1111 1101 100. .... .... .... @b3_rd_rs_imm5 |
| 557 | # SHLR rs, rd |
| 558 | SHLR_rr 1111 1101 0110 0000 .... .... @b3_rd_rs |
| 559 | |
| 560 | # SMOVB |
| 561 | # SSTR.<bwl> |
| 562 | { |
| 563 | SMOVB 0111 1111 1000 1011 |
| 564 | SSTR 0111 1111 1000 10 sz:2 |
| 565 | } |
| 566 | |
| 567 | # STNZ #imm, rd |
| 568 | STNZ 1111 1101 0111 ..00 1111 .... @b3_rd_li |
| 569 | # STZ #imm, rd |
| 570 | STZ 1111 1101 0111 ..00 1110 .... @b3_rd_li |
| 571 | |
| 572 | # SUB #uimm4, rd |
| 573 | SUB_ir 0110 0000 .... .... @b2_rds_uimm4 |
| 574 | # SUB dsp[rs].ub, rd |
| 575 | # SUB rs, rd |
| 576 | SUB_mr 0100 00.. .... .... @b2_rd_ld_ub |
| 577 | # SUB dsp[rs], rd |
| 578 | SUB_mr 0000 0110 ..00 00.. .... .... @b3_rd_ld |
| 579 | # SUB rs, rs2, rd |
| 580 | SUB_rrr 1111 1111 0000 .... .... .... @b3_rd_rs_rs2 |
| 581 | |
| 582 | # SCMPU |
| 583 | # SUNTIL.<bwl> |
| 584 | { |
| 585 | SCMPU 0111 1111 1000 0011 |
| 586 | SUNTIL 0111 1111 1000 00 sz:2 |
| 587 | } |
| 588 | |
| 589 | # SMOVU |
| 590 | # SWHILE.<bwl> |
| 591 | { |
| 592 | SMOVU 0111 1111 1000 0111 |
| 593 | SWHILE 0111 1111 1000 01 sz:2 |
| 594 | } |
| 595 | |
| 596 | # TST #imm, rd |
| 597 | TST_ir 1111 1101 0111 ..00 1100 .... @b3_rd_li |
| 598 | # TST dsp[rs].ub, rd |
| 599 | # TST rs, rd |
| 600 | TST_mr 1111 1100 0011 00.. .... .... @b3_rd_ld_ub |
| 601 | # TST dsp[rs], rd |
| 602 | TST_mr 0000 0110 ..10 00.. 0000 1100 .... .... @b4_rd_ldmi |
| 603 | |
| 604 | WAIT 0111 1111 1001 0110 |
| 605 | |
| 606 | # XCHG rs, rd |
| 607 | # XCHG dsp[rs].ub, rd |
| 608 | { |
| 609 | XCHG_rr 1111 1100 0100 0011 .... .... @b3_rd_rs |
| 610 | XCHG_mr 1111 1100 0100 00.. .... .... @b3_rd_ld_ub |
| 611 | } |
| 612 | # XCHG dsp[rs], rd |
| 613 | XCHG_mr 0000 0110 ..10 00.. 0001 0000 .... .... @b4_rd_ldmi |
| 614 | |
| 615 | # XOR #imm, rd |
| 616 | XOR_ir 1111 1101 0111 ..00 1101 .... @b3_rd_li |
| 617 | # XOR dsp[rs].ub, rd |
| 618 | # XOR rs, rd |
| 619 | XOR_mr 1111 1100 0011 01.. .... .... @b3_rd_ld_ub |
| 620 | # XOR dsp[rs], rd |
| 621 | XOR_mr 0000 0110 ..10 00.. 0000 1101 .... .... @b4_rd_ldmi |