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Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +01001/*
2 * IMX GPT Timer
3 *
4 * Copyright (c) 2008 OK Labs
5 * Copyright (c) 2011 NICTA Pty Ltd
6 * Originally written by Hans Jiang
7 * Updated by Peter Chubb
Jean-Christophe Duboisd647b262015-08-13 11:26:20 +01008 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +01009 *
10 * This code is licensed under GPL version 2 or later. See
11 * the COPYING file in the top-level directory.
12 *
13 */
14
Peter Maydell8ef94f02016-01-26 18:17:05 +000015#include "qemu/osdep.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020016#include "hw/irq.h"
Jean-Christophe Duboisd647b262015-08-13 11:26:20 +010017#include "hw/timer/imx_gpt.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020018#include "migration/vmstate.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020019#include "qemu/module.h"
Paolo Bonzini03dd0242015-12-15 13:16:16 +010020#include "qemu/log.h"
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +010021
Jean-Christophe Dubois05453522015-10-25 15:16:26 +010022#ifndef DEBUG_IMX_GPT
23#define DEBUG_IMX_GPT 0
24#endif
25
26#define DPRINTF(fmt, args...) \
27 do { \
28 if (DEBUG_IMX_GPT) { \
29 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \
30 __func__, ##args); \
31 } \
32 } while (0)
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +010033
Peter Maydelld6757652016-09-22 18:13:09 +010034static const char *imx_gpt_reg_name(uint32_t reg)
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +010035{
36 switch (reg) {
37 case 0:
38 return "CR";
39 case 1:
40 return "PR";
41 case 2:
42 return "SR";
43 case 3:
44 return "IR";
45 case 4:
46 return "OCR1";
47 case 5:
48 return "OCR2";
49 case 6:
50 return "OCR3";
51 case 7:
52 return "ICR1";
53 case 8:
54 return "ICR2";
55 case 9:
56 return "CNT";
57 default:
58 return "[?]";
59 }
60}
61
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +010062static const VMStateDescription vmstate_imx_timer_gpt = {
Jean-Christophe Dubois68b85292015-08-13 11:26:21 +010063 .name = TYPE_IMX_GPT,
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +010064 .version_id = 3,
65 .minimum_version_id = 3,
Juan Quintela8f1e8842014-05-13 16:09:35 +010066 .fields = (VMStateField[]) {
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +010067 VMSTATE_UINT32(cr, IMXGPTState),
68 VMSTATE_UINT32(pr, IMXGPTState),
69 VMSTATE_UINT32(sr, IMXGPTState),
70 VMSTATE_UINT32(ir, IMXGPTState),
71 VMSTATE_UINT32(ocr1, IMXGPTState),
72 VMSTATE_UINT32(ocr2, IMXGPTState),
73 VMSTATE_UINT32(ocr3, IMXGPTState),
74 VMSTATE_UINT32(icr1, IMXGPTState),
75 VMSTATE_UINT32(icr2, IMXGPTState),
76 VMSTATE_UINT32(cnt, IMXGPTState),
77 VMSTATE_UINT32(next_timeout, IMXGPTState),
78 VMSTATE_UINT32(next_int, IMXGPTState),
79 VMSTATE_UINT32(freq, IMXGPTState),
80 VMSTATE_PTIMER(timer, IMXGPTState),
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +010081 VMSTATE_END_OF_LIST()
82 }
83};
84
Jean-Christophe Dubois66542f62016-07-07 13:47:01 +010085static const IMXClk imx25_gpt_clocks[] = {
86 CLK_NONE, /* 000 No clock source */
87 CLK_IPG, /* 001 ipg_clk, 532MHz*/
88 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
89 CLK_NONE, /* 011 not defined */
90 CLK_32k, /* 100 ipg_clk_32k */
91 CLK_32k, /* 101 ipg_clk_32k */
92 CLK_32k, /* 110 ipg_clk_32k */
93 CLK_32k, /* 111 ipg_clk_32k */
94};
95
96static const IMXClk imx31_gpt_clocks[] = {
Jean-Christophe Duboisd552f672016-03-16 17:06:00 +000097 CLK_NONE, /* 000 No clock source */
98 CLK_IPG, /* 001 ipg_clk, 532MHz*/
99 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
100 CLK_NONE, /* 011 not defined */
101 CLK_32k, /* 100 ipg_clk_32k */
102 CLK_NONE, /* 101 not defined */
103 CLK_NONE, /* 110 not defined */
104 CLK_NONE, /* 111 not defined */
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100105};
106
Jean-Christophe Dubois66542f62016-07-07 13:47:01 +0100107static const IMXClk imx6_gpt_clocks[] = {
108 CLK_NONE, /* 000 No clock source */
109 CLK_IPG, /* 001 ipg_clk, 532MHz*/
110 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
111 CLK_EXT, /* 011 External clock */
112 CLK_32k, /* 100 ipg_clk_32k */
113 CLK_HIGH_DIV, /* 101 reference clock / 8 */
114 CLK_NONE, /* 110 not defined */
115 CLK_HIGH, /* 111 reference clock */
116};
117
Jean-Christophe Duboisa1e03952022-12-20 18:27:43 +0100118static const IMXClk imx6ul_gpt_clocks[] = {
119 CLK_NONE, /* 000 No clock source */
120 CLK_IPG, /* 001 ipg_clk, 532MHz*/
121 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
122 CLK_EXT, /* 011 External clock */
123 CLK_32k, /* 100 ipg_clk_32k */
124 CLK_NONE, /* 101 not defined */
125 CLK_NONE, /* 110 not defined */
126 CLK_NONE, /* 111 not defined */
127};
128
Andrey Smirnova62bf592018-02-09 10:40:30 +0000129static const IMXClk imx7_gpt_clocks[] = {
130 CLK_NONE, /* 000 No clock source */
131 CLK_IPG, /* 001 ipg_clk, 532MHz*/
132 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
133 CLK_EXT, /* 011 External clock */
134 CLK_32k, /* 100 ipg_clk_32k */
135 CLK_HIGH, /* 101 reference clock */
136 CLK_NONE, /* 110 not defined */
137 CLK_NONE, /* 111 not defined */
138};
139
Peter Maydell1b914992019-10-08 18:17:37 +0100140/* Must be called from within ptimer_transaction_begin/commit block */
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100141static void imx_gpt_set_freq(IMXGPTState *s)
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100142{
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100143 uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100144
Jean-Christophe Duboisaaa9ec32015-12-17 13:37:15 +0000145 s->freq = imx_ccm_get_clock_frequency(s->ccm,
Jean-Christophe Dubois66542f62016-07-07 13:47:01 +0100146 s->clocks[clksrc]) / (1 + s->pr);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100147
Jean-Christophe Duboisaaa9ec32015-12-17 13:37:15 +0000148 DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq);
149
150 if (s->freq) {
151 ptimer_set_freq(s->timer, s->freq);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100152 }
153}
154
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100155static void imx_gpt_update_int(IMXGPTState *s)
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100156{
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100157 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
158 qemu_irq_raise(s->irq);
159 } else {
160 qemu_irq_lower(s->irq);
161 }
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100162}
163
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100164static uint32_t imx_gpt_update_count(IMXGPTState *s)
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100165{
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100166 s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer);
167
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100168 return s->cnt;
169}
170
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100171static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
Jean-Christophe Dubois68b85292015-08-13 11:26:21 +0100172 uint32_t timeout)
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100173{
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100174 if ((count < reg) && (timeout > reg)) {
175 timeout = reg;
176 }
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100177
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100178 return timeout;
179}
180
Peter Maydell1b914992019-10-08 18:17:37 +0100181/* Must be called from within ptimer_transaction_begin/commit block */
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100182static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100183{
Michael Tokarev203d65a2014-08-02 00:14:48 +0400184 uint32_t timeout = GPT_TIMER_MAX;
Jean-Christophe Dubois4833e152016-03-16 17:05:59 +0000185 uint32_t count;
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100186 long long limit;
187
188 if (!(s->cr & GPT_CR_EN)) {
189 /* if not enabled just return */
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100190 return;
191 }
192
Jean-Christophe Dubois4833e152016-03-16 17:05:59 +0000193 /* update the count */
194 count = imx_gpt_update_count(s);
195
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100196 if (event) {
Jean-Christophe Dubois4833e152016-03-16 17:05:59 +0000197 /*
198 * This is an event (the ptimer reached 0 and stopped), and the
199 * timer counter is now equal to s->next_timeout.
200 */
201 if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) {
202 /* We are in restart mode and we crossed the compare channel 1
203 * value. We need to reset the counter to 0.
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100204 */
Jean-Christophe Dubois4833e152016-03-16 17:05:59 +0000205 count = s->cnt = s->next_timeout = 0;
206 } else if (count == GPT_TIMER_MAX) {
207 /* We reached GPT_TIMER_MAX so we need to rollover */
208 count = s->cnt = s->next_timeout = 0;
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100209 }
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100210 }
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100211
212 /* now, find the next timeout related to count */
213
214 if (s->ir & GPT_IR_OF1IE) {
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100215 timeout = imx_gpt_find_limit(count, s->ocr1, timeout);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100216 }
217 if (s->ir & GPT_IR_OF2IE) {
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100218 timeout = imx_gpt_find_limit(count, s->ocr2, timeout);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100219 }
220 if (s->ir & GPT_IR_OF3IE) {
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100221 timeout = imx_gpt_find_limit(count, s->ocr3, timeout);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100222 }
223
224 /* find the next set of interrupts to raise for next timer event */
225
226 s->next_int = 0;
227 if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) {
228 s->next_int |= GPT_SR_OF1;
229 }
230 if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) {
231 s->next_int |= GPT_SR_OF2;
232 }
233 if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) {
234 s->next_int |= GPT_SR_OF3;
235 }
Michael Tokarev203d65a2014-08-02 00:14:48 +0400236 if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) {
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100237 s->next_int |= GPT_SR_ROV;
238 }
239
240 /* the new range to count down from */
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100241 limit = timeout - imx_gpt_update_count(s);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100242
243 if (limit < 0) {
244 /*
245 * if we reach here, then QEMU is running too slow and we pass the
246 * timeout limit while computing it. Let's deliver the interrupt
247 * and compute a new limit.
248 */
249 s->sr |= s->next_int;
250
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100251 imx_gpt_compute_next_timeout(s, event);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100252
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100253 imx_gpt_update_int(s);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100254 } else {
255 /* New timeout value */
256 s->next_timeout = timeout;
257
258 /* reset the limit to the computed range */
259 ptimer_set_limit(s->timer, limit, 1);
260 }
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100261}
262
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100263static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100264{
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100265 IMXGPTState *s = IMX_GPT(opaque);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100266 uint32_t reg_value = 0;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100267
Jean-Christophe Dubois05453522015-10-25 15:16:26 +0100268 switch (offset >> 2) {
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100269 case 0: /* Control Register */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100270 reg_value = s->cr;
271 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100272
273 case 1: /* prescaler */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100274 reg_value = s->pr;
275 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100276
277 case 2: /* Status Register */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100278 reg_value = s->sr;
279 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100280
281 case 3: /* Interrupt Register */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100282 reg_value = s->ir;
283 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100284
285 case 4: /* Output Compare Register 1 */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100286 reg_value = s->ocr1;
287 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100288
289 case 5: /* Output Compare Register 2 */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100290 reg_value = s->ocr2;
291 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100292
293 case 6: /* Output Compare Register 3 */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100294 reg_value = s->ocr3;
295 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100296
297 case 7: /* input Capture Register 1 */
Jean-Christophe Dubois05453522015-10-25 15:16:26 +0100298 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n",
299 TYPE_IMX_GPT, __func__);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100300 reg_value = s->icr1;
301 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100302
303 case 8: /* input Capture Register 2 */
Jean-Christophe Dubois05453522015-10-25 15:16:26 +0100304 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n",
305 TYPE_IMX_GPT, __func__);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100306 reg_value = s->icr2;
307 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100308
309 case 9: /* cnt */
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100310 imx_gpt_update_count(s);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100311 reg_value = s->cnt;
312 break;
313
314 default:
Jean-Christophe Dubois05453522015-10-25 15:16:26 +0100315 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
316 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100317 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100318 }
319
Jean-Christophe Dubois05453522015-10-25 15:16:26 +0100320 DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100321
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100322 return reg_value;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100323}
324
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100325
Kurban Mallachievc98c9eb2017-02-28 12:08:16 +0000326static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset)
327{
Peter Maydell1b914992019-10-08 18:17:37 +0100328 ptimer_transaction_begin(s->timer);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100329 /* stop timer */
330 ptimer_stop(s->timer);
331
Kurban Mallachievc98c9eb2017-02-28 12:08:16 +0000332 /* Soft reset and hard reset differ only in their handling of the CR
333 * register -- soft reset preserves the values of some bits there.
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100334 */
Kurban Mallachievc98c9eb2017-02-28 12:08:16 +0000335 if (is_soft_reset) {
336 /* Clear all CR bits except those that are preserved by soft reset. */
337 s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN |
338 GPT_CR_WAITEN | GPT_CR_DBGEN |
339 (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT);
340 } else {
341 s->cr = 0;
342 }
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100343 s->sr = 0;
344 s->pr = 0;
345 s->ir = 0;
346 s->cnt = 0;
Michael Tokarev203d65a2014-08-02 00:14:48 +0400347 s->ocr1 = GPT_TIMER_MAX;
348 s->ocr2 = GPT_TIMER_MAX;
349 s->ocr3 = GPT_TIMER_MAX;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100350 s->icr1 = 0;
351 s->icr2 = 0;
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100352
Michael Tokarev203d65a2014-08-02 00:14:48 +0400353 s->next_timeout = GPT_TIMER_MAX;
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100354 s->next_int = 0;
355
356 /* compute new freq */
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100357 imx_gpt_set_freq(s);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100358
Michael Tokarev203d65a2014-08-02 00:14:48 +0400359 /* reset the limit to GPT_TIMER_MAX */
360 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100361
362 /* if the timer is still enabled, restart it */
363 if (s->freq && (s->cr & GPT_CR_EN)) {
364 ptimer_run(s->timer, 1);
365 }
Peter Maydell1b914992019-10-08 18:17:37 +0100366 ptimer_transaction_commit(s->timer);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100367}
368
Kurban Mallachievc98c9eb2017-02-28 12:08:16 +0000369static void imx_gpt_soft_reset(DeviceState *dev)
370{
371 IMXGPTState *s = IMX_GPT(dev);
372 imx_gpt_reset_common(s, true);
373}
374
375static void imx_gpt_reset(DeviceState *dev)
376{
377 IMXGPTState *s = IMX_GPT(dev);
378 imx_gpt_reset_common(s, false);
379}
380
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100381static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
382 unsigned size)
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100383{
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100384 IMXGPTState *s = IMX_GPT(opaque);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100385 uint32_t oldreg;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100386
Jean-Christophe Dubois05453522015-10-25 15:16:26 +0100387 DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2),
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100388 (uint32_t)value);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100389
Jean-Christophe Dubois05453522015-10-25 15:16:26 +0100390 switch (offset >> 2) {
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100391 case 0:
392 oldreg = s->cr;
393 s->cr = value & ~0x7c14;
394 if (s->cr & GPT_CR_SWR) { /* force reset */
395 /* handle the reset */
Kurban Mallachievc98c9eb2017-02-28 12:08:16 +0000396 imx_gpt_soft_reset(DEVICE(s));
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100397 } else {
398 /* set our freq, as the source might have changed */
Peter Maydell1b914992019-10-08 18:17:37 +0100399 ptimer_transaction_begin(s->timer);
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100400 imx_gpt_set_freq(s);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100401
402 if ((oldreg ^ s->cr) & GPT_CR_EN) {
403 if (s->cr & GPT_CR_EN) {
404 if (s->cr & GPT_CR_ENMOD) {
Michael Tokarev203d65a2014-08-02 00:14:48 +0400405 s->next_timeout = GPT_TIMER_MAX;
406 ptimer_set_count(s->timer, GPT_TIMER_MAX);
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100407 imx_gpt_compute_next_timeout(s, false);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100408 }
409 ptimer_run(s->timer, 1);
410 } else {
411 /* stop timer */
412 ptimer_stop(s->timer);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100413 }
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100414 }
Peter Maydell1b914992019-10-08 18:17:37 +0100415 ptimer_transaction_commit(s->timer);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100416 }
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100417 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100418
419 case 1: /* Prescaler */
420 s->pr = value & 0xfff;
Peter Maydell1b914992019-10-08 18:17:37 +0100421 ptimer_transaction_begin(s->timer);
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100422 imx_gpt_set_freq(s);
Peter Maydell1b914992019-10-08 18:17:37 +0100423 ptimer_transaction_commit(s->timer);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100424 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100425
426 case 2: /* SR */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100427 s->sr &= ~(value & 0x3f);
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100428 imx_gpt_update_int(s);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100429 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100430
431 case 3: /* IR -- interrupt register */
432 s->ir = value & 0x3f;
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100433 imx_gpt_update_int(s);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100434
Peter Maydell1b914992019-10-08 18:17:37 +0100435 ptimer_transaction_begin(s->timer);
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100436 imx_gpt_compute_next_timeout(s, false);
Peter Maydell1b914992019-10-08 18:17:37 +0100437 ptimer_transaction_commit(s->timer);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100438
439 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100440
441 case 4: /* OCR1 -- output compare register */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100442 s->ocr1 = value;
443
Peter Maydell1b914992019-10-08 18:17:37 +0100444 ptimer_transaction_begin(s->timer);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100445 /* In non-freerun mode, reset count when this register is written */
446 if (!(s->cr & GPT_CR_FRR)) {
Michael Tokarev203d65a2014-08-02 00:14:48 +0400447 s->next_timeout = GPT_TIMER_MAX;
448 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100449 }
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100450
451 /* compute the new timeout */
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100452 imx_gpt_compute_next_timeout(s, false);
Peter Maydell1b914992019-10-08 18:17:37 +0100453 ptimer_transaction_commit(s->timer);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100454
455 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100456
457 case 5: /* OCR2 -- output compare register */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100458 s->ocr2 = value;
459
460 /* compute the new timeout */
Peter Maydell1b914992019-10-08 18:17:37 +0100461 ptimer_transaction_begin(s->timer);
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100462 imx_gpt_compute_next_timeout(s, false);
Peter Maydell1b914992019-10-08 18:17:37 +0100463 ptimer_transaction_commit(s->timer);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100464
465 break;
466
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100467 case 6: /* OCR3 -- output compare register */
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100468 s->ocr3 = value;
469
470 /* compute the new timeout */
Peter Maydell1b914992019-10-08 18:17:37 +0100471 ptimer_transaction_begin(s->timer);
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100472 imx_gpt_compute_next_timeout(s, false);
Peter Maydell1b914992019-10-08 18:17:37 +0100473 ptimer_transaction_commit(s->timer);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100474
475 break;
476
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100477 default:
Jean-Christophe Dubois05453522015-10-25 15:16:26 +0100478 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
479 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100480 break;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100481 }
482}
483
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100484static void imx_gpt_timeout(void *opaque)
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100485{
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100486 IMXGPTState *s = IMX_GPT(opaque);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100487
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100488 DPRINTF("\n");
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100489
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100490 s->sr |= s->next_int;
491 s->next_int = 0;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100492
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100493 imx_gpt_compute_next_timeout(s, true);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100494
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100495 imx_gpt_update_int(s);
Jean-Christophe DUBOIS5ec694b2013-06-25 18:34:13 +0100496
497 if (s->freq && (s->cr & GPT_CR_EN)) {
498 ptimer_run(s->timer, 1);
499 }
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100500}
501
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100502static const MemoryRegionOps imx_gpt_ops = {
503 .read = imx_gpt_read,
504 .write = imx_gpt_write,
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100505 .endianness = DEVICE_NATIVE_ENDIAN,
506};
507
508
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100509static void imx_gpt_realize(DeviceState *dev, Error **errp)
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100510{
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100511 IMXGPTState *s = IMX_GPT(dev);
512 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100513
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100514 sysbus_init_irq(sbd, &s->irq);
Paolo Bonzini853dca12013-06-06 21:25:08 -0400515 memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100516 0x00001000);
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100517 sysbus_init_mmio(sbd, &s->iomem);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100518
Peter Maydell9598c1b2022-05-16 11:30:58 +0100519 s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_LEGACY);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100520}
521
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100522static void imx_gpt_class_init(ObjectClass *klass, void *data)
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100523{
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100524 DeviceClass *dc = DEVICE_CLASS(klass);
525
526 dc->realize = imx_gpt_realize;
527 dc->reset = imx_gpt_reset;
528 dc->vmsd = &vmstate_imx_timer_gpt;
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100529 dc->desc = "i.MX general timer";
530}
531
Jean-Christophe Dubois66542f62016-07-07 13:47:01 +0100532static void imx25_gpt_init(Object *obj)
533{
534 IMXGPTState *s = IMX_GPT(obj);
535
536 s->clocks = imx25_gpt_clocks;
537}
538
539static void imx31_gpt_init(Object *obj)
540{
541 IMXGPTState *s = IMX_GPT(obj);
542
543 s->clocks = imx31_gpt_clocks;
544}
545
546static void imx6_gpt_init(Object *obj)
547{
548 IMXGPTState *s = IMX_GPT(obj);
549
550 s->clocks = imx6_gpt_clocks;
551}
552
Jean-Christophe Duboisa1e03952022-12-20 18:27:43 +0100553static void imx6ul_gpt_init(Object *obj)
554{
555 IMXGPTState *s = IMX_GPT(obj);
556
557 s->clocks = imx6ul_gpt_clocks;
558}
559
Andrey Smirnova62bf592018-02-09 10:40:30 +0000560static void imx7_gpt_init(Object *obj)
561{
562 IMXGPTState *s = IMX_GPT(obj);
563
564 s->clocks = imx7_gpt_clocks;
565}
566
Jean-Christophe Dubois66542f62016-07-07 13:47:01 +0100567static const TypeInfo imx25_gpt_info = {
568 .name = TYPE_IMX25_GPT,
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100569 .parent = TYPE_SYS_BUS_DEVICE,
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100570 .instance_size = sizeof(IMXGPTState),
Jean-Christophe Dubois66542f62016-07-07 13:47:01 +0100571 .instance_init = imx25_gpt_init,
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100572 .class_init = imx_gpt_class_init,
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100573};
574
Jean-Christophe Dubois66542f62016-07-07 13:47:01 +0100575static const TypeInfo imx31_gpt_info = {
576 .name = TYPE_IMX31_GPT,
577 .parent = TYPE_IMX25_GPT,
578 .instance_init = imx31_gpt_init,
579};
580
581static const TypeInfo imx6_gpt_info = {
582 .name = TYPE_IMX6_GPT,
583 .parent = TYPE_IMX25_GPT,
584 .instance_init = imx6_gpt_init,
585};
586
Jean-Christophe Duboisa1e03952022-12-20 18:27:43 +0100587static const TypeInfo imx6ul_gpt_info = {
588 .name = TYPE_IMX6UL_GPT,
589 .parent = TYPE_IMX25_GPT,
590 .instance_init = imx6ul_gpt_init,
591};
592
Andrey Smirnova62bf592018-02-09 10:40:30 +0000593static const TypeInfo imx7_gpt_info = {
594 .name = TYPE_IMX7_GPT,
595 .parent = TYPE_IMX25_GPT,
596 .instance_init = imx7_gpt_init,
597};
598
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100599static void imx_gpt_register_types(void)
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100600{
Jean-Christophe Dubois66542f62016-07-07 13:47:01 +0100601 type_register_static(&imx25_gpt_info);
602 type_register_static(&imx31_gpt_info);
603 type_register_static(&imx6_gpt_info);
Jean-Christophe Duboisa1e03952022-12-20 18:27:43 +0100604 type_register_static(&imx6ul_gpt_info);
Andrey Smirnova62bf592018-02-09 10:40:30 +0000605 type_register_static(&imx7_gpt_info);
Jean-Christophe DUBOISa50c0d62013-06-03 17:17:45 +0100606}
607
Jean-Christophe DUBOIS67110c32013-06-25 18:34:13 +0100608type_init(imx_gpt_register_types)