blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU Sparc Sun4m ECC memory controller emulation |
| 3 | * |
| 4 | * Copyright (c) 2007 Robert Reif |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Blue Swirl | 49e6637 | 2009-07-12 08:16:55 +0000 | [diff] [blame] | 24 | |
Peter Maydell | 0d1c978 | 2016-01-26 18:17:17 +0000 | [diff] [blame] | 25 | #include "qemu/osdep.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 26 | #include "hw/irq.h" |
Markus Armbruster | a27bd6c | 2019-08-12 07:23:51 +0200 | [diff] [blame] | 27 | #include "hw/qdev-properties.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 28 | #include "hw/sysbus.h" |
Markus Armbruster | d645427 | 2019-08-12 07:23:45 +0200 | [diff] [blame] | 29 | #include "migration/vmstate.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 30 | #include "qemu/module.h" |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 31 | #include "trace.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 32 | #include "qom/object.h" |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 33 | |
| 34 | /* There are 3 versions of this chip used in SMP sun4m systems: |
| 35 | * MCC (version 0, implementation 0) SS-600MP |
| 36 | * EMC (version 0, implementation 1) SS-10 |
| 37 | * SMC (version 0, implementation 2) SS-10SX and SS-20 |
Blue Swirl | 5ac574c | 2009-10-24 15:27:28 +0000 | [diff] [blame] | 38 | * |
| 39 | * Chipset docs: |
| 40 | * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, |
| 41 | * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 42 | */ |
| 43 | |
blueswir1 | 0bb3602 | 2008-12-23 15:08:13 +0000 | [diff] [blame] | 44 | #define ECC_MCC 0x00000000 |
| 45 | #define ECC_EMC 0x10000000 |
| 46 | #define ECC_SMC 0x20000000 |
| 47 | |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 48 | /* Register indexes */ |
| 49 | #define ECC_MER 0 /* Memory Enable Register */ |
| 50 | #define ECC_MDR 1 /* Memory Delay Register */ |
| 51 | #define ECC_MFSR 2 /* Memory Fault Status Register */ |
| 52 | #define ECC_VCR 3 /* Video Configuration Register */ |
| 53 | #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ |
| 54 | #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ |
| 55 | #define ECC_DR 6 /* Diagnostic Register */ |
| 56 | #define ECC_ECR0 7 /* Event Count Register 0 */ |
| 57 | #define ECC_ECR1 8 /* Event Count Register 1 */ |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 58 | |
| 59 | /* ECC fault control register */ |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 60 | #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 61 | #define ECC_MER_EI 0x00000002 /* Enable Interrupts on |
| 62 | correctable errors */ |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 63 | #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ |
| 64 | #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ |
| 65 | #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ |
| 66 | #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ |
| 67 | #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ |
| 68 | #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ |
| 69 | #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ |
| 70 | #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ |
blueswir1 | 0bb3602 | 2008-12-23 15:08:13 +0000 | [diff] [blame] | 71 | #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 72 | #define ECC_MER_MRR 0x000003fc /* MRR mask */ |
blueswir1 | 0bb3602 | 2008-12-23 15:08:13 +0000 | [diff] [blame] | 73 | #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 74 | #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 75 | #define ECC_MER_VER 0x0f000000 /* Version */ |
| 76 | #define ECC_MER_IMPL 0xf0000000 /* Implementation */ |
blueswir1 | 0bb3602 | 2008-12-23 15:08:13 +0000 | [diff] [blame] | 77 | #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ |
| 78 | #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ |
| 79 | #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 80 | |
| 81 | /* ECC memory delay register */ |
| 82 | #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ |
| 83 | #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ |
| 84 | #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ |
| 85 | #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ |
| 86 | #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ |
| 87 | #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ |
| 88 | #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ |
| 89 | #define ECC_MDR_MASK 0x7fffffff |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 90 | |
| 91 | /* ECC fault status register */ |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 92 | #define ECC_MFSR_CE 0x00000001 /* Correctable error */ |
| 93 | #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ |
| 94 | #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ |
| 95 | #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ |
| 96 | #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ |
| 97 | #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ |
| 98 | #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ |
| 99 | #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 100 | |
| 101 | /* ECC fault address register 0 */ |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 102 | #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ |
| 103 | #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ |
| 104 | #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ |
| 105 | #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ |
| 106 | #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ |
| 107 | #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ |
| 108 | #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ |
| 109 | #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ |
| 110 | #define ECC_MFARO_MID 0xf0000000 /* Module ID */ |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 111 | |
| 112 | /* ECC diagnostic register */ |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 113 | #define ECC_DR_CBX 0x00000001 |
| 114 | #define ECC_DR_CB0 0x00000002 |
| 115 | #define ECC_DR_CB1 0x00000004 |
| 116 | #define ECC_DR_CB2 0x00000008 |
| 117 | #define ECC_DR_CB4 0x00000010 |
| 118 | #define ECC_DR_CB8 0x00000020 |
| 119 | #define ECC_DR_CB16 0x00000040 |
| 120 | #define ECC_DR_CB32 0x00000080 |
| 121 | #define ECC_DR_DMODE 0x00000c00 |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 122 | |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 123 | #define ECC_NREGS 9 |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 124 | #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 125 | |
| 126 | #define ECC_DIAG_SIZE 4 |
| 127 | #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 128 | |
Andreas Färber | 100bb15 | 2013-07-26 21:39:54 +0200 | [diff] [blame] | 129 | #define TYPE_ECC_MEMCTL "eccmemctl" |
Eduardo Habkost | 8063396 | 2020-09-16 14:25:19 -0400 | [diff] [blame] | 130 | OBJECT_DECLARE_SIMPLE_TYPE(ECCState, ECC_MEMCTL) |
Andreas Färber | 100bb15 | 2013-07-26 21:39:54 +0200 | [diff] [blame] | 131 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 132 | struct ECCState { |
Andreas Färber | 100bb15 | 2013-07-26 21:39:54 +0200 | [diff] [blame] | 133 | SysBusDevice parent_obj; |
| 134 | |
Avi Kivity | 7ef57cc | 2011-11-14 11:17:21 +0200 | [diff] [blame] | 135 | MemoryRegion iomem, iomem_diag; |
blueswir1 | e42c20b | 2008-01-17 21:04:16 +0000 | [diff] [blame] | 136 | qemu_irq irq; |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 137 | uint32_t regs[ECC_NREGS]; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 138 | uint8_t diag[ECC_DIAG_SIZE]; |
blueswir1 | 0bb3602 | 2008-12-23 15:08:13 +0000 | [diff] [blame] | 139 | uint32_t version; |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 140 | }; |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 141 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 142 | static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val, |
Avi Kivity | 7ef57cc | 2011-11-14 11:17:21 +0200 | [diff] [blame] | 143 | unsigned size) |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 144 | { |
| 145 | ECCState *s = opaque; |
| 146 | |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 147 | switch (addr >> 2) { |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 148 | case ECC_MER: |
blueswir1 | 0bb3602 | 2008-12-23 15:08:13 +0000 | [diff] [blame] | 149 | if (s->version == ECC_MCC) |
| 150 | s->regs[ECC_MER] = (val & ECC_MER_MASK_0); |
| 151 | else if (s->version == ECC_EMC) |
| 152 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); |
| 153 | else if (s->version == ECC_SMC) |
| 154 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 155 | trace_ecc_mem_writel_mer(val); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 156 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 157 | case ECC_MDR: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 158 | s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 159 | trace_ecc_mem_writel_mdr(val); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 160 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 161 | case ECC_MFSR: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 162 | s->regs[ECC_MFSR] = val; |
blueswir1 | 0bb3602 | 2008-12-23 15:08:13 +0000 | [diff] [blame] | 163 | qemu_irq_lower(s->irq); |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 164 | trace_ecc_mem_writel_mfsr(val); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 165 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 166 | case ECC_VCR: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 167 | s->regs[ECC_VCR] = val; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 168 | trace_ecc_mem_writel_vcr(val); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 169 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 170 | case ECC_DR: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 171 | s->regs[ECC_DR] = val; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 172 | trace_ecc_mem_writel_dr(val); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 173 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 174 | case ECC_ECR0: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 175 | s->regs[ECC_ECR0] = val; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 176 | trace_ecc_mem_writel_ecr0(val); |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 177 | break; |
| 178 | case ECC_ECR1: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 179 | s->regs[ECC_ECR0] = val; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 180 | trace_ecc_mem_writel_ecr1(val); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 181 | break; |
| 182 | } |
| 183 | } |
| 184 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 185 | static uint64_t ecc_mem_read(void *opaque, hwaddr addr, |
Avi Kivity | 7ef57cc | 2011-11-14 11:17:21 +0200 | [diff] [blame] | 186 | unsigned size) |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 187 | { |
| 188 | ECCState *s = opaque; |
| 189 | uint32_t ret = 0; |
| 190 | |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 191 | switch (addr >> 2) { |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 192 | case ECC_MER: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 193 | ret = s->regs[ECC_MER]; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 194 | trace_ecc_mem_readl_mer(ret); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 195 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 196 | case ECC_MDR: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 197 | ret = s->regs[ECC_MDR]; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 198 | trace_ecc_mem_readl_mdr(ret); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 199 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 200 | case ECC_MFSR: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 201 | ret = s->regs[ECC_MFSR]; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 202 | trace_ecc_mem_readl_mfsr(ret); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 203 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 204 | case ECC_VCR: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 205 | ret = s->regs[ECC_VCR]; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 206 | trace_ecc_mem_readl_vcr(ret); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 207 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 208 | case ECC_MFAR0: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 209 | ret = s->regs[ECC_MFAR0]; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 210 | trace_ecc_mem_readl_mfar0(ret); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 211 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 212 | case ECC_MFAR1: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 213 | ret = s->regs[ECC_MFAR1]; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 214 | trace_ecc_mem_readl_mfar1(ret); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 215 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 216 | case ECC_DR: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 217 | ret = s->regs[ECC_DR]; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 218 | trace_ecc_mem_readl_dr(ret); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 219 | break; |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 220 | case ECC_ECR0: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 221 | ret = s->regs[ECC_ECR0]; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 222 | trace_ecc_mem_readl_ecr0(ret); |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 223 | break; |
| 224 | case ECC_ECR1: |
blueswir1 | 8f2ad0a | 2008-06-19 17:38:15 +0000 | [diff] [blame] | 225 | ret = s->regs[ECC_ECR0]; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 226 | trace_ecc_mem_readl_ecr1(ret); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 227 | break; |
| 228 | } |
| 229 | return ret; |
| 230 | } |
| 231 | |
Avi Kivity | 7ef57cc | 2011-11-14 11:17:21 +0200 | [diff] [blame] | 232 | static const MemoryRegionOps ecc_mem_ops = { |
| 233 | .read = ecc_mem_read, |
| 234 | .write = ecc_mem_write, |
| 235 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 236 | .valid = { |
| 237 | .min_access_size = 4, |
| 238 | .max_access_size = 4, |
| 239 | }, |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 240 | }; |
| 241 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 242 | static void ecc_diag_mem_write(void *opaque, hwaddr addr, |
Avi Kivity | 7ef57cc | 2011-11-14 11:17:21 +0200 | [diff] [blame] | 243 | uint64_t val, unsigned size) |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 244 | { |
| 245 | ECCState *s = opaque; |
| 246 | |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 247 | trace_ecc_diag_mem_writeb(addr, val); |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 248 | s->diag[addr & ECC_DIAG_MASK] = val; |
| 249 | } |
| 250 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 251 | static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr, |
Avi Kivity | 7ef57cc | 2011-11-14 11:17:21 +0200 | [diff] [blame] | 252 | unsigned size) |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 253 | { |
| 254 | ECCState *s = opaque; |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 255 | uint32_t ret = s->diag[(int)addr]; |
| 256 | |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 257 | trace_ecc_diag_mem_readb(addr, ret); |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 258 | return ret; |
| 259 | } |
| 260 | |
Avi Kivity | 7ef57cc | 2011-11-14 11:17:21 +0200 | [diff] [blame] | 261 | static const MemoryRegionOps ecc_diag_mem_ops = { |
| 262 | .read = ecc_diag_mem_read, |
| 263 | .write = ecc_diag_mem_write, |
| 264 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 265 | .valid = { |
| 266 | .min_access_size = 1, |
| 267 | .max_access_size = 1, |
| 268 | }, |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 269 | }; |
| 270 | |
Blue Swirl | c21011a | 2009-08-29 16:36:58 +0300 | [diff] [blame] | 271 | static const VMStateDescription vmstate_ecc = { |
| 272 | .name ="ECC", |
| 273 | .version_id = 3, |
| 274 | .minimum_version_id = 3, |
Juan Quintela | 35d0845 | 2014-04-16 16:01:33 +0200 | [diff] [blame] | 275 | .fields = (VMStateField[]) { |
Blue Swirl | c21011a | 2009-08-29 16:36:58 +0300 | [diff] [blame] | 276 | VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS), |
| 277 | VMSTATE_BUFFER(diag, ECCState), |
| 278 | VMSTATE_UINT32(version, ECCState), |
| 279 | VMSTATE_END_OF_LIST() |
| 280 | } |
| 281 | }; |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 282 | |
Blue Swirl | 0284dc5 | 2009-10-24 14:14:39 +0000 | [diff] [blame] | 283 | static void ecc_reset(DeviceState *d) |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 284 | { |
Andreas Färber | 100bb15 | 2013-07-26 21:39:54 +0200 | [diff] [blame] | 285 | ECCState *s = ECC_MEMCTL(d); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 286 | |
Andreas Färber | 100bb15 | 2013-07-26 21:39:54 +0200 | [diff] [blame] | 287 | if (s->version == ECC_MCC) { |
blueswir1 | 0bb3602 | 2008-12-23 15:08:13 +0000 | [diff] [blame] | 288 | s->regs[ECC_MER] &= ECC_MER_REU; |
Andreas Färber | 100bb15 | 2013-07-26 21:39:54 +0200 | [diff] [blame] | 289 | } else { |
blueswir1 | 0bb3602 | 2008-12-23 15:08:13 +0000 | [diff] [blame] | 290 | s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | |
| 291 | ECC_MER_DCI); |
Andreas Färber | 100bb15 | 2013-07-26 21:39:54 +0200 | [diff] [blame] | 292 | } |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 293 | s->regs[ECC_MDR] = 0x20; |
| 294 | s->regs[ECC_MFSR] = 0; |
| 295 | s->regs[ECC_VCR] = 0; |
| 296 | s->regs[ECC_MFAR0] = 0x07c00000; |
| 297 | s->regs[ECC_MFAR1] = 0; |
| 298 | s->regs[ECC_DR] = 0; |
| 299 | s->regs[ECC_ECR0] = 0; |
| 300 | s->regs[ECC_ECR1] = 0; |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 301 | } |
| 302 | |
xiaoqiang zhao | b229a57 | 2017-05-25 21:34:44 +0800 | [diff] [blame] | 303 | static void ecc_init(Object *obj) |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 304 | { |
xiaoqiang zhao | b229a57 | 2017-05-25 21:34:44 +0800 | [diff] [blame] | 305 | ECCState *s = ECC_MEMCTL(obj); |
| 306 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 307 | |
Blue Swirl | 49e6637 | 2009-07-12 08:16:55 +0000 | [diff] [blame] | 308 | sysbus_init_irq(dev, &s->irq); |
xiaoqiang zhao | b229a57 | 2017-05-25 21:34:44 +0800 | [diff] [blame] | 309 | |
| 310 | memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE); |
Avi Kivity | 750ecd4 | 2011-11-27 11:38:10 +0200 | [diff] [blame] | 311 | sysbus_init_mmio(dev, &s->iomem); |
xiaoqiang zhao | b229a57 | 2017-05-25 21:34:44 +0800 | [diff] [blame] | 312 | } |
| 313 | |
| 314 | static void ecc_realize(DeviceState *dev, Error **errp) |
| 315 | { |
| 316 | ECCState *s = ECC_MEMCTL(dev); |
| 317 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 318 | |
| 319 | s->regs[0] = s->version; |
Blue Swirl | 49e6637 | 2009-07-12 08:16:55 +0000 | [diff] [blame] | 320 | |
| 321 | if (s->version == ECC_MCC) { // SS-600MP only |
Paolo Bonzini | 3c16154 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 322 | memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s, |
Avi Kivity | 7ef57cc | 2011-11-14 11:17:21 +0200 | [diff] [blame] | 323 | "ecc.diag", ECC_DIAG_SIZE); |
xiaoqiang zhao | b229a57 | 2017-05-25 21:34:44 +0800 | [diff] [blame] | 324 | sysbus_init_mmio(sbd, &s->iomem_diag); |
blueswir1 | dd53ded | 2008-05-06 16:33:45 +0000 | [diff] [blame] | 325 | } |
blueswir1 | 7eb0c8e | 2007-12-09 17:03:50 +0000 | [diff] [blame] | 326 | } |
Blue Swirl | 49e6637 | 2009-07-12 08:16:55 +0000 | [diff] [blame] | 327 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 328 | static Property ecc_properties[] = { |
Paolo Bonzini | c7bcc85 | 2014-02-08 11:01:53 +0100 | [diff] [blame] | 329 | DEFINE_PROP_UINT32("version", ECCState, version, -1), |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 330 | DEFINE_PROP_END_OF_LIST(), |
| 331 | }; |
| 332 | |
| 333 | static void ecc_class_init(ObjectClass *klass, void *data) |
| 334 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 335 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 336 | |
xiaoqiang zhao | b229a57 | 2017-05-25 21:34:44 +0800 | [diff] [blame] | 337 | dc->realize = ecc_realize; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 338 | dc->reset = ecc_reset; |
| 339 | dc->vmsd = &vmstate_ecc; |
Marc-André Lureau | 4f67d30 | 2020-01-10 19:30:32 +0400 | [diff] [blame] | 340 | device_class_set_props(dc, ecc_properties); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 341 | } |
| 342 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 343 | static const TypeInfo ecc_info = { |
Andreas Färber | 100bb15 | 2013-07-26 21:39:54 +0200 | [diff] [blame] | 344 | .name = TYPE_ECC_MEMCTL, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 345 | .parent = TYPE_SYS_BUS_DEVICE, |
| 346 | .instance_size = sizeof(ECCState), |
xiaoqiang zhao | b229a57 | 2017-05-25 21:34:44 +0800 | [diff] [blame] | 347 | .instance_init = ecc_init, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 348 | .class_init = ecc_class_init, |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 349 | }; |
| 350 | |
| 351 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 352 | static void ecc_register_types(void) |
Blue Swirl | 49e6637 | 2009-07-12 08:16:55 +0000 | [diff] [blame] | 353 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 354 | type_register_static(&ecc_info); |
Blue Swirl | 49e6637 | 2009-07-12 08:16:55 +0000 | [diff] [blame] | 355 | } |
| 356 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 357 | type_init(ecc_register_types) |