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blueswir17eb0c8e2007-12-09 17:03:50 +00001/*
2 * QEMU Sparc Sun4m ECC memory controller emulation
3 *
4 * Copyright (c) 2007 Robert Reif
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Blue Swirl49e66372009-07-12 08:16:55 +000024
Peter Maydell0d1c9782016-01-26 18:17:17 +000025#include "qemu/osdep.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020026#include "hw/irq.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020027#include "hw/qdev-properties.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010028#include "hw/sysbus.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020029#include "migration/vmstate.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020030#include "qemu/module.h"
Blue Swirl97bf4852010-10-31 09:24:14 +000031#include "trace.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040032#include "qom/object.h"
blueswir17eb0c8e2007-12-09 17:03:50 +000033
34/* There are 3 versions of this chip used in SMP sun4m systems:
35 * MCC (version 0, implementation 0) SS-600MP
36 * EMC (version 0, implementation 1) SS-10
37 * SMC (version 0, implementation 2) SS-10SX and SS-20
Blue Swirl5ac574c2009-10-24 15:27:28 +000038 *
39 * Chipset docs:
40 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
41 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
blueswir17eb0c8e2007-12-09 17:03:50 +000042 */
43
blueswir10bb36022008-12-23 15:08:13 +000044#define ECC_MCC 0x00000000
45#define ECC_EMC 0x10000000
46#define ECC_SMC 0x20000000
47
blueswir18f2ad0a2008-06-19 17:38:15 +000048/* Register indexes */
49#define ECC_MER 0 /* Memory Enable Register */
50#define ECC_MDR 1 /* Memory Delay Register */
51#define ECC_MFSR 2 /* Memory Fault Status Register */
52#define ECC_VCR 3 /* Video Configuration Register */
53#define ECC_MFAR0 4 /* Memory Fault Address Register 0 */
54#define ECC_MFAR1 5 /* Memory Fault Address Register 1 */
55#define ECC_DR 6 /* Diagnostic Register */
56#define ECC_ECR0 7 /* Event Count Register 0 */
57#define ECC_ECR1 8 /* Event Count Register 1 */
blueswir17eb0c8e2007-12-09 17:03:50 +000058
59/* ECC fault control register */
blueswir1dd53ded2008-05-06 16:33:45 +000060#define ECC_MER_EE 0x00000001 /* Enable ECC checking */
blueswir177f193d2008-05-12 16:13:33 +000061#define ECC_MER_EI 0x00000002 /* Enable Interrupts on
62 correctable errors */
blueswir1dd53ded2008-05-06 16:33:45 +000063#define ECC_MER_MRR0 0x00000004 /* SIMM 0 */
64#define ECC_MER_MRR1 0x00000008 /* SIMM 1 */
65#define ECC_MER_MRR2 0x00000010 /* SIMM 2 */
66#define ECC_MER_MRR3 0x00000020 /* SIMM 3 */
67#define ECC_MER_MRR4 0x00000040 /* SIMM 4 */
68#define ECC_MER_MRR5 0x00000080 /* SIMM 5 */
69#define ECC_MER_MRR6 0x00000100 /* SIMM 6 */
70#define ECC_MER_MRR7 0x00000200 /* SIMM 7 */
blueswir10bb36022008-12-23 15:08:13 +000071#define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */
blueswir1dd53ded2008-05-06 16:33:45 +000072#define ECC_MER_MRR 0x000003fc /* MRR mask */
blueswir10bb36022008-12-23 15:08:13 +000073#define ECC_MER_A 0x00000400 /* Memory controller addr map select */
blueswir177f193d2008-05-12 16:13:33 +000074#define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */
blueswir1dd53ded2008-05-06 16:33:45 +000075#define ECC_MER_VER 0x0f000000 /* Version */
76#define ECC_MER_IMPL 0xf0000000 /* Implementation */
blueswir10bb36022008-12-23 15:08:13 +000077#define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */
78#define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */
79#define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */
blueswir1dd53ded2008-05-06 16:33:45 +000080
81/* ECC memory delay register */
82#define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */
83#define ECC_MDR_MI 0x00001c00 /* MIH Delay */
84#define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */
85#define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */
86#define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */
87#define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */
88#define ECC_MDR_RSC 0x80000000 /* Refresh load control */
89#define ECC_MDR_MASK 0x7fffffff
blueswir17eb0c8e2007-12-09 17:03:50 +000090
91/* ECC fault status register */
blueswir1dd53ded2008-05-06 16:33:45 +000092#define ECC_MFSR_CE 0x00000001 /* Correctable error */
93#define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */
94#define ECC_MFSR_TO 0x00000004 /* Timeout on write */
95#define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */
96#define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */
97#define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */
98#define ECC_MFSR_ME 0x00010000 /* Multiple errors */
99#define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */
blueswir17eb0c8e2007-12-09 17:03:50 +0000100
101/* ECC fault address register 0 */
blueswir1dd53ded2008-05-06 16:33:45 +0000102#define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */
103#define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */
104#define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */
105#define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */
106#define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */
107#define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */
108#define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */
109#define ECC_MFAR0_S 0x08000000 /* Supervisor mode */
110#define ECC_MFARO_MID 0xf0000000 /* Module ID */
blueswir17eb0c8e2007-12-09 17:03:50 +0000111
112/* ECC diagnostic register */
blueswir1dd53ded2008-05-06 16:33:45 +0000113#define ECC_DR_CBX 0x00000001
114#define ECC_DR_CB0 0x00000002
115#define ECC_DR_CB1 0x00000004
116#define ECC_DR_CB2 0x00000008
117#define ECC_DR_CB4 0x00000010
118#define ECC_DR_CB8 0x00000020
119#define ECC_DR_CB16 0x00000040
120#define ECC_DR_CB32 0x00000080
121#define ECC_DR_DMODE 0x00000c00
blueswir17eb0c8e2007-12-09 17:03:50 +0000122
blueswir1dd53ded2008-05-06 16:33:45 +0000123#define ECC_NREGS 9
blueswir17eb0c8e2007-12-09 17:03:50 +0000124#define ECC_SIZE (ECC_NREGS * sizeof(uint32_t))
blueswir1dd53ded2008-05-06 16:33:45 +0000125
126#define ECC_DIAG_SIZE 4
127#define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
blueswir17eb0c8e2007-12-09 17:03:50 +0000128
Andreas Färber100bb152013-07-26 21:39:54 +0200129#define TYPE_ECC_MEMCTL "eccmemctl"
Eduardo Habkost80633962020-09-16 14:25:19 -0400130OBJECT_DECLARE_SIMPLE_TYPE(ECCState, ECC_MEMCTL)
Andreas Färber100bb152013-07-26 21:39:54 +0200131
Eduardo Habkostdb1015e2020-09-03 16:43:22 -0400132struct ECCState {
Andreas Färber100bb152013-07-26 21:39:54 +0200133 SysBusDevice parent_obj;
134
Avi Kivity7ef57cc2011-11-14 11:17:21 +0200135 MemoryRegion iomem, iomem_diag;
blueswir1e42c20b2008-01-17 21:04:16 +0000136 qemu_irq irq;
blueswir17eb0c8e2007-12-09 17:03:50 +0000137 uint32_t regs[ECC_NREGS];
blueswir1dd53ded2008-05-06 16:33:45 +0000138 uint8_t diag[ECC_DIAG_SIZE];
blueswir10bb36022008-12-23 15:08:13 +0000139 uint32_t version;
Eduardo Habkostdb1015e2020-09-03 16:43:22 -0400140};
blueswir17eb0c8e2007-12-09 17:03:50 +0000141
Avi Kivitya8170e52012-10-23 12:30:10 +0200142static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
Avi Kivity7ef57cc2011-11-14 11:17:21 +0200143 unsigned size)
blueswir17eb0c8e2007-12-09 17:03:50 +0000144{
145 ECCState *s = opaque;
146
blueswir1e64d7d52008-12-02 17:47:02 +0000147 switch (addr >> 2) {
blueswir1dd53ded2008-05-06 16:33:45 +0000148 case ECC_MER:
blueswir10bb36022008-12-23 15:08:13 +0000149 if (s->version == ECC_MCC)
150 s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
151 else if (s->version == ECC_EMC)
152 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);
153 else if (s->version == ECC_SMC)
154 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);
Blue Swirl97bf4852010-10-31 09:24:14 +0000155 trace_ecc_mem_writel_mer(val);
blueswir17eb0c8e2007-12-09 17:03:50 +0000156 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000157 case ECC_MDR:
blueswir18f2ad0a2008-06-19 17:38:15 +0000158 s->regs[ECC_MDR] = val & ECC_MDR_MASK;
Blue Swirl97bf4852010-10-31 09:24:14 +0000159 trace_ecc_mem_writel_mdr(val);
blueswir17eb0c8e2007-12-09 17:03:50 +0000160 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000161 case ECC_MFSR:
blueswir18f2ad0a2008-06-19 17:38:15 +0000162 s->regs[ECC_MFSR] = val;
blueswir10bb36022008-12-23 15:08:13 +0000163 qemu_irq_lower(s->irq);
Blue Swirl97bf4852010-10-31 09:24:14 +0000164 trace_ecc_mem_writel_mfsr(val);
blueswir17eb0c8e2007-12-09 17:03:50 +0000165 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000166 case ECC_VCR:
blueswir18f2ad0a2008-06-19 17:38:15 +0000167 s->regs[ECC_VCR] = val;
Blue Swirl97bf4852010-10-31 09:24:14 +0000168 trace_ecc_mem_writel_vcr(val);
blueswir17eb0c8e2007-12-09 17:03:50 +0000169 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000170 case ECC_DR:
blueswir18f2ad0a2008-06-19 17:38:15 +0000171 s->regs[ECC_DR] = val;
Blue Swirl97bf4852010-10-31 09:24:14 +0000172 trace_ecc_mem_writel_dr(val);
blueswir17eb0c8e2007-12-09 17:03:50 +0000173 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000174 case ECC_ECR0:
blueswir18f2ad0a2008-06-19 17:38:15 +0000175 s->regs[ECC_ECR0] = val;
Blue Swirl97bf4852010-10-31 09:24:14 +0000176 trace_ecc_mem_writel_ecr0(val);
blueswir1dd53ded2008-05-06 16:33:45 +0000177 break;
178 case ECC_ECR1:
blueswir18f2ad0a2008-06-19 17:38:15 +0000179 s->regs[ECC_ECR0] = val;
Blue Swirl97bf4852010-10-31 09:24:14 +0000180 trace_ecc_mem_writel_ecr1(val);
blueswir17eb0c8e2007-12-09 17:03:50 +0000181 break;
182 }
183}
184
Avi Kivitya8170e52012-10-23 12:30:10 +0200185static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
Avi Kivity7ef57cc2011-11-14 11:17:21 +0200186 unsigned size)
blueswir17eb0c8e2007-12-09 17:03:50 +0000187{
188 ECCState *s = opaque;
189 uint32_t ret = 0;
190
blueswir1e64d7d52008-12-02 17:47:02 +0000191 switch (addr >> 2) {
blueswir1dd53ded2008-05-06 16:33:45 +0000192 case ECC_MER:
blueswir18f2ad0a2008-06-19 17:38:15 +0000193 ret = s->regs[ECC_MER];
Blue Swirl97bf4852010-10-31 09:24:14 +0000194 trace_ecc_mem_readl_mer(ret);
blueswir17eb0c8e2007-12-09 17:03:50 +0000195 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000196 case ECC_MDR:
blueswir18f2ad0a2008-06-19 17:38:15 +0000197 ret = s->regs[ECC_MDR];
Blue Swirl97bf4852010-10-31 09:24:14 +0000198 trace_ecc_mem_readl_mdr(ret);
blueswir17eb0c8e2007-12-09 17:03:50 +0000199 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000200 case ECC_MFSR:
blueswir18f2ad0a2008-06-19 17:38:15 +0000201 ret = s->regs[ECC_MFSR];
Blue Swirl97bf4852010-10-31 09:24:14 +0000202 trace_ecc_mem_readl_mfsr(ret);
blueswir17eb0c8e2007-12-09 17:03:50 +0000203 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000204 case ECC_VCR:
blueswir18f2ad0a2008-06-19 17:38:15 +0000205 ret = s->regs[ECC_VCR];
Blue Swirl97bf4852010-10-31 09:24:14 +0000206 trace_ecc_mem_readl_vcr(ret);
blueswir17eb0c8e2007-12-09 17:03:50 +0000207 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000208 case ECC_MFAR0:
blueswir18f2ad0a2008-06-19 17:38:15 +0000209 ret = s->regs[ECC_MFAR0];
Blue Swirl97bf4852010-10-31 09:24:14 +0000210 trace_ecc_mem_readl_mfar0(ret);
blueswir17eb0c8e2007-12-09 17:03:50 +0000211 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000212 case ECC_MFAR1:
blueswir18f2ad0a2008-06-19 17:38:15 +0000213 ret = s->regs[ECC_MFAR1];
Blue Swirl97bf4852010-10-31 09:24:14 +0000214 trace_ecc_mem_readl_mfar1(ret);
blueswir17eb0c8e2007-12-09 17:03:50 +0000215 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000216 case ECC_DR:
blueswir18f2ad0a2008-06-19 17:38:15 +0000217 ret = s->regs[ECC_DR];
Blue Swirl97bf4852010-10-31 09:24:14 +0000218 trace_ecc_mem_readl_dr(ret);
blueswir17eb0c8e2007-12-09 17:03:50 +0000219 break;
blueswir1dd53ded2008-05-06 16:33:45 +0000220 case ECC_ECR0:
blueswir18f2ad0a2008-06-19 17:38:15 +0000221 ret = s->regs[ECC_ECR0];
Blue Swirl97bf4852010-10-31 09:24:14 +0000222 trace_ecc_mem_readl_ecr0(ret);
blueswir1dd53ded2008-05-06 16:33:45 +0000223 break;
224 case ECC_ECR1:
blueswir18f2ad0a2008-06-19 17:38:15 +0000225 ret = s->regs[ECC_ECR0];
Blue Swirl97bf4852010-10-31 09:24:14 +0000226 trace_ecc_mem_readl_ecr1(ret);
blueswir17eb0c8e2007-12-09 17:03:50 +0000227 break;
228 }
229 return ret;
230}
231
Avi Kivity7ef57cc2011-11-14 11:17:21 +0200232static const MemoryRegionOps ecc_mem_ops = {
233 .read = ecc_mem_read,
234 .write = ecc_mem_write,
235 .endianness = DEVICE_NATIVE_ENDIAN,
236 .valid = {
237 .min_access_size = 4,
238 .max_access_size = 4,
239 },
blueswir17eb0c8e2007-12-09 17:03:50 +0000240};
241
Avi Kivitya8170e52012-10-23 12:30:10 +0200242static void ecc_diag_mem_write(void *opaque, hwaddr addr,
Avi Kivity7ef57cc2011-11-14 11:17:21 +0200243 uint64_t val, unsigned size)
blueswir1dd53ded2008-05-06 16:33:45 +0000244{
245 ECCState *s = opaque;
246
Blue Swirl97bf4852010-10-31 09:24:14 +0000247 trace_ecc_diag_mem_writeb(addr, val);
blueswir1dd53ded2008-05-06 16:33:45 +0000248 s->diag[addr & ECC_DIAG_MASK] = val;
249}
250
Avi Kivitya8170e52012-10-23 12:30:10 +0200251static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
Avi Kivity7ef57cc2011-11-14 11:17:21 +0200252 unsigned size)
blueswir1dd53ded2008-05-06 16:33:45 +0000253{
254 ECCState *s = opaque;
blueswir1e64d7d52008-12-02 17:47:02 +0000255 uint32_t ret = s->diag[(int)addr];
256
Blue Swirl97bf4852010-10-31 09:24:14 +0000257 trace_ecc_diag_mem_readb(addr, ret);
blueswir1dd53ded2008-05-06 16:33:45 +0000258 return ret;
259}
260
Avi Kivity7ef57cc2011-11-14 11:17:21 +0200261static const MemoryRegionOps ecc_diag_mem_ops = {
262 .read = ecc_diag_mem_read,
263 .write = ecc_diag_mem_write,
264 .endianness = DEVICE_NATIVE_ENDIAN,
265 .valid = {
266 .min_access_size = 1,
267 .max_access_size = 1,
268 },
blueswir1dd53ded2008-05-06 16:33:45 +0000269};
270
Blue Swirlc21011a2009-08-29 16:36:58 +0300271static const VMStateDescription vmstate_ecc = {
272 .name ="ECC",
273 .version_id = 3,
274 .minimum_version_id = 3,
Juan Quintela35d08452014-04-16 16:01:33 +0200275 .fields = (VMStateField[]) {
Blue Swirlc21011a2009-08-29 16:36:58 +0300276 VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS),
277 VMSTATE_BUFFER(diag, ECCState),
278 VMSTATE_UINT32(version, ECCState),
279 VMSTATE_END_OF_LIST()
280 }
281};
blueswir17eb0c8e2007-12-09 17:03:50 +0000282
Blue Swirl0284dc52009-10-24 14:14:39 +0000283static void ecc_reset(DeviceState *d)
blueswir17eb0c8e2007-12-09 17:03:50 +0000284{
Andreas Färber100bb152013-07-26 21:39:54 +0200285 ECCState *s = ECC_MEMCTL(d);
blueswir17eb0c8e2007-12-09 17:03:50 +0000286
Andreas Färber100bb152013-07-26 21:39:54 +0200287 if (s->version == ECC_MCC) {
blueswir10bb36022008-12-23 15:08:13 +0000288 s->regs[ECC_MER] &= ECC_MER_REU;
Andreas Färber100bb152013-07-26 21:39:54 +0200289 } else {
blueswir10bb36022008-12-23 15:08:13 +0000290 s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
291 ECC_MER_DCI);
Andreas Färber100bb152013-07-26 21:39:54 +0200292 }
blueswir1dd53ded2008-05-06 16:33:45 +0000293 s->regs[ECC_MDR] = 0x20;
294 s->regs[ECC_MFSR] = 0;
295 s->regs[ECC_VCR] = 0;
296 s->regs[ECC_MFAR0] = 0x07c00000;
297 s->regs[ECC_MFAR1] = 0;
298 s->regs[ECC_DR] = 0;
299 s->regs[ECC_ECR0] = 0;
300 s->regs[ECC_ECR1] = 0;
blueswir17eb0c8e2007-12-09 17:03:50 +0000301}
302
xiaoqiang zhaob229a572017-05-25 21:34:44 +0800303static void ecc_init(Object *obj)
blueswir17eb0c8e2007-12-09 17:03:50 +0000304{
xiaoqiang zhaob229a572017-05-25 21:34:44 +0800305 ECCState *s = ECC_MEMCTL(obj);
306 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
blueswir17eb0c8e2007-12-09 17:03:50 +0000307
Blue Swirl49e66372009-07-12 08:16:55 +0000308 sysbus_init_irq(dev, &s->irq);
xiaoqiang zhaob229a572017-05-25 21:34:44 +0800309
310 memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE);
Avi Kivity750ecd42011-11-27 11:38:10 +0200311 sysbus_init_mmio(dev, &s->iomem);
xiaoqiang zhaob229a572017-05-25 21:34:44 +0800312}
313
314static void ecc_realize(DeviceState *dev, Error **errp)
315{
316 ECCState *s = ECC_MEMCTL(dev);
317 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
318
319 s->regs[0] = s->version;
Blue Swirl49e66372009-07-12 08:16:55 +0000320
321 if (s->version == ECC_MCC) { // SS-600MP only
Paolo Bonzini3c161542013-06-06 21:25:08 -0400322 memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s,
Avi Kivity7ef57cc2011-11-14 11:17:21 +0200323 "ecc.diag", ECC_DIAG_SIZE);
xiaoqiang zhaob229a572017-05-25 21:34:44 +0800324 sysbus_init_mmio(sbd, &s->iomem_diag);
blueswir1dd53ded2008-05-06 16:33:45 +0000325 }
blueswir17eb0c8e2007-12-09 17:03:50 +0000326}
Blue Swirl49e66372009-07-12 08:16:55 +0000327
Anthony Liguori999e12b2012-01-24 13:12:29 -0600328static Property ecc_properties[] = {
Paolo Bonzinic7bcc852014-02-08 11:01:53 +0100329 DEFINE_PROP_UINT32("version", ECCState, version, -1),
Anthony Liguori999e12b2012-01-24 13:12:29 -0600330 DEFINE_PROP_END_OF_LIST(),
331};
332
333static void ecc_class_init(ObjectClass *klass, void *data)
334{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600335 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600336
xiaoqiang zhaob229a572017-05-25 21:34:44 +0800337 dc->realize = ecc_realize;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600338 dc->reset = ecc_reset;
339 dc->vmsd = &vmstate_ecc;
Marc-André Lureau4f67d302020-01-10 19:30:32 +0400340 device_class_set_props(dc, ecc_properties);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600341}
342
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100343static const TypeInfo ecc_info = {
Andreas Färber100bb152013-07-26 21:39:54 +0200344 .name = TYPE_ECC_MEMCTL,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600345 .parent = TYPE_SYS_BUS_DEVICE,
346 .instance_size = sizeof(ECCState),
xiaoqiang zhaob229a572017-05-25 21:34:44 +0800347 .instance_init = ecc_init,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600348 .class_init = ecc_class_init,
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200349};
350
351
Andreas Färber83f7d432012-02-09 15:20:55 +0100352static void ecc_register_types(void)
Blue Swirl49e66372009-07-12 08:16:55 +0000353{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600354 type_register_static(&ecc_info);
Blue Swirl49e66372009-07-12 08:16:55 +0000355}
356
Andreas Färber83f7d432012-02-09 15:20:55 +0100357type_init(ecc_register_types)