Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * i.MX I2C Bus Serial Interface Emulation |
| 3 | * |
| 4 | * Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | * for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 18 | * |
| 19 | */ |
| 20 | |
Peter Maydell | 8ef94f0 | 2016-01-26 18:17:05 +0000 | [diff] [blame] | 21 | #include "qemu/osdep.h" |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 22 | #include "hw/i2c/imx_i2c.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 23 | #include "hw/irq.h" |
Markus Armbruster | d645427 | 2019-08-12 07:23:45 +0200 | [diff] [blame] | 24 | #include "migration/vmstate.h" |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 25 | #include "hw/i2c/i2c.h" |
Paolo Bonzini | 03dd024 | 2015-12-15 13:16:16 +0100 | [diff] [blame] | 26 | #include "qemu/log.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 27 | #include "qemu/module.h" |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 28 | |
Jean-Christophe Dubois | 3afcbb0 | 2015-10-25 15:16:14 +0100 | [diff] [blame] | 29 | #ifndef DEBUG_IMX_I2C |
| 30 | #define DEBUG_IMX_I2C 0 |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 31 | #endif |
| 32 | |
Jean-Christophe Dubois | 3afcbb0 | 2015-10-25 15:16:14 +0100 | [diff] [blame] | 33 | #define DPRINTF(fmt, args...) \ |
| 34 | do { \ |
| 35 | if (DEBUG_IMX_I2C) { \ |
| 36 | fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_I2C, \ |
| 37 | __func__, ##args); \ |
| 38 | } \ |
| 39 | } while (0) |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 40 | |
| 41 | static const char *imx_i2c_get_regname(unsigned offset) |
| 42 | { |
| 43 | switch (offset) { |
| 44 | case IADR_ADDR: |
| 45 | return "IADR"; |
| 46 | case IFDR_ADDR: |
| 47 | return "IFDR"; |
| 48 | case I2CR_ADDR: |
| 49 | return "I2CR"; |
| 50 | case I2SR_ADDR: |
| 51 | return "I2SR"; |
| 52 | case I2DR_ADDR: |
| 53 | return "I2DR"; |
| 54 | default: |
| 55 | return "[?]"; |
| 56 | } |
| 57 | } |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 58 | |
| 59 | static inline bool imx_i2c_is_enabled(IMXI2CState *s) |
| 60 | { |
| 61 | return s->i2cr & I2CR_IEN; |
| 62 | } |
| 63 | |
| 64 | static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState *s) |
| 65 | { |
| 66 | return s->i2cr & I2CR_IIEN; |
| 67 | } |
| 68 | |
| 69 | static inline bool imx_i2c_is_master(IMXI2CState *s) |
| 70 | { |
| 71 | return s->i2cr & I2CR_MSTA; |
| 72 | } |
| 73 | |
| 74 | static void imx_i2c_reset(DeviceState *dev) |
| 75 | { |
| 76 | IMXI2CState *s = IMX_I2C(dev); |
| 77 | |
| 78 | if (s->address != ADDR_RESET) { |
| 79 | i2c_end_transfer(s->bus); |
| 80 | } |
| 81 | |
| 82 | s->address = ADDR_RESET; |
| 83 | s->iadr = IADR_RESET; |
| 84 | s->ifdr = IFDR_RESET; |
| 85 | s->i2cr = I2CR_RESET; |
| 86 | s->i2sr = I2SR_RESET; |
| 87 | s->i2dr_read = I2DR_RESET; |
| 88 | s->i2dr_write = I2DR_RESET; |
| 89 | } |
| 90 | |
| 91 | static inline void imx_i2c_raise_interrupt(IMXI2CState *s) |
| 92 | { |
| 93 | /* |
| 94 | * raise an interrupt if the device is enabled and it is configured |
| 95 | * to generate some interrupts. |
| 96 | */ |
| 97 | if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) { |
| 98 | s->i2sr |= I2SR_IIF; |
| 99 | qemu_irq_raise(s->irq); |
| 100 | } |
| 101 | } |
| 102 | |
| 103 | static uint64_t imx_i2c_read(void *opaque, hwaddr offset, |
| 104 | unsigned size) |
| 105 | { |
| 106 | uint16_t value; |
| 107 | IMXI2CState *s = IMX_I2C(opaque); |
| 108 | |
| 109 | switch (offset) { |
| 110 | case IADR_ADDR: |
| 111 | value = s->iadr; |
| 112 | break; |
| 113 | case IFDR_ADDR: |
| 114 | value = s->ifdr; |
| 115 | break; |
| 116 | case I2CR_ADDR: |
| 117 | value = s->i2cr; |
| 118 | break; |
| 119 | case I2SR_ADDR: |
| 120 | value = s->i2sr; |
| 121 | break; |
| 122 | case I2DR_ADDR: |
| 123 | value = s->i2dr_read; |
| 124 | |
| 125 | if (imx_i2c_is_master(s)) { |
Corey Minyard | bc15cde | 2018-11-20 11:13:42 -0600 | [diff] [blame] | 126 | uint8_t ret = 0xff; |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 127 | |
| 128 | if (s->address == ADDR_RESET) { |
| 129 | /* something is wrong as the address is not set */ |
Jean-Christophe Dubois | 3afcbb0 | 2015-10-25 15:16:14 +0100 | [diff] [blame] | 130 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read " |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 131 | "without specifying the slave address\n", |
| 132 | TYPE_IMX_I2C, __func__); |
| 133 | } else if (s->i2cr & I2CR_MTX) { |
Jean-Christophe Dubois | 3afcbb0 | 2015-10-25 15:16:14 +0100 | [diff] [blame] | 134 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read " |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 135 | "but MTX is set\n", TYPE_IMX_I2C, __func__); |
| 136 | } else { |
| 137 | /* get the next byte */ |
| 138 | ret = i2c_recv(s->bus); |
Corey Minyard | bc15cde | 2018-11-20 11:13:42 -0600 | [diff] [blame] | 139 | imx_i2c_raise_interrupt(s); |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | s->i2dr_read = ret; |
| 143 | } else { |
Jean-Christophe Dubois | 3afcbb0 | 2015-10-25 15:16:14 +0100 | [diff] [blame] | 144 | qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n", |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 145 | TYPE_IMX_I2C, __func__); |
| 146 | } |
| 147 | break; |
| 148 | default: |
Jean-Christophe Dubois | 3afcbb0 | 2015-10-25 15:16:14 +0100 | [diff] [blame] | 149 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" |
| 150 | HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset); |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 151 | value = 0; |
| 152 | break; |
| 153 | } |
| 154 | |
Jean-Christophe Dubois | 3afcbb0 | 2015-10-25 15:16:14 +0100 | [diff] [blame] | 155 | DPRINTF("read %s [0x%" HWADDR_PRIx "] -> 0x%02x\n", |
| 156 | imx_i2c_get_regname(offset), offset, value); |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 157 | |
| 158 | return (uint64_t)value; |
| 159 | } |
| 160 | |
| 161 | static void imx_i2c_write(void *opaque, hwaddr offset, |
| 162 | uint64_t value, unsigned size) |
| 163 | { |
| 164 | IMXI2CState *s = IMX_I2C(opaque); |
| 165 | |
Jean-Christophe Dubois | 3afcbb0 | 2015-10-25 15:16:14 +0100 | [diff] [blame] | 166 | DPRINTF("write %s [0x%" HWADDR_PRIx "] <- 0x%02x\n", |
| 167 | imx_i2c_get_regname(offset), offset, (int)value); |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 168 | |
| 169 | value &= 0xff; |
| 170 | |
| 171 | switch (offset) { |
| 172 | case IADR_ADDR: |
| 173 | s->iadr = value & IADR_MASK; |
| 174 | /* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */ |
| 175 | break; |
| 176 | case IFDR_ADDR: |
| 177 | s->ifdr = value & IFDR_MASK; |
| 178 | break; |
| 179 | case I2CR_ADDR: |
| 180 | if (imx_i2c_is_enabled(s) && ((value & I2CR_IEN) == 0)) { |
| 181 | /* This is a soft reset. IADR is preserved during soft resets */ |
| 182 | uint16_t iadr = s->iadr; |
| 183 | imx_i2c_reset(DEVICE(s)); |
| 184 | s->iadr = iadr; |
| 185 | } else { /* normal write */ |
| 186 | s->i2cr = value & I2CR_MASK; |
| 187 | |
| 188 | if (imx_i2c_is_master(s)) { |
| 189 | /* set the bus to busy */ |
| 190 | s->i2sr |= I2SR_IBB; |
| 191 | } else { /* slave mode */ |
| 192 | /* bus is not busy anymore */ |
| 193 | s->i2sr &= ~I2SR_IBB; |
| 194 | |
| 195 | /* |
| 196 | * if we unset the master mode then it ends the ongoing |
| 197 | * transfer if any |
| 198 | */ |
| 199 | if (s->address != ADDR_RESET) { |
| 200 | i2c_end_transfer(s->bus); |
| 201 | s->address = ADDR_RESET; |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | if (s->i2cr & I2CR_RSTA) { /* Restart */ |
| 206 | /* if this is a restart then it ends the ongoing transfer */ |
| 207 | if (s->address != ADDR_RESET) { |
| 208 | i2c_end_transfer(s->bus); |
| 209 | s->address = ADDR_RESET; |
| 210 | s->i2cr &= ~I2CR_RSTA; |
| 211 | } |
| 212 | } |
| 213 | } |
| 214 | break; |
| 215 | case I2SR_ADDR: |
| 216 | /* |
| 217 | * if the user writes 0 to IIF then lower the interrupt and |
| 218 | * reset the bit |
| 219 | */ |
| 220 | if ((s->i2sr & I2SR_IIF) && !(value & I2SR_IIF)) { |
| 221 | s->i2sr &= ~I2SR_IIF; |
| 222 | qemu_irq_lower(s->irq); |
| 223 | } |
| 224 | |
| 225 | /* |
| 226 | * if the user writes 0 to IAL, reset the bit |
| 227 | */ |
| 228 | if ((s->i2sr & I2SR_IAL) && !(value & I2SR_IAL)) { |
| 229 | s->i2sr &= ~I2SR_IAL; |
| 230 | } |
| 231 | |
| 232 | break; |
| 233 | case I2DR_ADDR: |
| 234 | /* if the device is not enabled, nothing to do */ |
| 235 | if (!imx_i2c_is_enabled(s)) { |
| 236 | break; |
| 237 | } |
| 238 | |
| 239 | s->i2dr_write = value & I2DR_MASK; |
| 240 | |
| 241 | if (imx_i2c_is_master(s)) { |
| 242 | /* If this is the first write cycle then it is the slave addr */ |
| 243 | if (s->address == ADDR_RESET) { |
| 244 | if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7), |
| 245 | extract32(s->i2dr_write, 0, 1))) { |
Stefan Weil | cb8d4c8 | 2016-03-23 15:59:57 +0100 | [diff] [blame] | 246 | /* if non zero is returned, the address is not valid */ |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 247 | s->i2sr |= I2SR_RXAK; |
| 248 | } else { |
| 249 | s->address = s->i2dr_write; |
| 250 | s->i2sr &= ~I2SR_RXAK; |
| 251 | imx_i2c_raise_interrupt(s); |
| 252 | } |
| 253 | } else { /* This is a normal data write */ |
| 254 | if (i2c_send(s->bus, s->i2dr_write)) { |
| 255 | /* if the target return non zero then end the transfer */ |
| 256 | s->i2sr |= I2SR_RXAK; |
| 257 | s->address = ADDR_RESET; |
| 258 | i2c_end_transfer(s->bus); |
| 259 | } else { |
| 260 | s->i2sr &= ~I2SR_RXAK; |
| 261 | imx_i2c_raise_interrupt(s); |
| 262 | } |
| 263 | } |
| 264 | } else { |
Jean-Christophe Dubois | 3afcbb0 | 2015-10-25 15:16:14 +0100 | [diff] [blame] | 265 | qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n", |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 266 | TYPE_IMX_I2C, __func__); |
| 267 | } |
| 268 | break; |
| 269 | default: |
Jean-Christophe Dubois | 3afcbb0 | 2015-10-25 15:16:14 +0100 | [diff] [blame] | 270 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" |
| 271 | HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset); |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 272 | break; |
| 273 | } |
| 274 | } |
| 275 | |
| 276 | static const MemoryRegionOps imx_i2c_ops = { |
| 277 | .read = imx_i2c_read, |
| 278 | .write = imx_i2c_write, |
| 279 | .valid.min_access_size = 1, |
| 280 | .valid.max_access_size = 2, |
| 281 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 282 | }; |
| 283 | |
| 284 | static const VMStateDescription imx_i2c_vmstate = { |
| 285 | .name = TYPE_IMX_I2C, |
| 286 | .version_id = 1, |
| 287 | .minimum_version_id = 1, |
| 288 | .fields = (VMStateField[]) { |
| 289 | VMSTATE_UINT16(address, IMXI2CState), |
| 290 | VMSTATE_UINT16(iadr, IMXI2CState), |
| 291 | VMSTATE_UINT16(ifdr, IMXI2CState), |
| 292 | VMSTATE_UINT16(i2cr, IMXI2CState), |
| 293 | VMSTATE_UINT16(i2sr, IMXI2CState), |
| 294 | VMSTATE_UINT16(i2dr_read, IMXI2CState), |
| 295 | VMSTATE_UINT16(i2dr_write, IMXI2CState), |
| 296 | VMSTATE_END_OF_LIST() |
| 297 | } |
| 298 | }; |
| 299 | |
| 300 | static void imx_i2c_realize(DeviceState *dev, Error **errp) |
| 301 | { |
| 302 | IMXI2CState *s = IMX_I2C(dev); |
| 303 | |
| 304 | memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C, |
| 305 | IMX_I2C_MEM_SIZE); |
| 306 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); |
| 307 | sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); |
Philippe Mathieu-Daudé | 8e5c952 | 2020-05-12 09:00:20 +0200 | [diff] [blame] | 308 | s->bus = i2c_init_bus(dev, NULL); |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 309 | } |
| 310 | |
| 311 | static void imx_i2c_class_init(ObjectClass *klass, void *data) |
| 312 | { |
| 313 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 314 | |
| 315 | dc->vmsd = &imx_i2c_vmstate; |
| 316 | dc->reset = imx_i2c_reset; |
| 317 | dc->realize = imx_i2c_realize; |
Jean-Christophe Dubois | eccfa35 | 2016-03-16 17:06:00 +0000 | [diff] [blame] | 318 | dc->desc = "i.MX I2C Controller"; |
Jean-Christophe Dubois | 20d0f9c | 2015-09-07 10:39:30 +0100 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | static const TypeInfo imx_i2c_type_info = { |
| 322 | .name = TYPE_IMX_I2C, |
| 323 | .parent = TYPE_SYS_BUS_DEVICE, |
| 324 | .instance_size = sizeof(IMXI2CState), |
| 325 | .class_init = imx_i2c_class_init, |
| 326 | }; |
| 327 | |
| 328 | static void imx_i2c_register_types(void) |
| 329 | { |
| 330 | type_register_static(&imx_i2c_type_info); |
| 331 | } |
| 332 | |
| 333 | type_init(imx_i2c_register_types) |