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Peter Crosthwaitef49856d2015-05-14 19:23:09 -07001/*
2 * QEMU Cadence GEM emulation
3 *
4 * Copyright (c) 2011 Xilinx, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#ifndef CADENCE_GEM_H
Markus Armbruster0553d892019-06-04 20:16:15 +020026#define CADENCE_GEM_H
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040027#include "qom/object.h"
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070028
29#define TYPE_CADENCE_GEM "cadence_gem"
Eduardo Habkost80633962020-09-16 14:25:19 -040030OBJECT_DECLARE_SIMPLE_TYPE(CadenceGEMState, CADENCE_GEM)
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070031
32#include "net/net.h"
33#include "hw/sysbus.h"
34
Alistair Francise8e49942016-09-22 18:13:07 +010035#define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070036
Edgar E. Iglesias85683132018-10-11 04:19:23 +020037/* Max number of words in a DMA descriptor. */
Edgar E. Iglesiase48fdd92018-10-11 04:19:24 +020038#define DESC_MAX_NUM_WORDS 6
Edgar E. Iglesias85683132018-10-11 04:19:23 +020039
Alistair Francis2bf57f72016-09-22 18:13:07 +010040#define MAX_PRIORITY_QUEUES 8
Alistair Francise8e49942016-09-22 18:13:07 +010041#define MAX_TYPE1_SCREENERS 16
42#define MAX_TYPE2_SCREENERS 16
Alistair Francis2bf57f72016-09-22 18:13:07 +010043
Sai Pavan Boddu7ca151c2020-05-12 20:24:50 +053044#define MAX_JUMBO_FRAME_SIZE_MASK 0x3FFF
45#define MAX_FRAME_SIZE MAX_JUMBO_FRAME_SIZE_MASK
Sai Pavan Boddu24d62fd2020-05-12 20:24:48 +053046
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040047struct CadenceGEMState {
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070048 /*< private >*/
49 SysBusDevice parent_obj;
50
51 /*< public >*/
52 MemoryRegion iomem;
Edgar E. Iglesias84aec8e2018-10-11 04:19:25 +020053 MemoryRegion *dma_mr;
54 AddressSpace dma_as;
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070055 NICState *nic;
56 NICConf conf;
Alistair Francis2bf57f72016-09-22 18:13:07 +010057 qemu_irq irq[MAX_PRIORITY_QUEUES];
58
59 /* Static properties */
60 uint8_t num_priority_queues;
Alistair Francise8e49942016-09-22 18:13:07 +010061 uint8_t num_type1_screeners;
62 uint8_t num_type2_screeners;
Alistair Francisa5517662017-04-20 17:32:29 +010063 uint32_t revision;
Sai Pavan Boddu7ca151c2020-05-12 20:24:50 +053064 uint16_t jumbo_max_len;
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070065
66 /* GEM registers backing store */
67 uint32_t regs[CADENCE_GEM_MAXREG];
68 /* Mask of register bits which are write only */
69 uint32_t regs_wo[CADENCE_GEM_MAXREG];
70 /* Mask of register bits which are read only */
71 uint32_t regs_ro[CADENCE_GEM_MAXREG];
72 /* Mask of register bits which are clear on read */
73 uint32_t regs_rtc[CADENCE_GEM_MAXREG];
74 /* Mask of register bits which are write 1 to clear */
75 uint32_t regs_w1c[CADENCE_GEM_MAXREG];
76
Bin Meng64ac1362020-09-01 09:39:06 +080077 /* PHY address */
78 uint8_t phy_addr;
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070079 /* PHY registers backing store */
80 uint16_t phy_regs[32];
81
82 uint8_t phy_loop; /* Are we in phy loopback? */
83
84 /* The current DMA descriptor pointers */
Alistair Francis2bf57f72016-09-22 18:13:07 +010085 uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES];
86 uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES];
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070087
88 uint8_t can_rx_state; /* Debug only */
89
Sai Pavan Boddu24d62fd2020-05-12 20:24:48 +053090 uint8_t tx_packet[MAX_FRAME_SIZE];
91 uint8_t rx_packet[MAX_FRAME_SIZE];
Edgar E. Iglesias85683132018-10-11 04:19:23 +020092 uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS];
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070093
94 bool sar_active[4];
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040095};
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070096
Peter Crosthwaitef49856d2015-05-14 19:23:09 -070097#endif