commit fe84877ed44040dc128362b61dbfd923b851d6ef
author Richard Henderson <richard.henderson@linaro.org> Fri May 24 16:20:18 2024 -0700
committer Peter Maydell <peter.maydell@linaro.org> Tue May 28 14:29:01 2024 +0100
tree 357f04457b27d92ae473912d618303c42698ca85
parent db36e14501e8745a6e23f611f917d40a27cc5dee

target/arm: Zero-extend writeback for fp16 FCVTZS (scalar, integer)

Fixes RISU mismatch for "fcvtzs h31, h0, #14".

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target/arm/tcg/translate-a64.c

diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 4126aaa..d97acdb 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8707,6 +8707,9 @@
             read_vec_element_i32(s, tcg_op, rn, pass, size);
             fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
             if (is_scalar) {
+                if (size == MO_16 && !is_u) {
+                    tcg_gen_ext16u_i32(tcg_op, tcg_op);
+                }
                 write_fp_sreg(s, rd, tcg_op);
             } else {
                 write_vec_element_i32(s, tcg_op, rd, pass, size);